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authorFinn Thain <fthain@telegraphics.com.au>2016-03-23 06:10:16 -0400
committerMartin K. Petersen <martin.petersen@oracle.com>2016-04-11 16:57:09 -0400
commite5d55d1abcef09f7440e6211d5bd673baf547630 (patch)
tree15cecf89291ecf34f214ed59f79605424511259e
parentf825e40b235f4daf1c9017366809d34c7f5c8c7f (diff)
ncr5380: Remove BOARD_REQUIRES_NO_DELAY macro
The io_recovery_delay macro is intended to insert a microsecond delay between the chip register accesses that begin a DMA operation. This is reportedly needed for some ISA boards. Reverse the sense of the macro test so that in the common case, where no delay is required, drivers need not define the macro. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Reviewed-by: Hannes Reinecke <hare@suse.com> Tested-by: Michael Schmitz <schmitzmic@gmail.com> Tested-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
-rw-r--r--drivers/scsi/NCR5380.c18
-rw-r--r--drivers/scsi/dtc.h2
-rw-r--r--drivers/scsi/g_NCR5380.h2
-rw-r--r--drivers/scsi/t128.h2
4 files changed, 14 insertions, 10 deletions
diff --git a/drivers/scsi/NCR5380.c b/drivers/scsi/NCR5380.c
index fc86cde2d28e..014a01f6875f 100644
--- a/drivers/scsi/NCR5380.c
+++ b/drivers/scsi/NCR5380.c
@@ -39,12 +39,6 @@
39 * tagged queueing) 39 * tagged queueing)
40 */ 40 */
41 41
42#ifdef BOARD_REQUIRES_NO_DELAY
43#define io_recovery_delay(x)
44#else
45#define io_recovery_delay(x) udelay(x)
46#endif
47
48/* 42/*
49 * Design 43 * Design
50 * 44 *
@@ -150,6 +144,10 @@
150 * possible) function may be used. 144 * possible) function may be used.
151 */ 145 */
152 146
147#ifndef NCR5380_io_delay
148#define NCR5380_io_delay(x)
149#endif
150
153static int do_abort(struct Scsi_Host *); 151static int do_abort(struct Scsi_Host *);
154static void do_reset(struct Scsi_Host *); 152static void do_reset(struct Scsi_Host *);
155 153
@@ -1468,14 +1466,14 @@ static int NCR5380_transfer_dma(struct Scsi_Host *instance,
1468 */ 1466 */
1469 1467
1470 if (p & SR_IO) { 1468 if (p & SR_IO) {
1471 io_recovery_delay(1); 1469 NCR5380_io_delay(1);
1472 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0); 1470 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);
1473 } else { 1471 } else {
1474 io_recovery_delay(1); 1472 NCR5380_io_delay(1);
1475 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA); 1473 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1476 io_recovery_delay(1); 1474 NCR5380_io_delay(1);
1477 NCR5380_write(START_DMA_SEND_REG, 0); 1475 NCR5380_write(START_DMA_SEND_REG, 0);
1478 io_recovery_delay(1); 1476 NCR5380_io_delay(1);
1479 } 1477 }
1480 1478
1481/* 1479/*
diff --git a/drivers/scsi/dtc.h b/drivers/scsi/dtc.h
index 1bc638730dda..718f95adcec6 100644
--- a/drivers/scsi/dtc.h
+++ b/drivers/scsi/dtc.h
@@ -28,6 +28,8 @@
28#define NCR5380_bus_reset dtc_bus_reset 28#define NCR5380_bus_reset dtc_bus_reset
29#define NCR5380_info dtc_info 29#define NCR5380_info dtc_info
30 30
31#define NCR5380_io_delay(x) udelay(x)
32
31/* 15 12 11 10 33/* 15 12 11 10
32 1001 1100 0000 0000 */ 34 1001 1100 0000 0000 */
33 35
diff --git a/drivers/scsi/g_NCR5380.h b/drivers/scsi/g_NCR5380.h
index a231a8c52d87..637740f4c6c7 100644
--- a/drivers/scsi/g_NCR5380.h
+++ b/drivers/scsi/g_NCR5380.h
@@ -71,6 +71,8 @@
71#define NCR5380_pwrite generic_NCR5380_pwrite 71#define NCR5380_pwrite generic_NCR5380_pwrite
72#define NCR5380_info generic_NCR5380_info 72#define NCR5380_info generic_NCR5380_info
73 73
74#define NCR5380_io_delay(x) udelay(x)
75
74#define BOARD_NCR5380 0 76#define BOARD_NCR5380 0
75#define BOARD_NCR53C400 1 77#define BOARD_NCR53C400 1
76#define BOARD_NCR53C400A 2 78#define BOARD_NCR53C400A 2
diff --git a/drivers/scsi/t128.h b/drivers/scsi/t128.h
index c369b50de746..4caea9d62ac4 100644
--- a/drivers/scsi/t128.h
+++ b/drivers/scsi/t128.h
@@ -84,6 +84,8 @@
84#define NCR5380_bus_reset t128_bus_reset 84#define NCR5380_bus_reset t128_bus_reset
85#define NCR5380_info t128_info 85#define NCR5380_info t128_info
86 86
87#define NCR5380_io_delay(x) udelay(x)
88
87/* 15 14 12 10 7 5 3 89/* 15 14 12 10 7 5 3
88 1101 0100 1010 1000 */ 90 1101 0100 1010 1000 */
89 91