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authorAlexandre Belloni <alexandre.belloni@bootlin.com>2019-03-20 08:32:30 -0400
committerAlexandre Belloni <alexandre.belloni@bootlin.com>2019-04-04 04:07:08 -0400
commitdb7853414b3eb8fbd16017edd3d60e6f717170ff (patch)
tree36f40c7e2578b9ba5c5080c2d8683504e4a9e507
parent3a205b9dc87de108e096ac128e49feda9e3e58a8 (diff)
rtc: xgene: correct checkpatch issues
Correct trivial whitespace issues. Also sort the headers. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
-rw-r--r--drivers/rtc/rtc-xgene.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/rtc/rtc-xgene.c b/drivers/rtc/rtc-xgene.c
index ba9121d02f02..eb745deda936 100644
--- a/drivers/rtc/rtc-xgene.c
+++ b/drivers/rtc/rtc-xgene.c
@@ -7,15 +7,15 @@
7 * Loc Ho <lho@apm.com> 7 * Loc Ho <lho@apm.com>
8 */ 8 */
9 9
10#include <linux/clk.h>
11#include <linux/delay.h>
10#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/io.h>
11#include <linux/module.h> 14#include <linux/module.h>
12#include <linux/of.h> 15#include <linux/of.h>
13#include <linux/platform_device.h> 16#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/rtc.h> 17#include <linux/rtc.h>
18#include <linux/slab.h>
19 19
20/* RTC CSR Registers */ 20/* RTC CSR Registers */
21#define RTC_CCVR 0x00 21#define RTC_CCVR 0x00
@@ -58,7 +58,7 @@ static int xgene_rtc_set_mmss(struct device *dev, unsigned long secs)
58 * NOTE: After the following write, the RTC_CCVR is only reflected 58 * NOTE: After the following write, the RTC_CCVR is only reflected
59 * after the update cycle of 1 seconds. 59 * after the update cycle of 1 seconds.
60 */ 60 */
61 writel((u32) secs, pdata->csr_base + RTC_CLR); 61 writel((u32)secs, pdata->csr_base + RTC_CLR);
62 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */ 62 readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
63 63
64 return 0; 64 return 0;
@@ -106,7 +106,7 @@ static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
106 106
107 rtc_tm_to_time(&alrm->time, &alarm_time); 107 rtc_tm_to_time(&alrm->time, &alarm_time);
108 pdata->alarm_time = alarm_time; 108 pdata->alarm_time = alarm_time;
109 writel((u32) pdata->alarm_time, pdata->csr_base + RTC_CMR); 109 writel((u32)pdata->alarm_time, pdata->csr_base + RTC_CMR);
110 110
111 xgene_rtc_alarm_irq_enable(dev, alrm->enabled); 111 xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
112 112
@@ -123,7 +123,7 @@ static const struct rtc_class_ops xgene_rtc_ops = {
123 123
124static irqreturn_t xgene_rtc_interrupt(int irq, void *id) 124static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
125{ 125{
126 struct xgene_rtc_dev *pdata = (struct xgene_rtc_dev *) id; 126 struct xgene_rtc_dev *pdata = id;
127 127
128 /* Check if interrupt asserted */ 128 /* Check if interrupt asserted */
129 if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT)) 129 if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))