xtensa: add missing isync to the cpu_reset TLB code

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 5cb8a62e091c..7c3106093c75 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -511,6 +511,7 @@ void cpu_reset(void)
                                       "add      %2, %2, %7\n\t"
                                       "addi     %0, %0, -1\n\t"
                                       "bnez     %0, 1b\n\t"
+                                      "isync\n\t"
                                       /* Jump to identity mapping */
                                       "jx       %3\n"
                                       "2:\n\t"