diff options
author | Len Brown <len.brown@intel.com> | 2019-08-31 14:09:29 -0400 |
---|---|---|
committer | Len Brown <len.brown@intel.com> | 2019-08-31 14:48:39 -0400 |
commit | cd188af5282d9f9e65f63915b13239bafc746f8d (patch) | |
tree | e789d66ee8fe0acf8d11217f7c0fd1a17d248edf | |
parent | b62b3184576b8f87ca655dd9bfd1ae02fd4e50a5 (diff) |
tools/power turbostat: Fix Haswell Core systems
turbostat: cpu0: msr offset 0x630 read failed: Input/output error
because Haswell Core does not have C8-C10.
Output C8-C10 only on Haswell ULT.
Fixes: f5a4c76ad7de ("tools/power turbostat: consolidate duplicate model numbers")
Reported-by: Prarit Bhargava <prarit@redhat.com>
Suggested-by: Kosuke Tatsukawa <tatsu@ab.jp.nec.com>
Signed-off-by: Len Brown <len.brown@intel.com>
-rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 35f4366a522e..78e7c94b94bf 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c | |||
@@ -3217,6 +3217,7 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) | |||
3217 | break; | 3217 | break; |
3218 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | 3218 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
3219 | case INTEL_FAM6_HASWELL_X: /* HSX */ | 3219 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
3220 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | ||
3220 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | 3221 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ |
3221 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | 3222 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ |
3222 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | 3223 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ |
@@ -3413,6 +3414,7 @@ int has_config_tdp(unsigned int family, unsigned int model) | |||
3413 | case INTEL_FAM6_IVYBRIDGE: /* IVB */ | 3414 | case INTEL_FAM6_IVYBRIDGE: /* IVB */ |
3414 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | 3415 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
3415 | case INTEL_FAM6_HASWELL_X: /* HSX */ | 3416 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
3417 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | ||
3416 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | 3418 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ |
3417 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | 3419 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ |
3418 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | 3420 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ |
@@ -3849,6 +3851,7 @@ void rapl_probe_intel(unsigned int family, unsigned int model) | |||
3849 | case INTEL_FAM6_SANDYBRIDGE: | 3851 | case INTEL_FAM6_SANDYBRIDGE: |
3850 | case INTEL_FAM6_IVYBRIDGE: | 3852 | case INTEL_FAM6_IVYBRIDGE: |
3851 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | 3853 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
3854 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | ||
3852 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | 3855 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ |
3853 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | 3856 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ |
3854 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | 3857 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ |
@@ -4040,6 +4043,7 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model) | |||
4040 | 4043 | ||
4041 | switch (model) { | 4044 | switch (model) { |
4042 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | 4045 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
4046 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | ||
4043 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | 4047 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ |
4044 | do_gfx_perf_limit_reasons = 1; | 4048 | do_gfx_perf_limit_reasons = 1; |
4045 | case INTEL_FAM6_HASWELL_X: /* HSX */ | 4049 | case INTEL_FAM6_HASWELL_X: /* HSX */ |
@@ -4259,6 +4263,7 @@ int has_snb_msrs(unsigned int family, unsigned int model) | |||
4259 | case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ | 4263 | case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ |
4260 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ | 4264 | case INTEL_FAM6_HASWELL_CORE: /* HSW */ |
4261 | case INTEL_FAM6_HASWELL_X: /* HSW */ | 4265 | case INTEL_FAM6_HASWELL_X: /* HSW */ |
4266 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ | ||
4262 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ | 4267 | case INTEL_FAM6_HASWELL_GT3E: /* HSW */ |
4263 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | 4268 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ |
4264 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ | 4269 | case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ |
@@ -4292,7 +4297,7 @@ int has_hsw_msrs(unsigned int family, unsigned int model) | |||
4292 | return 0; | 4297 | return 0; |
4293 | 4298 | ||
4294 | switch (model) { | 4299 | switch (model) { |
4295 | case INTEL_FAM6_HASWELL_CORE: | 4300 | case INTEL_FAM6_HASWELL_ULT: /* HSW */ |
4296 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ | 4301 | case INTEL_FAM6_BROADWELL_CORE: /* BDW */ |
4297 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ | 4302 | case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ |
4298 | case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ | 4303 | case INTEL_FAM6_CANNONLAKE_MOBILE: /* CNL */ |
@@ -4576,9 +4581,6 @@ unsigned int intel_model_duplicates(unsigned int model) | |||
4576 | case INTEL_FAM6_XEON_PHI_KNM: | 4581 | case INTEL_FAM6_XEON_PHI_KNM: |
4577 | return INTEL_FAM6_XEON_PHI_KNL; | 4582 | return INTEL_FAM6_XEON_PHI_KNL; |
4578 | 4583 | ||
4579 | case INTEL_FAM6_HASWELL_ULT: | ||
4580 | return INTEL_FAM6_HASWELL_CORE; | ||
4581 | |||
4582 | case INTEL_FAM6_BROADWELL_X: | 4584 | case INTEL_FAM6_BROADWELL_X: |
4583 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ | 4585 | case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ |
4584 | return INTEL_FAM6_BROADWELL_X; | 4586 | return INTEL_FAM6_BROADWELL_X; |