diff options
| author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-08-22 10:06:32 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-08-26 13:08:50 -0400 |
| commit | cce8ccca80d8388982133192d0a6d9dc2e8ed712 (patch) | |
| tree | 4e37956f86eba2c619fe2a4d56af0b5c993411ae | |
| parent | 093347abc7a4e0490e3c962ecbde2dc272a8f708 (diff) | |
media: use the BIT() macro
As warned by cppcheck:
[drivers/media/dvb-frontends/cx24123.c:434]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
[drivers/media/pci/bt8xx/bttv-input.c:87]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
[drivers/media/pci/bt8xx/bttv-input.c:98]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
...
[drivers/media/v4l2-core/v4l2-ioctl.c:1391]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
There are lots of places where we're doing 1 << 31. That's bad,
as, depending on the architecture, this has an undefined behavior.
The BIT() macro is already prepared to handle this, so, let's
just switch all "1 << number" macros by BIT(number) at the header files
with has 1 << 31.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> # exynos4-is and s3c-camif
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # omap3isp, vsp1, xilinx, wl128x and ipu3
Reviewed-by: Benoit Parrot <bparrot@ti.com> # am437x and ti-vpe
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
| -rw-r--r-- | drivers/media/pci/cobalt/cobalt-driver.h | 63 | ||||
| -rw-r--r-- | drivers/media/pci/ivtv/ivtv-irq.h | 28 | ||||
| -rw-r--r-- | drivers/media/pci/mantis/mantis_reg.h | 152 | ||||
| -rw-r--r-- | drivers/media/pci/solo6x10/solo6x10-regs.h | 286 | ||||
| -rw-r--r-- | drivers/media/platform/am437x/am437x-vpfe_regs.h | 26 | ||||
| -rw-r--r-- | drivers/media/platform/davinci/dm644x_ccdc_regs.h | 20 | ||||
| -rw-r--r-- | drivers/media/platform/exynos4-is/fimc-lite-reg.h | 80 | ||||
| -rw-r--r-- | drivers/media/platform/exynos4-is/fimc-reg.h | 138 | ||||
| -rw-r--r-- | drivers/media/platform/omap3isp/ispreg.h | 584 | ||||
| -rw-r--r-- | drivers/media/platform/s3c-camif/camif-regs.h | 118 | ||||
| -rw-r--r-- | drivers/media/platform/tegra-cec/tegra_cec.h | 82 | ||||
| -rw-r--r-- | drivers/media/platform/ti-vpe/vpe_regs.h | 94 | ||||
| -rw-r--r-- | drivers/media/platform/vsp1/vsp1_regs.h | 224 | ||||
| -rw-r--r-- | drivers/media/platform/xilinx/xilinx-vip.h | 29 | ||||
| -rw-r--r-- | drivers/media/radio/wl128x/fmdrv_common.h | 88 | ||||
| -rw-r--r-- | drivers/staging/media/ipu3/ipu3-tables.h | 4 |
16 files changed, 1014 insertions, 1002 deletions
diff --git a/drivers/media/pci/cobalt/cobalt-driver.h b/drivers/media/pci/cobalt/cobalt-driver.h index 429bee4ef79c..bca68572b324 100644 --- a/drivers/media/pci/cobalt/cobalt-driver.h +++ b/drivers/media/pci/cobalt/cobalt-driver.h | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #ifndef COBALT_DRIVER_H | 11 | #ifndef COBALT_DRIVER_H |
| 12 | #define COBALT_DRIVER_H | 12 | #define COBALT_DRIVER_H |
| 13 | 13 | ||
| 14 | #include <linux/bitops.h> | ||
| 14 | #include <linux/module.h> | 15 | #include <linux/module.h> |
| 15 | #include <linux/pci.h> | 16 | #include <linux/pci.h> |
| 16 | #include <linux/spinlock.h> | 17 | #include <linux/spinlock.h> |
| @@ -61,37 +62,37 @@ | |||
| 61 | #define COBALT_CLK 50000000 | 62 | #define COBALT_CLK 50000000 |
| 62 | 63 | ||
| 63 | /* System status register */ | 64 | /* System status register */ |
| 64 | #define COBALT_SYSSTAT_DIP0_MSK (1 << 0) | 65 | #define COBALT_SYSSTAT_DIP0_MSK BIT(0) |
| 65 | #define COBALT_SYSSTAT_DIP1_MSK (1 << 1) | 66 | #define COBALT_SYSSTAT_DIP1_MSK BIT(1) |
| 66 | #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK (1 << 2) | 67 | #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK BIT(2) |
| 67 | #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK (1 << 3) | 68 | #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK BIT(3) |
| 68 | #define COBALT_SYSSTAT_VI0_5V_MSK (1 << 4) | 69 | #define COBALT_SYSSTAT_VI0_5V_MSK BIT(4) |
| 69 | #define COBALT_SYSSTAT_VI0_INT1_MSK (1 << 5) | 70 | #define COBALT_SYSSTAT_VI0_INT1_MSK BIT(5) |
| 70 | #define COBALT_SYSSTAT_VI0_INT2_MSK (1 << 6) | 71 | #define COBALT_SYSSTAT_VI0_INT2_MSK BIT(6) |
| 71 | #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK (1 << 7) | 72 | #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK BIT(7) |
| 72 | #define COBALT_SYSSTAT_VI1_5V_MSK (1 << 8) | 73 | #define COBALT_SYSSTAT_VI1_5V_MSK BIT(8) |
| 73 | #define COBALT_SYSSTAT_VI1_INT1_MSK (1 << 9) | 74 | #define COBALT_SYSSTAT_VI1_INT1_MSK BIT(9) |
| 74 | #define COBALT_SYSSTAT_VI1_INT2_MSK (1 << 10) | 75 | #define COBALT_SYSSTAT_VI1_INT2_MSK BIT(10) |
| 75 | #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK (1 << 11) | 76 | #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK BIT(11) |
| 76 | #define COBALT_SYSSTAT_VI2_5V_MSK (1 << 12) | 77 | #define COBALT_SYSSTAT_VI2_5V_MSK BIT(12) |
| 77 | #define COBALT_SYSSTAT_VI2_INT1_MSK (1 << 13) | 78 | #define COBALT_SYSSTAT_VI2_INT1_MSK BIT(13) |
| 78 | #define COBALT_SYSSTAT_VI2_INT2_MSK (1 << 14) | 79 | #define COBALT_SYSSTAT_VI2_INT2_MSK BIT(14) |
| 79 | #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK (1 << 15) | 80 | #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK BIT(15) |
| 80 | #define COBALT_SYSSTAT_VI3_5V_MSK (1 << 16) | 81 | #define COBALT_SYSSTAT_VI3_5V_MSK BIT(16) |
| 81 | #define COBALT_SYSSTAT_VI3_INT1_MSK (1 << 17) | 82 | #define COBALT_SYSSTAT_VI3_INT1_MSK BIT(17) |
| 82 | #define COBALT_SYSSTAT_VI3_INT2_MSK (1 << 18) | 83 | #define COBALT_SYSSTAT_VI3_INT2_MSK BIT(18) |
| 83 | #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK (1 << 19) | 84 | #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK BIT(19) |
| 84 | #define COBALT_SYSSTAT_VIHSMA_5V_MSK (1 << 20) | 85 | #define COBALT_SYSSTAT_VIHSMA_5V_MSK BIT(20) |
| 85 | #define COBALT_SYSSTAT_VIHSMA_INT1_MSK (1 << 21) | 86 | #define COBALT_SYSSTAT_VIHSMA_INT1_MSK BIT(21) |
| 86 | #define COBALT_SYSSTAT_VIHSMA_INT2_MSK (1 << 22) | 87 | #define COBALT_SYSSTAT_VIHSMA_INT2_MSK BIT(22) |
| 87 | #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK (1 << 23) | 88 | #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23) |
| 88 | #define COBALT_SYSSTAT_VOHSMA_INT1_MSK (1 << 24) | 89 | #define COBALT_SYSSTAT_VOHSMA_INT1_MSK BIT(24) |
| 89 | #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK (1 << 25) | 90 | #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK BIT(25) |
| 90 | #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK (1 << 26) | 91 | #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26) |
| 91 | #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK (1 << 28) | 92 | #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK BIT(28) |
| 92 | #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK (1 << 29) | 93 | #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29) |
| 93 | #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK (1 << 30) | 94 | #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK BIT(30) |
| 94 | #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK (1 << 31) | 95 | #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK BIT(31) |
| 95 | 96 | ||
| 96 | /* Cobalt memory map */ | 97 | /* Cobalt memory map */ |
| 97 | #define COBALT_I2C_0_BASE 0x0 | 98 | #define COBALT_I2C_0_BASE 0x0 |
diff --git a/drivers/media/pci/ivtv/ivtv-irq.h b/drivers/media/pci/ivtv/ivtv-irq.h index 7d2f45e2b83c..b8b0703a1c82 100644 --- a/drivers/media/pci/ivtv/ivtv-irq.h +++ b/drivers/media/pci/ivtv/ivtv-irq.h | |||
| @@ -10,20 +10,20 @@ | |||
| 10 | #ifndef IVTV_IRQ_H | 10 | #ifndef IVTV_IRQ_H |
| 11 | #define IVTV_IRQ_H | 11 | #define IVTV_IRQ_H |
| 12 | 12 | ||
| 13 | #define IVTV_IRQ_ENC_START_CAP (0x1 << 31) | 13 | #define IVTV_IRQ_ENC_START_CAP BIT(31) |
| 14 | #define IVTV_IRQ_ENC_EOS (0x1 << 30) | 14 | #define IVTV_IRQ_ENC_EOS BIT(30) |
| 15 | #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) | 15 | #define IVTV_IRQ_ENC_VBI_CAP BIT(29) |
| 16 | #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) | 16 | #define IVTV_IRQ_ENC_VIM_RST BIT(28) |
| 17 | #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) | 17 | #define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27) |
| 18 | #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) | 18 | #define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25) |
| 19 | #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) | 19 | #define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24) |
| 20 | #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) | 20 | #define IVTV_IRQ_DEC_DATA_REQ BIT(22) |
| 21 | #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) | 21 | #define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20) |
| 22 | #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) | 22 | #define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19) |
| 23 | #define IVTV_IRQ_DMA_ERR (0x1 << 18) | 23 | #define IVTV_IRQ_DMA_ERR BIT(18) |
| 24 | #define IVTV_IRQ_DMA_WRITE (0x1 << 17) | 24 | #define IVTV_IRQ_DMA_WRITE BIT(17) |
| 25 | #define IVTV_IRQ_DMA_READ (0x1 << 16) | 25 | #define IVTV_IRQ_DMA_READ BIT(16) |
| 26 | #define IVTV_IRQ_DEC_VSYNC (0x1 << 10) | 26 | #define IVTV_IRQ_DEC_VSYNC BIT(10) |
| 27 | 27 | ||
| 28 | /* IRQ Masks */ | 28 | /* IRQ Masks */ |
| 29 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ | 29 | #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ |
diff --git a/drivers/media/pci/mantis/mantis_reg.h b/drivers/media/pci/mantis/mantis_reg.h index 67a80e42b5c7..a1e66ef6ac2f 100644 --- a/drivers/media/pci/mantis/mantis_reg.h +++ b/drivers/media/pci/mantis/mantis_reg.h | |||
| @@ -14,44 +14,44 @@ | |||
| 14 | #define MANTIS_INT_MASK 0x04 | 14 | #define MANTIS_INT_MASK 0x04 |
| 15 | 15 | ||
| 16 | #define MANTIS_INT_RISCSTAT (0x0f << 28) | 16 | #define MANTIS_INT_RISCSTAT (0x0f << 28) |
| 17 | #define MANTIS_INT_RISCEN (0x01 << 27) | 17 | #define MANTIS_INT_RISCEN BIT(27) |
| 18 | #define MANTIS_INT_I2CRACK (0x01 << 26) | 18 | #define MANTIS_INT_I2CRACK BIT(26) |
| 19 | 19 | ||
| 20 | /* #define MANTIS_INT_GPIF (0xff << 12) */ | 20 | /* #define MANTIS_INT_GPIF (0xff << 12) */ |
| 21 | 21 | ||
| 22 | #define MANTIS_INT_PCMCIA7 (0x01 << 19) | 22 | #define MANTIS_INT_PCMCIA7 BIT(19) |
| 23 | #define MANTIS_INT_PCMCIA6 (0x01 << 18) | 23 | #define MANTIS_INT_PCMCIA6 BIT(18) |
| 24 | #define MANTIS_INT_PCMCIA5 (0x01 << 17) | 24 | #define MANTIS_INT_PCMCIA5 BIT(17) |
| 25 | #define MANTIS_INT_PCMCIA4 (0x01 << 16) | 25 | #define MANTIS_INT_PCMCIA4 BIT(16) |
| 26 | #define MANTIS_INT_PCMCIA3 (0x01 << 15) | 26 | #define MANTIS_INT_PCMCIA3 BIT(15) |
| 27 | #define MANTIS_INT_PCMCIA2 (0x01 << 14) | 27 | #define MANTIS_INT_PCMCIA2 BIT(14) |
| 28 | #define MANTIS_INT_PCMCIA1 (0x01 << 13) | 28 | #define MANTIS_INT_PCMCIA1 BIT(13) |
| 29 | #define MANTIS_INT_PCMCIA0 (0x01 << 12) | 29 | #define MANTIS_INT_PCMCIA0 BIT(12) |
| 30 | #define MANTIS_INT_IRQ1 (0x01 << 11) | 30 | #define MANTIS_INT_IRQ1 BIT(11) |
| 31 | #define MANTIS_INT_IRQ0 (0x01 << 10) | 31 | #define MANTIS_INT_IRQ0 BIT(10) |
| 32 | #define MANTIS_INT_OCERR (0x01 << 8) | 32 | #define MANTIS_INT_OCERR BIT(8) |
| 33 | #define MANTIS_INT_PABORT (0x01 << 7) | 33 | #define MANTIS_INT_PABORT BIT(7) |
| 34 | #define MANTIS_INT_RIPERR (0x01 << 6) | 34 | #define MANTIS_INT_RIPERR BIT(6) |
| 35 | #define MANTIS_INT_PPERR (0x01 << 5) | 35 | #define MANTIS_INT_PPERR BIT(5) |
| 36 | #define MANTIS_INT_FTRGT (0x01 << 3) | 36 | #define MANTIS_INT_FTRGT BIT(3) |
| 37 | #define MANTIS_INT_RISCI (0x01 << 1) | 37 | #define MANTIS_INT_RISCI BIT(1) |
| 38 | #define MANTIS_INT_I2CDONE (0x01 << 0) | 38 | #define MANTIS_INT_I2CDONE BIT(0) |
| 39 | 39 | ||
| 40 | /* DMA */ | 40 | /* DMA */ |
| 41 | #define MANTIS_DMA_CTL 0x08 | 41 | #define MANTIS_DMA_CTL 0x08 |
| 42 | #define MANTIS_GPIF_RD (0xff << 24) | 42 | #define MANTIS_GPIF_RD (0xff << 24) |
| 43 | #define MANTIS_GPIF_WR (0xff << 16) | 43 | #define MANTIS_GPIF_WR (0xff << 16) |
| 44 | #define MANTIS_CPU_DO (0x01 << 10) | 44 | #define MANTIS_CPU_DO BIT(10) |
| 45 | #define MANTIS_DRV_DO (0x01 << 9) | 45 | #define MANTIS_DRV_DO BIT(9) |
| 46 | #define MANTIS_I2C_RD (0x01 << 7) | 46 | #define MANTIS_I2C_RD BIT(7) |
| 47 | #define MANTIS_I2C_WR (0x01 << 6) | 47 | #define MANTIS_I2C_WR BIT(6) |
| 48 | #define MANTIS_DCAP_MODE (0x01 << 5) | 48 | #define MANTIS_DCAP_MODE BIT(5) |
| 49 | #define MANTIS_FIFO_TP_4 (0x00 << 3) | 49 | #define MANTIS_FIFO_TP_4 (0x00 << 3) |
| 50 | #define MANTIS_FIFO_TP_8 (0x01 << 3) | 50 | #define MANTIS_FIFO_TP_8 (0x01 << 3) |
| 51 | #define MANTIS_FIFO_TP_16 (0x02 << 3) | 51 | #define MANTIS_FIFO_TP_16 (0x02 << 3) |
| 52 | #define MANTIS_FIFO_EN (0x01 << 2) | 52 | #define MANTIS_FIFO_EN BIT(2) |
| 53 | #define MANTIS_DCAP_EN (0x01 << 1) | 53 | #define MANTIS_DCAP_EN BIT(1) |
| 54 | #define MANTIS_RISC_EN (0x01 << 0) | 54 | #define MANTIS_RISC_EN BIT(0) |
| 55 | 55 | ||
| 56 | /* DEBUG */ | 56 | /* DEBUG */ |
| 57 | #define MANTIS_DEBUGREG 0x0c | 57 | #define MANTIS_DEBUGREG 0x0c |
| @@ -68,8 +68,8 @@ | |||
| 68 | #define MANTIS_I2C_RATE_2 (0x01 << 6) | 68 | #define MANTIS_I2C_RATE_2 (0x01 << 6) |
| 69 | #define MANTIS_I2C_RATE_3 (0x02 << 6) | 69 | #define MANTIS_I2C_RATE_3 (0x02 << 6) |
| 70 | #define MANTIS_I2C_RATE_4 (0x03 << 6) | 70 | #define MANTIS_I2C_RATE_4 (0x03 << 6) |
| 71 | #define MANTIS_I2C_STOP (0x01 << 5) | 71 | #define MANTIS_I2C_STOP BIT(5) |
| 72 | #define MANTIS_I2C_PGMODE (0x01 << 3) | 72 | #define MANTIS_I2C_PGMODE BIT(3) |
| 73 | 73 | ||
| 74 | /* DATA */ | 74 | /* DATA */ |
| 75 | #define MANTIS_CMD_DATA_R1 0x20 | 75 | #define MANTIS_CMD_DATA_R1 0x20 |
| @@ -85,77 +85,77 @@ | |||
| 85 | #define MANTIS_CMD_DATA_4 (0xff << 0) | 85 | #define MANTIS_CMD_DATA_4 (0xff << 0) |
| 86 | 86 | ||
| 87 | #define MANTIS_CONTROL 0x28 | 87 | #define MANTIS_CONTROL 0x28 |
| 88 | #define MANTIS_DET (0x01 << 7) | 88 | #define MANTIS_DET BIT(7) |
| 89 | #define MANTIS_DAT_CF_EN (0x01 << 6) | 89 | #define MANTIS_DAT_CF_EN BIT(6) |
| 90 | #define MANTIS_ACS (0x03 << 4) | 90 | #define MANTIS_ACS (0x03 << 4) |
| 91 | #define MANTIS_VCCEN (0x01 << 3) | 91 | #define MANTIS_VCCEN BIT(3) |
| 92 | #define MANTIS_BYPASS (0x01 << 2) | 92 | #define MANTIS_BYPASS BIT(2) |
| 93 | #define MANTIS_MRST (0x01 << 1) | 93 | #define MANTIS_MRST BIT(1) |
| 94 | #define MANTIS_CRST_INT (0x01 << 0) | 94 | #define MANTIS_CRST_INT BIT(0) |
| 95 | 95 | ||
| 96 | #define MANTIS_GPIF_CFGSLA 0x84 | 96 | #define MANTIS_GPIF_CFGSLA 0x84 |
| 97 | #define MANTIS_GPIF_WAITSMPL (0x07 << 28) | 97 | #define MANTIS_GPIF_WAITSMPL (0x07 << 28) |
| 98 | #define MANTIS_GPIF_BYTEADDRSUB (0x01 << 25) | 98 | #define MANTIS_GPIF_BYTEADDRSUB BIT(25) |
| 99 | #define MANTIS_GPIF_WAITPOL (0x01 << 24) | 99 | #define MANTIS_GPIF_WAITPOL BIT(24) |
| 100 | #define MANTIS_GPIF_NCDELAY (0x07 << 20) | 100 | #define MANTIS_GPIF_NCDELAY (0x07 << 20) |
| 101 | #define MANTIS_GPIF_RW2CSDELAY (0x07 << 16) | 101 | #define MANTIS_GPIF_RW2CSDELAY (0x07 << 16) |
| 102 | #define MANTIS_GPIF_SLFTIMEDMODE (0x01 << 15) | 102 | #define MANTIS_GPIF_SLFTIMEDMODE BIT(15) |
| 103 | #define MANTIS_GPIF_SLFTIMEDDELY (0x7f << 8) | 103 | #define MANTIS_GPIF_SLFTIMEDDELY (0x7f << 8) |
| 104 | #define MANTIS_GPIF_DEVTYPE (0x07 << 4) | 104 | #define MANTIS_GPIF_DEVTYPE (0x07 << 4) |
| 105 | #define MANTIS_GPIF_BIGENDIAN (0x01 << 3) | 105 | #define MANTIS_GPIF_BIGENDIAN BIT(3) |
| 106 | #define MANTIS_GPIF_FETCHCMD (0x03 << 1) | 106 | #define MANTIS_GPIF_FETCHCMD (0x03 << 1) |
| 107 | #define MANTIS_GPIF_HWORDDEV (0x01 << 0) | 107 | #define MANTIS_GPIF_HWORDDEV BIT(0) |
| 108 | 108 | ||
| 109 | #define MANTIS_GPIF_WSTOPER 0x90 | 109 | #define MANTIS_GPIF_WSTOPER 0x90 |
| 110 | #define MANTIS_GPIF_WSTOPERWREN3 (0x01 << 31) | 110 | #define MANTIS_GPIF_WSTOPERWREN3 BIT(31) |
| 111 | #define MANTIS_GPIF_PARBOOTN (0x01 << 29) | 111 | #define MANTIS_GPIF_PARBOOTN BIT(29) |
| 112 | #define MANTIS_GPIF_WSTOPERSLID3 (0x1f << 24) | 112 | #define MANTIS_GPIF_WSTOPERSLID3 (0x1f << 24) |
| 113 | #define MANTIS_GPIF_WSTOPERWREN2 (0x01 << 23) | 113 | #define MANTIS_GPIF_WSTOPERWREN2 BIT(23) |
| 114 | #define MANTIS_GPIF_WSTOPERSLID2 (0x1f << 16) | 114 | #define MANTIS_GPIF_WSTOPERSLID2 (0x1f << 16) |
| 115 | #define MANTIS_GPIF_WSTOPERWREN1 (0x01 << 15) | 115 | #define MANTIS_GPIF_WSTOPERWREN1 BIT(15) |
| 116 | #define MANTIS_GPIF_WSTOPERSLID1 (0x1f << 8) | 116 | #define MANTIS_GPIF_WSTOPERSLID1 (0x1f << 8) |
| 117 | #define MANTIS_GPIF_WSTOPERWREN0 (0x01 << 7) | 117 | #define MANTIS_GPIF_WSTOPERWREN0 BIT(7) |
| 118 | #define MANTIS_GPIF_WSTOPERSLID0 (0x1f << 0) | 118 | #define MANTIS_GPIF_WSTOPERSLID0 (0x1f << 0) |
| 119 | 119 | ||
| 120 | #define MANTIS_GPIF_CS2RW 0x94 | 120 | #define MANTIS_GPIF_CS2RW 0x94 |
| 121 | #define MANTIS_GPIF_CS2RWWREN3 (0x01 << 31) | 121 | #define MANTIS_GPIF_CS2RWWREN3 BIT(31) |
| 122 | #define MANTIS_GPIF_CS2RWDELY3 (0x3f << 24) | 122 | #define MANTIS_GPIF_CS2RWDELY3 (0x3f << 24) |
| 123 | #define MANTIS_GPIF_CS2RWWREN2 (0x01 << 23) | 123 | #define MANTIS_GPIF_CS2RWWREN2 BIT(23) |
| 124 | #define MANTIS_GPIF_CS2RWDELY2 (0x3f << 16) | 124 | #define MANTIS_GPIF_CS2RWDELY2 (0x3f << 16) |
| 125 | #define MANTIS_GPIF_CS2RWWREN1 (0x01 << 15) | 125 | #define MANTIS_GPIF_CS2RWWREN1 BIT(15) |
| 126 | #define MANTIS_GPIF_CS2RWDELY1 (0x3f << 8) | 126 | #define MANTIS_GPIF_CS2RWDELY1 (0x3f << 8) |
| 127 | #define MANTIS_GPIF_CS2RWWREN0 (0x01 << 7) | 127 | #define MANTIS_GPIF_CS2RWWREN0 BIT(7) |
| 128 | #define MANTIS_GPIF_CS2RWDELY0 (0x3f << 0) | 128 | #define MANTIS_GPIF_CS2RWDELY0 (0x3f << 0) |
| 129 | 129 | ||
| 130 | #define MANTIS_GPIF_IRQCFG 0x98 | 130 | #define MANTIS_GPIF_IRQCFG 0x98 |
| 131 | #define MANTIS_GPIF_IRQPOL (0x01 << 8) | 131 | #define MANTIS_GPIF_IRQPOL BIT(8) |
| 132 | #define MANTIS_MASK_WRACK (0x01 << 7) | 132 | #define MANTIS_MASK_WRACK BIT(7) |
| 133 | #define MANTIS_MASK_BRRDY (0x01 << 6) | 133 | #define MANTIS_MASK_BRRDY BIT(6) |
| 134 | #define MANTIS_MASK_OVFLW (0x01 << 5) | 134 | #define MANTIS_MASK_OVFLW BIT(5) |
| 135 | #define MANTIS_MASK_OTHERR (0x01 << 4) | 135 | #define MANTIS_MASK_OTHERR BIT(4) |
| 136 | #define MANTIS_MASK_WSTO (0x01 << 3) | 136 | #define MANTIS_MASK_WSTO BIT(3) |
| 137 | #define MANTIS_MASK_EXTIRQ (0x01 << 2) | 137 | #define MANTIS_MASK_EXTIRQ BIT(2) |
| 138 | #define MANTIS_MASK_PLUGIN (0x01 << 1) | 138 | #define MANTIS_MASK_PLUGIN BIT(1) |
| 139 | #define MANTIS_MASK_PLUGOUT (0x01 << 0) | 139 | #define MANTIS_MASK_PLUGOUT BIT(0) |
| 140 | 140 | ||
| 141 | #define MANTIS_GPIF_STATUS 0x9c | 141 | #define MANTIS_GPIF_STATUS 0x9c |
| 142 | #define MANTIS_SBUF_KILLOP (0x01 << 15) | 142 | #define MANTIS_SBUF_KILLOP BIT(15) |
| 143 | #define MANTIS_SBUF_OPDONE (0x01 << 14) | 143 | #define MANTIS_SBUF_OPDONE BIT(14) |
| 144 | #define MANTIS_SBUF_EMPTY (0x01 << 13) | 144 | #define MANTIS_SBUF_EMPTY BIT(13) |
| 145 | #define MANTIS_GPIF_DETSTAT (0x01 << 9) | 145 | #define MANTIS_GPIF_DETSTAT BIT(9) |
| 146 | #define MANTIS_GPIF_INTSTAT (0x01 << 8) | 146 | #define MANTIS_GPIF_INTSTAT BIT(8) |
| 147 | #define MANTIS_GPIF_WRACK (0x01 << 7) | 147 | #define MANTIS_GPIF_WRACK BIT(7) |
| 148 | #define MANTIS_GPIF_BRRDY (0x01 << 6) | 148 | #define MANTIS_GPIF_BRRDY BIT(6) |
| 149 | #define MANTIS_SBUF_OVFLW (0x01 << 5) | 149 | #define MANTIS_SBUF_OVFLW BIT(5) |
| 150 | #define MANTIS_GPIF_OTHERR (0x01 << 4) | 150 | #define MANTIS_GPIF_OTHERR BIT(4) |
| 151 | #define MANTIS_SBUF_WSTO (0x01 << 3) | 151 | #define MANTIS_SBUF_WSTO BIT(3) |
| 152 | #define MANTIS_GPIF_EXTIRQ (0x01 << 2) | 152 | #define MANTIS_GPIF_EXTIRQ BIT(2) |
| 153 | #define MANTIS_CARD_PLUGIN (0x01 << 1) | 153 | #define MANTIS_CARD_PLUGIN BIT(1) |
| 154 | #define MANTIS_CARD_PLUGOUT (0x01 << 0) | 154 | #define MANTIS_CARD_PLUGOUT BIT(0) |
| 155 | 155 | ||
| 156 | #define MANTIS_GPIF_BRADDR 0xa0 | 156 | #define MANTIS_GPIF_BRADDR 0xa0 |
| 157 | #define MANTIS_GPIF_PCMCIAREG (0x01 << 27) | 157 | #define MANTIS_GPIF_PCMCIAREG BIT(27) |
| 158 | #define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) | 158 | #define MANTIS_GPIF_PCMCIAIOM BIT(26) |
| 159 | #define MANTIS_GPIF_BR_ADDR (0xfffffff << 0) | 159 | #define MANTIS_GPIF_BR_ADDR (0xfffffff << 0) |
| 160 | 160 | ||
| 161 | #define MANTIS_GPIF_BRBYTES 0xa4 | 161 | #define MANTIS_GPIF_BRBYTES 0xa4 |
| @@ -167,9 +167,9 @@ | |||
| 167 | #define MANTIS_CARD_RESET 0xac | 167 | #define MANTIS_CARD_RESET 0xac |
| 168 | 168 | ||
| 169 | #define MANTIS_GPIF_ADDR 0xb0 | 169 | #define MANTIS_GPIF_ADDR 0xb0 |
| 170 | #define MANTIS_GPIF_HIFRDWRN (0x01 << 31) | 170 | #define MANTIS_GPIF_HIFRDWRN BIT(31) |
| 171 | #define MANTIS_GPIF_PCMCIAREG (0x01 << 27) | 171 | #define MANTIS_GPIF_PCMCIAREG BIT(27) |
| 172 | #define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) | 172 | #define MANTIS_GPIF_PCMCIAIOM BIT(26) |
| 173 | #define MANTIS_GPIF_HIFADDR (0xfffffff << 0) | 173 | #define MANTIS_GPIF_HIFADDR (0xfffffff << 0) |
| 174 | 174 | ||
| 175 | #define MANTIS_GPIF_DOUT 0xb4 | 175 | #define MANTIS_GPIF_DOUT 0xb4 |
diff --git a/drivers/media/pci/solo6x10/solo6x10-regs.h b/drivers/media/pci/solo6x10/solo6x10-regs.h index d88cc02d01d3..804505d01b25 100644 --- a/drivers/media/pci/solo6x10/solo6x10-regs.h +++ b/drivers/media/pci/solo6x10/solo6x10-regs.h | |||
| @@ -12,6 +12,8 @@ | |||
| 12 | #ifndef __SOLO6X10_REGISTERS_H | 12 | #ifndef __SOLO6X10_REGISTERS_H |
| 13 | #define __SOLO6X10_REGISTERS_H | 13 | #define __SOLO6X10_REGISTERS_H |
| 14 | 14 | ||
| 15 | #include <linux/bitops.h> | ||
| 16 | |||
| 15 | #include "solo6x10-offsets.h" | 17 | #include "solo6x10-offsets.h" |
| 16 | 18 | ||
| 17 | /* Global 6010 system configuration */ | 19 | /* Global 6010 system configuration */ |
| @@ -32,17 +34,17 @@ | |||
| 32 | #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) | 34 | #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) |
| 33 | /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ | 35 | /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */ |
| 34 | #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) | 36 | #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) |
| 35 | #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT (1<<5) | 37 | #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT BIT(5) |
| 36 | #define SOLO_DMA_CTRL_STROBE_SELECT (1<<4) | 38 | #define SOLO_DMA_CTRL_STROBE_SELECT BIT(4) |
| 37 | #define SOLO_DMA_CTRL_READ_DATA_SELECT (1<<3) | 39 | #define SOLO_DMA_CTRL_READ_DATA_SELECT BIT(3) |
| 38 | #define SOLO_DMA_CTRL_READ_CLK_SELECT (1<<2) | 40 | #define SOLO_DMA_CTRL_READ_CLK_SELECT BIT(2) |
| 39 | #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) | 41 | #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) |
| 40 | 42 | ||
| 41 | /* Some things we set in this are undocumented. Why Softlogic?!?! */ | 43 | /* Some things we set in this are undocumented. Why Softlogic?!?! */ |
| 42 | #define SOLO_DMA_CTRL1 0x0008 | 44 | #define SOLO_DMA_CTRL1 0x0008 |
| 43 | 45 | ||
| 44 | #define SOLO_SYS_VCLK 0x000C | 46 | #define SOLO_SYS_VCLK 0x000C |
| 45 | #define SOLO_VCLK_INVERT (1<<22) | 47 | #define SOLO_VCLK_INVERT BIT(22) |
| 46 | /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ | 48 | /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */ |
| 47 | #define SOLO_VCLK_SELECT(n) ((n)<<20) | 49 | #define SOLO_VCLK_SELECT(n) ((n)<<20) |
| 48 | #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) | 50 | #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) |
| @@ -56,22 +58,22 @@ | |||
| 56 | 58 | ||
| 57 | #define SOLO_IRQ_STAT 0x0010 | 59 | #define SOLO_IRQ_STAT 0x0010 |
| 58 | #define SOLO_IRQ_MASK 0x0014 | 60 | #define SOLO_IRQ_MASK 0x0014 |
| 59 | #define SOLO_IRQ_P2M(n) (1<<((n)+17)) | 61 | #define SOLO_IRQ_P2M(n) BIT((n) + 17) |
| 60 | #define SOLO_IRQ_GPIO (1<<16) | 62 | #define SOLO_IRQ_GPIO BIT(16) |
| 61 | #define SOLO_IRQ_VIDEO_LOSS (1<<15) | 63 | #define SOLO_IRQ_VIDEO_LOSS BIT(15) |
| 62 | #define SOLO_IRQ_VIDEO_IN (1<<14) | 64 | #define SOLO_IRQ_VIDEO_IN BIT(14) |
| 63 | #define SOLO_IRQ_MOTION (1<<13) | 65 | #define SOLO_IRQ_MOTION BIT(13) |
| 64 | #define SOLO_IRQ_ATA_CMD (1<<12) | 66 | #define SOLO_IRQ_ATA_CMD BIT(12) |
| 65 | #define SOLO_IRQ_ATA_DIR (1<<11) | 67 | #define SOLO_IRQ_ATA_DIR BIT(11) |
| 66 | #define SOLO_IRQ_PCI_ERR (1<<10) | 68 | #define SOLO_IRQ_PCI_ERR BIT(10) |
| 67 | #define SOLO_IRQ_PS2_1 (1<<9) | 69 | #define SOLO_IRQ_PS2_1 BIT(9) |
| 68 | #define SOLO_IRQ_PS2_0 (1<<8) | 70 | #define SOLO_IRQ_PS2_0 BIT(8) |
| 69 | #define SOLO_IRQ_SPI (1<<7) | 71 | #define SOLO_IRQ_SPI BIT(7) |
| 70 | #define SOLO_IRQ_IIC (1<<6) | 72 | #define SOLO_IRQ_IIC BIT(6) |
| 71 | #define SOLO_IRQ_UART(n) (1<<((n) + 4)) | 73 | #define SOLO_IRQ_UART(n) BIT((n) + 4) |
| 72 | #define SOLO_IRQ_G723 (1<<3) | 74 | #define SOLO_IRQ_G723 BIT(3) |
| 73 | #define SOLO_IRQ_DECODER (1<<1) | 75 | #define SOLO_IRQ_DECODER BIT(1) |
| 74 | #define SOLO_IRQ_ENCODER (1<<0) | 76 | #define SOLO_IRQ_ENCODER BIT(0) |
| 75 | 77 | ||
| 76 | #define SOLO_CHIP_OPTION 0x001C | 78 | #define SOLO_CHIP_OPTION 0x001C |
| 77 | #define SOLO_CHIP_ID_MASK 0x00000007 | 79 | #define SOLO_CHIP_ID_MASK 0x00000007 |
| @@ -79,11 +81,11 @@ | |||
| 79 | #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ | 81 | #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */ |
| 80 | 82 | ||
| 81 | #define SOLO_EEPROM_CTRL 0x0060 | 83 | #define SOLO_EEPROM_CTRL 0x0060 |
| 82 | #define SOLO_EEPROM_ACCESS_EN (1<<7) | 84 | #define SOLO_EEPROM_ACCESS_EN BIT(7) |
| 83 | #define SOLO_EEPROM_CS (1<<3) | 85 | #define SOLO_EEPROM_CS BIT(3) |
| 84 | #define SOLO_EEPROM_CLK (1<<2) | 86 | #define SOLO_EEPROM_CLK BIT(2) |
| 85 | #define SOLO_EEPROM_DO (1<<1) | 87 | #define SOLO_EEPROM_DO BIT(1) |
| 86 | #define SOLO_EEPROM_DI (1<<0) | 88 | #define SOLO_EEPROM_DI BIT(0) |
| 87 | #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) | 89 | #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS) |
| 88 | 90 | ||
| 89 | #define SOLO_PCI_ERR 0x0070 | 91 | #define SOLO_PCI_ERR 0x0070 |
| @@ -102,13 +104,13 @@ | |||
| 102 | 104 | ||
| 103 | #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) | 105 | #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20)) |
| 104 | #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ | 106 | #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */ |
| 105 | #define SOLO_P2M_CSC_BYTE_REORDER (1<<5) /* BGR -> RGB */ | 107 | #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */ |
| 106 | /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ | 108 | /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */ |
| 107 | #define SOLO_P2M_CSC_16BIT_565 (1<<4) | 109 | #define SOLO_P2M_CSC_16BIT_565 BIT(4) |
| 108 | #define SOLO_P2M_UV_SWAP (1<<3) | 110 | #define SOLO_P2M_UV_SWAP BIT(3) |
| 109 | #define SOLO_P2M_PCI_MASTER_MODE (1<<2) | 111 | #define SOLO_P2M_PCI_MASTER_MODE BIT(2) |
| 110 | #define SOLO_P2M_DESC_INTR_OPT (1<<1) /* 1:Empty, 0:Each */ | 112 | #define SOLO_P2M_DESC_INTR_OPT BIT(1) /* 1:Empty, 0:Each */ |
| 111 | #define SOLO_P2M_DESC_MODE (1<<0) | 113 | #define SOLO_P2M_DESC_MODE BIT(0) |
| 112 | 114 | ||
| 113 | #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) | 115 | #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20)) |
| 114 | 116 | ||
| @@ -116,7 +118,7 @@ | |||
| 116 | #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) | 118 | #define SOLO_P2M_UPDATE_ID(n) ((n)<<0) |
| 117 | 119 | ||
| 118 | #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) | 120 | #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20)) |
| 119 | #define SOLO_P2M_COMMAND_DONE (1<<8) | 121 | #define SOLO_P2M_COMMAND_DONE BIT(8) |
| 120 | #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) | 122 | #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat)) |
| 121 | 123 | ||
| 122 | #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) | 124 | #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20)) |
| @@ -129,13 +131,13 @@ | |||
| 129 | #define SOLO_P2M_BURST_128 2 | 131 | #define SOLO_P2M_BURST_128 2 |
| 130 | #define SOLO_P2M_BURST_64 3 | 132 | #define SOLO_P2M_BURST_64 3 |
| 131 | #define SOLO_P2M_BURST_32 4 | 133 | #define SOLO_P2M_BURST_32 4 |
| 132 | #define SOLO_P2M_CSC_16BIT (1<<6) /* 0:24bit, 1:16bit */ | 134 | #define SOLO_P2M_CSC_16BIT BIT(6) /* 0:24bit, 1:16bit */ |
| 133 | /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ | 135 | /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */ |
| 134 | #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) | 136 | #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4) |
| 135 | #define SOLO_P2M_CSC_ON (1<<3) | 137 | #define SOLO_P2M_CSC_ON BIT(3) |
| 136 | #define SOLO_P2M_INTERRUPT_REQ (1<<2) | 138 | #define SOLO_P2M_INTERRUPT_REQ BIT(2) |
| 137 | #define SOLO_P2M_WRITE (1<<1) | 139 | #define SOLO_P2M_WRITE BIT(1) |
| 138 | #define SOLO_P2M_TRANS_ON (1<<0) | 140 | #define SOLO_P2M_TRANS_ON BIT(0) |
| 139 | 141 | ||
| 140 | #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) | 142 | #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20)) |
| 141 | #define SOLO_P2M_EXT_INC(n) ((n)<<20) | 143 | #define SOLO_P2M_EXT_INC(n) ((n)<<20) |
| @@ -157,9 +159,9 @@ | |||
| 157 | #define SOLO_VI_PROG_MASK(n) ((n)<<0) | 159 | #define SOLO_VI_PROG_MASK(n) ((n)<<0) |
| 158 | 160 | ||
| 159 | #define SOLO_VI_FMT_CFG 0x0114 | 161 | #define SOLO_VI_FMT_CFG 0x0114 |
| 160 | #define SOLO_VI_FMT_CHECK_VCOUNT (1<<31) | 162 | #define SOLO_VI_FMT_CHECK_VCOUNT BIT(31) |
| 161 | #define SOLO_VI_FMT_CHECK_HCOUNT (1<<30) | 163 | #define SOLO_VI_FMT_CHECK_HCOUNT BIT(30) |
| 162 | #define SOLO_VI_FMT_TEST_SIGNAL (1<<28) | 164 | #define SOLO_VI_FMT_TEST_SIGNAL BIT(28) |
| 163 | 165 | ||
| 164 | #define SOLO_VI_PAGE_SW 0x0118 | 166 | #define SOLO_VI_PAGE_SW 0x0118 |
| 165 | #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) | 167 | #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8) |
| @@ -171,7 +173,7 @@ | |||
| 171 | #define SOLO_VI_ACT_I_P 0x011C | 173 | #define SOLO_VI_ACT_I_P 0x011C |
| 172 | #define SOLO_VI_ACT_I_S 0x0120 | 174 | #define SOLO_VI_ACT_I_S 0x0120 |
| 173 | #define SOLO_VI_ACT_P 0x0124 | 175 | #define SOLO_VI_ACT_P 0x0124 |
| 174 | #define SOLO_VI_FI_INVERT (1<<31) | 176 | #define SOLO_VI_FI_INVERT BIT(31) |
| 175 | #define SOLO_VI_H_START(n) ((n)<<21) | 177 | #define SOLO_VI_H_START(n) ((n)<<21) |
| 176 | #define SOLO_VI_V_START(n) ((n)<<11) | 178 | #define SOLO_VI_V_START(n) ((n)<<11) |
| 177 | #define SOLO_VI_V_STOP(n) ((n)<<0) | 179 | #define SOLO_VI_V_STOP(n) ((n)<<0) |
| @@ -184,8 +186,8 @@ | |||
| 184 | #define DISP_PAGE(stat) ((stat) & 0x07) | 186 | #define DISP_PAGE(stat) ((stat) & 0x07) |
| 185 | 187 | ||
| 186 | #define SOLO_VI_PB_CONFIG 0x0130 | 188 | #define SOLO_VI_PB_CONFIG 0x0130 |
| 187 | #define SOLO_VI_PB_USER_MODE (1<<1) | 189 | #define SOLO_VI_PB_USER_MODE BIT(1) |
| 188 | #define SOLO_VI_PB_PAL (1<<0) | 190 | #define SOLO_VI_PB_PAL BIT(0) |
| 189 | #define SOLO_VI_PB_RANGE_HV 0x0134 | 191 | #define SOLO_VI_PB_RANGE_HV 0x0134 |
| 190 | #define SOLO_VI_PB_HSIZE(h) ((h)<<12) | 192 | #define SOLO_VI_PB_HSIZE(h) ((h)<<12) |
| 191 | #define SOLO_VI_PB_VSIZE(v) ((v)<<0) | 193 | #define SOLO_VI_PB_VSIZE(v) ((v)<<0) |
| @@ -226,35 +228,35 @@ | |||
| 226 | #define SOLO_VI_MOT_CTRL 0x0264 | 228 | #define SOLO_VI_MOT_CTRL 0x0264 |
| 227 | #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) | 229 | #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24) |
| 228 | #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) | 230 | #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16) |
| 229 | #define SOLO_VI_MOTION_INTR_START_STOP (1<<15) | 231 | #define SOLO_VI_MOTION_INTR_START_STOP BIT(15) |
| 230 | #define SOLO_VI_MOTION_FREEZE_DATA (1<<14) | 232 | #define SOLO_VI_MOTION_FREEZE_DATA BIT(14) |
| 231 | #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) | 233 | #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0) |
| 232 | #define SOLO_VI_MOT_CLEAR 0x0268 | 234 | #define SOLO_VI_MOT_CLEAR 0x0268 |
| 233 | #define SOLO_VI_MOT_STATUS 0x026C | 235 | #define SOLO_VI_MOT_STATUS 0x026C |
| 234 | #define SOLO_VI_MOTION_CNT(n) ((n)<<0) | 236 | #define SOLO_VI_MOTION_CNT(n) ((n)<<0) |
| 235 | #define SOLO_VI_MOTION_BORDER 0x0270 | 237 | #define SOLO_VI_MOTION_BORDER 0x0270 |
| 236 | #define SOLO_VI_MOTION_BAR 0x0274 | 238 | #define SOLO_VI_MOTION_BAR 0x0274 |
| 237 | #define SOLO_VI_MOTION_Y_SET (1<<29) | 239 | #define SOLO_VI_MOTION_Y_SET BIT(29) |
| 238 | #define SOLO_VI_MOTION_Y_ADD (1<<28) | 240 | #define SOLO_VI_MOTION_Y_ADD BIT(28) |
| 239 | #define SOLO_VI_MOTION_CB_SET (1<<27) | 241 | #define SOLO_VI_MOTION_CB_SET BIT(27) |
| 240 | #define SOLO_VI_MOTION_CB_ADD (1<<26) | 242 | #define SOLO_VI_MOTION_CB_ADD BIT(26) |
| 241 | #define SOLO_VI_MOTION_CR_SET (1<<25) | 243 | #define SOLO_VI_MOTION_CR_SET BIT(25) |
| 242 | #define SOLO_VI_MOTION_CR_ADD (1<<24) | 244 | #define SOLO_VI_MOTION_CR_ADD BIT(24) |
| 243 | #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) | 245 | #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16) |
| 244 | #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) | 246 | #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8) |
| 245 | #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) | 247 | #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0) |
| 246 | 248 | ||
| 247 | #define SOLO_VO_FMT_ENC 0x0300 | 249 | #define SOLO_VO_FMT_ENC 0x0300 |
| 248 | #define SOLO_VO_SCAN_MODE_PROGRESSIVE (1<<31) | 250 | #define SOLO_VO_SCAN_MODE_PROGRESSIVE BIT(31) |
| 249 | #define SOLO_VO_FMT_TYPE_PAL (1<<30) | 251 | #define SOLO_VO_FMT_TYPE_PAL BIT(30) |
| 250 | #define SOLO_VO_FMT_TYPE_NTSC 0 | 252 | #define SOLO_VO_FMT_TYPE_NTSC 0 |
| 251 | #define SOLO_VO_USER_SET (1<<29) | 253 | #define SOLO_VO_USER_SET BIT(29) |
| 252 | 254 | ||
| 253 | #define SOLO_VO_FI_CHANGE (1<<20) | 255 | #define SOLO_VO_FI_CHANGE BIT(20) |
| 254 | #define SOLO_VO_USER_COLOR_SET_VSYNC (1<<19) | 256 | #define SOLO_VO_USER_COLOR_SET_VSYNC BIT(19) |
| 255 | #define SOLO_VO_USER_COLOR_SET_HSYNC (1<<18) | 257 | #define SOLO_VO_USER_COLOR_SET_HSYNC BIT(18) |
| 256 | #define SOLO_VO_USER_COLOR_SET_NAH (1<<17) | 258 | #define SOLO_VO_USER_COLOR_SET_NAH BIT(17) |
| 257 | #define SOLO_VO_USER_COLOR_SET_NAV (1<<16) | 259 | #define SOLO_VO_USER_COLOR_SET_NAV BIT(16) |
| 258 | #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) | 260 | #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8) |
| 259 | #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) | 261 | #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4) |
| 260 | #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) | 262 | #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0) |
| @@ -270,32 +272,32 @@ | |||
| 270 | #define SOLO_VO_V_STOP(n) ((n)<<0) | 272 | #define SOLO_VO_V_STOP(n) ((n)<<0) |
| 271 | 273 | ||
| 272 | #define SOLO_VO_RANGE_HV 0x030C | 274 | #define SOLO_VO_RANGE_HV 0x030C |
| 273 | #define SOLO_VO_SYNC_INVERT (1<<24) | 275 | #define SOLO_VO_SYNC_INVERT BIT(24) |
| 274 | #define SOLO_VO_HSYNC_INVERT (1<<23) | 276 | #define SOLO_VO_HSYNC_INVERT BIT(23) |
| 275 | #define SOLO_VO_VSYNC_INVERT (1<<22) | 277 | #define SOLO_VO_VSYNC_INVERT BIT(22) |
| 276 | #define SOLO_VO_H_LEN(n) ((n)<<11) | 278 | #define SOLO_VO_H_LEN(n) ((n)<<11) |
| 277 | #define SOLO_VO_V_LEN(n) ((n)<<0) | 279 | #define SOLO_VO_V_LEN(n) ((n)<<0) |
| 278 | 280 | ||
| 279 | #define SOLO_VO_DISP_CTRL 0x0310 | 281 | #define SOLO_VO_DISP_CTRL 0x0310 |
| 280 | #define SOLO_VO_DISP_ON (1<<31) | 282 | #define SOLO_VO_DISP_ON BIT(31) |
| 281 | #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) | 283 | #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24) |
| 282 | #define SOLO_VO_DISP_DOUBLE_SCAN (1<<22) | 284 | #define SOLO_VO_DISP_DOUBLE_SCAN BIT(22) |
| 283 | #define SOLO_VO_DISP_SINGLE_PAGE (1<<21) | 285 | #define SOLO_VO_DISP_SINGLE_PAGE BIT(21) |
| 284 | #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) | 286 | #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff) |
| 285 | 287 | ||
| 286 | #define SOLO_VO_DISP_ERASE 0x0314 | 288 | #define SOLO_VO_DISP_ERASE 0x0314 |
| 287 | #define SOLO_VO_DISP_ERASE_ON (1<<0) | 289 | #define SOLO_VO_DISP_ERASE_ON BIT(0) |
| 288 | 290 | ||
| 289 | #define SOLO_VO_ZOOM_CTRL 0x0318 | 291 | #define SOLO_VO_ZOOM_CTRL 0x0318 |
| 290 | #define SOLO_VO_ZOOM_VER_ON (1<<24) | 292 | #define SOLO_VO_ZOOM_VER_ON BIT(24) |
| 291 | #define SOLO_VO_ZOOM_HOR_ON (1<<23) | 293 | #define SOLO_VO_ZOOM_HOR_ON BIT(23) |
| 292 | #define SOLO_VO_ZOOM_V_COMP (1<<22) | 294 | #define SOLO_VO_ZOOM_V_COMP BIT(22) |
| 293 | #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) | 295 | #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11) |
| 294 | #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) | 296 | #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0) |
| 295 | 297 | ||
| 296 | #define SOLO_VO_FREEZE_CTRL 0x031C | 298 | #define SOLO_VO_FREEZE_CTRL 0x031C |
| 297 | #define SOLO_VO_FREEZE_ON (1<<1) | 299 | #define SOLO_VO_FREEZE_ON BIT(1) |
| 298 | #define SOLO_VO_FREEZE_INTERPOLATION (1<<0) | 300 | #define SOLO_VO_FREEZE_INTERPOLATION BIT(0) |
| 299 | 301 | ||
| 300 | #define SOLO_VO_BKG_COLOR 0x0320 | 302 | #define SOLO_VO_BKG_COLOR 0x0320 |
| 301 | #define SOLO_BG_Y(y) ((y)<<16) | 303 | #define SOLO_BG_Y(y) ((y)<<16) |
| @@ -334,8 +336,8 @@ | |||
| 334 | #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) | 336 | #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4)) |
| 335 | 337 | ||
| 336 | #define SOLO_OSG_CONFIG 0x03E0 | 338 | #define SOLO_OSG_CONFIG 0x03E0 |
| 337 | #define SOLO_VO_OSG_ON (1<<31) | 339 | #define SOLO_VO_OSG_ON BIT(31) |
| 338 | #define SOLO_VO_OSG_COLOR_MUTE (1<<28) | 340 | #define SOLO_VO_OSG_COLOR_MUTE BIT(28) |
| 339 | #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) | 341 | #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22) |
| 340 | #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) | 342 | #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16) |
| 341 | #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) | 343 | #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff) |
| @@ -345,8 +347,8 @@ | |||
| 345 | #define SOLO_OSG_ERASE_OFF (0x00) | 347 | #define SOLO_OSG_ERASE_OFF (0x00) |
| 346 | 348 | ||
| 347 | #define SOLO_VO_OSG_BLINK 0x03E8 | 349 | #define SOLO_VO_OSG_BLINK 0x03E8 |
| 348 | #define SOLO_VO_OSG_BLINK_ON (1<<1) | 350 | #define SOLO_VO_OSG_BLINK_ON BIT(1) |
| 349 | #define SOLO_VO_OSG_BLINK_INTREVAL18 (1<<0) | 351 | #define SOLO_VO_OSG_BLINK_INTREVAL18 BIT(0) |
| 350 | 352 | ||
| 351 | #define SOLO_CAP_BASE 0x0400 | 353 | #define SOLO_CAP_BASE 0x0400 |
| 352 | #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) | 354 | #define SOLO_CAP_MAX_PAGE(n) ((n)<<16) |
| @@ -374,19 +376,19 @@ | |||
| 374 | 376 | ||
| 375 | 377 | ||
| 376 | #define SOLO_VE_CFG0 0x0610 | 378 | #define SOLO_VE_CFG0 0x0610 |
| 377 | #define SOLO_VE_TWO_PAGE_MODE (1<<31) | 379 | #define SOLO_VE_TWO_PAGE_MODE BIT(31) |
| 378 | #define SOLO_VE_INTR_CTRL(n) ((n)<<24) | 380 | #define SOLO_VE_INTR_CTRL(n) ((n)<<24) |
| 379 | #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) | 381 | #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16) |
| 380 | #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) | 382 | #define SOLO_VE_BLOCK_BASE(n) ((n)<<0) |
| 381 | 383 | ||
| 382 | #define SOLO_VE_CFG1 0x0614 | 384 | #define SOLO_VE_CFG1 0x0614 |
| 383 | #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) | 385 | #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24) |
| 384 | #define SOLO_VE_INSERT_INDEX (1<<18) | 386 | #define SOLO_VE_INSERT_INDEX BIT(18) |
| 385 | #define SOLO_VE_MOTION_MODE(n) ((n)<<16) | 387 | #define SOLO_VE_MOTION_MODE(n) ((n)<<16) |
| 386 | #define SOLO_VE_MOTION_BASE(n) ((n)<<0) | 388 | #define SOLO_VE_MOTION_BASE(n) ((n)<<0) |
| 387 | #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ | 389 | #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */ |
| 388 | #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ | 390 | #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */ |
| 389 | #define SOLO_VE_INSERT_INDEX_JPEG (1<<19) /* 6110 Only */ | 391 | #define SOLO_VE_INSERT_INDEX_JPEG BIT(19) /* 6110 Only */ |
| 390 | 392 | ||
| 391 | #define SOLO_VE_WMRK_POLY 0x061C | 393 | #define SOLO_VE_WMRK_POLY 0x061C |
| 392 | #define SOLO_VE_VMRK_INIT_KEY 0x0620 | 394 | #define SOLO_VE_VMRK_INIT_KEY 0x0620 |
| @@ -394,8 +396,8 @@ | |||
| 394 | #define SOLO_VE_ENCRYP_POLY 0x0628 | 396 | #define SOLO_VE_ENCRYP_POLY 0x0628 |
| 395 | #define SOLO_VE_ENCRYP_INIT 0x062C | 397 | #define SOLO_VE_ENCRYP_INIT 0x062C |
| 396 | #define SOLO_VE_ATTR 0x0630 | 398 | #define SOLO_VE_ATTR 0x0630 |
| 397 | #define SOLO_VE_LITTLE_ENDIAN (1<<31) | 399 | #define SOLO_VE_LITTLE_ENDIAN BIT(31) |
| 398 | #define SOLO_COMP_ATTR_RN (1<<30) | 400 | #define SOLO_COMP_ATTR_RN BIT(30) |
| 399 | #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) | 401 | #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27) |
| 400 | #define SOLO_COMP_TIME_INC(n) ((n)<<25) | 402 | #define SOLO_COMP_TIME_INC(n) ((n)<<25) |
| 401 | #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) | 403 | #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21) |
| @@ -416,9 +418,9 @@ | |||
| 416 | #define SOLO_VE_OSD_BASE 0x0694 | 418 | #define SOLO_VE_OSD_BASE 0x0694 |
| 417 | #define SOLO_VE_OSD_CLR 0x0698 | 419 | #define SOLO_VE_OSD_CLR 0x0698 |
| 418 | #define SOLO_VE_OSD_OPT 0x069C | 420 | #define SOLO_VE_OSD_OPT 0x069C |
| 419 | #define SOLO_VE_OSD_V_DOUBLE (1<<16) /* 6110 Only */ | 421 | #define SOLO_VE_OSD_V_DOUBLE BIT(16) /* 6110 Only */ |
| 420 | #define SOLO_VE_OSD_H_SHADOW (1<<15) | 422 | #define SOLO_VE_OSD_H_SHADOW BIT(15) |
| 421 | #define SOLO_VE_OSD_V_SHADOW (1<<14) | 423 | #define SOLO_VE_OSD_V_SHADOW BIT(14) |
| 422 | #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) | 424 | #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7) |
| 423 | #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) | 425 | #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f) |
| 424 | 426 | ||
| @@ -435,18 +437,18 @@ | |||
| 435 | #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) | 437 | #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8)) |
| 436 | 438 | ||
| 437 | #define SOLO_VD_CFG0 0x0900 | 439 | #define SOLO_VD_CFG0 0x0900 |
| 438 | #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW (1<<24) | 440 | #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW BIT(24) |
| 439 | #define SOLO_VD_CFG_BUSY_WIAT_CODE (1<<23) | 441 | #define SOLO_VD_CFG_BUSY_WIAT_CODE BIT(23) |
| 440 | #define SOLO_VD_CFG_BUSY_WIAT_REF (1<<22) | 442 | #define SOLO_VD_CFG_BUSY_WIAT_REF BIT(22) |
| 441 | #define SOLO_VD_CFG_BUSY_WIAT_RES (1<<21) | 443 | #define SOLO_VD_CFG_BUSY_WIAT_RES BIT(21) |
| 442 | #define SOLO_VD_CFG_BUSY_WIAT_MS (1<<20) | 444 | #define SOLO_VD_CFG_BUSY_WIAT_MS BIT(20) |
| 443 | #define SOLO_VD_CFG_SINGLE_MODE (1<<18) | 445 | #define SOLO_VD_CFG_SINGLE_MODE BIT(18) |
| 444 | #define SOLO_VD_CFG_SCAL_MANUAL (1<<17) | 446 | #define SOLO_VD_CFG_SCAL_MANUAL BIT(17) |
| 445 | #define SOLO_VD_CFG_USER_PAGE_CTRL (1<<16) | 447 | #define SOLO_VD_CFG_USER_PAGE_CTRL BIT(16) |
| 446 | #define SOLO_VD_CFG_LITTLE_ENDIAN (1<<15) | 448 | #define SOLO_VD_CFG_LITTLE_ENDIAN BIT(15) |
| 447 | #define SOLO_VD_CFG_START_FI (1<<14) | 449 | #define SOLO_VD_CFG_START_FI BIT(14) |
| 448 | #define SOLO_VD_CFG_ERR_LOCK (1<<13) | 450 | #define SOLO_VD_CFG_ERR_LOCK BIT(13) |
| 449 | #define SOLO_VD_CFG_ERR_INT_ENA (1<<12) | 451 | #define SOLO_VD_CFG_ERR_INT_ENA BIT(12) |
| 450 | #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) | 452 | #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8) |
| 451 | #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) | 453 | #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0) |
| 452 | 454 | ||
| @@ -459,37 +461,37 @@ | |||
| 459 | #define SOLO_VD_CODE_ADR 0x090C | 461 | #define SOLO_VD_CODE_ADR 0x090C |
| 460 | 462 | ||
| 461 | #define SOLO_VD_CTRL 0x0910 | 463 | #define SOLO_VD_CTRL 0x0910 |
| 462 | #define SOLO_VD_OPER_ON (1<<31) | 464 | #define SOLO_VD_OPER_ON BIT(31) |
| 463 | #define SOLO_VD_MAX_ITEM(n) ((n)<<0) | 465 | #define SOLO_VD_MAX_ITEM(n) ((n)<<0) |
| 464 | 466 | ||
| 465 | #define SOLO_VD_STATUS0 0x0920 | 467 | #define SOLO_VD_STATUS0 0x0920 |
| 466 | #define SOLO_VD_STATUS0_INTR_ACK (1<<22) | 468 | #define SOLO_VD_STATUS0_INTR_ACK BIT(22) |
| 467 | #define SOLO_VD_STATUS0_INTR_EMPTY (1<<21) | 469 | #define SOLO_VD_STATUS0_INTR_EMPTY BIT(21) |
| 468 | #define SOLO_VD_STATUS0_INTR_ERR (1<<20) | 470 | #define SOLO_VD_STATUS0_INTR_ERR BIT(20) |
| 469 | 471 | ||
| 470 | #define SOLO_VD_STATUS1 0x0924 | 472 | #define SOLO_VD_STATUS1 0x0924 |
| 471 | 473 | ||
| 472 | #define SOLO_VD_IDX0 0x0930 | 474 | #define SOLO_VD_IDX0 0x0930 |
| 473 | #define SOLO_VD_IDX_INTERLACE (1<<30) | 475 | #define SOLO_VD_IDX_INTERLACE BIT(30) |
| 474 | #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) | 476 | #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24) |
| 475 | #define SOLO_VD_IDX_SIZE(n) ((n)<<0) | 477 | #define SOLO_VD_IDX_SIZE(n) ((n)<<0) |
| 476 | 478 | ||
| 477 | #define SOLO_VD_IDX1 0x0934 | 479 | #define SOLO_VD_IDX1 0x0934 |
| 478 | #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) | 480 | #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28) |
| 479 | #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) | 481 | #define SOLO_VD_IDX_WINDOW(n) ((n)<<24) |
| 480 | #define SOLO_VD_IDX_DEINTERLACE (1<<16) | 482 | #define SOLO_VD_IDX_DEINTERLACE BIT(16) |
| 481 | #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) | 483 | #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8) |
| 482 | #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) | 484 | #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0) |
| 483 | 485 | ||
| 484 | #define SOLO_VD_IDX2 0x0938 | 486 | #define SOLO_VD_IDX2 0x0938 |
| 485 | #define SOLO_VD_IDX_REF_BASE_SIDE (1<<31) | 487 | #define SOLO_VD_IDX_REF_BASE_SIDE BIT(31) |
| 486 | #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) | 488 | #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff) |
| 487 | 489 | ||
| 488 | #define SOLO_VD_IDX3 0x093C | 490 | #define SOLO_VD_IDX3 0x093C |
| 489 | #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) | 491 | #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28) |
| 490 | #define SOLO_VD_IDX_INTERLACE_WR (1<<27) | 492 | #define SOLO_VD_IDX_INTERLACE_WR BIT(27) |
| 491 | #define SOLO_VD_IDX_INTERPOL (1<<26) | 493 | #define SOLO_VD_IDX_INTERPOL BIT(26) |
| 492 | #define SOLO_VD_IDX_HOR2X (1<<25) | 494 | #define SOLO_VD_IDX_HOR2X BIT(25) |
| 493 | #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) | 495 | #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12) |
| 494 | #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) | 496 | #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0) |
| 495 | 497 | ||
| @@ -511,21 +513,21 @@ | |||
| 511 | 513 | ||
| 512 | 514 | ||
| 513 | #define SOLO_IIC_CFG 0x0B20 | 515 | #define SOLO_IIC_CFG 0x0B20 |
| 514 | #define SOLO_IIC_ENABLE (1<<8) | 516 | #define SOLO_IIC_ENABLE BIT(8) |
| 515 | #define SOLO_IIC_PRESCALE(n) ((n)<<0) | 517 | #define SOLO_IIC_PRESCALE(n) ((n)<<0) |
| 516 | 518 | ||
| 517 | #define SOLO_IIC_CTRL 0x0B24 | 519 | #define SOLO_IIC_CTRL 0x0B24 |
| 518 | #define SOLO_IIC_AUTO_CLEAR (1<<20) | 520 | #define SOLO_IIC_AUTO_CLEAR BIT(20) |
| 519 | #define SOLO_IIC_STATE_RX_ACK (1<<19) | 521 | #define SOLO_IIC_STATE_RX_ACK BIT(19) |
| 520 | #define SOLO_IIC_STATE_BUSY (1<<18) | 522 | #define SOLO_IIC_STATE_BUSY BIT(18) |
| 521 | #define SOLO_IIC_STATE_SIG_ERR (1<<17) | 523 | #define SOLO_IIC_STATE_SIG_ERR BIT(17) |
| 522 | #define SOLO_IIC_STATE_TRNS (1<<16) | 524 | #define SOLO_IIC_STATE_TRNS BIT(16) |
| 523 | #define SOLO_IIC_CH_SET(n) ((n)<<5) | 525 | #define SOLO_IIC_CH_SET(n) ((n)<<5) |
| 524 | #define SOLO_IIC_ACK_EN (1<<4) | 526 | #define SOLO_IIC_ACK_EN BIT(4) |
| 525 | #define SOLO_IIC_START (1<<3) | 527 | #define SOLO_IIC_START BIT(3) |
| 526 | #define SOLO_IIC_STOP (1<<2) | 528 | #define SOLO_IIC_STOP BIT(2) |
| 527 | #define SOLO_IIC_READ (1<<1) | 529 | #define SOLO_IIC_READ BIT(1) |
| 528 | #define SOLO_IIC_WRITE (1<<0) | 530 | #define SOLO_IIC_WRITE BIT(0) |
| 529 | 531 | ||
| 530 | #define SOLO_IIC_TXD 0x0B28 | 532 | #define SOLO_IIC_TXD 0x0B28 |
| 531 | #define SOLO_IIC_RXD 0x0B2C | 533 | #define SOLO_IIC_RXD 0x0B2C |
| @@ -535,15 +537,15 @@ | |||
| 535 | */ | 537 | */ |
| 536 | #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) | 538 | #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20)) |
| 537 | #define SOLO_UART_CLK_DIV(n) ((n)<<24) | 539 | #define SOLO_UART_CLK_DIV(n) ((n)<<24) |
| 538 | #define SOLO_MODEM_CTRL_EN (1<<20) | 540 | #define SOLO_MODEM_CTRL_EN BIT(20) |
| 539 | #define SOLO_PARITY_ERROR_DROP (1<<18) | 541 | #define SOLO_PARITY_ERROR_DROP BIT(18) |
| 540 | #define SOLO_IRQ_ERR_EN (1<<17) | 542 | #define SOLO_IRQ_ERR_EN BIT(17) |
| 541 | #define SOLO_IRQ_RX_EN (1<<16) | 543 | #define SOLO_IRQ_RX_EN BIT(16) |
| 542 | #define SOLO_IRQ_TX_EN (1<<15) | 544 | #define SOLO_IRQ_TX_EN BIT(15) |
| 543 | #define SOLO_RX_EN (1<<14) | 545 | #define SOLO_RX_EN BIT(14) |
| 544 | #define SOLO_TX_EN (1<<13) | 546 | #define SOLO_TX_EN BIT(13) |
| 545 | #define SOLO_UART_HALF_DUPLEX (1<<12) | 547 | #define SOLO_UART_HALF_DUPLEX BIT(12) |
| 546 | #define SOLO_UART_LOOPBACK (1<<11) | 548 | #define SOLO_UART_LOOPBACK BIT(11) |
| 547 | 549 | ||
| 548 | #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) | 550 | #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6)) |
| 549 | #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) | 551 | #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6)) |
| @@ -569,12 +571,12 @@ | |||
| 569 | #define SOLO_UART_PARITY_ODD (3<<0) | 571 | #define SOLO_UART_PARITY_ODD (3<<0) |
| 570 | 572 | ||
| 571 | #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) | 573 | #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20)) |
| 572 | #define SOLO_UART_CTS (1<<15) | 574 | #define SOLO_UART_CTS BIT(15) |
| 573 | #define SOLO_UART_RX_BUSY (1<<14) | 575 | #define SOLO_UART_RX_BUSY BIT(14) |
| 574 | #define SOLO_UART_OVERRUN (1<<13) | 576 | #define SOLO_UART_OVERRUN BIT(13) |
| 575 | #define SOLO_UART_FRAME_ERR (1<<12) | 577 | #define SOLO_UART_FRAME_ERR BIT(12) |
| 576 | #define SOLO_UART_PARITY_ERR (1<<11) | 578 | #define SOLO_UART_PARITY_ERR BIT(11) |
| 577 | #define SOLO_UART_TX_BUSY (1<<5) | 579 | #define SOLO_UART_TX_BUSY BIT(5) |
| 578 | 580 | ||
| 579 | #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) | 581 | #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f) |
| 580 | #define SOLO_UART_RX_BUFF_SIZE 8 | 582 | #define SOLO_UART_RX_BUFF_SIZE 8 |
| @@ -582,9 +584,9 @@ | |||
| 582 | #define SOLO_UART_TX_BUFF_SIZE 8 | 584 | #define SOLO_UART_TX_BUFF_SIZE 8 |
| 583 | 585 | ||
| 584 | #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) | 586 | #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20)) |
| 585 | #define SOLO_UART_TX_DATA_PUSH (1<<8) | 587 | #define SOLO_UART_TX_DATA_PUSH BIT(8) |
| 586 | #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) | 588 | #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20)) |
| 587 | #define SOLO_UART_RX_DATA_POP (1<<8) | 589 | #define SOLO_UART_RX_DATA_POP BIT(8) |
| 588 | 590 | ||
| 589 | #define SOLO_TIMER_CLOCK_NUM 0x0be0 | 591 | #define SOLO_TIMER_CLOCK_NUM 0x0be0 |
| 590 | #define SOLO_TIMER_USEC 0x0be8 | 592 | #define SOLO_TIMER_USEC 0x0be8 |
| @@ -592,19 +594,19 @@ | |||
| 592 | #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ | 594 | #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */ |
| 593 | 595 | ||
| 594 | #define SOLO_AUDIO_CONTROL 0x0D00 | 596 | #define SOLO_AUDIO_CONTROL 0x0D00 |
| 595 | #define SOLO_AUDIO_ENABLE (1<<31) | 597 | #define SOLO_AUDIO_ENABLE BIT(31) |
| 596 | #define SOLO_AUDIO_MASTER_MODE (1<<30) | 598 | #define SOLO_AUDIO_MASTER_MODE BIT(30) |
| 597 | #define SOLO_AUDIO_I2S_MODE (1<<29) | 599 | #define SOLO_AUDIO_I2S_MODE BIT(29) |
| 598 | #define SOLO_AUDIO_I2S_LR_SWAP (1<<27) | 600 | #define SOLO_AUDIO_I2S_LR_SWAP BIT(27) |
| 599 | #define SOLO_AUDIO_I2S_8BIT (1<<26) | 601 | #define SOLO_AUDIO_I2S_8BIT BIT(26) |
| 600 | #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) | 602 | #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24) |
| 601 | #define SOLO_AUDIO_MIX_9TO0 (1<<23) | 603 | #define SOLO_AUDIO_MIX_9TO0 BIT(23) |
| 602 | #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) | 604 | #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20) |
| 603 | #define SOLO_AUDIO_MIX_19TO10 (1<<19) | 605 | #define SOLO_AUDIO_MIX_19TO10 BIT(19) |
| 604 | #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) | 606 | #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16) |
| 605 | #define SOLO_AUDIO_MODE(n) ((n)<<0) | 607 | #define SOLO_AUDIO_MODE(n) ((n)<<0) |
| 606 | #define SOLO_AUDIO_SAMPLE 0x0D04 | 608 | #define SOLO_AUDIO_SAMPLE 0x0D04 |
| 607 | #define SOLO_AUDIO_EE_MODE_ON (1<<30) | 609 | #define SOLO_AUDIO_EE_MODE_ON BIT(30) |
| 608 | #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) | 610 | #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25) |
| 609 | #define SOLO_AUDIO_BITRATE(n) ((n)<<16) | 611 | #define SOLO_AUDIO_BITRATE(n) ((n)<<16) |
| 610 | #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) | 612 | #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0) |
diff --git a/drivers/media/platform/am437x/am437x-vpfe_regs.h b/drivers/media/platform/am437x/am437x-vpfe_regs.h index 4a0ed29723e8..0746c48ec23f 100644 --- a/drivers/media/platform/am437x/am437x-vpfe_regs.h +++ b/drivers/media/platform/am437x/am437x-vpfe_regs.h | |||
| @@ -66,13 +66,13 @@ | |||
| 66 | #define VPFE_PIX_FMT_MASK 3 | 66 | #define VPFE_PIX_FMT_MASK 3 |
| 67 | #define VPFE_PIX_FMT_SHIFT 12 | 67 | #define VPFE_PIX_FMT_SHIFT 12 |
| 68 | #define VPFE_VP2SDR_DISABLE 0xfffbffff | 68 | #define VPFE_VP2SDR_DISABLE 0xfffbffff |
| 69 | #define VPFE_WEN_ENABLE (1 << 17) | 69 | #define VPFE_WEN_ENABLE BIT(17) |
| 70 | #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff | 70 | #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff |
| 71 | #define VPFE_VDHDEN_ENABLE (1 << 16) | 71 | #define VPFE_VDHDEN_ENABLE BIT(16) |
| 72 | #define VPFE_LPF_ENABLE (1 << 14) | 72 | #define VPFE_LPF_ENABLE BIT(14) |
| 73 | #define VPFE_ALAW_ENABLE (1 << 3) | 73 | #define VPFE_ALAW_ENABLE BIT(3) |
| 74 | #define VPFE_ALAW_GAMMA_WD_MASK 7 | 74 | #define VPFE_ALAW_GAMMA_WD_MASK 7 |
| 75 | #define VPFE_BLK_CLAMP_ENABLE (1 << 31) | 75 | #define VPFE_BLK_CLAMP_ENABLE BIT(31) |
| 76 | #define VPFE_BLK_SGAIN_MASK 0x1f | 76 | #define VPFE_BLK_SGAIN_MASK 0x1f |
| 77 | #define VPFE_BLK_ST_PXL_MASK 0x7fff | 77 | #define VPFE_BLK_ST_PXL_MASK 0x7fff |
| 78 | #define VPFE_BLK_ST_PXL_SHIFT 10 | 78 | #define VPFE_BLK_ST_PXL_SHIFT 10 |
| @@ -85,8 +85,8 @@ | |||
| 85 | #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 | 85 | #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 |
| 86 | #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 | 86 | #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 |
| 87 | #define VPFE_BLK_COMP_R_COMP_SHIFT 24 | 87 | #define VPFE_BLK_COMP_R_COMP_SHIFT 24 |
| 88 | #define VPFE_LATCH_ON_VSYNC_DISABLE (1 << 15) | 88 | #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15) |
| 89 | #define VPFE_DATA_PACK_ENABLE (1 << 11) | 89 | #define VPFE_DATA_PACK_ENABLE BIT(11) |
| 90 | #define VPFE_HORZ_INFO_SPH_SHIFT 16 | 90 | #define VPFE_HORZ_INFO_SPH_SHIFT 16 |
| 91 | #define VPFE_VERT_START_SLV0_SHIFT 16 | 91 | #define VPFE_VERT_START_SLV0_SHIFT 16 |
| 92 | #define VPFE_VDINT_VDINT0_SHIFT 16 | 92 | #define VPFE_VDINT_VDINT0_SHIFT 16 |
| @@ -114,15 +114,15 @@ | |||
| 114 | #define VPFE_SYN_FLDMODE_MASK 1 | 114 | #define VPFE_SYN_FLDMODE_MASK 1 |
| 115 | #define VPFE_SYN_FLDMODE_SHIFT 7 | 115 | #define VPFE_SYN_FLDMODE_SHIFT 7 |
| 116 | #define VPFE_REC656IF_BT656_EN 3 | 116 | #define VPFE_REC656IF_BT656_EN 3 |
| 117 | #define VPFE_SYN_MODE_VD_POL_NEGATIVE (1 << 2) | 117 | #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2) |
| 118 | #define VPFE_CCDCFG_Y8POS_SHIFT 11 | 118 | #define VPFE_CCDCFG_Y8POS_SHIFT 11 |
| 119 | #define VPFE_CCDCFG_BW656_10BIT (1 << 5) | 119 | #define VPFE_CCDCFG_BW656_10BIT BIT(5) |
| 120 | #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 | 120 | #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 |
| 121 | #define VPFE_NO_CULLING 0xffff00ff | 121 | #define VPFE_NO_CULLING 0xffff00ff |
| 122 | #define VPFE_VDINT0 (1 << 0) | 122 | #define VPFE_VDINT0 BIT(0) |
| 123 | #define VPFE_VDINT1 (1 << 1) | 123 | #define VPFE_VDINT1 BIT(1) |
| 124 | #define VPFE_VDINT2 (1 << 2) | 124 | #define VPFE_VDINT2 BIT(2) |
| 125 | #define VPFE_DMA_CNTL_OVERFLOW (1 << 31) | 125 | #define VPFE_DMA_CNTL_OVERFLOW BIT(31) |
| 126 | 126 | ||
| 127 | #define VPFE_CONFIG_PCLK_INV_SHIFT 0 | 127 | #define VPFE_CONFIG_PCLK_INV_SHIFT 0 |
| 128 | #define VPFE_CONFIG_PCLK_INV_MASK 1 | 128 | #define VPFE_CONFIG_PCLK_INV_MASK 1 |
diff --git a/drivers/media/platform/davinci/dm644x_ccdc_regs.h b/drivers/media/platform/davinci/dm644x_ccdc_regs.h index 3ae301320313..c4894f6a254e 100644 --- a/drivers/media/platform/davinci/dm644x_ccdc_regs.h +++ b/drivers/media/platform/davinci/dm644x_ccdc_regs.h | |||
| @@ -66,13 +66,13 @@ | |||
| 66 | #define CCDC_PIX_FMT_MASK 3 | 66 | #define CCDC_PIX_FMT_MASK 3 |
| 67 | #define CCDC_PIX_FMT_SHIFT 12 | 67 | #define CCDC_PIX_FMT_SHIFT 12 |
| 68 | #define CCDC_VP2SDR_DISABLE 0xFFFBFFFF | 68 | #define CCDC_VP2SDR_DISABLE 0xFFFBFFFF |
| 69 | #define CCDC_WEN_ENABLE (1 << 17) | 69 | #define CCDC_WEN_ENABLE BIT(17) |
| 70 | #define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF | 70 | #define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF |
| 71 | #define CCDC_VDHDEN_ENABLE (1 << 16) | 71 | #define CCDC_VDHDEN_ENABLE BIT(16) |
| 72 | #define CCDC_LPF_ENABLE (1 << 14) | 72 | #define CCDC_LPF_ENABLE BIT(14) |
| 73 | #define CCDC_ALAW_ENABLE (1 << 3) | 73 | #define CCDC_ALAW_ENABLE BIT(3) |
| 74 | #define CCDC_ALAW_GAMMA_WD_MASK 7 | 74 | #define CCDC_ALAW_GAMMA_WD_MASK 7 |
| 75 | #define CCDC_BLK_CLAMP_ENABLE (1 << 31) | 75 | #define CCDC_BLK_CLAMP_ENABLE BIT(31) |
| 76 | #define CCDC_BLK_SGAIN_MASK 0x1F | 76 | #define CCDC_BLK_SGAIN_MASK 0x1F |
| 77 | #define CCDC_BLK_ST_PXL_MASK 0x7FFF | 77 | #define CCDC_BLK_ST_PXL_MASK 0x7FFF |
| 78 | #define CCDC_BLK_ST_PXL_SHIFT 10 | 78 | #define CCDC_BLK_ST_PXL_SHIFT 10 |
| @@ -85,11 +85,11 @@ | |||
| 85 | #define CCDC_BLK_COMP_GB_COMP_SHIFT 8 | 85 | #define CCDC_BLK_COMP_GB_COMP_SHIFT 8 |
| 86 | #define CCDC_BLK_COMP_GR_COMP_SHIFT 16 | 86 | #define CCDC_BLK_COMP_GR_COMP_SHIFT 16 |
| 87 | #define CCDC_BLK_COMP_R_COMP_SHIFT 24 | 87 | #define CCDC_BLK_COMP_R_COMP_SHIFT 24 |
| 88 | #define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) | 88 | #define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15) |
| 89 | #define CCDC_FPC_ENABLE (1 << 15) | 89 | #define CCDC_FPC_ENABLE BIT(15) |
| 90 | #define CCDC_FPC_DISABLE 0 | 90 | #define CCDC_FPC_DISABLE 0 |
| 91 | #define CCDC_FPC_FPC_NUM_MASK 0x7FFF | 91 | #define CCDC_FPC_FPC_NUM_MASK 0x7FFF |
| 92 | #define CCDC_DATA_PACK_ENABLE (1 << 11) | 92 | #define CCDC_DATA_PACK_ENABLE BIT(11) |
| 93 | #define CCDC_FMTCFG_VPIN_MASK 7 | 93 | #define CCDC_FMTCFG_VPIN_MASK 7 |
| 94 | #define CCDC_FMTCFG_VPIN_SHIFT 12 | 94 | #define CCDC_FMTCFG_VPIN_SHIFT 12 |
| 95 | #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF | 95 | #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF |
| @@ -132,9 +132,9 @@ | |||
| 132 | #define CCDC_SYN_FLDMODE_MASK 1 | 132 | #define CCDC_SYN_FLDMODE_MASK 1 |
| 133 | #define CCDC_SYN_FLDMODE_SHIFT 7 | 133 | #define CCDC_SYN_FLDMODE_SHIFT 7 |
| 134 | #define CCDC_REC656IF_BT656_EN 3 | 134 | #define CCDC_REC656IF_BT656_EN 3 |
| 135 | #define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2) | 135 | #define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2) |
| 136 | #define CCDC_CCDCFG_Y8POS_SHIFT 11 | 136 | #define CCDC_CCDCFG_Y8POS_SHIFT 11 |
| 137 | #define CCDC_CCDCFG_BW656_10BIT (1 << 5) | 137 | #define CCDC_CCDCFG_BW656_10BIT BIT(5) |
| 138 | #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 | 138 | #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 |
| 139 | #define CCDC_NO_CULLING 0xffff00ff | 139 | #define CCDC_NO_CULLING 0xffff00ff |
| 140 | #endif | 140 | #endif |
diff --git a/drivers/media/platform/exynos4-is/fimc-lite-reg.h b/drivers/media/platform/exynos4-is/fimc-lite-reg.h index 48f2cf1148b8..c5656e902750 100644 --- a/drivers/media/platform/exynos4-is/fimc-lite-reg.h +++ b/drivers/media/platform/exynos4-is/fimc-lite-reg.h | |||
| @@ -6,6 +6,8 @@ | |||
| 6 | #ifndef FIMC_LITE_REG_H_ | 6 | #ifndef FIMC_LITE_REG_H_ |
| 7 | #define FIMC_LITE_REG_H_ | 7 | #define FIMC_LITE_REG_H_ |
| 8 | 8 | ||
| 9 | #include <linux/bitops.h> | ||
| 10 | |||
| 9 | #include "fimc-lite.h" | 11 | #include "fimc-lite.h" |
| 10 | 12 | ||
| 11 | /* Camera Source size */ | 13 | /* Camera Source size */ |
| @@ -27,27 +29,27 @@ | |||
| 27 | /* User defined formats. x = 0...15 */ | 29 | /* User defined formats. x = 0...15 */ |
| 28 | #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) | 30 | #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) |
| 29 | #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) | 31 | #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) |
| 30 | #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21) | 32 | #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21) |
| 31 | #define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20) | 33 | #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20) |
| 32 | #define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19) | 34 | #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19) |
| 33 | #define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18) | 35 | #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18) |
| 34 | #define FLITE_REG_CIGCTRL_SWRST (1 << 17) | 36 | #define FLITE_REG_CIGCTRL_SWRST BIT(17) |
| 35 | #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15) | 37 | #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15) |
| 36 | #define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14) | 38 | #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14) |
| 37 | #define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13) | 39 | #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13) |
| 38 | #define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12) | 40 | #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12) |
| 39 | /* Interrupts mask bits (1 disables an interrupt) */ | 41 | /* Interrupts mask bits (1 disables an interrupt) */ |
| 40 | #define FLITE_REG_CIGCTRL_IRQ_LASTEN (1 << 8) | 42 | #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8) |
| 41 | #define FLITE_REG_CIGCTRL_IRQ_ENDEN (1 << 7) | 43 | #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7) |
| 42 | #define FLITE_REG_CIGCTRL_IRQ_STARTEN (1 << 6) | 44 | #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6) |
| 43 | #define FLITE_REG_CIGCTRL_IRQ_OVFEN (1 << 5) | 45 | #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5) |
| 44 | #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) | 46 | #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) |
| 45 | #define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3) | 47 | #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3) |
| 46 | 48 | ||
| 47 | /* Image Capture Enable */ | 49 | /* Image Capture Enable */ |
| 48 | #define FLITE_REG_CIIMGCPT 0x08 | 50 | #define FLITE_REG_CIIMGCPT 0x08 |
| 49 | #define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31) | 51 | #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31) |
| 50 | #define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25) | 52 | #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25) |
| 51 | #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) | 53 | #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) |
| 52 | #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) | 54 | #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) |
| 53 | 55 | ||
| @@ -56,10 +58,10 @@ | |||
| 56 | 58 | ||
| 57 | /* Camera Window Offset */ | 59 | /* Camera Window Offset */ |
| 58 | #define FLITE_REG_CIWDOFST 0x10 | 60 | #define FLITE_REG_CIWDOFST 0x10 |
| 59 | #define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31) | 61 | #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31) |
| 60 | #define FLITE_REG_CIWDOFST_CLROVIY (1 << 31) | 62 | #define FLITE_REG_CIWDOFST_CLROVIY BIT(31) |
| 61 | #define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15) | 63 | #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15) |
| 62 | #define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14) | 64 | #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14) |
| 63 | #define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) | 65 | #define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) |
| 64 | 66 | ||
| 65 | /* Camera Window Offset2 */ | 67 | /* Camera Window Offset2 */ |
| @@ -67,8 +69,8 @@ | |||
| 67 | 69 | ||
| 68 | /* Camera Output DMA Format */ | 70 | /* Camera Output DMA Format */ |
| 69 | #define FLITE_REG_CIODMAFMT 0x18 | 71 | #define FLITE_REG_CIODMAFMT 0x18 |
| 70 | #define FLITE_REG_CIODMAFMT_RAW_CON (1 << 15) | 72 | #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15) |
| 71 | #define FLITE_REG_CIODMAFMT_PACK12 (1 << 14) | 73 | #define FLITE_REG_CIODMAFMT_PACK12 BIT(14) |
| 72 | #define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) | 74 | #define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) |
| 73 | #define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) | 75 | #define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) |
| 74 | #define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) | 76 | #define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) |
| @@ -88,34 +90,34 @@ | |||
| 88 | 90 | ||
| 89 | /* Camera Status */ | 91 | /* Camera Status */ |
| 90 | #define FLITE_REG_CISTATUS 0x40 | 92 | #define FLITE_REG_CISTATUS 0x40 |
| 91 | #define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22) | 93 | #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22) |
| 92 | #define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21) | 94 | #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21) |
| 93 | #define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20) | 95 | #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20) |
| 94 | #define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14) | 96 | #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14) |
| 95 | #define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13) | 97 | #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13) |
| 96 | #define FLITE_REG_CISTATUS_OVFIY (1 << 10) | 98 | #define FLITE_REG_CISTATUS_OVFIY BIT(10) |
| 97 | #define FLITE_REG_CISTATUS_OVFICB (1 << 9) | 99 | #define FLITE_REG_CISTATUS_OVFICB BIT(9) |
| 98 | #define FLITE_REG_CISTATUS_OVFICR (1 << 8) | 100 | #define FLITE_REG_CISTATUS_OVFICR BIT(8) |
| 99 | #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7) | 101 | #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7) |
| 100 | #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6) | 102 | #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6) |
| 101 | #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5) | 103 | #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5) |
| 102 | #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4) | 104 | #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4) |
| 103 | #define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0) | 105 | #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0) |
| 104 | #define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) | 106 | #define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) |
| 105 | 107 | ||
| 106 | /* Camera Status2 */ | 108 | /* Camera Status2 */ |
| 107 | #define FLITE_REG_CISTATUS2 0x44 | 109 | #define FLITE_REG_CISTATUS2 0x44 |
| 108 | #define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1) | 110 | #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1) |
| 109 | #define FLITE_REG_CISTATUS2_FRMEND (1 << 0) | 111 | #define FLITE_REG_CISTATUS2_FRMEND BIT(0) |
| 110 | 112 | ||
| 111 | /* Qos Threshold */ | 113 | /* Qos Threshold */ |
| 112 | #define FLITE_REG_CITHOLD 0xf0 | 114 | #define FLITE_REG_CITHOLD 0xf0 |
| 113 | #define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30) | 115 | #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30) |
| 114 | 116 | ||
| 115 | /* Camera General Purpose */ | 117 | /* Camera General Purpose */ |
| 116 | #define FLITE_REG_CIGENERAL 0xfc | 118 | #define FLITE_REG_CIGENERAL 0xfc |
| 117 | /* b0: 1 - camera B, 0 - camera A */ | 119 | /* b0: 1 - camera B, 0 - camera A */ |
| 118 | #define FLITE_REG_CIGENERAL_CAM_B (1 << 0) | 120 | #define FLITE_REG_CIGENERAL_CAM_B BIT(0) |
| 119 | 121 | ||
| 120 | #define FLITE_REG_CIFCNTSEQ 0x100 | 122 | #define FLITE_REG_CIFCNTSEQ 0x100 |
| 121 | #define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) | 123 | #define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) |
diff --git a/drivers/media/platform/exynos4-is/fimc-reg.h b/drivers/media/platform/exynos4-is/fimc-reg.h index 03ba6c2bc84b..b81826d04936 100644 --- a/drivers/media/platform/exynos4-is/fimc-reg.h +++ b/drivers/media/platform/exynos4-is/fimc-reg.h | |||
| @@ -8,12 +8,14 @@ | |||
| 8 | #ifndef FIMC_REG_H_ | 8 | #ifndef FIMC_REG_H_ |
| 9 | #define FIMC_REG_H_ | 9 | #define FIMC_REG_H_ |
| 10 | 10 | ||
| 11 | #include <linux/bitops.h> | ||
| 12 | |||
| 11 | #include "fimc-core.h" | 13 | #include "fimc-core.h" |
| 12 | 14 | ||
| 13 | /* Input source format */ | 15 | /* Input source format */ |
| 14 | #define FIMC_REG_CISRCFMT 0x00 | 16 | #define FIMC_REG_CISRCFMT 0x00 |
| 15 | #define FIMC_REG_CISRCFMT_ITU601_8BIT (1 << 31) | 17 | #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31) |
| 16 | #define FIMC_REG_CISRCFMT_ITU601_16BIT (1 << 29) | 18 | #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29) |
| 17 | #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14) | 19 | #define FIMC_REG_CISRCFMT_ORDER422_YCBYCR (0 << 14) |
| 18 | #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14) | 20 | #define FIMC_REG_CISRCFMT_ORDER422_YCRYCB (1 << 14) |
| 19 | #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14) | 21 | #define FIMC_REG_CISRCFMT_ORDER422_CBYCRY (2 << 14) |
| @@ -21,45 +23,45 @@ | |||
| 21 | 23 | ||
| 22 | /* Window offset */ | 24 | /* Window offset */ |
| 23 | #define FIMC_REG_CIWDOFST 0x04 | 25 | #define FIMC_REG_CIWDOFST 0x04 |
| 24 | #define FIMC_REG_CIWDOFST_OFF_EN (1 << 31) | 26 | #define FIMC_REG_CIWDOFST_OFF_EN BIT(31) |
| 25 | #define FIMC_REG_CIWDOFST_CLROVFIY (1 << 30) | 27 | #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30) |
| 26 | #define FIMC_REG_CIWDOFST_CLROVRLB (1 << 29) | 28 | #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29) |
| 27 | #define FIMC_REG_CIWDOFST_HOROFF_MASK (0x7ff << 16) | 29 | #define FIMC_REG_CIWDOFST_HOROFF_MASK (0x7ff << 16) |
| 28 | #define FIMC_REG_CIWDOFST_CLROVFICB (1 << 15) | 30 | #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15) |
| 29 | #define FIMC_REG_CIWDOFST_CLROVFICR (1 << 14) | 31 | #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14) |
| 30 | #define FIMC_REG_CIWDOFST_VEROFF_MASK (0xfff << 0) | 32 | #define FIMC_REG_CIWDOFST_VEROFF_MASK (0xfff << 0) |
| 31 | 33 | ||
| 32 | /* Global control */ | 34 | /* Global control */ |
| 33 | #define FIMC_REG_CIGCTRL 0x08 | 35 | #define FIMC_REG_CIGCTRL 0x08 |
| 34 | #define FIMC_REG_CIGCTRL_SWRST (1 << 31) | 36 | #define FIMC_REG_CIGCTRL_SWRST BIT(31) |
| 35 | #define FIMC_REG_CIGCTRL_CAMRST_A (1 << 30) | 37 | #define FIMC_REG_CIGCTRL_CAMRST_A BIT(30) |
| 36 | #define FIMC_REG_CIGCTRL_SELCAM_ITU_A (1 << 29) | 38 | #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29) |
| 37 | #define FIMC_REG_CIGCTRL_TESTPAT_NORMAL (0 << 27) | 39 | #define FIMC_REG_CIGCTRL_TESTPAT_NORMAL (0 << 27) |
| 38 | #define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27) | 40 | #define FIMC_REG_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27) |
| 39 | #define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC (2 << 27) | 41 | #define FIMC_REG_CIGCTRL_TESTPAT_HOR_INC (2 << 27) |
| 40 | #define FIMC_REG_CIGCTRL_TESTPAT_VER_INC (3 << 27) | 42 | #define FIMC_REG_CIGCTRL_TESTPAT_VER_INC (3 << 27) |
| 41 | #define FIMC_REG_CIGCTRL_TESTPAT_MASK (3 << 27) | 43 | #define FIMC_REG_CIGCTRL_TESTPAT_MASK (3 << 27) |
| 42 | #define FIMC_REG_CIGCTRL_TESTPAT_SHIFT 27 | 44 | #define FIMC_REG_CIGCTRL_TESTPAT_SHIFT 27 |
| 43 | #define FIMC_REG_CIGCTRL_INVPOLPCLK (1 << 26) | 45 | #define FIMC_REG_CIGCTRL_INVPOLPCLK BIT(26) |
| 44 | #define FIMC_REG_CIGCTRL_INVPOLVSYNC (1 << 25) | 46 | #define FIMC_REG_CIGCTRL_INVPOLVSYNC BIT(25) |
| 45 | #define FIMC_REG_CIGCTRL_INVPOLHREF (1 << 24) | 47 | #define FIMC_REG_CIGCTRL_INVPOLHREF BIT(24) |
| 46 | #define FIMC_REG_CIGCTRL_IRQ_OVFEN (1 << 22) | 48 | #define FIMC_REG_CIGCTRL_IRQ_OVFEN BIT(22) |
| 47 | #define FIMC_REG_CIGCTRL_HREF_MASK (1 << 21) | 49 | #define FIMC_REG_CIGCTRL_HREF_MASK BIT(21) |
| 48 | #define FIMC_REG_CIGCTRL_IRQ_LEVEL (1 << 20) | 50 | #define FIMC_REG_CIGCTRL_IRQ_LEVEL BIT(20) |
| 49 | #define FIMC_REG_CIGCTRL_IRQ_CLR (1 << 19) | 51 | #define FIMC_REG_CIGCTRL_IRQ_CLR BIT(19) |
| 50 | #define FIMC_REG_CIGCTRL_IRQ_ENABLE (1 << 16) | 52 | #define FIMC_REG_CIGCTRL_IRQ_ENABLE BIT(16) |
| 51 | #define FIMC_REG_CIGCTRL_SHDW_DISABLE (1 << 12) | 53 | #define FIMC_REG_CIGCTRL_SHDW_DISABLE BIT(12) |
| 52 | /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */ | 54 | /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */ |
| 53 | #define FIMC_REG_CIGCTRL_SELWB_A (1 << 10) | 55 | #define FIMC_REG_CIGCTRL_SELWB_A BIT(10) |
| 54 | #define FIMC_REG_CIGCTRL_CAM_JPEG (1 << 8) | 56 | #define FIMC_REG_CIGCTRL_CAM_JPEG BIT(8) |
| 55 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A (1 << 7) | 57 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI_A BIT(7) |
| 56 | #define FIMC_REG_CIGCTRL_CAMIF_SELWB (1 << 6) | 58 | #define FIMC_REG_CIGCTRL_CAMIF_SELWB BIT(6) |
| 57 | /* 0 - ITU601; 1 - ITU709 */ | 59 | /* 0 - ITU601; 1 - ITU709 */ |
| 58 | #define FIMC_REG_CIGCTRL_CSC_ITU601_709 (1 << 5) | 60 | #define FIMC_REG_CIGCTRL_CSC_ITU601_709 BIT(5) |
| 59 | #define FIMC_REG_CIGCTRL_INVPOLHSYNC (1 << 4) | 61 | #define FIMC_REG_CIGCTRL_INVPOLHSYNC BIT(4) |
| 60 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI (1 << 3) | 62 | #define FIMC_REG_CIGCTRL_SELCAM_MIPI BIT(3) |
| 61 | #define FIMC_REG_CIGCTRL_INVPOLFIELD (1 << 1) | 63 | #define FIMC_REG_CIGCTRL_INVPOLFIELD BIT(1) |
| 62 | #define FIMC_REG_CIGCTRL_INTERLACE (1 << 0) | 64 | #define FIMC_REG_CIGCTRL_INTERLACE BIT(0) |
| 63 | 65 | ||
| 64 | /* Window offset 2 */ | 66 | /* Window offset 2 */ |
| 65 | #define FIMC_REG_CIWDOFST2 0x14 | 67 | #define FIMC_REG_CIWDOFST2 0x14 |
| @@ -73,7 +75,7 @@ | |||
| 73 | 75 | ||
| 74 | /* Target image format */ | 76 | /* Target image format */ |
| 75 | #define FIMC_REG_CITRGFMT 0x48 | 77 | #define FIMC_REG_CITRGFMT 0x48 |
| 76 | #define FIMC_REG_CITRGFMT_INROT90 (1 << 31) | 78 | #define FIMC_REG_CITRGFMT_INROT90 BIT(31) |
| 77 | #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29) | 79 | #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29) |
| 78 | #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29) | 80 | #define FIMC_REG_CITRGFMT_YCBCR422 (1 << 29) |
| 79 | #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29) | 81 | #define FIMC_REG_CITRGFMT_YCBCR422_1P (2 << 29) |
| @@ -86,7 +88,7 @@ | |||
| 86 | #define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR (2 << 14) | 88 | #define FIMC_REG_CITRGFMT_FLIP_Y_MIRROR (2 << 14) |
| 87 | #define FIMC_REG_CITRGFMT_FLIP_180 (3 << 14) | 89 | #define FIMC_REG_CITRGFMT_FLIP_180 (3 << 14) |
| 88 | #define FIMC_REG_CITRGFMT_FLIP_MASK (3 << 14) | 90 | #define FIMC_REG_CITRGFMT_FLIP_MASK (3 << 14) |
| 89 | #define FIMC_REG_CITRGFMT_OUTROT90 (1 << 13) | 91 | #define FIMC_REG_CITRGFMT_OUTROT90 BIT(13) |
| 90 | #define FIMC_REG_CITRGFMT_VSIZE_MASK (0xfff << 0) | 92 | #define FIMC_REG_CITRGFMT_VSIZE_MASK (0xfff << 0) |
| 91 | 93 | ||
| 92 | /* Output DMA control */ | 94 | /* Output DMA control */ |
| @@ -96,7 +98,7 @@ | |||
| 96 | #define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (1 << 0) | 98 | #define FIMC_REG_CIOCTRL_ORDER422_YCRYCB (1 << 0) |
| 97 | #define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (2 << 0) | 99 | #define FIMC_REG_CIOCTRL_ORDER422_CBYCRY (2 << 0) |
| 98 | #define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (3 << 0) | 100 | #define FIMC_REG_CIOCTRL_ORDER422_CRYCBY (3 << 0) |
| 99 | #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE (1 << 2) | 101 | #define FIMC_REG_CIOCTRL_LASTIRQ_ENABLE BIT(2) |
| 100 | #define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3) | 102 | #define FIMC_REG_CIOCTRL_YCBCR_3PLANE (0 << 3) |
| 101 | #define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3) | 103 | #define FIMC_REG_CIOCTRL_YCBCR_2PLANE (1 << 3) |
| 102 | #define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) | 104 | #define FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) |
| @@ -116,14 +118,14 @@ | |||
| 116 | 118 | ||
| 117 | /* Main scaler control */ | 119 | /* Main scaler control */ |
| 118 | #define FIMC_REG_CISCCTRL 0x58 | 120 | #define FIMC_REG_CISCCTRL 0x58 |
| 119 | #define FIMC_REG_CISCCTRL_SCALERBYPASS (1 << 31) | 121 | #define FIMC_REG_CISCCTRL_SCALERBYPASS BIT(31) |
| 120 | #define FIMC_REG_CISCCTRL_SCALEUP_H (1 << 30) | 122 | #define FIMC_REG_CISCCTRL_SCALEUP_H BIT(30) |
| 121 | #define FIMC_REG_CISCCTRL_SCALEUP_V (1 << 29) | 123 | #define FIMC_REG_CISCCTRL_SCALEUP_V BIT(29) |
| 122 | #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE (1 << 28) | 124 | #define FIMC_REG_CISCCTRL_CSCR2Y_WIDE BIT(28) |
| 123 | #define FIMC_REG_CISCCTRL_CSCY2R_WIDE (1 << 27) | 125 | #define FIMC_REG_CISCCTRL_CSCY2R_WIDE BIT(27) |
| 124 | #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO (1 << 26) | 126 | #define FIMC_REG_CISCCTRL_LCDPATHEN_FIFO BIT(26) |
| 125 | #define FIMC_REG_CISCCTRL_INTERLACE (1 << 25) | 127 | #define FIMC_REG_CISCCTRL_INTERLACE BIT(25) |
| 126 | #define FIMC_REG_CISCCTRL_SCALERSTART (1 << 15) | 128 | #define FIMC_REG_CISCCTRL_SCALERSTART BIT(15) |
| 127 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) | 129 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) |
| 128 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) | 130 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) |
| 129 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) | 131 | #define FIMC_REG_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) |
| @@ -132,8 +134,8 @@ | |||
| 132 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) | 134 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) |
| 133 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) | 135 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) |
| 134 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK (3 << 11) | 136 | #define FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK (3 << 11) |
| 135 | #define FIMC_REG_CISCCTRL_RGB_EXT (1 << 10) | 137 | #define FIMC_REG_CISCCTRL_RGB_EXT BIT(10) |
| 136 | #define FIMC_REG_CISCCTRL_ONE2ONE (1 << 9) | 138 | #define FIMC_REG_CISCCTRL_ONE2ONE BIT(9) |
| 137 | #define FIMC_REG_CISCCTRL_MHRATIO(x) ((x) << 16) | 139 | #define FIMC_REG_CISCCTRL_MHRATIO(x) ((x) << 16) |
| 138 | #define FIMC_REG_CISCCTRL_MVRATIO(x) ((x) << 0) | 140 | #define FIMC_REG_CISCCTRL_MVRATIO(x) ((x) << 0) |
| 139 | #define FIMC_REG_CISCCTRL_MHRATIO_MASK (0x1ff << 16) | 141 | #define FIMC_REG_CISCCTRL_MHRATIO_MASK (0x1ff << 16) |
| @@ -147,39 +149,39 @@ | |||
| 147 | 149 | ||
| 148 | /* General status */ | 150 | /* General status */ |
| 149 | #define FIMC_REG_CISTATUS 0x64 | 151 | #define FIMC_REG_CISTATUS 0x64 |
| 150 | #define FIMC_REG_CISTATUS_OVFIY (1 << 31) | 152 | #define FIMC_REG_CISTATUS_OVFIY BIT(31) |
| 151 | #define FIMC_REG_CISTATUS_OVFICB (1 << 30) | 153 | #define FIMC_REG_CISTATUS_OVFICB BIT(30) |
| 152 | #define FIMC_REG_CISTATUS_OVFICR (1 << 29) | 154 | #define FIMC_REG_CISTATUS_OVFICR BIT(29) |
| 153 | #define FIMC_REG_CISTATUS_VSYNC (1 << 28) | 155 | #define FIMC_REG_CISTATUS_VSYNC BIT(28) |
| 154 | #define FIMC_REG_CISTATUS_FRAMECNT_MASK (3 << 26) | 156 | #define FIMC_REG_CISTATUS_FRAMECNT_MASK (3 << 26) |
| 155 | #define FIMC_REG_CISTATUS_FRAMECNT_SHIFT 26 | 157 | #define FIMC_REG_CISTATUS_FRAMECNT_SHIFT 26 |
| 156 | #define FIMC_REG_CISTATUS_WINOFF_EN (1 << 25) | 158 | #define FIMC_REG_CISTATUS_WINOFF_EN BIT(25) |
| 157 | #define FIMC_REG_CISTATUS_IMGCPT_EN (1 << 22) | 159 | #define FIMC_REG_CISTATUS_IMGCPT_EN BIT(22) |
| 158 | #define FIMC_REG_CISTATUS_IMGCPT_SCEN (1 << 21) | 160 | #define FIMC_REG_CISTATUS_IMGCPT_SCEN BIT(21) |
| 159 | #define FIMC_REG_CISTATUS_VSYNC_A (1 << 20) | 161 | #define FIMC_REG_CISTATUS_VSYNC_A BIT(20) |
| 160 | #define FIMC_REG_CISTATUS_VSYNC_B (1 << 19) | 162 | #define FIMC_REG_CISTATUS_VSYNC_B BIT(19) |
| 161 | #define FIMC_REG_CISTATUS_OVRLB (1 << 18) | 163 | #define FIMC_REG_CISTATUS_OVRLB BIT(18) |
| 162 | #define FIMC_REG_CISTATUS_FRAME_END (1 << 17) | 164 | #define FIMC_REG_CISTATUS_FRAME_END BIT(17) |
| 163 | #define FIMC_REG_CISTATUS_LASTCAPT_END (1 << 16) | 165 | #define FIMC_REG_CISTATUS_LASTCAPT_END BIT(16) |
| 164 | #define FIMC_REG_CISTATUS_VVALID_A (1 << 15) | 166 | #define FIMC_REG_CISTATUS_VVALID_A BIT(15) |
| 165 | #define FIMC_REG_CISTATUS_VVALID_B (1 << 14) | 167 | #define FIMC_REG_CISTATUS_VVALID_B BIT(14) |
| 166 | 168 | ||
| 167 | /* Indexes to the last and the currently processed buffer. */ | 169 | /* Indexes to the last and the currently processed buffer. */ |
| 168 | #define FIMC_REG_CISTATUS2 0x68 | 170 | #define FIMC_REG_CISTATUS2 0x68 |
| 169 | 171 | ||
| 170 | /* Image capture control */ | 172 | /* Image capture control */ |
| 171 | #define FIMC_REG_CIIMGCPT 0xc0 | 173 | #define FIMC_REG_CIIMGCPT 0xc0 |
| 172 | #define FIMC_REG_CIIMGCPT_IMGCPTEN (1 << 31) | 174 | #define FIMC_REG_CIIMGCPT_IMGCPTEN BIT(31) |
| 173 | #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC (1 << 30) | 175 | #define FIMC_REG_CIIMGCPT_IMGCPTEN_SC BIT(30) |
| 174 | #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) | 176 | #define FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE BIT(25) |
| 175 | #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) | 177 | #define FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT BIT(18) |
| 176 | 178 | ||
| 177 | /* Frame capture sequence */ | 179 | /* Frame capture sequence */ |
| 178 | #define FIMC_REG_CICPTSEQ 0xc4 | 180 | #define FIMC_REG_CICPTSEQ 0xc4 |
| 179 | 181 | ||
| 180 | /* Image effect */ | 182 | /* Image effect */ |
| 181 | #define FIMC_REG_CIIMGEFF 0xd0 | 183 | #define FIMC_REG_CIIMGEFF 0xd0 |
| 182 | #define FIMC_REG_CIIMGEFF_IE_ENABLE (1 << 30) | 184 | #define FIMC_REG_CIIMGEFF_IE_ENABLE BIT(30) |
| 183 | #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29) | 185 | #define FIMC_REG_CIIMGEFF_IE_SC_BEFORE (0 << 29) |
| 184 | #define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29) | 186 | #define FIMC_REG_CIIMGEFF_IE_SC_AFTER (1 << 29) |
| 185 | #define FIMC_REG_CIIMGEFF_FIN_BYPASS (0 << 26) | 187 | #define FIMC_REG_CIIMGEFF_FIN_BYPASS (0 << 26) |
| @@ -198,8 +200,8 @@ | |||
| 198 | 200 | ||
| 199 | /* Real input DMA image size */ | 201 | /* Real input DMA image size */ |
| 200 | #define FIMC_REG_CIREAL_ISIZE 0xf8 | 202 | #define FIMC_REG_CIREAL_ISIZE 0xf8 |
| 201 | #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31) | 203 | #define FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN BIT(31) |
| 202 | #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30) | 204 | #define FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS BIT(30) |
| 203 | 205 | ||
| 204 | /* Input DMA control */ | 206 | /* Input DMA control */ |
| 205 | #define FIMC_REG_MSCTRL 0xfc | 207 | #define FIMC_REG_MSCTRL 0xfc |
| @@ -215,7 +217,7 @@ | |||
| 215 | #define FIMC_REG_MSCTRL_FLIP_X_MIRROR (1 << 13) | 217 | #define FIMC_REG_MSCTRL_FLIP_X_MIRROR (1 << 13) |
| 216 | #define FIMC_REG_MSCTRL_FLIP_Y_MIRROR (2 << 13) | 218 | #define FIMC_REG_MSCTRL_FLIP_Y_MIRROR (2 << 13) |
| 217 | #define FIMC_REG_MSCTRL_FLIP_180 (3 << 13) | 219 | #define FIMC_REG_MSCTRL_FLIP_180 (3 << 13) |
| 218 | #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL (1 << 12) | 220 | #define FIMC_REG_MSCTRL_FIFO_CTRL_FULL BIT(12) |
| 219 | #define FIMC_REG_MSCTRL_ORDER422_SHIFT 4 | 221 | #define FIMC_REG_MSCTRL_ORDER422_SHIFT 4 |
| 220 | #define FIMC_REG_MSCTRL_ORDER422_CRYCBY (0 << 4) | 222 | #define FIMC_REG_MSCTRL_ORDER422_CRYCBY (0 << 4) |
| 221 | #define FIMC_REG_MSCTRL_ORDER422_YCRYCB (1 << 4) | 223 | #define FIMC_REG_MSCTRL_ORDER422_YCRYCB (1 << 4) |
| @@ -223,14 +225,14 @@ | |||
| 223 | #define FIMC_REG_MSCTRL_ORDER422_YCBYCR (3 << 4) | 225 | #define FIMC_REG_MSCTRL_ORDER422_YCBYCR (3 << 4) |
| 224 | #define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4) | 226 | #define FIMC_REG_MSCTRL_ORDER422_MASK (3 << 4) |
| 225 | #define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3) | 227 | #define FIMC_REG_MSCTRL_INPUT_EXTCAM (0 << 3) |
| 226 | #define FIMC_REG_MSCTRL_INPUT_MEMORY (1 << 3) | 228 | #define FIMC_REG_MSCTRL_INPUT_MEMORY BIT(3) |
| 227 | #define FIMC_REG_MSCTRL_INPUT_MASK (1 << 3) | 229 | #define FIMC_REG_MSCTRL_INPUT_MASK BIT(3) |
| 228 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR420 (0 << 1) | 230 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR420 (0 << 1) |
| 229 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422 (1 << 1) | 231 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422 (1 << 1) |
| 230 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1) | 232 | #define FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1) |
| 231 | #define FIMC_REG_MSCTRL_INFORMAT_RGB (3 << 1) | 233 | #define FIMC_REG_MSCTRL_INFORMAT_RGB (3 << 1) |
| 232 | #define FIMC_REG_MSCTRL_INFORMAT_MASK (3 << 1) | 234 | #define FIMC_REG_MSCTRL_INFORMAT_MASK (3 << 1) |
| 233 | #define FIMC_REG_MSCTRL_ENVID (1 << 0) | 235 | #define FIMC_REG_MSCTRL_ENVID BIT(0) |
| 234 | #define FIMC_REG_MSCTRL_IN_BURST_COUNT(x) ((x) << 24) | 236 | #define FIMC_REG_MSCTRL_IN_BURST_COUNT(x) ((x) << 24) |
| 235 | 237 | ||
| 236 | /* Output DMA Y/Cb/Cr offset */ | 238 | /* Output DMA Y/Cb/Cr offset */ |
| @@ -277,10 +279,10 @@ | |||
| 277 | 279 | ||
| 278 | /* SYSREG ISP Writeback register address offsets */ | 280 | /* SYSREG ISP Writeback register address offsets */ |
| 279 | #define SYSREG_ISPBLK 0x020c | 281 | #define SYSREG_ISPBLK 0x020c |
| 280 | #define SYSREG_ISPBLK_FIFORST_CAM_BLK (1 << 7) | 282 | #define SYSREG_ISPBLK_FIFORST_CAM_BLK BIT(7) |
| 281 | 283 | ||
| 282 | #define SYSREG_CAMBLK 0x0218 | 284 | #define SYSREG_CAMBLK 0x0218 |
| 283 | #define SYSREG_CAMBLK_FIFORST_ISP (1 << 15) | 285 | #define SYSREG_CAMBLK_FIFORST_ISP BIT(15) |
| 284 | #define SYSREG_CAMBLK_ISPWB_FULL_EN (7 << 20) | 286 | #define SYSREG_CAMBLK_ISPWB_FULL_EN (7 << 20) |
| 285 | 287 | ||
| 286 | /* | 288 | /* |
diff --git a/drivers/media/platform/omap3isp/ispreg.h b/drivers/media/platform/omap3isp/ispreg.h index 38e2b99b3f10..86b6ebb0438d 100644 --- a/drivers/media/platform/omap3isp/ispreg.h +++ b/drivers/media/platform/omap3isp/ispreg.h | |||
| @@ -45,7 +45,7 @@ | |||
| 45 | 45 | ||
| 46 | #define ISPCCP2_REVISION (0x000) | 46 | #define ISPCCP2_REVISION (0x000) |
| 47 | #define ISPCCP2_SYSCONFIG (0x004) | 47 | #define ISPCCP2_SYSCONFIG (0x004) |
| 48 | #define ISPCCP2_SYSCONFIG_SOFT_RESET (1 << 1) | 48 | #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1) |
| 49 | #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1 | 49 | #define ISPCCP2_SYSCONFIG_AUTO_IDLE 0x1 |
| 50 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12 | 50 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12 |
| 51 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \ | 51 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE \ |
| @@ -55,44 +55,44 @@ | |||
| 55 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \ | 55 | #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART \ |
| 56 | (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) | 56 | (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
| 57 | #define ISPCCP2_SYSSTATUS (0x008) | 57 | #define ISPCCP2_SYSSTATUS (0x008) |
| 58 | #define ISPCCP2_SYSSTATUS_RESET_DONE (1 << 0) | 58 | #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0) |
| 59 | #define ISPCCP2_LC01_IRQENABLE (0x00C) | 59 | #define ISPCCP2_LC01_IRQENABLE (0x00C) |
| 60 | #define ISPCCP2_LC01_IRQSTATUS (0x010) | 60 | #define ISPCCP2_LC01_IRQSTATUS (0x010) |
| 61 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ (1 << 11) | 61 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11) |
| 62 | #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ (1 << 10) | 62 | #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10) |
| 63 | #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ (1 << 9) | 63 | #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9) |
| 64 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ (1 << 8) | 64 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8) |
| 65 | #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ (1 << 7) | 65 | #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7) |
| 66 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5) | 66 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5) |
| 67 | #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ (1 << 4) | 67 | #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ BIT(4) |
| 68 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ (1 << 3) | 68 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ BIT(3) |
| 69 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ (1 << 2) | 69 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ BIT(2) |
| 70 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ (1 << 1) | 70 | #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ BIT(1) |
| 71 | #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ (1 << 0) | 71 | #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ BIT(0) |
| 72 | 72 | ||
| 73 | #define ISPCCP2_LC23_IRQENABLE (0x014) | 73 | #define ISPCCP2_LC23_IRQENABLE (0x014) |
| 74 | #define ISPCCP2_LC23_IRQSTATUS (0x018) | 74 | #define ISPCCP2_LC23_IRQSTATUS (0x018) |
| 75 | #define ISPCCP2_LCM_IRQENABLE (0x02C) | 75 | #define ISPCCP2_LCM_IRQENABLE (0x02C) |
| 76 | #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ (1 << 0) | 76 | #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ BIT(0) |
| 77 | #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ (1 << 1) | 77 | #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ BIT(1) |
| 78 | #define ISPCCP2_LCM_IRQSTATUS (0x030) | 78 | #define ISPCCP2_LCM_IRQSTATUS (0x030) |
| 79 | #define ISPCCP2_CTRL (0x040) | 79 | #define ISPCCP2_CTRL (0x040) |
| 80 | #define ISPCCP2_CTRL_IF_EN (1 << 0) | 80 | #define ISPCCP2_CTRL_IF_EN BIT(0) |
| 81 | #define ISPCCP2_CTRL_PHY_SEL (1 << 1) | 81 | #define ISPCCP2_CTRL_PHY_SEL BIT(1) |
| 82 | #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1) | 82 | #define ISPCCP2_CTRL_PHY_SEL_CLOCK (0 << 1) |
| 83 | #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1) | 83 | #define ISPCCP2_CTRL_PHY_SEL_STROBE (1 << 1) |
| 84 | #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1 | 84 | #define ISPCCP2_CTRL_PHY_SEL_MASK 0x1 |
| 85 | #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1 | 85 | #define ISPCCP2_CTRL_PHY_SEL_SHIFT 1 |
| 86 | #define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2) | 86 | #define ISPCCP2_CTRL_IO_OUT_SEL BIT(2) |
| 87 | #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1 | 87 | #define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1 |
| 88 | #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2 | 88 | #define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2 |
| 89 | #define ISPCCP2_CTRL_MODE (1 << 4) | 89 | #define ISPCCP2_CTRL_MODE BIT(4) |
| 90 | #define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9) | 90 | #define ISPCCP2_CTRL_VP_CLK_FORCE_ON BIT(9) |
| 91 | #define ISPCCP2_CTRL_INV (1 << 10) | 91 | #define ISPCCP2_CTRL_INV BIT(10) |
| 92 | #define ISPCCP2_CTRL_INV_MASK 0x1 | 92 | #define ISPCCP2_CTRL_INV_MASK 0x1 |
| 93 | #define ISPCCP2_CTRL_INV_SHIFT 10 | 93 | #define ISPCCP2_CTRL_INV_SHIFT 10 |
| 94 | #define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11) | 94 | #define ISPCCP2_CTRL_VP_ONLY_EN BIT(11) |
| 95 | #define ISPCCP2_CTRL_VP_CLK_POL (1 << 12) | 95 | #define ISPCCP2_CTRL_VP_CLK_POL BIT(12) |
| 96 | #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1 | 96 | #define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1 |
| 97 | #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12 | 97 | #define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12 |
| 98 | #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15 | 98 | #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15 |
| @@ -102,12 +102,12 @@ | |||
| 102 | #define ISPCCP2_DBG (0x044) | 102 | #define ISPCCP2_DBG (0x044) |
| 103 | #define ISPCCP2_GNQ (0x048) | 103 | #define ISPCCP2_GNQ (0x048) |
| 104 | #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x)) | 104 | #define ISPCCP2_LCx_CTRL(x) ((0x050)+0x30*(x)) |
| 105 | #define ISPCCP2_LCx_CTRL_CHAN_EN (1 << 0) | 105 | #define ISPCCP2_LCx_CTRL_CHAN_EN BIT(0) |
| 106 | #define ISPCCP2_LCx_CTRL_CRC_EN (1 << 19) | 106 | #define ISPCCP2_LCx_CTRL_CRC_EN BIT(19) |
| 107 | #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1 | 107 | #define ISPCCP2_LCx_CTRL_CRC_MASK 0x1 |
| 108 | #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2 | 108 | #define ISPCCP2_LCx_CTRL_CRC_SHIFT 2 |
| 109 | #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19 | 109 | #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0 19 |
| 110 | #define ISPCCP2_LCx_CTRL_REGION_EN (1 << 1) | 110 | #define ISPCCP2_LCx_CTRL_REGION_EN BIT(1) |
| 111 | #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1 | 111 | #define ISPCCP2_LCx_CTRL_REGION_MASK 0x1 |
| 112 | #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1 | 112 | #define ISPCCP2_LCx_CTRL_REGION_SHIFT 1 |
| 113 | #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f | 113 | #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0 0x3f |
| @@ -127,8 +127,8 @@ | |||
| 127 | #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x)) | 127 | #define ISPCCP2_LCx_DAT_PONG_ADDR(x) ((0x074)+0x30*(x)) |
| 128 | #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x)) | 128 | #define ISPCCP2_LCx_DAT_OFST(x) ((0x078)+0x30*(x)) |
| 129 | #define ISPCCP2_LCM_CTRL (0x1D0) | 129 | #define ISPCCP2_LCM_CTRL (0x1D0) |
| 130 | #define ISPCCP2_LCM_CTRL_CHAN_EN (1 << 0) | 130 | #define ISPCCP2_LCM_CTRL_CHAN_EN BIT(0) |
| 131 | #define ISPCCP2_LCM_CTRL_DST_PORT (1 << 2) | 131 | #define ISPCCP2_LCM_CTRL_DST_PORT BIT(2) |
| 132 | #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2 | 132 | #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT 2 |
| 133 | #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3 | 133 | #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT 3 |
| 134 | #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11 | 134 | #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK 0x11 |
| @@ -138,8 +138,8 @@ | |||
| 138 | #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7 | 138 | #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK 0x7 |
| 139 | #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20 | 139 | #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT 20 |
| 140 | #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3 | 140 | #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK 0x3 |
| 141 | #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED (1 << 22) | 141 | #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED BIT(22) |
| 142 | #define ISPCCP2_LCM_CTRL_SRC_PACK (1 << 23) | 142 | #define ISPCCP2_LCM_CTRL_SRC_PACK BIT(23) |
| 143 | #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24 | 143 | #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT 24 |
| 144 | #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7 | 144 | #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK 0x7 |
| 145 | #define ISPCCP2_LCM_VSIZE (0x1D4) | 145 | #define ISPCCP2_LCM_VSIZE (0x1D4) |
| @@ -201,19 +201,19 @@ | |||
| 201 | 201 | ||
| 202 | /* SBL */ | 202 | /* SBL */ |
| 203 | #define ISPSBL_PCR 0x4 | 203 | #define ISPSBL_PCR 0x4 |
| 204 | #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF (1 << 16) | 204 | #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF BIT(16) |
| 205 | #define ISPSBL_PCR_H3A_AF_WBL_OVF (1 << 17) | 205 | #define ISPSBL_PCR_H3A_AF_WBL_OVF BIT(17) |
| 206 | #define ISPSBL_PCR_RSZ4_WBL_OVF (1 << 18) | 206 | #define ISPSBL_PCR_RSZ4_WBL_OVF BIT(18) |
| 207 | #define ISPSBL_PCR_RSZ3_WBL_OVF (1 << 19) | 207 | #define ISPSBL_PCR_RSZ3_WBL_OVF BIT(19) |
| 208 | #define ISPSBL_PCR_RSZ2_WBL_OVF (1 << 20) | 208 | #define ISPSBL_PCR_RSZ2_WBL_OVF BIT(20) |
| 209 | #define ISPSBL_PCR_RSZ1_WBL_OVF (1 << 21) | 209 | #define ISPSBL_PCR_RSZ1_WBL_OVF BIT(21) |
| 210 | #define ISPSBL_PCR_PRV_WBL_OVF (1 << 22) | 210 | #define ISPSBL_PCR_PRV_WBL_OVF BIT(22) |
| 211 | #define ISPSBL_PCR_CCDC_WBL_OVF (1 << 23) | 211 | #define ISPSBL_PCR_CCDC_WBL_OVF BIT(23) |
| 212 | #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF (1 << 24) | 212 | #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF BIT(24) |
| 213 | #define ISPSBL_PCR_CSIA_WBL_OVF (1 << 25) | 213 | #define ISPSBL_PCR_CSIA_WBL_OVF BIT(25) |
| 214 | #define ISPSBL_PCR_CSIB_WBL_OVF (1 << 26) | 214 | #define ISPSBL_PCR_CSIB_WBL_OVF BIT(26) |
| 215 | #define ISPSBL_CCDC_WR_0 (0x028) | 215 | #define ISPSBL_CCDC_WR_0 (0x028) |
| 216 | #define ISPSBL_CCDC_WR_0_DATA_READY (1 << 21) | 216 | #define ISPSBL_CCDC_WR_0_DATA_READY BIT(21) |
| 217 | #define ISPSBL_CCDC_WR_1 (0x02C) | 217 | #define ISPSBL_CCDC_WR_1 (0x02C) |
| 218 | #define ISPSBL_CCDC_WR_2 (0x030) | 218 | #define ISPSBL_CCDC_WR_2 (0x030) |
| 219 | #define ISPSBL_CCDC_WR_3 (0x034) | 219 | #define ISPSBL_CCDC_WR_3 (0x034) |
| @@ -366,16 +366,16 @@ | |||
| 366 | 366 | ||
| 367 | #define ISP_INT_CLR 0xFF113F11 | 367 | #define ISP_INT_CLR 0xFF113F11 |
| 368 | #define ISPPRV_PCR_EN 1 | 368 | #define ISPPRV_PCR_EN 1 |
| 369 | #define ISPPRV_PCR_BUSY (1 << 1) | 369 | #define ISPPRV_PCR_BUSY BIT(1) |
| 370 | #define ISPPRV_PCR_SOURCE (1 << 2) | 370 | #define ISPPRV_PCR_SOURCE BIT(2) |
| 371 | #define ISPPRV_PCR_ONESHOT (1 << 3) | 371 | #define ISPPRV_PCR_ONESHOT BIT(3) |
| 372 | #define ISPPRV_PCR_WIDTH (1 << 4) | 372 | #define ISPPRV_PCR_WIDTH BIT(4) |
| 373 | #define ISPPRV_PCR_INVALAW (1 << 5) | 373 | #define ISPPRV_PCR_INVALAW BIT(5) |
| 374 | #define ISPPRV_PCR_DRKFEN (1 << 6) | 374 | #define ISPPRV_PCR_DRKFEN BIT(6) |
| 375 | #define ISPPRV_PCR_DRKFCAP (1 << 7) | 375 | #define ISPPRV_PCR_DRKFCAP BIT(7) |
| 376 | #define ISPPRV_PCR_HMEDEN (1 << 8) | 376 | #define ISPPRV_PCR_HMEDEN BIT(8) |
| 377 | #define ISPPRV_PCR_NFEN (1 << 9) | 377 | #define ISPPRV_PCR_NFEN BIT(9) |
| 378 | #define ISPPRV_PCR_CFAEN (1 << 10) | 378 | #define ISPPRV_PCR_CFAEN BIT(10) |
| 379 | #define ISPPRV_PCR_CFAFMT_SHIFT 11 | 379 | #define ISPPRV_PCR_CFAFMT_SHIFT 11 |
| 380 | #define ISPPRV_PCR_CFAFMT_MASK 0x7800 | 380 | #define ISPPRV_PCR_CFAFMT_MASK 0x7800 |
| 381 | #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11) | 381 | #define ISPPRV_PCR_CFAFMT_BAYER (0 << 11) |
| @@ -384,22 +384,22 @@ | |||
| 384 | #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11) | 384 | #define ISPPRV_PCR_CFAFMT_DNSPL (3 << 11) |
| 385 | #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11) | 385 | #define ISPPRV_PCR_CFAFMT_HONEYCOMB (4 << 11) |
| 386 | #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11) | 386 | #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON (5 << 11) |
| 387 | #define ISPPRV_PCR_YNENHEN (1 << 15) | 387 | #define ISPPRV_PCR_YNENHEN BIT(15) |
| 388 | #define ISPPRV_PCR_SUPEN (1 << 16) | 388 | #define ISPPRV_PCR_SUPEN BIT(16) |
| 389 | #define ISPPRV_PCR_YCPOS_SHIFT 17 | 389 | #define ISPPRV_PCR_YCPOS_SHIFT 17 |
| 390 | #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17) | 390 | #define ISPPRV_PCR_YCPOS_YCrYCb (0 << 17) |
| 391 | #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17) | 391 | #define ISPPRV_PCR_YCPOS_YCbYCr (1 << 17) |
| 392 | #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17) | 392 | #define ISPPRV_PCR_YCPOS_CbYCrY (2 << 17) |
| 393 | #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17) | 393 | #define ISPPRV_PCR_YCPOS_CrYCbY (3 << 17) |
| 394 | #define ISPPRV_PCR_RSZPORT (1 << 19) | 394 | #define ISPPRV_PCR_RSZPORT BIT(19) |
| 395 | #define ISPPRV_PCR_SDRPORT (1 << 20) | 395 | #define ISPPRV_PCR_SDRPORT BIT(20) |
| 396 | #define ISPPRV_PCR_SCOMP_EN (1 << 21) | 396 | #define ISPPRV_PCR_SCOMP_EN BIT(21) |
| 397 | #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22) | 397 | #define ISPPRV_PCR_SCOMP_SFT_SHIFT (22) |
| 398 | #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22) | 398 | #define ISPPRV_PCR_SCOMP_SFT_MASK (7 << 22) |
| 399 | #define ISPPRV_PCR_GAMMA_BYPASS (1 << 26) | 399 | #define ISPPRV_PCR_GAMMA_BYPASS BIT(26) |
| 400 | #define ISPPRV_PCR_DCOREN (1 << 27) | 400 | #define ISPPRV_PCR_DCOREN BIT(27) |
| 401 | #define ISPPRV_PCR_DCCOUP (1 << 28) | 401 | #define ISPPRV_PCR_DCCOUP BIT(28) |
| 402 | #define ISPPRV_PCR_DRK_FAIL (1 << 31) | 402 | #define ISPPRV_PCR_DRK_FAIL BIT(31) |
| 403 | 403 | ||
| 404 | #define ISPPRV_HORZ_INFO_EPH_SHIFT 0 | 404 | #define ISPPRV_HORZ_INFO_EPH_SHIFT 0 |
| 405 | #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff | 405 | #define ISPPRV_HORZ_INFO_EPH_MASK 0x3fff |
| @@ -423,8 +423,8 @@ | |||
| 423 | #define ISPPRV_AVE_ODDDIST_4 0x3 | 423 | #define ISPPRV_AVE_ODDDIST_4 0x3 |
| 424 | 424 | ||
| 425 | #define ISPPRV_HMED_THRESHOLD_SHIFT 0 | 425 | #define ISPPRV_HMED_THRESHOLD_SHIFT 0 |
| 426 | #define ISPPRV_HMED_EVENDIST (1 << 8) | 426 | #define ISPPRV_HMED_EVENDIST BIT(8) |
| 427 | #define ISPPRV_HMED_ODDDIST (1 << 9) | 427 | #define ISPPRV_HMED_ODDDIST BIT(9) |
| 428 | 428 | ||
| 429 | #define ISPPRV_WBGAIN_COEF0_SHIFT 0 | 429 | #define ISPPRV_WBGAIN_COEF0_SHIFT 0 |
| 430 | #define ISPPRV_WBGAIN_COEF1_SHIFT 8 | 430 | #define ISPPRV_WBGAIN_COEF1_SHIFT 8 |
| @@ -517,8 +517,8 @@ | |||
| 517 | /* Define bit fields within selected registers */ | 517 | /* Define bit fields within selected registers */ |
| 518 | #define ISP_REVISION_SHIFT 0 | 518 | #define ISP_REVISION_SHIFT 0 |
| 519 | 519 | ||
| 520 | #define ISP_SYSCONFIG_AUTOIDLE (1 << 0) | 520 | #define ISP_SYSCONFIG_AUTOIDLE BIT(0) |
| 521 | #define ISP_SYSCONFIG_SOFTRESET (1 << 1) | 521 | #define ISP_SYSCONFIG_SOFTRESET BIT(1) |
| 522 | #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12 | 522 | #define ISP_SYSCONFIG_MIDLEMODE_SHIFT 12 |
| 523 | #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0 | 523 | #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY 0x0 |
| 524 | #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1 | 524 | #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY 0x1 |
| @@ -526,68 +526,68 @@ | |||
| 526 | 526 | ||
| 527 | #define ISP_SYSSTATUS_RESETDONE 0 | 527 | #define ISP_SYSSTATUS_RESETDONE 0 |
| 528 | 528 | ||
| 529 | #define IRQ0ENABLE_CSIA_IRQ (1 << 0) | 529 | #define IRQ0ENABLE_CSIA_IRQ BIT(0) |
| 530 | #define IRQ0ENABLE_CSIC_IRQ (1 << 1) | 530 | #define IRQ0ENABLE_CSIC_IRQ BIT(1) |
| 531 | #define IRQ0ENABLE_CCP2_LCM_IRQ (1 << 3) | 531 | #define IRQ0ENABLE_CCP2_LCM_IRQ BIT(3) |
| 532 | #define IRQ0ENABLE_CCP2_LC0_IRQ (1 << 4) | 532 | #define IRQ0ENABLE_CCP2_LC0_IRQ BIT(4) |
| 533 | #define IRQ0ENABLE_CCP2_LC1_IRQ (1 << 5) | 533 | #define IRQ0ENABLE_CCP2_LC1_IRQ BIT(5) |
| 534 | #define IRQ0ENABLE_CCP2_LC2_IRQ (1 << 6) | 534 | #define IRQ0ENABLE_CCP2_LC2_IRQ BIT(6) |
| 535 | #define IRQ0ENABLE_CCP2_LC3_IRQ (1 << 7) | 535 | #define IRQ0ENABLE_CCP2_LC3_IRQ BIT(7) |
| 536 | #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \ | 536 | #define IRQ0ENABLE_CSIB_IRQ (IRQ0ENABLE_CCP2_LCM_IRQ | \ |
| 537 | IRQ0ENABLE_CCP2_LC0_IRQ | \ | 537 | IRQ0ENABLE_CCP2_LC0_IRQ | \ |
| 538 | IRQ0ENABLE_CCP2_LC1_IRQ | \ | 538 | IRQ0ENABLE_CCP2_LC1_IRQ | \ |
| 539 | IRQ0ENABLE_CCP2_LC2_IRQ | \ | 539 | IRQ0ENABLE_CCP2_LC2_IRQ | \ |
| 540 | IRQ0ENABLE_CCP2_LC3_IRQ) | 540 | IRQ0ENABLE_CCP2_LC3_IRQ) |
| 541 | 541 | ||
| 542 | #define IRQ0ENABLE_CCDC_VD0_IRQ (1 << 8) | 542 | #define IRQ0ENABLE_CCDC_VD0_IRQ BIT(8) |
| 543 | #define IRQ0ENABLE_CCDC_VD1_IRQ (1 << 9) | 543 | #define IRQ0ENABLE_CCDC_VD1_IRQ BIT(9) |
| 544 | #define IRQ0ENABLE_CCDC_VD2_IRQ (1 << 10) | 544 | #define IRQ0ENABLE_CCDC_VD2_IRQ BIT(10) |
| 545 | #define IRQ0ENABLE_CCDC_ERR_IRQ (1 << 11) | 545 | #define IRQ0ENABLE_CCDC_ERR_IRQ BIT(11) |
| 546 | #define IRQ0ENABLE_H3A_AF_DONE_IRQ (1 << 12) | 546 | #define IRQ0ENABLE_H3A_AF_DONE_IRQ BIT(12) |
| 547 | #define IRQ0ENABLE_H3A_AWB_DONE_IRQ (1 << 13) | 547 | #define IRQ0ENABLE_H3A_AWB_DONE_IRQ BIT(13) |
| 548 | #define IRQ0ENABLE_HIST_DONE_IRQ (1 << 16) | 548 | #define IRQ0ENABLE_HIST_DONE_IRQ BIT(16) |
| 549 | #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ (1 << 17) | 549 | #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ BIT(17) |
| 550 | #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ (1 << 18) | 550 | #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ BIT(18) |
| 551 | #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ (1 << 19) | 551 | #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ BIT(19) |
| 552 | #define IRQ0ENABLE_PRV_DONE_IRQ (1 << 20) | 552 | #define IRQ0ENABLE_PRV_DONE_IRQ BIT(20) |
| 553 | #define IRQ0ENABLE_RSZ_DONE_IRQ (1 << 24) | 553 | #define IRQ0ENABLE_RSZ_DONE_IRQ BIT(24) |
| 554 | #define IRQ0ENABLE_OVF_IRQ (1 << 25) | 554 | #define IRQ0ENABLE_OVF_IRQ BIT(25) |
| 555 | #define IRQ0ENABLE_PING_IRQ (1 << 26) | 555 | #define IRQ0ENABLE_PING_IRQ BIT(26) |
| 556 | #define IRQ0ENABLE_PONG_IRQ (1 << 27) | 556 | #define IRQ0ENABLE_PONG_IRQ BIT(27) |
| 557 | #define IRQ0ENABLE_MMU_ERR_IRQ (1 << 28) | 557 | #define IRQ0ENABLE_MMU_ERR_IRQ BIT(28) |
| 558 | #define IRQ0ENABLE_OCP_ERR_IRQ (1 << 29) | 558 | #define IRQ0ENABLE_OCP_ERR_IRQ BIT(29) |
| 559 | #define IRQ0ENABLE_SEC_ERR_IRQ (1 << 30) | 559 | #define IRQ0ENABLE_SEC_ERR_IRQ BIT(30) |
| 560 | #define IRQ0ENABLE_HS_VS_IRQ (1 << 31) | 560 | #define IRQ0ENABLE_HS_VS_IRQ BIT(31) |
| 561 | 561 | ||
| 562 | #define IRQ0STATUS_CSIA_IRQ (1 << 0) | 562 | #define IRQ0STATUS_CSIA_IRQ BIT(0) |
| 563 | #define IRQ0STATUS_CSI2C_IRQ (1 << 1) | 563 | #define IRQ0STATUS_CSI2C_IRQ BIT(1) |
| 564 | #define IRQ0STATUS_CCP2_LCM_IRQ (1 << 3) | 564 | #define IRQ0STATUS_CCP2_LCM_IRQ BIT(3) |
| 565 | #define IRQ0STATUS_CCP2_LC0_IRQ (1 << 4) | 565 | #define IRQ0STATUS_CCP2_LC0_IRQ BIT(4) |
| 566 | #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \ | 566 | #define IRQ0STATUS_CSIB_IRQ (IRQ0STATUS_CCP2_LCM_IRQ | \ |
| 567 | IRQ0STATUS_CCP2_LC0_IRQ) | 567 | IRQ0STATUS_CCP2_LC0_IRQ) |
| 568 | 568 | ||
| 569 | #define IRQ0STATUS_CSIB_LC1_IRQ (1 << 5) | 569 | #define IRQ0STATUS_CSIB_LC1_IRQ BIT(5) |
| 570 | #define IRQ0STATUS_CSIB_LC2_IRQ (1 << 6) | 570 | #define IRQ0STATUS_CSIB_LC2_IRQ BIT(6) |
| 571 | #define IRQ0STATUS_CSIB_LC3_IRQ (1 << 7) | 571 | #define IRQ0STATUS_CSIB_LC3_IRQ BIT(7) |
| 572 | #define IRQ0STATUS_CCDC_VD0_IRQ (1 << 8) | 572 | #define IRQ0STATUS_CCDC_VD0_IRQ BIT(8) |
| 573 | #define IRQ0STATUS_CCDC_VD1_IRQ (1 << 9) | 573 | #define IRQ0STATUS_CCDC_VD1_IRQ BIT(9) |
| 574 | #define IRQ0STATUS_CCDC_VD2_IRQ (1 << 10) | 574 | #define IRQ0STATUS_CCDC_VD2_IRQ BIT(10) |
| 575 | #define IRQ0STATUS_CCDC_ERR_IRQ (1 << 11) | 575 | #define IRQ0STATUS_CCDC_ERR_IRQ BIT(11) |
| 576 | #define IRQ0STATUS_H3A_AF_DONE_IRQ (1 << 12) | 576 | #define IRQ0STATUS_H3A_AF_DONE_IRQ BIT(12) |
| 577 | #define IRQ0STATUS_H3A_AWB_DONE_IRQ (1 << 13) | 577 | #define IRQ0STATUS_H3A_AWB_DONE_IRQ BIT(13) |
| 578 | #define IRQ0STATUS_HIST_DONE_IRQ (1 << 16) | 578 | #define IRQ0STATUS_HIST_DONE_IRQ BIT(16) |
| 579 | #define IRQ0STATUS_CCDC_LSC_DONE_IRQ (1 << 17) | 579 | #define IRQ0STATUS_CCDC_LSC_DONE_IRQ BIT(17) |
| 580 | #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ (1 << 18) | 580 | #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ BIT(18) |
| 581 | #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ (1 << 19) | 581 | #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ BIT(19) |
| 582 | #define IRQ0STATUS_PRV_DONE_IRQ (1 << 20) | 582 | #define IRQ0STATUS_PRV_DONE_IRQ BIT(20) |
| 583 | #define IRQ0STATUS_RSZ_DONE_IRQ (1 << 24) | 583 | #define IRQ0STATUS_RSZ_DONE_IRQ BIT(24) |
| 584 | #define IRQ0STATUS_OVF_IRQ (1 << 25) | 584 | #define IRQ0STATUS_OVF_IRQ BIT(25) |
| 585 | #define IRQ0STATUS_PING_IRQ (1 << 26) | 585 | #define IRQ0STATUS_PING_IRQ BIT(26) |
| 586 | #define IRQ0STATUS_PONG_IRQ (1 << 27) | 586 | #define IRQ0STATUS_PONG_IRQ BIT(27) |
| 587 | #define IRQ0STATUS_MMU_ERR_IRQ (1 << 28) | 587 | #define IRQ0STATUS_MMU_ERR_IRQ BIT(28) |
| 588 | #define IRQ0STATUS_OCP_ERR_IRQ (1 << 29) | 588 | #define IRQ0STATUS_OCP_ERR_IRQ BIT(29) |
| 589 | #define IRQ0STATUS_SEC_ERR_IRQ (1 << 30) | 589 | #define IRQ0STATUS_SEC_ERR_IRQ BIT(30) |
| 590 | #define IRQ0STATUS_HS_VS_IRQ (1 << 31) | 590 | #define IRQ0STATUS_HS_VS_IRQ BIT(31) |
| 591 | 591 | ||
| 592 | #define TCTRL_GRESET_LEN 0 | 592 | #define TCTRL_GRESET_LEN 0 |
| 593 | 593 | ||
| @@ -607,20 +607,20 @@ | |||
| 607 | #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2) | 607 | #define ISPCTRL_PAR_BRIDGE_MASK (0x3 << 2) |
| 608 | 608 | ||
| 609 | #define ISPCTRL_PAR_CLK_POL_SHIFT 4 | 609 | #define ISPCTRL_PAR_CLK_POL_SHIFT 4 |
| 610 | #define ISPCTRL_PAR_CLK_POL_INV (1 << 4) | 610 | #define ISPCTRL_PAR_CLK_POL_INV BIT(4) |
| 611 | #define ISPCTRL_PING_PONG_EN (1 << 5) | 611 | #define ISPCTRL_PING_PONG_EN BIT(5) |
| 612 | #define ISPCTRL_SHIFT_SHIFT 6 | 612 | #define ISPCTRL_SHIFT_SHIFT 6 |
| 613 | #define ISPCTRL_SHIFT_0 (0x0 << 6) | 613 | #define ISPCTRL_SHIFT_0 (0x0 << 6) |
| 614 | #define ISPCTRL_SHIFT_2 (0x1 << 6) | 614 | #define ISPCTRL_SHIFT_2 (0x1 << 6) |
| 615 | #define ISPCTRL_SHIFT_4 (0x2 << 6) | 615 | #define ISPCTRL_SHIFT_4 (0x2 << 6) |
| 616 | #define ISPCTRL_SHIFT_MASK (0x3 << 6) | 616 | #define ISPCTRL_SHIFT_MASK (0x3 << 6) |
| 617 | 617 | ||
| 618 | #define ISPCTRL_CCDC_CLK_EN (1 << 8) | 618 | #define ISPCTRL_CCDC_CLK_EN BIT(8) |
| 619 | #define ISPCTRL_SCMP_CLK_EN (1 << 9) | 619 | #define ISPCTRL_SCMP_CLK_EN BIT(9) |
| 620 | #define ISPCTRL_H3A_CLK_EN (1 << 10) | 620 | #define ISPCTRL_H3A_CLK_EN BIT(10) |
| 621 | #define ISPCTRL_HIST_CLK_EN (1 << 11) | 621 | #define ISPCTRL_HIST_CLK_EN BIT(11) |
| 622 | #define ISPCTRL_PREV_CLK_EN (1 << 12) | 622 | #define ISPCTRL_PREV_CLK_EN BIT(12) |
| 623 | #define ISPCTRL_RSZ_CLK_EN (1 << 13) | 623 | #define ISPCTRL_RSZ_CLK_EN BIT(13) |
| 624 | #define ISPCTRL_SYNC_DETECT_SHIFT 14 | 624 | #define ISPCTRL_SYNC_DETECT_SHIFT 14 |
| 625 | #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT) | 625 | #define ISPCTRL_SYNC_DETECT_HSFALL (0x0 << ISPCTRL_SYNC_DETECT_SHIFT) |
| 626 | #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT) | 626 | #define ISPCTRL_SYNC_DETECT_HSRISE (0x1 << ISPCTRL_SYNC_DETECT_SHIFT) |
| @@ -628,17 +628,17 @@ | |||
| 628 | #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) | 628 | #define ISPCTRL_SYNC_DETECT_VSRISE (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) |
| 629 | #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) | 629 | #define ISPCTRL_SYNC_DETECT_MASK (0x3 << ISPCTRL_SYNC_DETECT_SHIFT) |
| 630 | 630 | ||
| 631 | #define ISPCTRL_CCDC_RAM_EN (1 << 16) | 631 | #define ISPCTRL_CCDC_RAM_EN BIT(16) |
| 632 | #define ISPCTRL_PREV_RAM_EN (1 << 17) | 632 | #define ISPCTRL_PREV_RAM_EN BIT(17) |
| 633 | #define ISPCTRL_SBL_RD_RAM_EN (1 << 18) | 633 | #define ISPCTRL_SBL_RD_RAM_EN BIT(18) |
| 634 | #define ISPCTRL_SBL_WR1_RAM_EN (1 << 19) | 634 | #define ISPCTRL_SBL_WR1_RAM_EN BIT(19) |
| 635 | #define ISPCTRL_SBL_WR0_RAM_EN (1 << 20) | 635 | #define ISPCTRL_SBL_WR0_RAM_EN BIT(20) |
| 636 | #define ISPCTRL_SBL_AUTOIDLE (1 << 21) | 636 | #define ISPCTRL_SBL_AUTOIDLE BIT(21) |
| 637 | #define ISPCTRL_SBL_SHARED_WPORTC (1 << 26) | 637 | #define ISPCTRL_SBL_SHARED_WPORTC BIT(26) |
| 638 | #define ISPCTRL_SBL_SHARED_RPORTA (1 << 27) | 638 | #define ISPCTRL_SBL_SHARED_RPORTA BIT(27) |
| 639 | #define ISPCTRL_SBL_SHARED_RPORTB (1 << 28) | 639 | #define ISPCTRL_SBL_SHARED_RPORTB BIT(28) |
| 640 | #define ISPCTRL_JPEG_FLUSH (1 << 30) | 640 | #define ISPCTRL_JPEG_FLUSH BIT(30) |
| 641 | #define ISPCTRL_CCDC_FLUSH (1 << 31) | 641 | #define ISPCTRL_CCDC_FLUSH BIT(31) |
| 642 | 642 | ||
| 643 | #define ISPSECURE_SECUREMODE 0 | 643 | #define ISPSECURE_SECUREMODE 0 |
| 644 | 644 | ||
| @@ -655,20 +655,20 @@ | |||
| 655 | #define ISPTCTRL_CTRL_DIVC_SHIFT 10 | 655 | #define ISPTCTRL_CTRL_DIVC_SHIFT 10 |
| 656 | #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10) | 656 | #define ISPTCTRL_CTRL_DIVC_NOCLOCK (0x0 << 10) |
| 657 | 657 | ||
| 658 | #define ISPTCTRL_CTRL_SHUTEN (1 << 21) | 658 | #define ISPTCTRL_CTRL_SHUTEN BIT(21) |
| 659 | #define ISPTCTRL_CTRL_PSTRBEN (1 << 22) | 659 | #define ISPTCTRL_CTRL_PSTRBEN BIT(22) |
| 660 | #define ISPTCTRL_CTRL_STRBEN (1 << 23) | 660 | #define ISPTCTRL_CTRL_STRBEN BIT(23) |
| 661 | #define ISPTCTRL_CTRL_SHUTPOL (1 << 24) | 661 | #define ISPTCTRL_CTRL_SHUTPOL BIT(24) |
| 662 | #define ISPTCTRL_CTRL_STRBPSTRBPOL (1 << 26) | 662 | #define ISPTCTRL_CTRL_STRBPSTRBPOL BIT(26) |
| 663 | 663 | ||
| 664 | #define ISPTCTRL_CTRL_INSEL_SHIFT 27 | 664 | #define ISPTCTRL_CTRL_INSEL_SHIFT 27 |
| 665 | #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27) | 665 | #define ISPTCTRL_CTRL_INSEL_PARALLEL (0x0 << 27) |
| 666 | #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27) | 666 | #define ISPTCTRL_CTRL_INSEL_CSIA (0x1 << 27) |
| 667 | #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27) | 667 | #define ISPTCTRL_CTRL_INSEL_CSIB (0x2 << 27) |
| 668 | 668 | ||
| 669 | #define ISPTCTRL_CTRL_GRESETEn (1 << 29) | 669 | #define ISPTCTRL_CTRL_GRESETEn BIT(29) |
| 670 | #define ISPTCTRL_CTRL_GRESETPOL (1 << 30) | 670 | #define ISPTCTRL_CTRL_GRESETPOL BIT(30) |
| 671 | #define ISPTCTRL_CTRL_GRESETDIR (1 << 31) | 671 | #define ISPTCTRL_CTRL_GRESETDIR BIT(31) |
| 672 | 672 | ||
| 673 | #define ISPTCTRL_FRAME_SHUT_SHIFT 0 | 673 | #define ISPTCTRL_FRAME_SHUT_SHIFT 0 |
| 674 | #define ISPTCTRL_FRAME_PSTRB_SHIFT 6 | 674 | #define ISPTCTRL_FRAME_PSTRB_SHIFT 6 |
| @@ -679,33 +679,33 @@ | |||
| 679 | #define ISPCCDC_PID_TID_SHIFT 16 | 679 | #define ISPCCDC_PID_TID_SHIFT 16 |
| 680 | 680 | ||
| 681 | #define ISPCCDC_PCR_EN 1 | 681 | #define ISPCCDC_PCR_EN 1 |
| 682 | #define ISPCCDC_PCR_BUSY (1 << 1) | 682 | #define ISPCCDC_PCR_BUSY BIT(1) |
| 683 | 683 | ||
| 684 | #define ISPCCDC_SYN_MODE_VDHDOUT 0x1 | 684 | #define ISPCCDC_SYN_MODE_VDHDOUT 0x1 |
| 685 | #define ISPCCDC_SYN_MODE_FLDOUT (1 << 1) | 685 | #define ISPCCDC_SYN_MODE_FLDOUT BIT(1) |
| 686 | #define ISPCCDC_SYN_MODE_VDPOL (1 << 2) | 686 | #define ISPCCDC_SYN_MODE_VDPOL BIT(2) |
| 687 | #define ISPCCDC_SYN_MODE_HDPOL (1 << 3) | 687 | #define ISPCCDC_SYN_MODE_HDPOL BIT(3) |
| 688 | #define ISPCCDC_SYN_MODE_FLDPOL (1 << 4) | 688 | #define ISPCCDC_SYN_MODE_FLDPOL BIT(4) |
| 689 | #define ISPCCDC_SYN_MODE_EXWEN (1 << 5) | 689 | #define ISPCCDC_SYN_MODE_EXWEN BIT(5) |
| 690 | #define ISPCCDC_SYN_MODE_DATAPOL (1 << 6) | 690 | #define ISPCCDC_SYN_MODE_DATAPOL BIT(6) |
| 691 | #define ISPCCDC_SYN_MODE_FLDMODE (1 << 7) | 691 | #define ISPCCDC_SYN_MODE_FLDMODE BIT(7) |
| 692 | #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8) | 692 | #define ISPCCDC_SYN_MODE_DATSIZ_MASK (0x7 << 8) |
| 693 | #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8) | 693 | #define ISPCCDC_SYN_MODE_DATSIZ_8_16 (0x0 << 8) |
| 694 | #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8) | 694 | #define ISPCCDC_SYN_MODE_DATSIZ_12 (0x4 << 8) |
| 695 | #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8) | 695 | #define ISPCCDC_SYN_MODE_DATSIZ_11 (0x5 << 8) |
| 696 | #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8) | 696 | #define ISPCCDC_SYN_MODE_DATSIZ_10 (0x6 << 8) |
| 697 | #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8) | 697 | #define ISPCCDC_SYN_MODE_DATSIZ_8 (0x7 << 8) |
| 698 | #define ISPCCDC_SYN_MODE_PACK8 (1 << 11) | 698 | #define ISPCCDC_SYN_MODE_PACK8 BIT(11) |
| 699 | #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12) | 699 | #define ISPCCDC_SYN_MODE_INPMOD_MASK (3 << 12) |
| 700 | #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12) | 700 | #define ISPCCDC_SYN_MODE_INPMOD_RAW (0 << 12) |
| 701 | #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12) | 701 | #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16 (1 << 12) |
| 702 | #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12) | 702 | #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8 (2 << 12) |
| 703 | #define ISPCCDC_SYN_MODE_LPF (1 << 14) | 703 | #define ISPCCDC_SYN_MODE_LPF BIT(14) |
| 704 | #define ISPCCDC_SYN_MODE_FLDSTAT (1 << 15) | 704 | #define ISPCCDC_SYN_MODE_FLDSTAT BIT(15) |
| 705 | #define ISPCCDC_SYN_MODE_VDHDEN (1 << 16) | 705 | #define ISPCCDC_SYN_MODE_VDHDEN BIT(16) |
| 706 | #define ISPCCDC_SYN_MODE_WEN (1 << 17) | 706 | #define ISPCCDC_SYN_MODE_WEN BIT(17) |
| 707 | #define ISPCCDC_SYN_MODE_VP2SDR (1 << 18) | 707 | #define ISPCCDC_SYN_MODE_VP2SDR BIT(18) |
| 708 | #define ISPCCDC_SYN_MODE_SDR2RSZ (1 << 19) | 708 | #define ISPCCDC_SYN_MODE_SDR2RSZ BIT(19) |
| 709 | 709 | ||
| 710 | #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0 | 710 | #define ISPCCDC_HD_VD_WID_VDW_SHIFT 0 |
| 711 | #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16 | 711 | #define ISPCCDC_HD_VD_WID_HDW_SHIFT 16 |
| @@ -731,7 +731,7 @@ | |||
| 731 | 731 | ||
| 732 | #define ISPCCDC_HSIZE_OFF_SHIFT 0 | 732 | #define ISPCCDC_HSIZE_OFF_SHIFT 0 |
| 733 | 733 | ||
| 734 | #define ISPCCDC_SDOFST_FIINV (1 << 14) | 734 | #define ISPCCDC_SDOFST_FIINV BIT(14) |
| 735 | #define ISPCCDC_SDOFST_FOFST_SHIFT 12 | 735 | #define ISPCCDC_SDOFST_FOFST_SHIFT 12 |
| 736 | #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12) | 736 | #define ISPCCDC_SDOFST_FOFST_MASK (3 << 12) |
| 737 | #define ISPCCDC_SDOFST_LOFST3_SHIFT 0 | 737 | #define ISPCCDC_SDOFST_LOFST3_SHIFT 0 |
| @@ -743,7 +743,7 @@ | |||
| 743 | #define ISPCCDC_CLAMP_OBST_SHIFT 10 | 743 | #define ISPCCDC_CLAMP_OBST_SHIFT 10 |
| 744 | #define ISPCCDC_CLAMP_OBSLN_SHIFT 25 | 744 | #define ISPCCDC_CLAMP_OBSLN_SHIFT 25 |
| 745 | #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28 | 745 | #define ISPCCDC_CLAMP_OBSLEN_SHIFT 28 |
| 746 | #define ISPCCDC_CLAMP_CLAMPEN (1 << 31) | 746 | #define ISPCCDC_CLAMP_CLAMPEN BIT(31) |
| 747 | 747 | ||
| 748 | #define ISPCCDC_COLPTN_R_Ye 0x0 | 748 | #define ISPCCDC_COLPTN_R_Ye 0x0 |
| 749 | #define ISPCCDC_COLPTN_Gr_Cy 0x1 | 749 | #define ISPCCDC_COLPTN_Gr_Cy 0x1 |
| @@ -772,8 +772,8 @@ | |||
| 772 | #define ISPCCDC_BLKCMP_R_YE_SHIFT 24 | 772 | #define ISPCCDC_BLKCMP_R_YE_SHIFT 24 |
| 773 | 773 | ||
| 774 | #define ISPCCDC_FPC_FPNUM_SHIFT 0 | 774 | #define ISPCCDC_FPC_FPNUM_SHIFT 0 |
| 775 | #define ISPCCDC_FPC_FPCEN (1 << 15) | 775 | #define ISPCCDC_FPC_FPCEN BIT(15) |
| 776 | #define ISPCCDC_FPC_FPERR (1 << 16) | 776 | #define ISPCCDC_FPC_FPERR BIT(16) |
| 777 | 777 | ||
| 778 | #define ISPCCDC_VDINT_1_SHIFT 0 | 778 | #define ISPCCDC_VDINT_1_SHIFT 0 |
| 779 | #define ISPCCDC_VDINT_1_MASK 0x00007fff | 779 | #define ISPCCDC_VDINT_1_MASK 0x00007fff |
| @@ -784,23 +784,23 @@ | |||
| 784 | #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0) | 784 | #define ISPCCDC_ALAW_GWDI_11_2 (0x4 << 0) |
| 785 | #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0) | 785 | #define ISPCCDC_ALAW_GWDI_10_1 (0x5 << 0) |
| 786 | #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0) | 786 | #define ISPCCDC_ALAW_GWDI_9_0 (0x6 << 0) |
| 787 | #define ISPCCDC_ALAW_CCDTBL (1 << 3) | 787 | #define ISPCCDC_ALAW_CCDTBL BIT(3) |
| 788 | 788 | ||
| 789 | #define ISPCCDC_REC656IF_R656ON 1 | 789 | #define ISPCCDC_REC656IF_R656ON 1 |
| 790 | #define ISPCCDC_REC656IF_ECCFVH (1 << 1) | 790 | #define ISPCCDC_REC656IF_ECCFVH BIT(1) |
| 791 | 791 | ||
| 792 | #define ISPCCDC_CFG_BW656 (1 << 5) | 792 | #define ISPCCDC_CFG_BW656 BIT(5) |
| 793 | #define ISPCCDC_CFG_FIDMD_SHIFT 6 | 793 | #define ISPCCDC_CFG_FIDMD_SHIFT 6 |
| 794 | #define ISPCCDC_CFG_WENLOG (1 << 8) | 794 | #define ISPCCDC_CFG_WENLOG BIT(8) |
| 795 | #define ISPCCDC_CFG_WENLOG_AND (0 << 8) | 795 | #define ISPCCDC_CFG_WENLOG_AND (0 << 8) |
| 796 | #define ISPCCDC_CFG_WENLOG_OR (1 << 8) | 796 | #define ISPCCDC_CFG_WENLOG_OR (1 << 8) |
| 797 | #define ISPCCDC_CFG_Y8POS (1 << 11) | 797 | #define ISPCCDC_CFG_Y8POS BIT(11) |
| 798 | #define ISPCCDC_CFG_BSWD (1 << 12) | 798 | #define ISPCCDC_CFG_BSWD BIT(12) |
| 799 | #define ISPCCDC_CFG_MSBINVI (1 << 13) | 799 | #define ISPCCDC_CFG_MSBINVI BIT(13) |
| 800 | #define ISPCCDC_CFG_VDLC (1 << 15) | 800 | #define ISPCCDC_CFG_VDLC BIT(15) |
| 801 | 801 | ||
| 802 | #define ISPCCDC_FMTCFG_FMTEN 0x1 | 802 | #define ISPCCDC_FMTCFG_FMTEN 0x1 |
| 803 | #define ISPCCDC_FMTCFG_LNALT (1 << 1) | 803 | #define ISPCCDC_FMTCFG_LNALT BIT(1) |
| 804 | #define ISPCCDC_FMTCFG_LNUM_SHIFT 2 | 804 | #define ISPCCDC_FMTCFG_LNUM_SHIFT 2 |
| 805 | #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4 | 805 | #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT 4 |
| 806 | #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8 | 806 | #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT 8 |
| @@ -809,7 +809,7 @@ | |||
| 809 | #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12) | 809 | #define ISPCCDC_FMTCFG_VPIN_11_2 (0x4 << 12) |
| 810 | #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12) | 810 | #define ISPCCDC_FMTCFG_VPIN_10_1 (0x5 << 12) |
| 811 | #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12) | 811 | #define ISPCCDC_FMTCFG_VPIN_9_0 (0x6 << 12) |
| 812 | #define ISPCCDC_FMTCFG_VPEN (1 << 15) | 812 | #define ISPCCDC_FMTCFG_VPEN BIT(15) |
| 813 | 813 | ||
| 814 | #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000 | 814 | #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK 0x003f0000 |
| 815 | #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16 | 815 | #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT 16 |
| @@ -839,9 +839,9 @@ | |||
| 839 | #define ISPRSZ_PID_CID_SHIFT 8 | 839 | #define ISPRSZ_PID_CID_SHIFT 8 |
| 840 | #define ISPRSZ_PID_TID_SHIFT 16 | 840 | #define ISPRSZ_PID_TID_SHIFT 16 |
| 841 | 841 | ||
| 842 | #define ISPRSZ_PCR_ENABLE (1 << 0) | 842 | #define ISPRSZ_PCR_ENABLE BIT(0) |
| 843 | #define ISPRSZ_PCR_BUSY (1 << 1) | 843 | #define ISPRSZ_PCR_BUSY BIT(1) |
| 844 | #define ISPRSZ_PCR_ONESHOT (1 << 2) | 844 | #define ISPRSZ_PCR_ONESHOT BIT(2) |
| 845 | 845 | ||
| 846 | #define ISPRSZ_CNT_HRSZ_SHIFT 0 | 846 | #define ISPRSZ_CNT_HRSZ_SHIFT 0 |
| 847 | #define ISPRSZ_CNT_HRSZ_MASK \ | 847 | #define ISPRSZ_CNT_HRSZ_MASK \ |
| @@ -853,10 +853,10 @@ | |||
| 853 | #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT) | 853 | #define ISPRSZ_CNT_HSTPH_MASK (0x7 << ISPRSZ_CNT_HSTPH_SHIFT) |
| 854 | #define ISPRSZ_CNT_VSTPH_SHIFT 23 | 854 | #define ISPRSZ_CNT_VSTPH_SHIFT 23 |
| 855 | #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT) | 855 | #define ISPRSZ_CNT_VSTPH_MASK (0x7 << ISPRSZ_CNT_VSTPH_SHIFT) |
| 856 | #define ISPRSZ_CNT_YCPOS (1 << 26) | 856 | #define ISPRSZ_CNT_YCPOS BIT(26) |
| 857 | #define ISPRSZ_CNT_INPTYP (1 << 27) | 857 | #define ISPRSZ_CNT_INPTYP BIT(27) |
| 858 | #define ISPRSZ_CNT_INPSRC (1 << 28) | 858 | #define ISPRSZ_CNT_INPSRC BIT(28) |
| 859 | #define ISPRSZ_CNT_CBILIN (1 << 29) | 859 | #define ISPRSZ_CNT_CBILIN BIT(29) |
| 860 | 860 | ||
| 861 | #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0 | 861 | #define ISPRSZ_OUT_SIZE_HORZ_SHIFT 0 |
| 862 | #define ISPRSZ_OUT_SIZE_HORZ_MASK \ | 862 | #define ISPRSZ_OUT_SIZE_HORZ_MASK \ |
| @@ -1081,8 +1081,8 @@ | |||
| 1081 | #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11 | 1081 | #define ISPH3A_PCR_AF_RGBPOS_SHIFT 11 |
| 1082 | #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22 | 1082 | #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT 22 |
| 1083 | #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000 | 1083 | #define ISPH3A_PCR_AEW_AVE2LMT_MASK 0xFFC00000 |
| 1084 | #define ISPH3A_PCR_BUSYAF (1 << 15) | 1084 | #define ISPH3A_PCR_BUSYAF BIT(15) |
| 1085 | #define ISPH3A_PCR_BUSYAEAWB (1 << 18) | 1085 | #define ISPH3A_PCR_BUSYAEAWB BIT(18) |
| 1086 | 1086 | ||
| 1087 | #define ISPH3A_AEWWIN1_WINHC_SHIFT 0 | 1087 | #define ISPH3A_AEWWIN1_WINHC_SHIFT 0 |
| 1088 | #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F | 1088 | #define ISPH3A_AEWWIN1_WINHC_MASK 0x3F |
| @@ -1166,15 +1166,15 @@ | |||
| 1166 | 1166 | ||
| 1167 | #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF | 1167 | #define ISPHIST_HV_INFO_MASK 0x3FFF3FFF |
| 1168 | 1168 | ||
| 1169 | #define ISPCCDC_LSC_ENABLE 1 | 1169 | #define ISPCCDC_LSC_ENABLE BIT(0) |
| 1170 | #define ISPCCDC_LSC_BUSY (1 << 7) | 1170 | #define ISPCCDC_LSC_BUSY BIT(7) |
| 1171 | #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700 | 1171 | #define ISPCCDC_LSC_GAIN_MODE_N_MASK 0x700 |
| 1172 | #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8 | 1172 | #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT 8 |
| 1173 | #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800 | 1173 | #define ISPCCDC_LSC_GAIN_MODE_M_MASK 0x3800 |
| 1174 | #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12 | 1174 | #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT 12 |
| 1175 | #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE | 1175 | #define ISPCCDC_LSC_GAIN_FORMAT_MASK 0xE |
| 1176 | #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1 | 1176 | #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT 1 |
| 1177 | #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK (1<<6) | 1177 | #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK BIT(6) |
| 1178 | 1178 | ||
| 1179 | #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F | 1179 | #define ISPCCDC_LSC_INITIAL_X_MASK 0x3F |
| 1180 | #define ISPCCDC_LSC_INITIAL_X_SHIFT 0 | 1180 | #define ISPCCDC_LSC_INITIAL_X_SHIFT 0 |
| @@ -1196,43 +1196,43 @@ | |||
| 1196 | (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) | 1196 | (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
| 1197 | #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \ | 1197 | #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART \ |
| 1198 | (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) | 1198 | (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT) |
| 1199 | #define ISPCSI2_SYSCONFIG_SOFT_RESET (1 << 1) | 1199 | #define ISPCSI2_SYSCONFIG_SOFT_RESET BIT(1) |
| 1200 | #define ISPCSI2_SYSCONFIG_AUTO_IDLE (1 << 0) | 1200 | #define ISPCSI2_SYSCONFIG_AUTO_IDLE BIT(0) |
| 1201 | 1201 | ||
| 1202 | #define ISPCSI2_SYSSTATUS (0x014) | 1202 | #define ISPCSI2_SYSSTATUS (0x014) |
| 1203 | #define ISPCSI2_SYSSTATUS_RESET_DONE (1 << 0) | 1203 | #define ISPCSI2_SYSSTATUS_RESET_DONE BIT(0) |
| 1204 | 1204 | ||
| 1205 | #define ISPCSI2_IRQSTATUS (0x018) | 1205 | #define ISPCSI2_IRQSTATUS (0x018) |
| 1206 | #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ (1 << 14) | 1206 | #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ BIT(14) |
| 1207 | #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ (1 << 13) | 1207 | #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ BIT(13) |
| 1208 | #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 12) | 1208 | #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ BIT(12) |
| 1209 | #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11) | 1209 | #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ BIT(11) |
| 1210 | #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ (1 << 10) | 1210 | #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ BIT(10) |
| 1211 | #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ (1 << 9) | 1211 | #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ BIT(9) |
| 1212 | #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ (1 << 8) | 1212 | #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ BIT(8) |
| 1213 | #define ISPCSI2_IRQSTATUS_CONTEXT(n) (1 << (n)) | 1213 | #define ISPCSI2_IRQSTATUS_CONTEXT(n) BIT(n) |
| 1214 | 1214 | ||
| 1215 | #define ISPCSI2_IRQENABLE (0x01c) | 1215 | #define ISPCSI2_IRQENABLE (0x01c) |
| 1216 | #define ISPCSI2_CTRL (0x040) | 1216 | #define ISPCSI2_CTRL (0x040) |
| 1217 | #define ISPCSI2_CTRL_VP_CLK_EN (1 << 15) | 1217 | #define ISPCSI2_CTRL_VP_CLK_EN BIT(15) |
| 1218 | #define ISPCSI2_CTRL_VP_ONLY_EN (1 << 11) | 1218 | #define ISPCSI2_CTRL_VP_ONLY_EN BIT(11) |
| 1219 | #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8 | 1219 | #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT 8 |
| 1220 | #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \ | 1220 | #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK \ |
| 1221 | (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) | 1221 | (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT) |
| 1222 | #define ISPCSI2_CTRL_DBG_EN (1 << 7) | 1222 | #define ISPCSI2_CTRL_DBG_EN BIT(7) |
| 1223 | #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5 | 1223 | #define ISPCSI2_CTRL_BURST_SIZE_SHIFT 5 |
| 1224 | #define ISPCSI2_CTRL_BURST_SIZE_MASK \ | 1224 | #define ISPCSI2_CTRL_BURST_SIZE_MASK \ |
| 1225 | (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT) | 1225 | (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT) |
| 1226 | #define ISPCSI2_CTRL_FRAME (1 << 3) | 1226 | #define ISPCSI2_CTRL_FRAME BIT(3) |
| 1227 | #define ISPCSI2_CTRL_ECC_EN (1 << 2) | 1227 | #define ISPCSI2_CTRL_ECC_EN BIT(2) |
| 1228 | #define ISPCSI2_CTRL_SECURE (1 << 1) | 1228 | #define ISPCSI2_CTRL_SECURE BIT(1) |
| 1229 | #define ISPCSI2_CTRL_IF_EN (1 << 0) | 1229 | #define ISPCSI2_CTRL_IF_EN BIT(0) |
| 1230 | 1230 | ||
| 1231 | #define ISPCSI2_DBG_H (0x044) | 1231 | #define ISPCSI2_DBG_H (0x044) |
| 1232 | #define ISPCSI2_GNQ (0x048) | 1232 | #define ISPCSI2_GNQ (0x048) |
| 1233 | #define ISPCSI2_PHY_CFG (0x050) | 1233 | #define ISPCSI2_PHY_CFG (0x050) |
| 1234 | #define ISPCSI2_PHY_CFG_RESET_CTRL (1 << 30) | 1234 | #define ISPCSI2_PHY_CFG_RESET_CTRL BIT(30) |
| 1235 | #define ISPCSI2_PHY_CFG_RESET_DONE (1 << 29) | 1235 | #define ISPCSI2_PHY_CFG_RESET_DONE BIT(29) |
| 1236 | #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27 | 1236 | #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT 27 |
| 1237 | #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \ | 1237 | #define ISPCSI2_PHY_CFG_PWR_CMD_MASK \ |
| 1238 | (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) | 1238 | (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT) |
| @@ -1251,7 +1251,7 @@ | |||
| 1251 | (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) | 1251 | (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
| 1252 | #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \ | 1252 | #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW \ |
| 1253 | (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) | 1253 | (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT) |
| 1254 | #define ISPCSI2_PHY_CFG_PWR_AUTO (1 << 24) | 1254 | #define ISPCSI2_PHY_CFG_PWR_AUTO BIT(24) |
| 1255 | 1255 | ||
| 1256 | #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4)) | 1256 | #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n) (3 + ((n) * 4)) |
| 1257 | #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \ | 1257 | #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n) \ |
| @@ -1300,63 +1300,63 @@ | |||
| 1300 | (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) | 1300 | (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT) |
| 1301 | 1301 | ||
| 1302 | #define ISPCSI2_PHY_IRQSTATUS (0x054) | 1302 | #define ISPCSI2_PHY_IRQSTATUS (0x054) |
| 1303 | #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT (1 << 26) | 1303 | #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT BIT(26) |
| 1304 | #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25) | 1304 | #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER BIT(25) |
| 1305 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 (1 << 24) | 1305 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5 BIT(24) |
| 1306 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 (1 << 23) | 1306 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4 BIT(23) |
| 1307 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 (1 << 22) | 1307 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3 BIT(22) |
| 1308 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 (1 << 21) | 1308 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2 BIT(21) |
| 1309 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 (1 << 20) | 1309 | #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1 BIT(20) |
| 1310 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 (1 << 19) | 1310 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5 BIT(19) |
| 1311 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 (1 << 18) | 1311 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4 BIT(18) |
| 1312 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 (1 << 17) | 1312 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3 BIT(17) |
| 1313 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 (1 << 16) | 1313 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2 BIT(16) |
| 1314 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 (1 << 15) | 1314 | #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1 BIT(15) |
| 1315 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 (1 << 14) | 1315 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC5 BIT(14) |
| 1316 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 (1 << 13) | 1316 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC4 BIT(13) |
| 1317 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 (1 << 12) | 1317 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC3 BIT(12) |
| 1318 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 (1 << 11) | 1318 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC2 BIT(11) |
| 1319 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 (1 << 10) | 1319 | #define ISPCSI2_PHY_IRQSTATUS_ERRESC1 BIT(10) |
| 1320 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 (1 << 9) | 1320 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5 BIT(9) |
| 1321 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 (1 << 8) | 1321 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4 BIT(8) |
| 1322 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 (1 << 7) | 1322 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3 BIT(7) |
| 1323 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 (1 << 6) | 1323 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2 BIT(6) |
| 1324 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 (1 << 5) | 1324 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1 BIT(5) |
| 1325 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 (1 << 4) | 1325 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5 BIT(4) |
| 1326 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 (1 << 3) | 1326 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4 BIT(3) |
| 1327 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 (1 << 2) | 1327 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3 BIT(2) |
| 1328 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 (1 << 1) | 1328 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2 BIT(1) |
| 1329 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 1 | 1329 | #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1 BIT(0) |
| 1330 | 1330 | ||
| 1331 | #define ISPCSI2_SHORT_PACKET (0x05c) | 1331 | #define ISPCSI2_SHORT_PACKET (0x05c) |
| 1332 | #define ISPCSI2_PHY_IRQENABLE (0x060) | 1332 | #define ISPCSI2_PHY_IRQENABLE (0x060) |
| 1333 | #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT (1 << 26) | 1333 | #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT BIT(26) |
| 1334 | #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25) | 1334 | #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER BIT(25) |
| 1335 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 (1 << 24) | 1335 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM5 BIT(24) |
| 1336 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 (1 << 23) | 1336 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM4 BIT(23) |
| 1337 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 (1 << 22) | 1337 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM3 BIT(22) |
| 1338 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 (1 << 21) | 1338 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM2 BIT(21) |
| 1339 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 (1 << 20) | 1339 | #define ISPCSI2_PHY_IRQENABLE_STATEULPM1 BIT(20) |
| 1340 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 (1 << 19) | 1340 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 BIT(19) |
| 1341 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 (1 << 18) | 1341 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 BIT(18) |
| 1342 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 (1 << 17) | 1342 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 BIT(17) |
| 1343 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 (1 << 16) | 1343 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 BIT(16) |
| 1344 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 (1 << 15) | 1344 | #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 BIT(15) |
| 1345 | #define ISPCSI2_PHY_IRQENABLE_ERRESC5 (1 << 14) | 1345 | #define ISPCSI2_PHY_IRQENABLE_ERRESC5 BIT(14) |
| 1346 | #define ISPCSI2_PHY_IRQENABLE_ERRESC4 (1 << 13) | 1346 | #define ISPCSI2_PHY_IRQENABLE_ERRESC4 BIT(13) |
| 1347 | #define ISPCSI2_PHY_IRQENABLE_ERRESC3 (1 << 12) | 1347 | #define ISPCSI2_PHY_IRQENABLE_ERRESC3 BIT(12) |
| 1348 | #define ISPCSI2_PHY_IRQENABLE_ERRESC2 (1 << 11) | 1348 | #define ISPCSI2_PHY_IRQENABLE_ERRESC2 BIT(11) |
| 1349 | #define ISPCSI2_PHY_IRQENABLE_ERRESC1 (1 << 10) | 1349 | #define ISPCSI2_PHY_IRQENABLE_ERRESC1 BIT(10) |
| 1350 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 (1 << 9) | 1350 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 BIT(9) |
| 1351 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 (1 << 8) | 1351 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 BIT(8) |
| 1352 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 (1 << 7) | 1352 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 BIT(7) |
| 1353 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 (1 << 6) | 1353 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 BIT(6) |
| 1354 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 (1 << 5) | 1354 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 BIT(5) |
| 1355 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 (1 << 4) | 1355 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 BIT(4) |
| 1356 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 (1 << 3) | 1356 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 BIT(3) |
| 1357 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 (1 << 2) | 1357 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 BIT(2) |
| 1358 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 (1 << 1) | 1358 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 BIT(1) |
| 1359 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 (1 << 0) | 1359 | #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1 BIT(0) |
| 1360 | 1360 | ||
| 1361 | #define ISPCSI2_DBG_P (0x068) | 1361 | #define ISPCSI2_DBG_P (0x068) |
| 1362 | #define ISPCSI2_TIMING (0x06c) | 1362 | #define ISPCSI2_TIMING (0x06c) |
| @@ -1371,12 +1371,12 @@ | |||
| 1371 | #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8 | 1371 | #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT 8 |
| 1372 | #define ISPCSI2_CTX_CTRL1_COUNT_MASK \ | 1372 | #define ISPCSI2_CTX_CTRL1_COUNT_MASK \ |
| 1373 | (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT) | 1373 | (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT) |
| 1374 | #define ISPCSI2_CTX_CTRL1_EOF_EN (1 << 7) | 1374 | #define ISPCSI2_CTX_CTRL1_EOF_EN BIT(7) |
| 1375 | #define ISPCSI2_CTX_CTRL1_EOL_EN (1 << 6) | 1375 | #define ISPCSI2_CTX_CTRL1_EOL_EN BIT(6) |
| 1376 | #define ISPCSI2_CTX_CTRL1_CS_EN (1 << 5) | 1376 | #define ISPCSI2_CTX_CTRL1_CS_EN BIT(5) |
| 1377 | #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK (1 << 4) | 1377 | #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK BIT(4) |
| 1378 | #define ISPCSI2_CTX_CTRL1_PING_PONG (1 << 3) | 1378 | #define ISPCSI2_CTX_CTRL1_PING_PONG BIT(3) |
| 1379 | #define ISPCSI2_CTX_CTRL1_CTX_EN (1 << 0) | 1379 | #define ISPCSI2_CTX_CTRL1_CTX_EN BIT(0) |
| 1380 | 1380 | ||
| 1381 | #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n)) | 1381 | #define ISPCSI2_CTX_CTRL2(n) ((0x074) + 0x20 * (n)) |
| 1382 | #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13 | 1382 | #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT 13 |
| @@ -1385,7 +1385,7 @@ | |||
| 1385 | #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11 | 1385 | #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT 11 |
| 1386 | #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \ | 1386 | #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK \ |
| 1387 | (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT) | 1387 | (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT) |
| 1388 | #define ISPCSI2_CTX_CTRL2_DPCM_PRED (1 << 10) | 1388 | #define ISPCSI2_CTX_CTRL2_DPCM_PRED BIT(10) |
| 1389 | #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0 | 1389 | #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT 0 |
| 1390 | #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \ | 1390 | #define ISPCSI2_CTX_CTRL2_FORMAT_MASK \ |
| 1391 | (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) | 1391 | (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT) |
| @@ -1401,24 +1401,24 @@ | |||
| 1401 | #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n)) | 1401 | #define ISPCSI2_CTX_DAT_PING_ADDR(n) ((0x07c) + 0x20 * (n)) |
| 1402 | #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n)) | 1402 | #define ISPCSI2_CTX_DAT_PONG_ADDR(n) ((0x080) + 0x20 * (n)) |
| 1403 | #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n)) | 1403 | #define ISPCSI2_CTX_IRQENABLE(n) ((0x084) + 0x20 * (n)) |
| 1404 | #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ (1 << 8) | 1404 | #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ BIT(8) |
| 1405 | #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ (1 << 7) | 1405 | #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ BIT(7) |
| 1406 | #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ (1 << 6) | 1406 | #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ BIT(6) |
| 1407 | #define ISPCSI2_CTX_IRQENABLE_CS_IRQ (1 << 5) | 1407 | #define ISPCSI2_CTX_IRQENABLE_CS_IRQ BIT(5) |
| 1408 | #define ISPCSI2_CTX_IRQENABLE_LE_IRQ (1 << 3) | 1408 | #define ISPCSI2_CTX_IRQENABLE_LE_IRQ BIT(3) |
| 1409 | #define ISPCSI2_CTX_IRQENABLE_LS_IRQ (1 << 2) | 1409 | #define ISPCSI2_CTX_IRQENABLE_LS_IRQ BIT(2) |
| 1410 | #define ISPCSI2_CTX_IRQENABLE_FE_IRQ (1 << 1) | 1410 | #define ISPCSI2_CTX_IRQENABLE_FE_IRQ BIT(1) |
| 1411 | #define ISPCSI2_CTX_IRQENABLE_FS_IRQ (1 << 0) | 1411 | #define ISPCSI2_CTX_IRQENABLE_FS_IRQ BIT(0) |
| 1412 | 1412 | ||
| 1413 | #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n)) | 1413 | #define ISPCSI2_CTX_IRQSTATUS(n) ((0x088) + 0x20 * (n)) |
| 1414 | #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ (1 << 8) | 1414 | #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ BIT(8) |
| 1415 | #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ (1 << 7) | 1415 | #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ BIT(7) |
| 1416 | #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ (1 << 6) | 1416 | #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ BIT(6) |
| 1417 | #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ (1 << 5) | 1417 | #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ BIT(5) |
| 1418 | #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ (1 << 3) | 1418 | #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ BIT(3) |
| 1419 | #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ (1 << 2) | 1419 | #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ BIT(2) |
| 1420 | #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ (1 << 1) | 1420 | #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ BIT(1) |
| 1421 | #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ (1 << 0) | 1421 | #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ BIT(0) |
| 1422 | 1422 | ||
| 1423 | #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n)) | 1423 | #define ISPCSI2_CTX_CTRL3(n) ((0x08c) + 0x20 * (n)) |
| 1424 | #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5 | 1424 | #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT 5 |
| @@ -1454,9 +1454,9 @@ | |||
| 1454 | (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT) | 1454 | (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT) |
| 1455 | 1455 | ||
| 1456 | #define ISPCSIPHY_REG1 (0x004) | 1456 | #define ISPCSIPHY_REG1 (0x004) |
| 1457 | #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK (1 << 29) | 1457 | #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK BIT(29) |
| 1458 | /* This field is for OMAP3630 only */ | 1458 | /* This field is for OMAP3630 only */ |
| 1459 | #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS (1 << 25) | 1459 | #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS BIT(25) |
| 1460 | #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18 | 1460 | #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT 18 |
| 1461 | #define ISPCSIPHY_REG1_TCLK_TERM_MASK \ | 1461 | #define ISPCSIPHY_REG1_TCLK_TERM_MASK \ |
| 1462 | (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT) | 1462 | (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT) |
| @@ -1498,11 +1498,11 @@ | |||
| 1498 | */ | 1498 | */ |
| 1499 | 1499 | ||
| 1500 | /* OMAP343X_CONTROL_CSIRXFE */ | 1500 | /* OMAP343X_CONTROL_CSIRXFE */ |
| 1501 | #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV (1 << 7) | 1501 | #define OMAP343X_CONTROL_CSIRXFE_CSIB_INV BIT(7) |
| 1502 | #define OMAP343X_CONTROL_CSIRXFE_RESENABLE (1 << 8) | 1502 | #define OMAP343X_CONTROL_CSIRXFE_RESENABLE BIT(8) |
| 1503 | #define OMAP343X_CONTROL_CSIRXFE_SELFORM (1 << 10) | 1503 | #define OMAP343X_CONTROL_CSIRXFE_SELFORM BIT(10) |
| 1504 | #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ (1 << 12) | 1504 | #define OMAP343X_CONTROL_CSIRXFE_PWRDNZ BIT(12) |
| 1505 | #define OMAP343X_CONTROL_CSIRXFE_RESET (1 << 13) | 1505 | #define OMAP343X_CONTROL_CSIRXFE_RESET BIT(13) |
| 1506 | 1506 | ||
| 1507 | /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */ | 1507 | /* OMAP3630_CONTROL_CAMERA_PHY_CTRL */ |
| 1508 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2 | 1508 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT 2 |
| @@ -1513,6 +1513,6 @@ | |||
| 1513 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3 | 1513 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI 0x3 |
| 1514 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3 | 1514 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK 0x3 |
| 1515 | /* CCP2B: set to receive data from PHY2 instead of PHY1 */ | 1515 | /* CCP2B: set to receive data from PHY2 instead of PHY1 */ |
| 1516 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 (1 << 4) | 1516 | #define OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2 BIT(4) |
| 1517 | 1517 | ||
| 1518 | #endif /* OMAP3_ISP_REG_H */ | 1518 | #endif /* OMAP3_ISP_REG_H */ |
diff --git a/drivers/media/platform/s3c-camif/camif-regs.h b/drivers/media/platform/s3c-camif/camif-regs.h index 29f839cdb486..052948a7b669 100644 --- a/drivers/media/platform/s3c-camif/camif-regs.h +++ b/drivers/media/platform/s3c-camif/camif-regs.h | |||
| @@ -9,6 +9,8 @@ | |||
| 9 | #ifndef CAMIF_REGS_H_ | 9 | #ifndef CAMIF_REGS_H_ |
| 10 | #define CAMIF_REGS_H_ | 10 | #define CAMIF_REGS_H_ |
| 11 | 11 | ||
| 12 | #include <linux/bitops.h> | ||
| 13 | |||
| 12 | #include "camif-core.h" | 14 | #include "camif-core.h" |
| 13 | #include <media/drv-intf/s3c_camif.h> | 15 | #include <media/drv-intf/s3c_camif.h> |
| 14 | 16 | ||
| @@ -19,7 +21,7 @@ | |||
| 19 | 21 | ||
| 20 | /* Camera input format */ | 22 | /* Camera input format */ |
| 21 | #define S3C_CAMIF_REG_CISRCFMT 0x00 | 23 | #define S3C_CAMIF_REG_CISRCFMT 0x00 |
| 22 | #define CISRCFMT_ITU601_8BIT (1 << 31) | 24 | #define CISRCFMT_ITU601_8BIT BIT(31) |
| 23 | #define CISRCFMT_ITU656_8BIT (0 << 31) | 25 | #define CISRCFMT_ITU656_8BIT (0 << 31) |
| 24 | #define CISRCFMT_ORDER422_YCBYCR (0 << 14) | 26 | #define CISRCFMT_ORDER422_YCBYCR (0 << 14) |
| 25 | #define CISRCFMT_ORDER422_YCRYCB (1 << 14) | 27 | #define CISRCFMT_ORDER422_YCRYCB (1 << 14) |
| @@ -30,14 +32,14 @@ | |||
| 30 | 32 | ||
| 31 | /* Window offset */ | 33 | /* Window offset */ |
| 32 | #define S3C_CAMIF_REG_CIWDOFST 0x04 | 34 | #define S3C_CAMIF_REG_CIWDOFST 0x04 |
| 33 | #define CIWDOFST_WINOFSEN (1 << 31) | 35 | #define CIWDOFST_WINOFSEN BIT(31) |
| 34 | #define CIWDOFST_CLROVCOFIY (1 << 30) | 36 | #define CIWDOFST_CLROVCOFIY BIT(30) |
| 35 | #define CIWDOFST_CLROVRLB_PR (1 << 28) | 37 | #define CIWDOFST_CLROVRLB_PR BIT(28) |
| 36 | /* #define CIWDOFST_CLROVPRFIY (1 << 27) */ | 38 | /* #define CIWDOFST_CLROVPRFIY BIT(27) */ |
| 37 | #define CIWDOFST_CLROVCOFICB (1 << 15) | 39 | #define CIWDOFST_CLROVCOFICB BIT(15) |
| 38 | #define CIWDOFST_CLROVCOFICR (1 << 14) | 40 | #define CIWDOFST_CLROVCOFICR BIT(14) |
| 39 | #define CIWDOFST_CLROVPRFICB (1 << 13) | 41 | #define CIWDOFST_CLROVPRFICB BIT(13) |
| 40 | #define CIWDOFST_CLROVPRFICR (1 << 12) | 42 | #define CIWDOFST_CLROVPRFICR BIT(12) |
| 41 | #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff) | 43 | #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff) |
| 42 | 44 | ||
| 43 | /* Window offset 2 */ | 45 | /* Window offset 2 */ |
| @@ -46,24 +48,24 @@ | |||
| 46 | 48 | ||
| 47 | /* Global control */ | 49 | /* Global control */ |
| 48 | #define S3C_CAMIF_REG_CIGCTRL 0x08 | 50 | #define S3C_CAMIF_REG_CIGCTRL 0x08 |
| 49 | #define CIGCTRL_SWRST (1 << 31) | 51 | #define CIGCTRL_SWRST BIT(31) |
| 50 | #define CIGCTRL_CAMRST (1 << 30) | 52 | #define CIGCTRL_CAMRST BIT(30) |
| 51 | #define CIGCTRL_TESTPATTERN_NORMAL (0 << 27) | 53 | #define CIGCTRL_TESTPATTERN_NORMAL (0 << 27) |
| 52 | #define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) | 54 | #define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) |
| 53 | #define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) | 55 | #define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) |
| 54 | #define CIGCTRL_TESTPATTERN_VER_INC (3 << 27) | 56 | #define CIGCTRL_TESTPATTERN_VER_INC (3 << 27) |
| 55 | #define CIGCTRL_TESTPATTERN_MASK (3 << 27) | 57 | #define CIGCTRL_TESTPATTERN_MASK (3 << 27) |
| 56 | #define CIGCTRL_INVPOLPCLK (1 << 26) | 58 | #define CIGCTRL_INVPOLPCLK BIT(26) |
| 57 | #define CIGCTRL_INVPOLVSYNC (1 << 25) | 59 | #define CIGCTRL_INVPOLVSYNC BIT(25) |
| 58 | #define CIGCTRL_INVPOLHREF (1 << 24) | 60 | #define CIGCTRL_INVPOLHREF BIT(24) |
| 59 | #define CIGCTRL_IRQ_OVFEN (1 << 22) | 61 | #define CIGCTRL_IRQ_OVFEN BIT(22) |
| 60 | #define CIGCTRL_HREF_MASK (1 << 21) | 62 | #define CIGCTRL_HREF_MASK BIT(21) |
| 61 | #define CIGCTRL_IRQ_LEVEL (1 << 20) | 63 | #define CIGCTRL_IRQ_LEVEL BIT(20) |
| 62 | /* IRQ_CLR_C, IRQ_CLR_P */ | 64 | /* IRQ_CLR_C, IRQ_CLR_P */ |
| 63 | #define CIGCTRL_IRQ_CLR(id) (1 << (19 - (id))) | 65 | #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) |
| 64 | #define CIGCTRL_FIELDMODE (1 << 2) | 66 | #define CIGCTRL_FIELDMODE BIT(2) |
| 65 | #define CIGCTRL_INVPOLFIELD (1 << 1) | 67 | #define CIGCTRL_INVPOLFIELD BIT(1) |
| 66 | #define CIGCTRL_CAM_INTERLACE (1 << 0) | 68 | #define CIGCTRL_CAM_INTERLACE BIT(0) |
| 67 | 69 | ||
| 68 | /* Y DMA output frame start address. n = 0..3. */ | 70 | /* Y DMA output frame start address. n = 0..3. */ |
| 69 | #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) | 71 | #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) |
| @@ -74,8 +76,8 @@ | |||
| 74 | 76 | ||
| 75 | /* CICOTRGFMT, CIPRTRGFMT - Target format */ | 77 | /* CICOTRGFMT, CIPRTRGFMT - Target format */ |
| 76 | #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) | 78 | #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) |
| 77 | #define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */ | 79 | #define CITRGFMT_IN422 BIT(31) /* only for s3c24xx */ |
| 78 | #define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */ | 80 | #define CITRGFMT_OUT422 BIT(30) /* only for s3c24xx */ |
| 79 | #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */ | 81 | #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */ |
| 80 | #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */ | 82 | #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */ |
| 81 | #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */ | 83 | #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */ |
| @@ -88,7 +90,7 @@ | |||
| 88 | #define CITRGFMT_FLIP_180 (3 << 14) | 90 | #define CITRGFMT_FLIP_180 (3 << 14) |
| 89 | #define CITRGFMT_FLIP_MASK (3 << 14) | 91 | #define CITRGFMT_FLIP_MASK (3 << 14) |
| 90 | /* Preview path only */ | 92 | /* Preview path only */ |
| 91 | #define CITRGFMT_ROT90_PR (1 << 13) | 93 | #define CITRGFMT_ROT90_PR BIT(13) |
| 92 | #define CITRGFMT_TARGETVSIZE(x) ((x) << 0) | 94 | #define CITRGFMT_TARGETVSIZE(x) ((x) << 0) |
| 93 | #define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff) | 95 | #define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff) |
| 94 | 96 | ||
| @@ -102,7 +104,7 @@ | |||
| 102 | #define CICTRL_RGBBURST2(x) ((x) << 14) | 104 | #define CICTRL_RGBBURST2(x) ((x) << 14) |
| 103 | #define CICTRL_CBURST1(x) ((x) << 9) | 105 | #define CICTRL_CBURST1(x) ((x) << 9) |
| 104 | #define CICTRL_CBURST2(x) ((x) << 4) | 106 | #define CICTRL_CBURST2(x) ((x) << 4) |
| 105 | #define CICTRL_LASTIRQ_ENABLE (1 << 2) | 107 | #define CICTRL_LASTIRQ_ENABLE BIT(2) |
| 106 | #define CICTRL_ORDER422_MASK (3 << 0) | 108 | #define CICTRL_ORDER422_MASK (3 << 0) |
| 107 | 109 | ||
| 108 | /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */ | 110 | /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */ |
| @@ -113,22 +115,22 @@ | |||
| 113 | 115 | ||
| 114 | /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */ | 116 | /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */ |
| 115 | #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) | 117 | #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) |
| 116 | #define CISCCTRL_SCALERBYPASS (1 << 31) | 118 | #define CISCCTRL_SCALERBYPASS BIT(31) |
| 117 | /* s3c244x preview path only, s3c64xx both */ | 119 | /* s3c244x preview path only, s3c64xx both */ |
| 118 | #define CIPRSCCTRL_SAMPLE (1 << 31) | 120 | #define CIPRSCCTRL_SAMPLE BIT(31) |
| 119 | /* 0 - 16-bit RGB, 1 - 24-bit RGB */ | 121 | /* 0 - 16-bit RGB, 1 - 24-bit RGB */ |
| 120 | #define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */ | 122 | #define CIPRSCCTRL_RGB_FORMAT_24BIT BIT(30) /* only for s3c244x */ |
| 121 | #define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */ | 123 | #define CIPRSCCTRL_SCALEUP_H BIT(29) /* only for s3c244x */ |
| 122 | #define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */ | 124 | #define CIPRSCCTRL_SCALEUP_V BIT(28) /* only for s3c244x */ |
| 123 | /* s3c64xx */ | 125 | /* s3c64xx */ |
| 124 | #define CISCCTRL_SCALEUP_H (1 << 30) | 126 | #define CISCCTRL_SCALEUP_H BIT(30) |
| 125 | #define CISCCTRL_SCALEUP_V (1 << 29) | 127 | #define CISCCTRL_SCALEUP_V BIT(29) |
| 126 | #define CISCCTRL_SCALEUP_MASK (0x3 << 29) | 128 | #define CISCCTRL_SCALEUP_MASK (0x3 << 29) |
| 127 | #define CISCCTRL_CSCR2Y_WIDE (1 << 28) | 129 | #define CISCCTRL_CSCR2Y_WIDE BIT(28) |
| 128 | #define CISCCTRL_CSCY2R_WIDE (1 << 27) | 130 | #define CISCCTRL_CSCY2R_WIDE BIT(27) |
| 129 | #define CISCCTRL_LCDPATHEN_FIFO (1 << 26) | 131 | #define CISCCTRL_LCDPATHEN_FIFO BIT(26) |
| 130 | #define CISCCTRL_INTERLACE (1 << 25) | 132 | #define CISCCTRL_INTERLACE BIT(25) |
| 131 | #define CISCCTRL_SCALERSTART (1 << 15) | 133 | #define CISCCTRL_SCALERSTART BIT(15) |
| 132 | #define CISCCTRL_INRGB_FMT_RGB565 (0 << 13) | 134 | #define CISCCTRL_INRGB_FMT_RGB565 (0 << 13) |
| 133 | #define CISCCTRL_INRGB_FMT_RGB666 (1 << 13) | 135 | #define CISCCTRL_INRGB_FMT_RGB666 (1 << 13) |
| 134 | #define CISCCTRL_INRGB_FMT_RGB888 (2 << 13) | 136 | #define CISCCTRL_INRGB_FMT_RGB888 (2 << 13) |
| @@ -137,8 +139,8 @@ | |||
| 137 | #define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) | 139 | #define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) |
| 138 | #define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) | 140 | #define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) |
| 139 | #define CISCCTRL_OUTRGB_FMT_MASK (3 << 11) | 141 | #define CISCCTRL_OUTRGB_FMT_MASK (3 << 11) |
| 140 | #define CISCCTRL_EXTRGB_EXTENSION (1 << 10) | 142 | #define CISCCTRL_EXTRGB_EXTENSION BIT(10) |
| 141 | #define CISCCTRL_ONE2ONE (1 << 9) | 143 | #define CISCCTRL_ONE2ONE BIT(9) |
| 142 | #define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff) | 144 | #define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff) |
| 143 | 145 | ||
| 144 | /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */ | 146 | /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */ |
| @@ -147,38 +149,38 @@ | |||
| 147 | 149 | ||
| 148 | /* Codec (id = 0) or preview (id = 1) path status. */ | 150 | /* Codec (id = 0) or preview (id = 1) path status. */ |
| 149 | #define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs))) | 151 | #define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs))) |
| 150 | #define CISTATUS_OVFIY_STATUS (1 << 31) | 152 | #define CISTATUS_OVFIY_STATUS BIT(31) |
| 151 | #define CISTATUS_OVFICB_STATUS (1 << 30) | 153 | #define CISTATUS_OVFICB_STATUS BIT(30) |
| 152 | #define CISTATUS_OVFICR_STATUS (1 << 29) | 154 | #define CISTATUS_OVFICR_STATUS BIT(29) |
| 153 | #define CISTATUS_OVF_MASK (0x7 << 29) | 155 | #define CISTATUS_OVF_MASK (0x7 << 29) |
| 154 | #define CIPRSTATUS_OVF_MASK (0x3 << 30) | 156 | #define CIPRSTATUS_OVF_MASK (0x3 << 30) |
| 155 | #define CISTATUS_VSYNC_STATUS (1 << 28) | 157 | #define CISTATUS_VSYNC_STATUS BIT(28) |
| 156 | #define CISTATUS_FRAMECNT_MASK (3 << 26) | 158 | #define CISTATUS_FRAMECNT_MASK (3 << 26) |
| 157 | #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) | 159 | #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) |
| 158 | #define CISTATUS_WINOFSTEN_STATUS (1 << 25) | 160 | #define CISTATUS_WINOFSTEN_STATUS BIT(25) |
| 159 | #define CISTATUS_IMGCPTEN_STATUS (1 << 22) | 161 | #define CISTATUS_IMGCPTEN_STATUS BIT(22) |
| 160 | #define CISTATUS_IMGCPTENSC_STATUS (1 << 21) | 162 | #define CISTATUS_IMGCPTENSC_STATUS BIT(21) |
| 161 | #define CISTATUS_VSYNC_A_STATUS (1 << 20) | 163 | #define CISTATUS_VSYNC_A_STATUS BIT(20) |
| 162 | #define CISTATUS_FRAMEEND_STATUS (1 << 19) /* 17 on s3c64xx */ | 164 | #define CISTATUS_FRAMEEND_STATUS BIT(19) /* 17 on s3c64xx */ |
| 163 | 165 | ||
| 164 | /* Image capture enable */ | 166 | /* Image capture enable */ |
| 165 | #define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs)) | 167 | #define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs)) |
| 166 | #define CIIMGCPT_IMGCPTEN (1 << 31) | 168 | #define CIIMGCPT_IMGCPTEN BIT(31) |
| 167 | #define CIIMGCPT_IMGCPTEN_SC(id) (1 << (30 - (id))) | 169 | #define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id)) |
| 168 | /* Frame control: 1 - one-shot, 0 - free run */ | 170 | /* Frame control: 1 - one-shot, 0 - free run */ |
| 169 | #define CIIMGCPT_CPT_FREN_ENABLE(id) (1 << (25 - (id))) | 171 | #define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id)) |
| 170 | #define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18) | 172 | #define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18) |
| 171 | #define CIIMGCPT_CPT_FRMOD_CNT (1 << 18) | 173 | #define CIIMGCPT_CPT_FRMOD_CNT BIT(18) |
| 172 | 174 | ||
| 173 | /* Capture sequence */ | 175 | /* Capture sequence */ |
| 174 | #define S3C_CAMIF_REG_CICPTSEQ 0xc4 | 176 | #define S3C_CAMIF_REG_CICPTSEQ 0xc4 |
| 175 | 177 | ||
| 176 | /* Image effects */ | 178 | /* Image effects */ |
| 177 | #define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs)) | 179 | #define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs)) |
| 178 | #define CIIMGEFF_IE_ENABLE(id) (1 << (30 + (id))) | 180 | #define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id)) |
| 179 | #define CIIMGEFF_IE_ENABLE_MASK (3 << 30) | 181 | #define CIIMGEFF_IE_ENABLE_MASK (3 << 30) |
| 180 | /* Image effect: 1 - after scaler, 0 - before scaler */ | 182 | /* Image effect: 1 - after scaler, 0 - before scaler */ |
| 181 | #define CIIMGEFF_IE_AFTER_SC (1 << 29) | 183 | #define CIIMGEFF_IE_AFTER_SC BIT(29) |
| 182 | #define CIIMGEFF_FIN_MASK (7 << 26) | 184 | #define CIIMGEFF_FIN_MASK (7 << 26) |
| 183 | #define CIIMGEFF_FIN_BYPASS (0 << 26) | 185 | #define CIIMGEFF_FIN_BYPASS (0 << 26) |
| 184 | #define CIIMGEFF_FIN_ARBITRARY (1 << 26) | 186 | #define CIIMGEFF_FIN_ARBITRARY (1 << 26) |
| @@ -207,8 +209,8 @@ | |||
| 207 | 209 | ||
| 208 | /* Real input DMA data size. n = 0 - codec, 1 - preview. */ | 210 | /* Real input DMA data size. n = 0 - codec, 1 - preview. */ |
| 209 | #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c) | 211 | #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c) |
| 210 | #define AUTOLOAD_ENABLE (1 << 31) | 212 | #define AUTOLOAD_ENABLE BIT(31) |
| 211 | #define ADDR_CH_DIS (1 << 30) | 213 | #define ADDR_CH_DIS BIT(30) |
| 212 | #define MSHEIGHT(x) (((x) & 0x3ff) << 16) | 214 | #define MSHEIGHT(x) (((x) & 0x3ff) << 16) |
| 213 | #define MSWIDTH(x) ((x) & 0x3ff) | 215 | #define MSWIDTH(x) ((x) & 0x3ff) |
| 214 | 216 | ||
| @@ -219,12 +221,12 @@ | |||
| 219 | #define MSCTRL_ORDER422_M_CBYCRY (2 << 4) | 221 | #define MSCTRL_ORDER422_M_CBYCRY (2 << 4) |
| 220 | #define MSCTRL_ORDER422_M_CRYCBY (3 << 4) | 222 | #define MSCTRL_ORDER422_M_CRYCBY (3 << 4) |
| 221 | /* 0 - camera, 1 - DMA */ | 223 | /* 0 - camera, 1 - DMA */ |
| 222 | #define MSCTRL_SEL_DMA_CAM (1 << 3) | 224 | #define MSCTRL_SEL_DMA_CAM BIT(3) |
| 223 | #define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1) | 225 | #define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1) |
| 224 | #define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1) | 226 | #define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1) |
| 225 | #define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1) | 227 | #define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1) |
| 226 | #define MSCTRL_INFORMAT_M_RGB (3 << 1) | 228 | #define MSCTRL_INFORMAT_M_RGB (3 << 1) |
| 227 | #define MSCTRL_ENVID_M (1 << 0) | 229 | #define MSCTRL_ENVID_M BIT(0) |
| 228 | 230 | ||
| 229 | /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */ | 231 | /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */ |
| 230 | #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c) | 232 | #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c) |
diff --git a/drivers/media/platform/tegra-cec/tegra_cec.h b/drivers/media/platform/tegra-cec/tegra_cec.h index 32d7d69f9491..8c370be38e1e 100644 --- a/drivers/media/platform/tegra-cec/tegra_cec.h +++ b/drivers/media/platform/tegra-cec/tegra_cec.h | |||
| @@ -34,24 +34,24 @@ | |||
| 34 | #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff | 34 | #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff |
| 35 | #define TEGRA_CEC_HWCTRL_RX_LADDR(x) \ | 35 | #define TEGRA_CEC_HWCTRL_RX_LADDR(x) \ |
| 36 | ((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK) | 36 | ((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK) |
| 37 | #define TEGRA_CEC_HWCTRL_RX_SNOOP (1 << 15) | 37 | #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15) |
| 38 | #define TEGRA_CEC_HWCTRL_RX_NAK_MODE (1 << 16) | 38 | #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16) |
| 39 | #define TEGRA_CEC_HWCTRL_TX_NAK_MODE (1 << 24) | 39 | #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24) |
| 40 | #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE (1 << 30) | 40 | #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30) |
| 41 | #define TEGRA_CEC_HWCTRL_TX_RX_MODE (1 << 31) | 41 | #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31) |
| 42 | 42 | ||
| 43 | #define TEGRA_CEC_INPUT_FILTER_MODE (1 << 31) | 43 | #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31) |
| 44 | #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0 | 44 | #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0 |
| 45 | 45 | ||
| 46 | #define TEGRA_CEC_TX_REG_DATA_SHIFT 0 | 46 | #define TEGRA_CEC_TX_REG_DATA_SHIFT 0 |
| 47 | #define TEGRA_CEC_TX_REG_EOM (1 << 8) | 47 | #define TEGRA_CEC_TX_REG_EOM BIT(8) |
| 48 | #define TEGRA_CEC_TX_REG_BCAST (1 << 12) | 48 | #define TEGRA_CEC_TX_REG_BCAST BIT(12) |
| 49 | #define TEGRA_CEC_TX_REG_START_BIT (1 << 16) | 49 | #define TEGRA_CEC_TX_REG_START_BIT BIT(16) |
| 50 | #define TEGRA_CEC_TX_REG_RETRY (1 << 17) | 50 | #define TEGRA_CEC_TX_REG_RETRY BIT(17) |
| 51 | 51 | ||
| 52 | #define TEGRA_CEC_RX_REGISTER_SHIFT 0 | 52 | #define TEGRA_CEC_RX_REGISTER_SHIFT 0 |
| 53 | #define TEGRA_CEC_RX_REGISTER_EOM (1 << 8) | 53 | #define TEGRA_CEC_RX_REGISTER_EOM BIT(8) |
| 54 | #define TEGRA_CEC_RX_REGISTER_ACK (1 << 9) | 54 | #define TEGRA_CEC_RX_REGISTER_ACK BIT(9) |
| 55 | 55 | ||
| 56 | #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0 | 56 | #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0 |
| 57 | #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8 | 57 | #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8 |
| @@ -79,38 +79,38 @@ | |||
| 79 | #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT 4 | 79 | #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT 4 |
| 80 | #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8 | 80 | #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8 |
| 81 | 81 | ||
| 82 | #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY (1 << 0) | 82 | #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY BIT(0) |
| 83 | #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (1 << 1) | 83 | #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN BIT(1) |
| 84 | #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD (1 << 2) | 84 | #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD BIT(2) |
| 85 | #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED (1 << 3) | 85 | #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED BIT(3) |
| 86 | #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED (1 << 4) | 86 | #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED BIT(4) |
| 87 | #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED (1 << 5) | 87 | #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED BIT(5) |
| 88 | #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL (1 << 8) | 88 | #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL BIT(8) |
| 89 | #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN (1 << 9) | 89 | #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN BIT(9) |
| 90 | #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED (1 << 10) | 90 | #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED BIT(10) |
| 91 | #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED (1 << 11) | 91 | #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED BIT(11) |
| 92 | #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED (1 << 12) | 92 | #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED BIT(12) |
| 93 | #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) | 93 | #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13) |
| 94 | #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) | 94 | #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14) |
| 95 | 95 | ||
| 96 | #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY (1 << 0) | 96 | #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY BIT(0) |
| 97 | #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN (1 << 1) | 97 | #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN BIT(1) |
| 98 | #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD (1 << 2) | 98 | #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD BIT(2) |
| 99 | #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED (1 << 3) | 99 | #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED BIT(3) |
| 100 | #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED (1 << 4) | 100 | #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED BIT(4) |
| 101 | #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED (1 << 5) | 101 | #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED BIT(5) |
| 102 | #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL (1 << 8) | 102 | #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL BIT(8) |
| 103 | #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN (1 << 9) | 103 | #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN BIT(9) |
| 104 | #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED (1 << 10) | 104 | #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED BIT(10) |
| 105 | #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED (1 << 11) | 105 | #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED BIT(11) |
| 106 | #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED (1 << 12) | 106 | #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED BIT(12) |
| 107 | #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) | 107 | #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13) |
| 108 | #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) | 108 | #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14) |
| 109 | 109 | ||
| 110 | #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0 | 110 | #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0 |
| 111 | #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT 17 | 111 | #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT 17 |
| 112 | #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT 21 | 112 | #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT 21 |
| 113 | #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT (1 << 25) | 113 | #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT BIT(25) |
| 114 | #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER (1 << 26) | 114 | #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER BIT(26) |
| 115 | 115 | ||
| 116 | #endif /* TEGRA_CEC_H */ | 116 | #endif /* TEGRA_CEC_H */ |
diff --git a/drivers/media/platform/ti-vpe/vpe_regs.h b/drivers/media/platform/ti-vpe/vpe_regs.h index 9969bea0dded..1a1ad5ae1228 100644 --- a/drivers/media/platform/ti-vpe/vpe_regs.h +++ b/drivers/media/platform/ti-vpe/vpe_regs.h | |||
| @@ -48,24 +48,24 @@ | |||
| 48 | #define VPE_INT0_ENABLE0_SET 0x0030 | 48 | #define VPE_INT0_ENABLE0_SET 0x0030 |
| 49 | #define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET | 49 | #define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET |
| 50 | #define VPE_INT0_ENABLE0_CLR 0x0038 | 50 | #define VPE_INT0_ENABLE0_CLR 0x0038 |
| 51 | #define VPE_INT0_LIST0_COMPLETE (1 << 0) | 51 | #define VPE_INT0_LIST0_COMPLETE BIT(0) |
| 52 | #define VPE_INT0_LIST0_NOTIFY (1 << 1) | 52 | #define VPE_INT0_LIST0_NOTIFY BIT(1) |
| 53 | #define VPE_INT0_LIST1_COMPLETE (1 << 2) | 53 | #define VPE_INT0_LIST1_COMPLETE BIT(2) |
| 54 | #define VPE_INT0_LIST1_NOTIFY (1 << 3) | 54 | #define VPE_INT0_LIST1_NOTIFY BIT(3) |
| 55 | #define VPE_INT0_LIST2_COMPLETE (1 << 4) | 55 | #define VPE_INT0_LIST2_COMPLETE BIT(4) |
| 56 | #define VPE_INT0_LIST2_NOTIFY (1 << 5) | 56 | #define VPE_INT0_LIST2_NOTIFY BIT(5) |
| 57 | #define VPE_INT0_LIST3_COMPLETE (1 << 6) | 57 | #define VPE_INT0_LIST3_COMPLETE BIT(6) |
| 58 | #define VPE_INT0_LIST3_NOTIFY (1 << 7) | 58 | #define VPE_INT0_LIST3_NOTIFY BIT(7) |
| 59 | #define VPE_INT0_LIST4_COMPLETE (1 << 8) | 59 | #define VPE_INT0_LIST4_COMPLETE BIT(8) |
| 60 | #define VPE_INT0_LIST4_NOTIFY (1 << 9) | 60 | #define VPE_INT0_LIST4_NOTIFY BIT(9) |
| 61 | #define VPE_INT0_LIST5_COMPLETE (1 << 10) | 61 | #define VPE_INT0_LIST5_COMPLETE BIT(10) |
| 62 | #define VPE_INT0_LIST5_NOTIFY (1 << 11) | 62 | #define VPE_INT0_LIST5_NOTIFY BIT(11) |
| 63 | #define VPE_INT0_LIST6_COMPLETE (1 << 12) | 63 | #define VPE_INT0_LIST6_COMPLETE BIT(12) |
| 64 | #define VPE_INT0_LIST6_NOTIFY (1 << 13) | 64 | #define VPE_INT0_LIST6_NOTIFY BIT(13) |
| 65 | #define VPE_INT0_LIST7_COMPLETE (1 << 14) | 65 | #define VPE_INT0_LIST7_COMPLETE BIT(14) |
| 66 | #define VPE_INT0_LIST7_NOTIFY (1 << 15) | 66 | #define VPE_INT0_LIST7_NOTIFY BIT(15) |
| 67 | #define VPE_INT0_DESCRIPTOR (1 << 16) | 67 | #define VPE_INT0_DESCRIPTOR BIT(16) |
| 68 | #define VPE_DEI_FMD_INT (1 << 18) | 68 | #define VPE_DEI_FMD_INT BIT(18) |
| 69 | 69 | ||
| 70 | #define VPE_INT0_STATUS1_RAW_SET 0x0024 | 70 | #define VPE_INT0_STATUS1_RAW_SET 0x0024 |
| 71 | #define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET | 71 | #define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET |
| @@ -74,21 +74,21 @@ | |||
| 74 | #define VPE_INT0_ENABLE1_SET 0x0034 | 74 | #define VPE_INT0_ENABLE1_SET 0x0034 |
| 75 | #define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET | 75 | #define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET |
| 76 | #define VPE_INT0_ENABLE1_CLR 0x003c | 76 | #define VPE_INT0_ENABLE1_CLR 0x003c |
| 77 | #define VPE_INT0_CHANNEL_GROUP0 (1 << 0) | 77 | #define VPE_INT0_CHANNEL_GROUP0 BIT(0) |
| 78 | #define VPE_INT0_CHANNEL_GROUP1 (1 << 1) | 78 | #define VPE_INT0_CHANNEL_GROUP1 BIT(1) |
| 79 | #define VPE_INT0_CHANNEL_GROUP2 (1 << 2) | 79 | #define VPE_INT0_CHANNEL_GROUP2 BIT(2) |
| 80 | #define VPE_INT0_CHANNEL_GROUP3 (1 << 3) | 80 | #define VPE_INT0_CHANNEL_GROUP3 BIT(3) |
| 81 | #define VPE_INT0_CHANNEL_GROUP4 (1 << 4) | 81 | #define VPE_INT0_CHANNEL_GROUP4 BIT(4) |
| 82 | #define VPE_INT0_CHANNEL_GROUP5 (1 << 5) | 82 | #define VPE_INT0_CHANNEL_GROUP5 BIT(5) |
| 83 | #define VPE_INT0_CLIENT (1 << 7) | 83 | #define VPE_INT0_CLIENT BIT(7) |
| 84 | #define VPE_DEI_ERROR_INT (1 << 16) | 84 | #define VPE_DEI_ERROR_INT BIT(16) |
| 85 | #define VPE_DS1_UV_ERROR_INT (1 << 22) | 85 | #define VPE_DS1_UV_ERROR_INT BIT(22) |
| 86 | 86 | ||
| 87 | #define VPE_INTC_EOI 0x00a0 | 87 | #define VPE_INTC_EOI 0x00a0 |
| 88 | 88 | ||
| 89 | #define VPE_CLK_ENABLE 0x0100 | 89 | #define VPE_CLK_ENABLE 0x0100 |
| 90 | #define VPE_VPEDMA_CLK_ENABLE (1 << 0) | 90 | #define VPE_VPEDMA_CLK_ENABLE BIT(0) |
| 91 | #define VPE_DATA_PATH_CLK_ENABLE (1 << 1) | 91 | #define VPE_DATA_PATH_CLK_ENABLE BIT(1) |
| 92 | 92 | ||
| 93 | #define VPE_CLK_RESET 0x0104 | 93 | #define VPE_CLK_RESET 0x0104 |
| 94 | #define VPE_VPDMA_CLK_RESET_MASK 0x1 | 94 | #define VPE_VPDMA_CLK_RESET_MASK 0x1 |
| @@ -101,11 +101,11 @@ | |||
| 101 | #define VPE_CLK_FORMAT_SELECT 0x010c | 101 | #define VPE_CLK_FORMAT_SELECT 0x010c |
| 102 | #define VPE_CSC_SRC_SELECT_MASK 0x03 | 102 | #define VPE_CSC_SRC_SELECT_MASK 0x03 |
| 103 | #define VPE_CSC_SRC_SELECT_SHIFT 0 | 103 | #define VPE_CSC_SRC_SELECT_SHIFT 0 |
| 104 | #define VPE_RGB_OUT_SELECT (1 << 8) | 104 | #define VPE_RGB_OUT_SELECT BIT(8) |
| 105 | #define VPE_DS_SRC_SELECT_MASK 0x07 | 105 | #define VPE_DS_SRC_SELECT_MASK 0x07 |
| 106 | #define VPE_DS_SRC_SELECT_SHIFT 9 | 106 | #define VPE_DS_SRC_SELECT_SHIFT 9 |
| 107 | #define VPE_DS_BYPASS (1 << 16) | 107 | #define VPE_DS_BYPASS BIT(16) |
| 108 | #define VPE_COLOR_SEPARATE_422 (1 << 18) | 108 | #define VPE_COLOR_SEPARATE_422 BIT(18) |
| 109 | 109 | ||
| 110 | #define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT) | 110 | #define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT) |
| 111 | #define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT) | 111 | #define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT) |
| @@ -115,8 +115,8 @@ | |||
| 115 | #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0 | 115 | #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0 |
| 116 | #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07 | 116 | #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07 |
| 117 | #define VPE_RANGE_RANGE_MAP_UV_SHIFT 3 | 117 | #define VPE_RANGE_RANGE_MAP_UV_SHIFT 3 |
| 118 | #define VPE_RANGE_MAP_ON (1 << 6) | 118 | #define VPE_RANGE_MAP_ON BIT(6) |
| 119 | #define VPE_RANGE_REDUCTION_ON (1 << 28) | 119 | #define VPE_RANGE_REDUCTION_ON BIT(28) |
| 120 | 120 | ||
| 121 | /* VPE chrominance upsampler regs */ | 121 | /* VPE chrominance upsampler regs */ |
| 122 | #define VPE_US1_R0 0x0304 | 122 | #define VPE_US1_R0 0x0304 |
| @@ -195,13 +195,13 @@ | |||
| 195 | #define VPE_DEI_WIDTH_SHIFT 0 | 195 | #define VPE_DEI_WIDTH_SHIFT 0 |
| 196 | #define VPE_DEI_HEIGHT_MASK 0x07ff | 196 | #define VPE_DEI_HEIGHT_MASK 0x07ff |
| 197 | #define VPE_DEI_HEIGHT_SHIFT 16 | 197 | #define VPE_DEI_HEIGHT_SHIFT 16 |
| 198 | #define VPE_DEI_INTERLACE_BYPASS (1 << 29) | 198 | #define VPE_DEI_INTERLACE_BYPASS BIT(29) |
| 199 | #define VPE_DEI_FIELD_FLUSH (1 << 30) | 199 | #define VPE_DEI_FIELD_FLUSH BIT(30) |
| 200 | #define VPE_DEI_PROGRESSIVE (1 << 31) | 200 | #define VPE_DEI_PROGRESSIVE BIT(31) |
| 201 | 201 | ||
| 202 | #define VPE_MDT_BYPASS 0x0604 | 202 | #define VPE_MDT_BYPASS 0x0604 |
| 203 | #define VPE_MDT_TEMPMAX_BYPASS (1 << 0) | 203 | #define VPE_MDT_TEMPMAX_BYPASS BIT(0) |
| 204 | #define VPE_MDT_SPATMAX_BYPASS (1 << 1) | 204 | #define VPE_MDT_SPATMAX_BYPASS BIT(1) |
| 205 | 205 | ||
| 206 | #define VPE_MDT_SF_THRESHOLD 0x0608 | 206 | #define VPE_MDT_SF_THRESHOLD 0x0608 |
| 207 | #define VPE_MDT_SF_SC_THR1_MASK 0xff | 207 | #define VPE_MDT_SF_SC_THR1_MASK 0xff |
| @@ -214,8 +214,8 @@ | |||
| 214 | #define VPE_EDI_CONFIG 0x060c | 214 | #define VPE_EDI_CONFIG 0x060c |
| 215 | #define VPE_EDI_INP_MODE_MASK 0x03 | 215 | #define VPE_EDI_INP_MODE_MASK 0x03 |
| 216 | #define VPE_EDI_INP_MODE_SHIFT 0 | 216 | #define VPE_EDI_INP_MODE_SHIFT 0 |
| 217 | #define VPE_EDI_ENABLE_3D (1 << 2) | 217 | #define VPE_EDI_ENABLE_3D BIT(2) |
| 218 | #define VPE_EDI_ENABLE_CHROMA_3D (1 << 3) | 218 | #define VPE_EDI_ENABLE_CHROMA_3D BIT(3) |
| 219 | #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff | 219 | #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff |
| 220 | #define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8 | 220 | #define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8 |
| 221 | #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff | 221 | #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff |
| @@ -268,7 +268,7 @@ | |||
| 268 | #define VPE_FMD_WINDOW_MINX_SHIFT 0 | 268 | #define VPE_FMD_WINDOW_MINX_SHIFT 0 |
| 269 | #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff | 269 | #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff |
| 270 | #define VPE_FMD_WINDOW_MAXX_SHIFT 16 | 270 | #define VPE_FMD_WINDOW_MAXX_SHIFT 16 |
| 271 | #define VPE_FMD_WINDOW_ENABLE (1 << 31) | 271 | #define VPE_FMD_WINDOW_ENABLE BIT(31) |
| 272 | 272 | ||
| 273 | #define VPE_DEI_FMD_WINDOW_R1 0x0624 | 273 | #define VPE_DEI_FMD_WINDOW_R1 0x0624 |
| 274 | #define VPE_FMD_WINDOW_MINY_MASK 0x07ff | 274 | #define VPE_FMD_WINDOW_MINY_MASK 0x07ff |
| @@ -277,10 +277,10 @@ | |||
| 277 | #define VPE_FMD_WINDOW_MAXY_SHIFT 16 | 277 | #define VPE_FMD_WINDOW_MAXY_SHIFT 16 |
| 278 | 278 | ||
| 279 | #define VPE_DEI_FMD_CONTROL_R0 0x0628 | 279 | #define VPE_DEI_FMD_CONTROL_R0 0x0628 |
| 280 | #define VPE_FMD_ENABLE (1 << 0) | 280 | #define VPE_FMD_ENABLE BIT(0) |
| 281 | #define VPE_FMD_LOCK (1 << 1) | 281 | #define VPE_FMD_LOCK BIT(1) |
| 282 | #define VPE_FMD_JAM_DIR (1 << 2) | 282 | #define VPE_FMD_JAM_DIR BIT(2) |
| 283 | #define VPE_FMD_BED_ENABLE (1 << 3) | 283 | #define VPE_FMD_BED_ENABLE BIT(3) |
| 284 | #define VPE_FMD_CAF_FIELD_THR_MASK 0xff | 284 | #define VPE_FMD_CAF_FIELD_THR_MASK 0xff |
| 285 | #define VPE_FMD_CAF_FIELD_THR_SHIFT 16 | 285 | #define VPE_FMD_CAF_FIELD_THR_SHIFT 16 |
| 286 | #define VPE_FMD_CAF_LINE_THR_MASK 0xff | 286 | #define VPE_FMD_CAF_LINE_THR_MASK 0xff |
| @@ -293,7 +293,7 @@ | |||
| 293 | #define VPE_DEI_FMD_STATUS_R0 0x0630 | 293 | #define VPE_DEI_FMD_STATUS_R0 0x0630 |
| 294 | #define VPE_FMD_CAF_MASK 0x000fffff | 294 | #define VPE_FMD_CAF_MASK 0x000fffff |
| 295 | #define VPE_FMD_CAF_SHIFT 0 | 295 | #define VPE_FMD_CAF_SHIFT 0 |
| 296 | #define VPE_FMD_RESET (1 << 24) | 296 | #define VPE_FMD_RESET BIT(24) |
| 297 | 297 | ||
| 298 | #define VPE_DEI_FMD_STATUS_R1 0x0634 | 298 | #define VPE_DEI_FMD_STATUS_R1 0x0634 |
| 299 | #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff | 299 | #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff |
diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h index 1bb1d39c60d9..5c67ff92d97a 100644 --- a/drivers/media/platform/vsp1/vsp1_regs.h +++ b/drivers/media/platform/vsp1/vsp1_regs.h | |||
| @@ -15,8 +15,8 @@ | |||
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #define VI6_CMD(n) (0x0000 + (n) * 4) | 17 | #define VI6_CMD(n) (0x0000 + (n) * 4) |
| 18 | #define VI6_CMD_UPDHDR (1 << 4) | 18 | #define VI6_CMD_UPDHDR BIT(4) |
| 19 | #define VI6_CMD_STRCMD (1 << 0) | 19 | #define VI6_CMD_STRCMD BIT(0) |
| 20 | 20 | ||
| 21 | #define VI6_CLK_DCSWT 0x0018 | 21 | #define VI6_CLK_DCSWT 0x0018 |
| 22 | #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8) | 22 | #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8) |
| @@ -25,29 +25,29 @@ | |||
| 25 | #define VI6_CLK_DCSWT_CSTRW_SHIFT 0 | 25 | #define VI6_CLK_DCSWT_CSTRW_SHIFT 0 |
| 26 | 26 | ||
| 27 | #define VI6_SRESET 0x0028 | 27 | #define VI6_SRESET 0x0028 |
| 28 | #define VI6_SRESET_SRTS(n) (1 << (n)) | 28 | #define VI6_SRESET_SRTS(n) BIT(n) |
| 29 | 29 | ||
| 30 | #define VI6_STATUS 0x0038 | 30 | #define VI6_STATUS 0x0038 |
| 31 | #define VI6_STATUS_FLD_STD(n) (1 << ((n) + 28)) | 31 | #define VI6_STATUS_FLD_STD(n) BIT((n) + 28) |
| 32 | #define VI6_STATUS_SYS_ACT(n) (1 << ((n) + 8)) | 32 | #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) |
| 33 | 33 | ||
| 34 | #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) | 34 | #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) |
| 35 | #define VI6_WFP_IRQ_ENB_DFEE (1 << 1) | 35 | #define VI6_WFP_IRQ_ENB_DFEE BIT(1) |
| 36 | #define VI6_WFP_IRQ_ENB_FREE (1 << 0) | 36 | #define VI6_WFP_IRQ_ENB_FREE BIT(0) |
| 37 | 37 | ||
| 38 | #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) | 38 | #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) |
| 39 | #define VI6_WFP_IRQ_STA_DFE (1 << 1) | 39 | #define VI6_WFP_IRQ_STA_DFE BIT(1) |
| 40 | #define VI6_WFP_IRQ_STA_FRE (1 << 0) | 40 | #define VI6_WFP_IRQ_STA_FRE BIT(0) |
| 41 | 41 | ||
| 42 | #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60) | 42 | #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60) |
| 43 | #define VI6_DISP_IRQ_ENB_DSTE (1 << 8) | 43 | #define VI6_DISP_IRQ_ENB_DSTE BIT(8) |
| 44 | #define VI6_DISP_IRQ_ENB_MAEE (1 << 5) | 44 | #define VI6_DISP_IRQ_ENB_MAEE BIT(5) |
| 45 | #define VI6_DISP_IRQ_ENB_LNEE(n) (1 << (n)) | 45 | #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n) |
| 46 | 46 | ||
| 47 | #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60) | 47 | #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60) |
| 48 | #define VI6_DISP_IRQ_STA_DST (1 << 8) | 48 | #define VI6_DISP_IRQ_STA_DST BIT(8) |
| 49 | #define VI6_DISP_IRQ_STA_MAE (1 << 5) | 49 | #define VI6_DISP_IRQ_STA_MAE BIT(5) |
| 50 | #define VI6_DISP_IRQ_STA_LNE(n) (1 << (n)) | 50 | #define VI6_DISP_IRQ_STA_LNE(n) BIT(n) |
| 51 | 51 | ||
| 52 | #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4) | 52 | #define VI6_WPF_LINE_COUNT(n) (0x0084 + (n) * 4) |
| 53 | #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0) | 53 | #define VI6_WPF_LINE_COUNT_MASK (0x1fffff << 0) |
| @@ -59,32 +59,32 @@ | |||
| 59 | #define VI6_DL_CTRL 0x0100 | 59 | #define VI6_DL_CTRL 0x0100 |
| 60 | #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16) | 60 | #define VI6_DL_CTRL_AR_WAIT_MASK (0xffff << 16) |
| 61 | #define VI6_DL_CTRL_AR_WAIT_SHIFT 16 | 61 | #define VI6_DL_CTRL_AR_WAIT_SHIFT 16 |
| 62 | #define VI6_DL_CTRL_DC2 (1 << 12) | 62 | #define VI6_DL_CTRL_DC2 BIT(12) |
| 63 | #define VI6_DL_CTRL_DC1 (1 << 8) | 63 | #define VI6_DL_CTRL_DC1 BIT(8) |
| 64 | #define VI6_DL_CTRL_DC0 (1 << 4) | 64 | #define VI6_DL_CTRL_DC0 BIT(4) |
| 65 | #define VI6_DL_CTRL_CFM0 (1 << 2) | 65 | #define VI6_DL_CTRL_CFM0 BIT(2) |
| 66 | #define VI6_DL_CTRL_NH0 (1 << 1) | 66 | #define VI6_DL_CTRL_NH0 BIT(1) |
| 67 | #define VI6_DL_CTRL_DLE (1 << 0) | 67 | #define VI6_DL_CTRL_DLE BIT(0) |
| 68 | 68 | ||
| 69 | #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4) | 69 | #define VI6_DL_HDR_ADDR(n) (0x0104 + (n) * 4) |
| 70 | 70 | ||
| 71 | #define VI6_DL_SWAP 0x0114 | 71 | #define VI6_DL_SWAP 0x0114 |
| 72 | #define VI6_DL_SWAP_LWS (1 << 2) | 72 | #define VI6_DL_SWAP_LWS BIT(2) |
| 73 | #define VI6_DL_SWAP_WDS (1 << 1) | 73 | #define VI6_DL_SWAP_WDS BIT(1) |
| 74 | #define VI6_DL_SWAP_BTS (1 << 0) | 74 | #define VI6_DL_SWAP_BTS BIT(0) |
| 75 | 75 | ||
| 76 | #define VI6_DL_EXT_CTRL(n) (0x011c + (n) * 36) | 76 | #define VI6_DL_EXT_CTRL(n) (0x011c + (n) * 36) |
| 77 | #define VI6_DL_EXT_CTRL_NWE (1 << 16) | 77 | #define VI6_DL_EXT_CTRL_NWE BIT(16) |
| 78 | #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8) | 78 | #define VI6_DL_EXT_CTRL_POLINT_MASK (0x3f << 8) |
| 79 | #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8 | 79 | #define VI6_DL_EXT_CTRL_POLINT_SHIFT 8 |
| 80 | #define VI6_DL_EXT_CTRL_DLPRI (1 << 5) | 80 | #define VI6_DL_EXT_CTRL_DLPRI BIT(5) |
| 81 | #define VI6_DL_EXT_CTRL_EXPRI (1 << 4) | 81 | #define VI6_DL_EXT_CTRL_EXPRI BIT(4) |
| 82 | #define VI6_DL_EXT_CTRL_EXT (1 << 0) | 82 | #define VI6_DL_EXT_CTRL_EXT BIT(0) |
| 83 | 83 | ||
| 84 | #define VI6_DL_EXT_AUTOFLD_INT BIT(0) | 84 | #define VI6_DL_EXT_AUTOFLD_INT BIT(0) |
| 85 | 85 | ||
| 86 | #define VI6_DL_BODY_SIZE 0x0120 | 86 | #define VI6_DL_BODY_SIZE 0x0120 |
| 87 | #define VI6_DL_BODY_SIZE_UPD (1 << 24) | 87 | #define VI6_DL_BODY_SIZE_UPD BIT(24) |
| 88 | #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0) | 88 | #define VI6_DL_BODY_SIZE_BS_MASK (0x1ffff << 0) |
| 89 | #define VI6_DL_BODY_SIZE_BS_SHIFT 0 | 89 | #define VI6_DL_BODY_SIZE_BS_SHIFT 0 |
| 90 | 90 | ||
| @@ -107,10 +107,10 @@ | |||
| 107 | #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0 | 107 | #define VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT 0 |
| 108 | 108 | ||
| 109 | #define VI6_RPF_INFMT 0x0308 | 109 | #define VI6_RPF_INFMT 0x0308 |
| 110 | #define VI6_RPF_INFMT_VIR (1 << 28) | 110 | #define VI6_RPF_INFMT_VIR BIT(28) |
| 111 | #define VI6_RPF_INFMT_CIPM (1 << 16) | 111 | #define VI6_RPF_INFMT_CIPM BIT(16) |
| 112 | #define VI6_RPF_INFMT_SPYCS (1 << 15) | 112 | #define VI6_RPF_INFMT_SPYCS BIT(15) |
| 113 | #define VI6_RPF_INFMT_SPUVS (1 << 14) | 113 | #define VI6_RPF_INFMT_SPUVS BIT(14) |
| 114 | #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12) | 114 | #define VI6_RPF_INFMT_CEXT_ZERO (0 << 12) |
| 115 | #define VI6_RPF_INFMT_CEXT_EXT (1 << 12) | 115 | #define VI6_RPF_INFMT_CEXT_EXT (1 << 12) |
| 116 | #define VI6_RPF_INFMT_CEXT_ONE (2 << 12) | 116 | #define VI6_RPF_INFMT_CEXT_ONE (2 << 12) |
| @@ -120,19 +120,19 @@ | |||
| 120 | #define VI6_RPF_INFMT_RDTM_BT709 (2 << 9) | 120 | #define VI6_RPF_INFMT_RDTM_BT709 (2 << 9) |
| 121 | #define VI6_RPF_INFMT_RDTM_BT709_EXT (3 << 9) | 121 | #define VI6_RPF_INFMT_RDTM_BT709_EXT (3 << 9) |
| 122 | #define VI6_RPF_INFMT_RDTM_MASK (7 << 9) | 122 | #define VI6_RPF_INFMT_RDTM_MASK (7 << 9) |
| 123 | #define VI6_RPF_INFMT_CSC (1 << 8) | 123 | #define VI6_RPF_INFMT_CSC BIT(8) |
| 124 | #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0) | 124 | #define VI6_RPF_INFMT_RDFMT_MASK (0x7f << 0) |
| 125 | #define VI6_RPF_INFMT_RDFMT_SHIFT 0 | 125 | #define VI6_RPF_INFMT_RDFMT_SHIFT 0 |
| 126 | 126 | ||
| 127 | #define VI6_RPF_DSWAP 0x030c | 127 | #define VI6_RPF_DSWAP 0x030c |
| 128 | #define VI6_RPF_DSWAP_A_LLS (1 << 11) | 128 | #define VI6_RPF_DSWAP_A_LLS BIT(11) |
| 129 | #define VI6_RPF_DSWAP_A_LWS (1 << 10) | 129 | #define VI6_RPF_DSWAP_A_LWS BIT(10) |
| 130 | #define VI6_RPF_DSWAP_A_WDS (1 << 9) | 130 | #define VI6_RPF_DSWAP_A_WDS BIT(9) |
| 131 | #define VI6_RPF_DSWAP_A_BTS (1 << 8) | 131 | #define VI6_RPF_DSWAP_A_BTS BIT(8) |
| 132 | #define VI6_RPF_DSWAP_P_LLS (1 << 3) | 132 | #define VI6_RPF_DSWAP_P_LLS BIT(3) |
| 133 | #define VI6_RPF_DSWAP_P_LWS (1 << 2) | 133 | #define VI6_RPF_DSWAP_P_LWS BIT(2) |
| 134 | #define VI6_RPF_DSWAP_P_WDS (1 << 1) | 134 | #define VI6_RPF_DSWAP_P_WDS BIT(1) |
| 135 | #define VI6_RPF_DSWAP_P_BTS (1 << 0) | 135 | #define VI6_RPF_DSWAP_P_BTS BIT(0) |
| 136 | 136 | ||
| 137 | #define VI6_RPF_LOC 0x0310 | 137 | #define VI6_RPF_LOC 0x0310 |
| 138 | #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16) | 138 | #define VI6_RPF_LOC_HCOORD_MASK (0x1fff << 16) |
| @@ -150,7 +150,7 @@ | |||
| 150 | #define VI6_RPF_ALPH_SEL_ASEL_SHIFT 28 | 150 | #define VI6_RPF_ALPH_SEL_ASEL_SHIFT 28 |
| 151 | #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24) | 151 | #define VI6_RPF_ALPH_SEL_IROP_MASK (0xf << 24) |
| 152 | #define VI6_RPF_ALPH_SEL_IROP_SHIFT 24 | 152 | #define VI6_RPF_ALPH_SEL_IROP_SHIFT 24 |
| 153 | #define VI6_RPF_ALPH_SEL_BSEL (1 << 23) | 153 | #define VI6_RPF_ALPH_SEL_BSEL BIT(23) |
| 154 | #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18) | 154 | #define VI6_RPF_ALPH_SEL_AEXT_ZERO (0 << 18) |
| 155 | #define VI6_RPF_ALPH_SEL_AEXT_EXT (1 << 18) | 155 | #define VI6_RPF_ALPH_SEL_AEXT_EXT (1 << 18) |
| 156 | #define VI6_RPF_ALPH_SEL_AEXT_ONE (2 << 18) | 156 | #define VI6_RPF_ALPH_SEL_AEXT_ONE (2 << 18) |
| @@ -171,7 +171,7 @@ | |||
| 171 | #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0 | 171 | #define VI6_RPF_VRTCOL_SET_LAYB_SHIFT 0 |
| 172 | 172 | ||
| 173 | #define VI6_RPF_MSK_CTRL 0x031c | 173 | #define VI6_RPF_MSK_CTRL 0x031c |
| 174 | #define VI6_RPF_MSK_CTRL_MSK_EN (1 << 24) | 174 | #define VI6_RPF_MSK_CTRL_MSK_EN BIT(24) |
| 175 | #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16) | 175 | #define VI6_RPF_MSK_CTRL_MGR_MASK (0xff << 16) |
| 176 | #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16 | 176 | #define VI6_RPF_MSK_CTRL_MGR_SHIFT 16 |
| 177 | #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8) | 177 | #define VI6_RPF_MSK_CTRL_MGG_MASK (0xff << 8) |
| @@ -191,9 +191,9 @@ | |||
| 191 | #define VI6_RPF_MSK_SET_MSB_SHIFT 0 | 191 | #define VI6_RPF_MSK_SET_MSB_SHIFT 0 |
| 192 | 192 | ||
| 193 | #define VI6_RPF_CKEY_CTRL 0x0328 | 193 | #define VI6_RPF_CKEY_CTRL 0x0328 |
| 194 | #define VI6_RPF_CKEY_CTRL_CV (1 << 4) | 194 | #define VI6_RPF_CKEY_CTRL_CV BIT(4) |
| 195 | #define VI6_RPF_CKEY_CTRL_SAPE1 (1 << 1) | 195 | #define VI6_RPF_CKEY_CTRL_SAPE1 BIT(1) |
| 196 | #define VI6_RPF_CKEY_CTRL_SAPE0 (1 << 0) | 196 | #define VI6_RPF_CKEY_CTRL_SAPE0 BIT(0) |
| 197 | 197 | ||
| 198 | #define VI6_RPF_CKEY_SET0 0x032c | 198 | #define VI6_RPF_CKEY_SET0 0x032c |
| 199 | #define VI6_RPF_CKEY_SET1 0x0330 | 199 | #define VI6_RPF_CKEY_SET1 0x0330 |
| @@ -250,7 +250,7 @@ | |||
| 250 | 250 | ||
| 251 | #define VI6_WPF_HSZCLIP 0x1004 | 251 | #define VI6_WPF_HSZCLIP 0x1004 |
| 252 | #define VI6_WPF_VSZCLIP 0x1008 | 252 | #define VI6_WPF_VSZCLIP 0x1008 |
| 253 | #define VI6_WPF_SZCLIP_EN (1 << 28) | 253 | #define VI6_WPF_SZCLIP_EN BIT(28) |
| 254 | #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16) | 254 | #define VI6_WPF_SZCLIP_OFST_MASK (0xff << 16) |
| 255 | #define VI6_WPF_SZCLIP_OFST_SHIFT 16 | 255 | #define VI6_WPF_SZCLIP_OFST_SHIFT 16 |
| 256 | #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0) | 256 | #define VI6_WPF_SZCLIP_SIZE_MASK (0xfff << 0) |
| @@ -259,12 +259,12 @@ | |||
| 259 | #define VI6_WPF_OUTFMT 0x100c | 259 | #define VI6_WPF_OUTFMT 0x100c |
| 260 | #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24) | 260 | #define VI6_WPF_OUTFMT_PDV_MASK (0xff << 24) |
| 261 | #define VI6_WPF_OUTFMT_PDV_SHIFT 24 | 261 | #define VI6_WPF_OUTFMT_PDV_SHIFT 24 |
| 262 | #define VI6_WPF_OUTFMT_PXA (1 << 23) | 262 | #define VI6_WPF_OUTFMT_PXA BIT(23) |
| 263 | #define VI6_WPF_OUTFMT_ROT (1 << 18) | 263 | #define VI6_WPF_OUTFMT_ROT BIT(18) |
| 264 | #define VI6_WPF_OUTFMT_HFLP (1 << 17) | 264 | #define VI6_WPF_OUTFMT_HFLP BIT(17) |
| 265 | #define VI6_WPF_OUTFMT_FLP (1 << 16) | 265 | #define VI6_WPF_OUTFMT_FLP BIT(16) |
| 266 | #define VI6_WPF_OUTFMT_SPYCS (1 << 15) | 266 | #define VI6_WPF_OUTFMT_SPYCS BIT(15) |
| 267 | #define VI6_WPF_OUTFMT_SPUVS (1 << 14) | 267 | #define VI6_WPF_OUTFMT_SPUVS BIT(14) |
| 268 | #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12) | 268 | #define VI6_WPF_OUTFMT_DITH_DIS (0 << 12) |
| 269 | #define VI6_WPF_OUTFMT_DITH_EN (3 << 12) | 269 | #define VI6_WPF_OUTFMT_DITH_EN (3 << 12) |
| 270 | #define VI6_WPF_OUTFMT_DITH_MASK (3 << 12) | 270 | #define VI6_WPF_OUTFMT_DITH_MASK (3 << 12) |
| @@ -273,18 +273,18 @@ | |||
| 273 | #define VI6_WPF_OUTFMT_WRTM_BT709 (2 << 9) | 273 | #define VI6_WPF_OUTFMT_WRTM_BT709 (2 << 9) |
| 274 | #define VI6_WPF_OUTFMT_WRTM_BT709_EXT (3 << 9) | 274 | #define VI6_WPF_OUTFMT_WRTM_BT709_EXT (3 << 9) |
| 275 | #define VI6_WPF_OUTFMT_WRTM_MASK (7 << 9) | 275 | #define VI6_WPF_OUTFMT_WRTM_MASK (7 << 9) |
| 276 | #define VI6_WPF_OUTFMT_CSC (1 << 8) | 276 | #define VI6_WPF_OUTFMT_CSC BIT(8) |
| 277 | #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0) | 277 | #define VI6_WPF_OUTFMT_WRFMT_MASK (0x7f << 0) |
| 278 | #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0 | 278 | #define VI6_WPF_OUTFMT_WRFMT_SHIFT 0 |
| 279 | 279 | ||
| 280 | #define VI6_WPF_DSWAP 0x1010 | 280 | #define VI6_WPF_DSWAP 0x1010 |
| 281 | #define VI6_WPF_DSWAP_P_LLS (1 << 3) | 281 | #define VI6_WPF_DSWAP_P_LLS BIT(3) |
| 282 | #define VI6_WPF_DSWAP_P_LWS (1 << 2) | 282 | #define VI6_WPF_DSWAP_P_LWS BIT(2) |
| 283 | #define VI6_WPF_DSWAP_P_WDS (1 << 1) | 283 | #define VI6_WPF_DSWAP_P_WDS BIT(1) |
| 284 | #define VI6_WPF_DSWAP_P_BTS (1 << 0) | 284 | #define VI6_WPF_DSWAP_P_BTS BIT(0) |
| 285 | 285 | ||
| 286 | #define VI6_WPF_RNDCTRL 0x1014 | 286 | #define VI6_WPF_RNDCTRL 0x1014 |
| 287 | #define VI6_WPF_RNDCTRL_CBRM (1 << 28) | 287 | #define VI6_WPF_RNDCTRL_CBRM BIT(28) |
| 288 | #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24) | 288 | #define VI6_WPF_RNDCTRL_ABRM_TRUNC (0 << 24) |
| 289 | #define VI6_WPF_RNDCTRL_ABRM_ROUND (1 << 24) | 289 | #define VI6_WPF_RNDCTRL_ABRM_ROUND (1 << 24) |
| 290 | #define VI6_WPF_RNDCTRL_ABRM_THRESH (2 << 24) | 290 | #define VI6_WPF_RNDCTRL_ABRM_THRESH (2 << 24) |
| @@ -297,7 +297,7 @@ | |||
| 297 | #define VI6_WPF_RNDCTRL_CLMD_MASK (3 << 12) | 297 | #define VI6_WPF_RNDCTRL_CLMD_MASK (3 << 12) |
| 298 | 298 | ||
| 299 | #define VI6_WPF_ROT_CTRL 0x1018 | 299 | #define VI6_WPF_ROT_CTRL 0x1018 |
| 300 | #define VI6_WPF_ROT_CTRL_LN16 (1 << 17) | 300 | #define VI6_WPF_ROT_CTRL_LN16 BIT(17) |
| 301 | #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0) | 301 | #define VI6_WPF_ROT_CTRL_LMEM_WD_MASK (0x1fff << 0) |
| 302 | #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0 | 302 | #define VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT 0 |
| 303 | 303 | ||
| @@ -308,7 +308,7 @@ | |||
| 308 | #define VI6_WPF_DSTM_ADDR_C1 0x102c | 308 | #define VI6_WPF_DSTM_ADDR_C1 0x102c |
| 309 | 309 | ||
| 310 | #define VI6_WPF_WRBCK_CTRL(n) (0x1034 + (n) * 0x100) | 310 | #define VI6_WPF_WRBCK_CTRL(n) (0x1034 + (n) * 0x100) |
| 311 | #define VI6_WPF_WRBCK_CTRL_WBMD (1 << 0) | 311 | #define VI6_WPF_WRBCK_CTRL_WBMD BIT(0) |
| 312 | 312 | ||
| 313 | /* ----------------------------------------------------------------------------- | 313 | /* ----------------------------------------------------------------------------- |
| 314 | * UIF Control Registers | 314 | * UIF Control Registers |
| @@ -317,20 +317,20 @@ | |||
| 317 | #define VI6_UIF_OFFSET 0x100 | 317 | #define VI6_UIF_OFFSET 0x100 |
| 318 | 318 | ||
| 319 | #define VI6_UIF_DISCOM_DOCMCR 0x1c00 | 319 | #define VI6_UIF_DISCOM_DOCMCR 0x1c00 |
| 320 | #define VI6_UIF_DISCOM_DOCMCR_CMPRU (1 << 16) | 320 | #define VI6_UIF_DISCOM_DOCMCR_CMPRU BIT(16) |
| 321 | #define VI6_UIF_DISCOM_DOCMCR_CMPR (1 << 0) | 321 | #define VI6_UIF_DISCOM_DOCMCR_CMPR BIT(0) |
| 322 | 322 | ||
| 323 | #define VI6_UIF_DISCOM_DOCMSTR 0x1c04 | 323 | #define VI6_UIF_DISCOM_DOCMSTR 0x1c04 |
| 324 | #define VI6_UIF_DISCOM_DOCMSTR_CMPPRE (1 << 1) | 324 | #define VI6_UIF_DISCOM_DOCMSTR_CMPPRE BIT(1) |
| 325 | #define VI6_UIF_DISCOM_DOCMSTR_CMPST (1 << 0) | 325 | #define VI6_UIF_DISCOM_DOCMSTR_CMPST BIT(0) |
| 326 | 326 | ||
| 327 | #define VI6_UIF_DISCOM_DOCMCLSTR 0x1c08 | 327 | #define VI6_UIF_DISCOM_DOCMCLSTR 0x1c08 |
| 328 | #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE (1 << 1) | 328 | #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE BIT(1) |
| 329 | #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST (1 << 0) | 329 | #define VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST BIT(0) |
| 330 | 330 | ||
| 331 | #define VI6_UIF_DISCOM_DOCMIENR 0x1c0c | 331 | #define VI6_UIF_DISCOM_DOCMIENR 0x1c0c |
| 332 | #define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN (1 << 1) | 332 | #define VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN BIT(1) |
| 333 | #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN (1 << 0) | 333 | #define VI6_UIF_DISCOM_DOCMIENR_CMPIEN BIT(0) |
| 334 | 334 | ||
| 335 | #define VI6_UIF_DISCOM_DOCMMDR 0x1c10 | 335 | #define VI6_UIF_DISCOM_DOCMMDR 0x1c10 |
| 336 | #define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n) ((n) << 16) | 336 | #define VI6_UIF_DISCOM_DOCMMDR_INTHRH(n) ((n) << 16) |
| @@ -338,7 +338,7 @@ | |||
| 338 | #define VI6_UIF_DISCOM_DOCMPMR 0x1c14 | 338 | #define VI6_UIF_DISCOM_DOCMPMR 0x1c14 |
| 339 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDFF(n) ((n) << 17) | 339 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDFF(n) ((n) << 17) |
| 340 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n) ((n) << 8) | 340 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDFA(n) ((n) << 8) |
| 341 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF (1 << 7) | 341 | #define VI6_UIF_DISCOM_DOCMPMR_CMPDAUF BIT(7) |
| 342 | #define VI6_UIF_DISCOM_DOCMPMR_SEL(n) ((n) << 0) | 342 | #define VI6_UIF_DISCOM_DOCMPMR_SEL(n) ((n) << 0) |
| 343 | 343 | ||
| 344 | #define VI6_UIF_DISCOM_DOCMECRCR 0x1c18 | 344 | #define VI6_UIF_DISCOM_DOCMECRCR 0x1c18 |
| @@ -365,7 +365,7 @@ | |||
| 365 | #define VI6_DPR_HSI_ROUTE 0x2048 | 365 | #define VI6_DPR_HSI_ROUTE 0x2048 |
| 366 | #define VI6_DPR_BRU_ROUTE 0x204c | 366 | #define VI6_DPR_BRU_ROUTE 0x204c |
| 367 | #define VI6_DPR_ILV_BRS_ROUTE 0x2050 | 367 | #define VI6_DPR_ILV_BRS_ROUTE 0x2050 |
| 368 | #define VI6_DPR_ROUTE_BRSSEL (1 << 28) | 368 | #define VI6_DPR_ROUTE_BRSSEL BIT(28) |
| 369 | #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16) | 369 | #define VI6_DPR_ROUTE_FXA_MASK (0xff << 16) |
| 370 | #define VI6_DPR_ROUTE_FXA_SHIFT 16 | 370 | #define VI6_DPR_ROUTE_FXA_SHIFT 16 |
| 371 | #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) | 371 | #define VI6_DPR_ROUTE_FP_MASK (0x3f << 8) |
| @@ -407,10 +407,10 @@ | |||
| 407 | #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8) | 407 | #define VI6_SRU_CTRL0_PARAM1_MASK (0x1f << 8) |
| 408 | #define VI6_SRU_CTRL0_PARAM1_SHIFT 8 | 408 | #define VI6_SRU_CTRL0_PARAM1_SHIFT 8 |
| 409 | #define VI6_SRU_CTRL0_MODE_UPSCALE (4 << 4) | 409 | #define VI6_SRU_CTRL0_MODE_UPSCALE (4 << 4) |
| 410 | #define VI6_SRU_CTRL0_PARAM2 (1 << 3) | 410 | #define VI6_SRU_CTRL0_PARAM2 BIT(3) |
| 411 | #define VI6_SRU_CTRL0_PARAM3 (1 << 2) | 411 | #define VI6_SRU_CTRL0_PARAM3 BIT(2) |
| 412 | #define VI6_SRU_CTRL0_PARAM4 (1 << 1) | 412 | #define VI6_SRU_CTRL0_PARAM4 BIT(1) |
| 413 | #define VI6_SRU_CTRL0_EN (1 << 0) | 413 | #define VI6_SRU_CTRL0_EN BIT(0) |
| 414 | 414 | ||
| 415 | #define VI6_SRU_CTRL1 0x2204 | 415 | #define VI6_SRU_CTRL1 0x2204 |
| 416 | #define VI6_SRU_CTRL1_PARAM5 0x7ff | 416 | #define VI6_SRU_CTRL1_PARAM5 0x7ff |
| @@ -427,18 +427,18 @@ | |||
| 427 | #define VI6_UDS_OFFSET 0x100 | 427 | #define VI6_UDS_OFFSET 0x100 |
| 428 | 428 | ||
| 429 | #define VI6_UDS_CTRL 0x2300 | 429 | #define VI6_UDS_CTRL 0x2300 |
| 430 | #define VI6_UDS_CTRL_AMD (1 << 30) | 430 | #define VI6_UDS_CTRL_AMD BIT(30) |
| 431 | #define VI6_UDS_CTRL_FMD (1 << 29) | 431 | #define VI6_UDS_CTRL_FMD BIT(29) |
| 432 | #define VI6_UDS_CTRL_BLADV (1 << 28) | 432 | #define VI6_UDS_CTRL_BLADV BIT(28) |
| 433 | #define VI6_UDS_CTRL_AON (1 << 25) | 433 | #define VI6_UDS_CTRL_AON BIT(25) |
| 434 | #define VI6_UDS_CTRL_ATHON (1 << 24) | 434 | #define VI6_UDS_CTRL_ATHON BIT(24) |
| 435 | #define VI6_UDS_CTRL_BC (1 << 20) | 435 | #define VI6_UDS_CTRL_BC BIT(20) |
| 436 | #define VI6_UDS_CTRL_NE_A (1 << 19) | 436 | #define VI6_UDS_CTRL_NE_A BIT(19) |
| 437 | #define VI6_UDS_CTRL_NE_RCR (1 << 18) | 437 | #define VI6_UDS_CTRL_NE_RCR BIT(18) |
| 438 | #define VI6_UDS_CTRL_NE_GY (1 << 17) | 438 | #define VI6_UDS_CTRL_NE_GY BIT(17) |
| 439 | #define VI6_UDS_CTRL_NE_BCB (1 << 16) | 439 | #define VI6_UDS_CTRL_NE_BCB BIT(16) |
| 440 | #define VI6_UDS_CTRL_AMDSLH (1 << 2) | 440 | #define VI6_UDS_CTRL_AMDSLH BIT(2) |
| 441 | #define VI6_UDS_CTRL_TDIPC (1 << 1) | 441 | #define VI6_UDS_CTRL_TDIPC BIT(1) |
| 442 | 442 | ||
| 443 | #define VI6_UDS_SCALE 0x2304 | 443 | #define VI6_UDS_SCALE 0x2304 |
| 444 | #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28) | 444 | #define VI6_UDS_SCALE_HMANT_MASK (0xf << 28) |
| @@ -477,12 +477,12 @@ | |||
| 477 | #define VI6_UDS_HPHASE_HEDP_SHIFT 0 | 477 | #define VI6_UDS_HPHASE_HEDP_SHIFT 0 |
| 478 | 478 | ||
| 479 | #define VI6_UDS_IPC 0x2318 | 479 | #define VI6_UDS_IPC 0x2318 |
| 480 | #define VI6_UDS_IPC_FIELD (1 << 27) | 480 | #define VI6_UDS_IPC_FIELD BIT(27) |
| 481 | #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0) | 481 | #define VI6_UDS_IPC_VEDP_MASK (0xfff << 0) |
| 482 | #define VI6_UDS_IPC_VEDP_SHIFT 0 | 482 | #define VI6_UDS_IPC_VEDP_SHIFT 0 |
| 483 | 483 | ||
| 484 | #define VI6_UDS_HSZCLIP 0x231c | 484 | #define VI6_UDS_HSZCLIP 0x231c |
| 485 | #define VI6_UDS_HSZCLIP_HCEN (1 << 28) | 485 | #define VI6_UDS_HSZCLIP_HCEN BIT(28) |
| 486 | #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16) | 486 | #define VI6_UDS_HSZCLIP_HCL_OFST_MASK (0xff << 16) |
| 487 | #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT 16 | 487 | #define VI6_UDS_HSZCLIP_HCL_OFST_SHIFT 16 |
| 488 | #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0) | 488 | #define VI6_UDS_HSZCLIP_HCL_SIZE_MASK (0x1fff << 0) |
| @@ -507,36 +507,36 @@ | |||
| 507 | */ | 507 | */ |
| 508 | 508 | ||
| 509 | #define VI6_LUT_CTRL 0x2800 | 509 | #define VI6_LUT_CTRL 0x2800 |
| 510 | #define VI6_LUT_CTRL_EN (1 << 0) | 510 | #define VI6_LUT_CTRL_EN BIT(0) |
| 511 | 511 | ||
| 512 | /* ----------------------------------------------------------------------------- | 512 | /* ----------------------------------------------------------------------------- |
| 513 | * CLU Control Registers | 513 | * CLU Control Registers |
| 514 | */ | 514 | */ |
| 515 | 515 | ||
| 516 | #define VI6_CLU_CTRL 0x2900 | 516 | #define VI6_CLU_CTRL 0x2900 |
| 517 | #define VI6_CLU_CTRL_AAI (1 << 28) | 517 | #define VI6_CLU_CTRL_AAI BIT(28) |
| 518 | #define VI6_CLU_CTRL_MVS (1 << 24) | 518 | #define VI6_CLU_CTRL_MVS BIT(24) |
| 519 | #define VI6_CLU_CTRL_AX1I_2D (3 << 14) | 519 | #define VI6_CLU_CTRL_AX1I_2D (3 << 14) |
| 520 | #define VI6_CLU_CTRL_AX2I_2D (1 << 12) | 520 | #define VI6_CLU_CTRL_AX2I_2D (1 << 12) |
| 521 | #define VI6_CLU_CTRL_OS0_2D (3 << 8) | 521 | #define VI6_CLU_CTRL_OS0_2D (3 << 8) |
| 522 | #define VI6_CLU_CTRL_OS1_2D (1 << 6) | 522 | #define VI6_CLU_CTRL_OS1_2D (1 << 6) |
| 523 | #define VI6_CLU_CTRL_OS2_2D (3 << 4) | 523 | #define VI6_CLU_CTRL_OS2_2D (3 << 4) |
| 524 | #define VI6_CLU_CTRL_M2D (1 << 1) | 524 | #define VI6_CLU_CTRL_M2D BIT(1) |
| 525 | #define VI6_CLU_CTRL_EN (1 << 0) | 525 | #define VI6_CLU_CTRL_EN BIT(0) |
| 526 | 526 | ||
| 527 | /* ----------------------------------------------------------------------------- | 527 | /* ----------------------------------------------------------------------------- |
| 528 | * HST Control Registers | 528 | * HST Control Registers |
| 529 | */ | 529 | */ |
| 530 | 530 | ||
| 531 | #define VI6_HST_CTRL 0x2a00 | 531 | #define VI6_HST_CTRL 0x2a00 |
| 532 | #define VI6_HST_CTRL_EN (1 << 0) | 532 | #define VI6_HST_CTRL_EN BIT(0) |
| 533 | 533 | ||
| 534 | /* ----------------------------------------------------------------------------- | 534 | /* ----------------------------------------------------------------------------- |
| 535 | * HSI Control Registers | 535 | * HSI Control Registers |
| 536 | */ | 536 | */ |
| 537 | 537 | ||
| 538 | #define VI6_HSI_CTRL 0x2b00 | 538 | #define VI6_HSI_CTRL 0x2b00 |
| 539 | #define VI6_HSI_CTRL_EN (1 << 0) | 539 | #define VI6_HSI_CTRL_EN BIT(0) |
| 540 | 540 | ||
| 541 | /* ----------------------------------------------------------------------------- | 541 | /* ----------------------------------------------------------------------------- |
| 542 | * BRS and BRU Control Registers | 542 | * BRS and BRU Control Registers |
| @@ -563,7 +563,7 @@ | |||
| 563 | #define VI6_BRS_BASE 0x3900 | 563 | #define VI6_BRS_BASE 0x3900 |
| 564 | 564 | ||
| 565 | #define VI6_BRU_INCTRL 0x0000 | 565 | #define VI6_BRU_INCTRL 0x0000 |
| 566 | #define VI6_BRU_INCTRL_NRM (1 << 28) | 566 | #define VI6_BRU_INCTRL_NRM BIT(28) |
| 567 | #define VI6_BRU_INCTRL_DnON (1 << (16 + (n))) | 567 | #define VI6_BRU_INCTRL_DnON (1 << (16 + (n))) |
| 568 | #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4)) | 568 | #define VI6_BRU_INCTRL_DITHn_OFF (0 << ((n) * 4)) |
| 569 | #define VI6_BRU_INCTRL_DITHn_18BPP (1 << ((n) * 4)) | 569 | #define VI6_BRU_INCTRL_DITHn_18BPP (1 << ((n) * 4)) |
| @@ -597,7 +597,7 @@ | |||
| 597 | #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0 | 597 | #define VI6_BRU_VIRRPF_COL_BCB_SHIFT 0 |
| 598 | 598 | ||
| 599 | #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4)) | 599 | #define VI6_BRU_CTRL(n) (0x0010 + (n) * 8 + ((n) <= 3 ? 0 : 4)) |
| 600 | #define VI6_BRU_CTRL_RBC (1 << 31) | 600 | #define VI6_BRU_CTRL_RBC BIT(31) |
| 601 | #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) | 601 | #define VI6_BRU_CTRL_DSTSEL_BRUIN(n) (((n) <= 3 ? (n) : (n)+1) << 20) |
| 602 | #define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20) | 602 | #define VI6_BRU_CTRL_DSTSEL_VRPF (4 << 20) |
| 603 | #define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20) | 603 | #define VI6_BRU_CTRL_DSTSEL_MASK (7 << 20) |
| @@ -610,7 +610,7 @@ | |||
| 610 | #define VI6_BRU_CTRL_AROP_MASK (0xf << 0) | 610 | #define VI6_BRU_CTRL_AROP_MASK (0xf << 0) |
| 611 | 611 | ||
| 612 | #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4)) | 612 | #define VI6_BRU_BLD(n) (0x0014 + (n) * 8 + ((n) <= 3 ? 0 : 4)) |
| 613 | #define VI6_BRU_BLD_CBES (1 << 31) | 613 | #define VI6_BRU_BLD_CBES BIT(31) |
| 614 | #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28) | 614 | #define VI6_BRU_BLD_CCMDX_DST_A (0 << 28) |
| 615 | #define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28) | 615 | #define VI6_BRU_BLD_CCMDX_255_DST_A (1 << 28) |
| 616 | #define VI6_BRU_BLD_CCMDX_SRC_A (2 << 28) | 616 | #define VI6_BRU_BLD_CCMDX_SRC_A (2 << 28) |
| @@ -624,7 +624,7 @@ | |||
| 624 | #define VI6_BRU_BLD_CCMDY_COEFY (4 << 24) | 624 | #define VI6_BRU_BLD_CCMDY_COEFY (4 << 24) |
| 625 | #define VI6_BRU_BLD_CCMDY_MASK (7 << 24) | 625 | #define VI6_BRU_BLD_CCMDY_MASK (7 << 24) |
| 626 | #define VI6_BRU_BLD_CCMDY_SHIFT 24 | 626 | #define VI6_BRU_BLD_CCMDY_SHIFT 24 |
| 627 | #define VI6_BRU_BLD_ABES (1 << 23) | 627 | #define VI6_BRU_BLD_ABES BIT(23) |
| 628 | #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20) | 628 | #define VI6_BRU_BLD_ACMDX_DST_A (0 << 20) |
| 629 | #define VI6_BRU_BLD_ACMDX_255_DST_A (1 << 20) | 629 | #define VI6_BRU_BLD_ACMDX_255_DST_A (1 << 20) |
| 630 | #define VI6_BRU_BLD_ACMDX_SRC_A (2 << 20) | 630 | #define VI6_BRU_BLD_ACMDX_SRC_A (2 << 20) |
| @@ -662,11 +662,11 @@ | |||
| 662 | #define VI6_HGO_SIZE_HSIZE_SHIFT 16 | 662 | #define VI6_HGO_SIZE_HSIZE_SHIFT 16 |
| 663 | #define VI6_HGO_SIZE_VSIZE_SHIFT 0 | 663 | #define VI6_HGO_SIZE_VSIZE_SHIFT 0 |
| 664 | #define VI6_HGO_MODE 0x3008 | 664 | #define VI6_HGO_MODE 0x3008 |
| 665 | #define VI6_HGO_MODE_STEP (1 << 10) | 665 | #define VI6_HGO_MODE_STEP BIT(10) |
| 666 | #define VI6_HGO_MODE_MAXRGB (1 << 7) | 666 | #define VI6_HGO_MODE_MAXRGB BIT(7) |
| 667 | #define VI6_HGO_MODE_OFSB_R (1 << 6) | 667 | #define VI6_HGO_MODE_OFSB_R BIT(6) |
| 668 | #define VI6_HGO_MODE_OFSB_G (1 << 5) | 668 | #define VI6_HGO_MODE_OFSB_G BIT(5) |
| 669 | #define VI6_HGO_MODE_OFSB_B (1 << 4) | 669 | #define VI6_HGO_MODE_OFSB_B BIT(4) |
| 670 | #define VI6_HGO_MODE_HRATIO_SHIFT 2 | 670 | #define VI6_HGO_MODE_HRATIO_SHIFT 2 |
| 671 | #define VI6_HGO_MODE_VRATIO_SHIFT 0 | 671 | #define VI6_HGO_MODE_VRATIO_SHIFT 0 |
| 672 | #define VI6_HGO_LB_TH 0x300c | 672 | #define VI6_HGO_LB_TH 0x300c |
| @@ -687,7 +687,7 @@ | |||
| 687 | #define VI6_HGO_EXT_HIST_ADDR 0x335c | 687 | #define VI6_HGO_EXT_HIST_ADDR 0x335c |
| 688 | #define VI6_HGO_EXT_HIST_DATA 0x3360 | 688 | #define VI6_HGO_EXT_HIST_DATA 0x3360 |
| 689 | #define VI6_HGO_REGRST 0x33fc | 689 | #define VI6_HGO_REGRST 0x33fc |
| 690 | #define VI6_HGO_REGRST_RCLEA (1 << 0) | 690 | #define VI6_HGO_REGRST_RCLEA BIT(0) |
| 691 | 691 | ||
| 692 | /* ----------------------------------------------------------------------------- | 692 | /* ----------------------------------------------------------------------------- |
| 693 | * HGT Control Registers | 693 | * HGT Control Registers |
| @@ -713,7 +713,7 @@ | |||
| 713 | #define VI6_HGT_SUM 0x3754 | 713 | #define VI6_HGT_SUM 0x3754 |
| 714 | #define VI6_HGT_LB_DET 0x3758 | 714 | #define VI6_HGT_LB_DET 0x3758 |
| 715 | #define VI6_HGT_REGRST 0x37fc | 715 | #define VI6_HGT_REGRST 0x37fc |
| 716 | #define VI6_HGT_REGRST_RCLEA (1 << 0) | 716 | #define VI6_HGT_REGRST_RCLEA BIT(0) |
| 717 | 717 | ||
| 718 | /* ----------------------------------------------------------------------------- | 718 | /* ----------------------------------------------------------------------------- |
| 719 | * LIF Control Registers | 719 | * LIF Control Registers |
| @@ -724,9 +724,9 @@ | |||
| 724 | #define VI6_LIF_CTRL 0x3b00 | 724 | #define VI6_LIF_CTRL 0x3b00 |
| 725 | #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16) | 725 | #define VI6_LIF_CTRL_OBTH_MASK (0x7ff << 16) |
| 726 | #define VI6_LIF_CTRL_OBTH_SHIFT 16 | 726 | #define VI6_LIF_CTRL_OBTH_SHIFT 16 |
| 727 | #define VI6_LIF_CTRL_CFMT (1 << 4) | 727 | #define VI6_LIF_CTRL_CFMT BIT(4) |
| 728 | #define VI6_LIF_CTRL_REQSEL (1 << 1) | 728 | #define VI6_LIF_CTRL_REQSEL BIT(1) |
| 729 | #define VI6_LIF_CTRL_LIF_EN (1 << 0) | 729 | #define VI6_LIF_CTRL_LIF_EN BIT(0) |
| 730 | 730 | ||
| 731 | #define VI6_LIF_CSBTH 0x3b04 | 731 | #define VI6_LIF_CSBTH 0x3b04 |
| 732 | #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16) | 732 | #define VI6_LIF_CSBTH_HBTH_MASK (0x7ff << 16) |
| @@ -735,7 +735,7 @@ | |||
| 735 | #define VI6_LIF_CSBTH_LBTH_SHIFT 0 | 735 | #define VI6_LIF_CSBTH_LBTH_SHIFT 0 |
| 736 | 736 | ||
| 737 | #define VI6_LIF_LBA 0x3b0c | 737 | #define VI6_LIF_LBA 0x3b0c |
| 738 | #define VI6_LIF_LBA_LBA0 (1 << 31) | 738 | #define VI6_LIF_LBA_LBA0 BIT(31) |
| 739 | #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16) | 739 | #define VI6_LIF_LBA_LBA1_MASK (0xfff << 16) |
| 740 | #define VI6_LIF_LBA_LBA1_SHIFT 16 | 740 | #define VI6_LIF_LBA_LBA1_SHIFT 16 |
| 741 | 741 | ||
diff --git a/drivers/media/platform/xilinx/xilinx-vip.h b/drivers/media/platform/xilinx/xilinx-vip.h index 47da39211ae4..f71e2b650453 100644 --- a/drivers/media/platform/xilinx/xilinx-vip.h +++ b/drivers/media/platform/xilinx/xilinx-vip.h | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #ifndef __XILINX_VIP_H__ | 12 | #ifndef __XILINX_VIP_H__ |
| 13 | #define __XILINX_VIP_H__ | 13 | #define __XILINX_VIP_H__ |
| 14 | 14 | ||
| 15 | #include <linux/bitops.h> | ||
| 15 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 16 | #include <media/v4l2-subdev.h> | 17 | #include <media/v4l2-subdev.h> |
| 17 | 18 | ||
| @@ -35,23 +36,23 @@ struct clk; | |||
| 35 | 36 | ||
| 36 | /* Xilinx Video IP Control Registers */ | 37 | /* Xilinx Video IP Control Registers */ |
| 37 | #define XVIP_CTRL_CONTROL 0x0000 | 38 | #define XVIP_CTRL_CONTROL 0x0000 |
| 38 | #define XVIP_CTRL_CONTROL_SW_ENABLE (1 << 0) | 39 | #define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0) |
| 39 | #define XVIP_CTRL_CONTROL_REG_UPDATE (1 << 1) | 40 | #define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1) |
| 40 | #define XVIP_CTRL_CONTROL_BYPASS (1 << 4) | 41 | #define XVIP_CTRL_CONTROL_BYPASS BIT(4) |
| 41 | #define XVIP_CTRL_CONTROL_TEST_PATTERN (1 << 5) | 42 | #define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5) |
| 42 | #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET (1 << 30) | 43 | #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30) |
| 43 | #define XVIP_CTRL_CONTROL_SW_RESET (1 << 31) | 44 | #define XVIP_CTRL_CONTROL_SW_RESET BIT(31) |
| 44 | #define XVIP_CTRL_STATUS 0x0004 | 45 | #define XVIP_CTRL_STATUS 0x0004 |
| 45 | #define XVIP_CTRL_STATUS_PROC_STARTED (1 << 0) | 46 | #define XVIP_CTRL_STATUS_PROC_STARTED BIT(0) |
| 46 | #define XVIP_CTRL_STATUS_EOF (1 << 1) | 47 | #define XVIP_CTRL_STATUS_EOF BIT(1) |
| 47 | #define XVIP_CTRL_ERROR 0x0008 | 48 | #define XVIP_CTRL_ERROR 0x0008 |
| 48 | #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY (1 << 0) | 49 | #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0) |
| 49 | #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE (1 << 1) | 50 | #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1) |
| 50 | #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY (1 << 2) | 51 | #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2) |
| 51 | #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE (1 << 3) | 52 | #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3) |
| 52 | #define XVIP_CTRL_IRQ_ENABLE 0x000c | 53 | #define XVIP_CTRL_IRQ_ENABLE 0x000c |
| 53 | #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED (1 << 0) | 54 | #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0) |
| 54 | #define XVIP_CTRL_IRQ_EOF (1 << 1) | 55 | #define XVIP_CTRL_IRQ_EOF BIT(1) |
| 55 | #define XVIP_CTRL_VERSION 0x0010 | 56 | #define XVIP_CTRL_VERSION 0x0010 |
| 56 | #define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24) | 57 | #define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24) |
| 57 | #define XVIP_CTRL_VERSION_MAJOR_SHIFT 24 | 58 | #define XVIP_CTRL_VERSION_MAJOR_SHIFT 24 |
diff --git a/drivers/media/radio/wl128x/fmdrv_common.h b/drivers/media/radio/wl128x/fmdrv_common.h index 7d7a2b17aa76..6a287eadae75 100644 --- a/drivers/media/radio/wl128x/fmdrv_common.h +++ b/drivers/media/radio/wl128x/fmdrv_common.h | |||
| @@ -159,18 +159,18 @@ struct fm_event_msg_hdr { | |||
| 159 | #define FM_DISABLE 0 | 159 | #define FM_DISABLE 0 |
| 160 | 160 | ||
| 161 | /* FLAG_GET register bits */ | 161 | /* FLAG_GET register bits */ |
| 162 | #define FM_FR_EVENT (1 << 0) | 162 | #define FM_FR_EVENT BIT(0) |
| 163 | #define FM_BL_EVENT (1 << 1) | 163 | #define FM_BL_EVENT BIT(1) |
| 164 | #define FM_RDS_EVENT (1 << 2) | 164 | #define FM_RDS_EVENT BIT(2) |
| 165 | #define FM_BBLK_EVENT (1 << 3) | 165 | #define FM_BBLK_EVENT BIT(3) |
| 166 | #define FM_LSYNC_EVENT (1 << 4) | 166 | #define FM_LSYNC_EVENT BIT(4) |
| 167 | #define FM_LEV_EVENT (1 << 5) | 167 | #define FM_LEV_EVENT BIT(5) |
| 168 | #define FM_IFFR_EVENT (1 << 6) | 168 | #define FM_IFFR_EVENT BIT(6) |
| 169 | #define FM_PI_EVENT (1 << 7) | 169 | #define FM_PI_EVENT BIT(7) |
| 170 | #define FM_PD_EVENT (1 << 8) | 170 | #define FM_PD_EVENT BIT(8) |
| 171 | #define FM_STIC_EVENT (1 << 9) | 171 | #define FM_STIC_EVENT BIT(9) |
| 172 | #define FM_MAL_EVENT (1 << 10) | 172 | #define FM_MAL_EVENT BIT(10) |
| 173 | #define FM_POW_ENB_EVENT (1 << 11) | 173 | #define FM_POW_ENB_EVENT BIT(11) |
| 174 | 174 | ||
| 175 | /* | 175 | /* |
| 176 | * Firmware files of FM. ASIC ID and ASIC version will be appened to this, | 176 | * Firmware files of FM. ASIC ID and ASIC version will be appened to this, |
| @@ -268,38 +268,38 @@ struct fm_event_msg_hdr { | |||
| 268 | * Represents an RDS group type & version. | 268 | * Represents an RDS group type & version. |
| 269 | * There are 15 groups, each group has 2 versions: A and B. | 269 | * There are 15 groups, each group has 2 versions: A and B. |
| 270 | */ | 270 | */ |
| 271 | #define FM_RDS_GROUP_TYPE_MASK_0A ((unsigned long)1<<0) | 271 | #define FM_RDS_GROUP_TYPE_MASK_0A BIT(0) |
| 272 | #define FM_RDS_GROUP_TYPE_MASK_0B ((unsigned long)1<<1) | 272 | #define FM_RDS_GROUP_TYPE_MASK_0B BIT(1) |
| 273 | #define FM_RDS_GROUP_TYPE_MASK_1A ((unsigned long)1<<2) | 273 | #define FM_RDS_GROUP_TYPE_MASK_1A BIT(2) |
| 274 | #define FM_RDS_GROUP_TYPE_MASK_1B ((unsigned long)1<<3) | 274 | #define FM_RDS_GROUP_TYPE_MASK_1B BIT(3) |
| 275 | #define FM_RDS_GROUP_TYPE_MASK_2A ((unsigned long)1<<4) | 275 | #define FM_RDS_GROUP_TYPE_MASK_2A BIT(4) |
| 276 | #define FM_RDS_GROUP_TYPE_MASK_2B ((unsigned long)1<<5) | 276 | #define FM_RDS_GROUP_TYPE_MASK_2B BIT(5) |
| 277 | #define FM_RDS_GROUP_TYPE_MASK_3A ((unsigned long)1<<6) | 277 | #define FM_RDS_GROUP_TYPE_MASK_3A BIT(6) |
| 278 | #define FM_RDS_GROUP_TYPE_MASK_3B ((unsigned long)1<<7) | 278 | #define FM_RDS_GROUP_TYPE_MASK_3B BIT(7) |
| 279 | #define FM_RDS_GROUP_TYPE_MASK_4A ((unsigned long)1<<8) | 279 | #define FM_RDS_GROUP_TYPE_MASK_4A BIT(8) |
| 280 | #define FM_RDS_GROUP_TYPE_MASK_4B ((unsigned long)1<<9) | 280 | #define FM_RDS_GROUP_TYPE_MASK_4B BIT(9) |
| 281 | #define FM_RDS_GROUP_TYPE_MASK_5A ((unsigned long)1<<10) | 281 | #define FM_RDS_GROUP_TYPE_MASK_5A BIT(10) |
| 282 | #define FM_RDS_GROUP_TYPE_MASK_5B ((unsigned long)1<<11) | 282 | #define FM_RDS_GROUP_TYPE_MASK_5B BIT(11) |
| 283 | #define FM_RDS_GROUP_TYPE_MASK_6A ((unsigned long)1<<12) | 283 | #define FM_RDS_GROUP_TYPE_MASK_6A BIT(12) |
| 284 | #define FM_RDS_GROUP_TYPE_MASK_6B ((unsigned long)1<<13) | 284 | #define FM_RDS_GROUP_TYPE_MASK_6B BIT(13) |
| 285 | #define FM_RDS_GROUP_TYPE_MASK_7A ((unsigned long)1<<14) | 285 | #define FM_RDS_GROUP_TYPE_MASK_7A BIT(14) |
| 286 | #define FM_RDS_GROUP_TYPE_MASK_7B ((unsigned long)1<<15) | 286 | #define FM_RDS_GROUP_TYPE_MASK_7B BIT(15) |
| 287 | #define FM_RDS_GROUP_TYPE_MASK_8A ((unsigned long)1<<16) | 287 | #define FM_RDS_GROUP_TYPE_MASK_8A BIT(16) |
| 288 | #define FM_RDS_GROUP_TYPE_MASK_8B ((unsigned long)1<<17) | 288 | #define FM_RDS_GROUP_TYPE_MASK_8B BIT(17) |
| 289 | #define FM_RDS_GROUP_TYPE_MASK_9A ((unsigned long)1<<18) | 289 | #define FM_RDS_GROUP_TYPE_MASK_9A BIT(18) |
| 290 | #define FM_RDS_GROUP_TYPE_MASK_9B ((unsigned long)1<<19) | 290 | #define FM_RDS_GROUP_TYPE_MASK_9B BIT(19) |
| 291 | #define FM_RDS_GROUP_TYPE_MASK_10A ((unsigned long)1<<20) | 291 | #define FM_RDS_GROUP_TYPE_MASK_10A BIT(20) |
| 292 | #define FM_RDS_GROUP_TYPE_MASK_10B ((unsigned long)1<<21) | 292 | #define FM_RDS_GROUP_TYPE_MASK_10B BIT(21) |
| 293 | #define FM_RDS_GROUP_TYPE_MASK_11A ((unsigned long)1<<22) | 293 | #define FM_RDS_GROUP_TYPE_MASK_11A BIT(22) |
| 294 | #define FM_RDS_GROUP_TYPE_MASK_11B ((unsigned long)1<<23) | 294 | #define FM_RDS_GROUP_TYPE_MASK_11B BIT(23) |
| 295 | #define FM_RDS_GROUP_TYPE_MASK_12A ((unsigned long)1<<24) | 295 | #define FM_RDS_GROUP_TYPE_MASK_12A BIT(24) |
| 296 | #define FM_RDS_GROUP_TYPE_MASK_12B ((unsigned long)1<<25) | 296 | #define FM_RDS_GROUP_TYPE_MASK_12B BIT(25) |
| 297 | #define FM_RDS_GROUP_TYPE_MASK_13A ((unsigned long)1<<26) | 297 | #define FM_RDS_GROUP_TYPE_MASK_13A BIT(26) |
| 298 | #define FM_RDS_GROUP_TYPE_MASK_13B ((unsigned long)1<<27) | 298 | #define FM_RDS_GROUP_TYPE_MASK_13B BIT(27) |
| 299 | #define FM_RDS_GROUP_TYPE_MASK_14A ((unsigned long)1<<28) | 299 | #define FM_RDS_GROUP_TYPE_MASK_14A BIT(28) |
| 300 | #define FM_RDS_GROUP_TYPE_MASK_14B ((unsigned long)1<<29) | 300 | #define FM_RDS_GROUP_TYPE_MASK_14B BIT(29) |
| 301 | #define FM_RDS_GROUP_TYPE_MASK_15A ((unsigned long)1<<30) | 301 | #define FM_RDS_GROUP_TYPE_MASK_15A BIT(30) |
| 302 | #define FM_RDS_GROUP_TYPE_MASK_15B ((unsigned long)1<<31) | 302 | #define FM_RDS_GROUP_TYPE_MASK_15B BIT(31) |
| 303 | 303 | ||
| 304 | /* RX Alternate Frequency info */ | 304 | /* RX Alternate Frequency info */ |
| 305 | #define FM_RDS_MIN_AF 1 | 305 | #define FM_RDS_MIN_AF 1 |
diff --git a/drivers/staging/media/ipu3/ipu3-tables.h b/drivers/staging/media/ipu3/ipu3-tables.h index a1bf3286f380..9f719c48b432 100644 --- a/drivers/staging/media/ipu3/ipu3-tables.h +++ b/drivers/staging/media/ipu3/ipu3-tables.h | |||
| @@ -4,6 +4,8 @@ | |||
| 4 | #ifndef __IPU3_TABLES_H | 4 | #ifndef __IPU3_TABLES_H |
| 5 | #define __IPU3_TABLES_H | 5 | #define __IPU3_TABLES_H |
| 6 | 6 | ||
| 7 | #include <linux/bitops.h> | ||
| 8 | |||
| 7 | #include "ipu3-abi.h" | 9 | #include "ipu3-abi.h" |
| 8 | 10 | ||
| 9 | #define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */ | 11 | #define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */ |
| @@ -12,7 +14,7 @@ | |||
| 12 | 14 | ||
| 13 | #define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128 | 15 | #define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128 |
| 14 | #define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64 | 16 | #define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64 |
| 15 | #define IMGU_SCALER_FP ((u32)1 << 31) /* 1.0 in fixed point */ | 17 | #define IMGU_SCALER_FP BIT(31) /* 1.0 in fixed point */ |
| 16 | 18 | ||
| 17 | #define IMGU_XNR3_VMEM_LUT_LEN 16 | 19 | #define IMGU_XNR3_VMEM_LUT_LEN 16 |
| 18 | 20 | ||