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authorChen-Yu Tsai <wens@csie.org>2017-05-31 03:58:21 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-05-31 15:57:27 -0400
commitc4be8c68e6900b1811bc64f74cb13d5032a389ce (patch)
tree1cffd42e211b79ba430da8b611387e266da6c387
parenta91afc974ee8441940241e3c39c75d7b8f38e911 (diff)
clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.h4
-rw-r--r--include/dt-bindings/clock/sun8i-h3-ccu.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 85973d1e8165..1b4baea37d81 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -29,7 +29,9 @@
29#define CLK_PLL_VIDEO 6 29#define CLK_PLL_VIDEO 6
30#define CLK_PLL_VE 7 30#define CLK_PLL_VE 7
31#define CLK_PLL_DDR 8 31#define CLK_PLL_DDR 8
32#define CLK_PLL_PERIPH0 9 32
33/* PLL_PERIPH0 exported for PRCM */
34
33#define CLK_PLL_PERIPH0_2X 10 35#define CLK_PLL_PERIPH0_2X 10
34#define CLK_PLL_GPU 11 36#define CLK_PLL_GPU 11
35#define CLK_PLL_PERIPH1 12 37#define CLK_PLL_PERIPH1 12
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index c2afc41d6964..e139fe5c62ec 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -43,6 +43,8 @@
43#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ 43#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
44#define _DT_BINDINGS_CLK_SUN8I_H3_H_ 44#define _DT_BINDINGS_CLK_SUN8I_H3_H_
45 45
46#define CLK_PLL_PERIPH0 9
47
46#define CLK_CPUX 14 48#define CLK_CPUX 14
47 49
48#define CLK_BUS_CE 20 50#define CLK_BUS_CE 20