summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMaxime Chevallier <maxime.chevallier@bootlin.com>2019-02-22 18:37:42 -0500
committerDavid S. Miller <davem@davemloft.net>2019-02-24 20:45:25 -0500
commitc47455f9a7fc9129cb2e8d839e8bb70b96d7ded2 (patch)
tree802b3be0552584ef1e6a3500f37d85eaffaac580
parent631ba9063b446800e96debb41ad45eba85f880a8 (diff)
net: phy: marvell10g: Force reading of 2.5/5G
As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates whether or not we should read register (1.21) "2.52/5G PMA Extended Abilities", which contains information on the support of 2.5GBASET and 5GBASET. After testing on several variants of PHYS of this family, it appears that bit 14 in (1.11) isn't always set when it should be. PHYs 88X3310 (on MacchiatoBin) and 88E2010 do support 2.5G and 5GBASET, but don't have 1.11.14 set. Their register 1.21 is filled with the correct values, indicating 2.5G and 5G support. PHYs 88E2110 do have their 1.11.14 bit set, as it should. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/phy/marvell10g.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9c0b8f16cec5..8f354c3f3876 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -27,6 +27,9 @@
27#include <linux/marvell_phy.h> 27#include <linux/marvell_phy.h>
28#include <linux/phy.h> 28#include <linux/phy.h>
29 29
30#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
31#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
32
30enum { 33enum {
31 MV_PCS_BASE_T = 0x0000, 34 MV_PCS_BASE_T = 0x0000,
32 MV_PCS_BASE_R = 0x1000, 35 MV_PCS_BASE_R = 0x1000,
@@ -231,6 +234,23 @@ static int mv3310_resume(struct phy_device *phydev)
231 return mv3310_hwmon_config(phydev, true); 234 return mv3310_hwmon_config(phydev, true);
232} 235}
233 236
237/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
238 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
239 * support 2.5GBASET and 5GBASET. For these models, we can still read their
240 * 2.5G/5G extended abilities register (1.21). We detect these models based on
241 * the PMA device identifier, with a mask matching models known to have this
242 * issue
243 */
244static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
245{
246 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
247 return false;
248
249 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
250 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
251 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
252}
253
234static int mv3310_config_init(struct phy_device *phydev) 254static int mv3310_config_init(struct phy_device *phydev)
235{ 255{
236 /* Check that the PHY interface type is compatible */ 256 /* Check that the PHY interface type is compatible */
@@ -262,6 +282,21 @@ static int mv3310_get_features(struct phy_device *phydev)
262 if (ret) 282 if (ret)
263 return ret; 283 return ret;
264 284
285 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
286 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
287 MDIO_PMA_NG_EXTABLE);
288 if (val < 0)
289 return val;
290
291 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
292 phydev->supported,
293 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
294
295 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
296 phydev->supported,
297 val & MDIO_PMA_NG_EXTABLE_5GBT);
298 }
299
265 return 0; 300 return 0;
266} 301}
267 302