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authorAndrey Smirnov <andrew.smirnov@gmail.com>2016-06-18 21:09:27 -0400
committerShawn Guo <shawnguo@kernel.org>2016-06-21 08:39:25 -0400
commitc00e4c54d56cdce018e9b09614511e5ad17e2f8c (patch)
tree711c4d2ae10c83c881c2820f8479005e785da18f
parentead812669980aad571fdcfeb239d47c405dd248b (diff)
ARM: i.MX: system.c: Convert goto to if statement
Using goto here doesn't bring any advantages and only makes the code flow less clear. No functional changes. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/mach-imx/system.c36
1 files changed, 17 insertions, 19 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 105d1ce4ed9d..d9f8b0e1d96a 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -106,26 +106,24 @@ void __init imx_init_l2cache(void)
106 goto out; 106 goto out;
107 } 107 }
108 108
109 if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) 109 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
110 goto skip_if_enabled; 110 /* Configure the L2 PREFETCH and POWER registers */
111 111 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
112 /* Configure the L2 PREFETCH and POWER registers */ 112 val |= 0x70800000;
113 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); 113 /*
114 val |= 0x70800000; 114 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
115 /* 115 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
116 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 116 * But according to ARM PL310 errata: 752271
117 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 117 * ID: 752271: Double linefill feature can cause data corruption
118 * But according to ARM PL310 errata: 752271 118 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
119 * ID: 752271: Double linefill feature can cause data corruption 119 * Workaround: The only workaround to this erratum is to disable the
120 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 120 * double linefill feature. This is the default behavior.
121 * Workaround: The only workaround to this erratum is to disable the 121 */
122 * double linefill feature. This is the default behavior. 122 if (cpu_is_imx6q())
123 */ 123 val &= ~(1 << 30 | 1 << 23);
124 if (cpu_is_imx6q()) 124 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
125 val &= ~(1 << 30 | 1 << 23); 125 }
126 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
127 126
128skip_if_enabled:
129 iounmap(l2x0_base); 127 iounmap(l2x0_base);
130 of_node_put(np); 128 of_node_put(np);
131 129