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authorMark Brown <broonie@kernel.org>2019-09-15 05:32:06 -0400
committerMark Brown <broonie@kernel.org>2019-09-15 05:32:06 -0400
commitb769c5ba8aedc395ed04abe6db84a556d28beec1 (patch)
treedd00c955f899f65785d60c2b4673785c28054b30
parent262a2f33454fcecdc2032ca84d6fecdb08233468 (diff)
parentfdeae8f5a2e5eb3fcc9c295bfb28503c3abd4d6e (diff)
Merge branch 'spi-5.4' into spi-next
Diffstat
-rw-r--r--Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt47
-rw-r--r--Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt9
-rw-r--r--Documentation/devicetree/bindings/spi/spi-mt65xx.txt1
-rw-r--r--Documentation/devicetree/bindings/spi/spi-sprd-adi.txt11
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c2
-rw-r--r--arch/arm/mach-ep93xx/simone.c2
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c4
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c2
-rw-r--r--drivers/dma/bcm2835-dma.c38
-rw-r--r--drivers/platform/chrome/cros_ec_spi.c2
-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/atmel-quadspi.c1
-rw-r--r--drivers/spi/spi-altera.c4
-rw-r--r--drivers/spi/spi-armada-3700.c5
-rw-r--r--drivers/spi/spi-ath79.c4
-rw-r--r--drivers/spi/spi-atmel.c5
-rw-r--r--drivers/spi/spi-axi-spi-engine.c4
-rw-r--r--drivers/spi/spi-bcm-qspi.c1
-rw-r--r--drivers/spi/spi-bcm2835.c456
-rw-r--r--drivers/spi/spi-bcm2835aux.c5
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c8
-rw-r--r--drivers/spi/spi-bcm63xx.c4
-rw-r--r--drivers/spi/spi-cadence.c5
-rw-r--r--drivers/spi/spi-cavium-octeon.c4
-rw-r--r--drivers/spi/spi-clps711x.c4
-rw-r--r--drivers/spi/spi-coldfire-qspi.c4
-rw-r--r--drivers/spi/spi-dw-mmio.c18
-rw-r--r--drivers/spi/spi-dw-pci.c6
-rw-r--r--drivers/spi/spi-efm32.c4
-rw-r--r--drivers/spi/spi-ep93xx.c4
-rw-r--r--drivers/spi/spi-fsl-cpm.c6
-rw-r--r--drivers/spi/spi-fsl-dspi.c720
-rw-r--r--drivers/spi/spi-fsl-lib.h3
-rw-r--r--drivers/spi/spi-fsl-qspi.c4
-rw-r--r--drivers/spi/spi-fsl-spi.c193
-rw-r--r--drivers/spi/spi-geni-qcom.c8
-rw-r--r--drivers/spi/spi-gpio.c5
-rw-r--r--drivers/spi/spi-lantiq-ssc.c12
-rw-r--r--drivers/spi/spi-lp8841-rtc.c4
-rw-r--r--drivers/spi/spi-meson-spicc.c4
-rw-r--r--drivers/spi/spi-meson-spifc.c4
-rw-r--r--drivers/spi/spi-mt65xx.c54
-rw-r--r--drivers/spi/spi-mt7621.c4
-rw-r--r--drivers/spi/spi-mxs.c4
-rw-r--r--drivers/spi/spi-npcm-fiu.c769
-rw-r--r--drivers/spi/spi-npcm-pspi.c5
-rw-r--r--drivers/spi/spi-nuc900.c5
-rw-r--r--drivers/spi/spi-nxp-fspi.c4
-rw-r--r--drivers/spi/spi-oc-tiny.c4
-rw-r--r--drivers/spi/spi-pic32-sqi.c5
-rw-r--r--drivers/spi/spi-pic32.c12
-rw-r--r--drivers/spi/spi-qcom-qspi.c8
-rw-r--r--drivers/spi/spi-rb4xx.c4
-rw-r--r--drivers/spi/spi-s3c24xx.c5
-rw-r--r--drivers/spi/spi-sh-msiof.c5
-rw-r--r--drivers/spi/spi-sh.c4
-rw-r--r--drivers/spi/spi-sifive.c5
-rw-r--r--drivers/spi/spi-sirf.c4
-rw-r--r--drivers/spi/spi-slave-mt27xx.c1
-rw-r--r--drivers/spi/spi-sprd-adi.c92
-rw-r--r--drivers/spi/spi-sprd.c4
-rw-r--r--drivers/spi/spi-st-ssc4.c4
-rw-r--r--drivers/spi/spi-stm32-qspi.c5
-rw-r--r--drivers/spi/spi-sun4i.c5
-rw-r--r--drivers/spi/spi-sun6i.c5
-rw-r--r--drivers/spi/spi-synquacer.c2
-rw-r--r--drivers/spi/spi-tegra20-sflash.c4
-rw-r--r--drivers/spi/spi-ti-qspi.c1
-rw-r--r--drivers/spi/spi-uniphier.c89
-rw-r--r--drivers/spi/spi-xlp.c8
-rw-r--r--drivers/spi/spi-zynq-qspi.c5
-rw-r--r--drivers/spi/spi-zynqmp-gqspi.c5
-rw-r--r--drivers/spi/spi.c53
74 files changed, 1921 insertions, 901 deletions
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
new file mode 100644
index 000000000000..a388005842ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
@@ -0,0 +1,47 @@
1* Nuvoton FLASH Interface Unit (FIU) SPI Controller
2
3NPCM FIU supports single, dual and quad communication interface.
4
5The NPCM7XX supports three FIU modules,
6FIU0 and FIUx supports two chip selects,
7FIU3 support four chip select.
8
9Required properties:
10 - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
11 - #address-cells : should be 1.
12 - #size-cells : should be 0.
13 - reg : the first contains the register location and length,
14 the second contains the memory mapping address and length
15 - reg-names: Should contain the reg names "control" and "memory"
16 - clocks : phandle of FIU reference clock.
17
18Required properties in case the pins can be muxed:
19 - pinctrl-names : a pinctrl state named "default" must be defined.
20 - pinctrl-0 : phandle referencing pin configuration of the device.
21
22Optional property:
23 - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
24
25Aliases:
26- All the FIU controller nodes should be represented in the aliases node using
27 the following format 'fiu{n}' where n is a unique number for the alias.
28 In the NPCM7XX BMC:
29 fiu0 represent fiu 0 controller
30 fiu1 represent fiu 3 controller
31 fiu2 represent fiu x controller
32
33Example:
34fiu3: spi@c00000000 {
35 compatible = "nuvoton,npcm750-fiu";
36 #address-cells = <1>;
37 #size-cells = <0>;
38 reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
39 reg-names = "control", "memory";
40 clocks = <&clk NPCM7XX_CLK_AHB>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&spi3_pins>;
43 spi-nor@0 {
44 ...
45 };
46};
47
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
index e8f1d627d288..69dc5d57b1ef 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt
@@ -3,9 +3,8 @@
3Required properties: 3Required properties:
4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", 4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi", 5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
6 "fsl,ls1021a-qspi" 6 "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
7 or 7 or
8 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
9 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" 8 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
10 - reg : the first contains the register location and length, 9 - reg : the first contains the register location and length,
11 the second contains the memory mapping address and length 10 the second contains the memory mapping address and length
@@ -34,7 +33,11 @@ qspi0: quadspi@40044000 {
34 clock-names = "qspi_en", "qspi"; 33 clock-names = "qspi_en", "qspi";
35 34
36 flash0: s25fl128s@0 { 35 flash0: s25fl128s@0 {
37 .... 36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "spansion,s25fl128s", "jedec,spi-nor";
39 spi-max-frequency = <50000000>;
40 reg = <0>;
38 }; 41 };
39}; 42};
40 43
diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
index c0f6c8ecfa2e..3a8079eb18c8 100644
--- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
+++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
@@ -5,6 +5,7 @@ Required properties:
5 - mediatek,mt2701-spi: for mt2701 platforms 5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms 6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms 7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
8 - mediatek,mt7622-spi: for mt7622 platforms 9 - mediatek,mt7622-spi: for mt7622 platforms
9 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms 10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
10 - mediatek,mt8135-spi: for mt8135 platforms 11 - mediatek,mt8135-spi: for mt8135 platforms
diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt
index 8de589b376ce..2567c829e2dc 100644
--- a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt
@@ -25,18 +25,23 @@ data by ADI software channels at the same time, or two parallel routine of setti
25ADI registers will make ADI controller registers chaos to lead incorrect results. 25ADI registers will make ADI controller registers chaos to lead incorrect results.
26Then we need one hardware spinlock to synchronize between the multiple subsystems. 26Then we need one hardware spinlock to synchronize between the multiple subsystems.
27 27
28The new version ADI controller supplies multiple master channels for different
29subsystem accessing, that means no need to add hardware spinlock to synchronize,
30thus change the hardware spinlock support to be optional to keep backward
31compatibility.
32
28Required properties: 33Required properties:
29- compatible: Should be "sprd,sc9860-adi". 34- compatible: Should be "sprd,sc9860-adi".
30- reg: Offset and length of ADI-SPI controller register space. 35- reg: Offset and length of ADI-SPI controller register space.
31- hwlocks: Reference to a phandle of a hwlock provider node.
32- hwlock-names: Reference to hwlock name strings defined in the same order
33 as the hwlocks, should be "adi".
34- #address-cells: Number of cells required to define a chip select address 36- #address-cells: Number of cells required to define a chip select address
35 on the ADI-SPI bus. Should be set to 1. 37 on the ADI-SPI bus. Should be set to 1.
36- #size-cells: Size of cells required to define a chip select address size 38- #size-cells: Size of cells required to define a chip select address size
37 on the ADI-SPI bus. Should be set to 0. 39 on the ADI-SPI bus. Should be set to 0.
38 40
39Optional properties: 41Optional properties:
42- hwlocks: Reference to a phandle of a hwlock provider node.
43- hwlock-names: Reference to hwlock name strings defined in the same order
44 as the hwlocks, should be "adi".
40- sprd,hw-channels: This is an array of channel values up to 49 channels. 45- sprd,hw-channels: This is an array of channel values up to 49 channels.
41 The first value specifies the hardware channel id which is used to 46 The first value specifies the hardware channel id which is used to
42 transfer data triggered by hardware automatically, and the second 47 transfer data triggered by hardware automatically, and the second
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 1f0da76a39de..7b7280c21ee0 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -103,7 +103,7 @@ static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
103}; 103};
104 104
105static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = { 105static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = {
106 .dev_id = "ep93xx-spi.0", 106 .dev_id = "spi0",
107 .table = { 107 .table = {
108 GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW), 108 GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW),
109 { }, 109 { },
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index e2658e22bba1..8a53b74dc4b2 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -73,7 +73,7 @@ static struct spi_board_info simone_spi_devices[] __initdata = {
73 * v1.3 parts will still work, since the signal on SFRMOUT is automatic. 73 * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
74 */ 74 */
75static struct gpiod_lookup_table simone_spi_cs_gpio_table = { 75static struct gpiod_lookup_table simone_spi_cs_gpio_table = {
76 .dev_id = "ep93xx-spi.0", 76 .dev_id = "spi0",
77 .table = { 77 .table = {
78 GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW), 78 GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW),
79 { }, 79 { },
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 582e06e104fd..e0e1b11032f1 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -267,7 +267,7 @@ static struct spi_board_info bk3_spi_board_info[] __initdata = {
267 * goes through CPLD 267 * goes through CPLD
268 */ 268 */
269static struct gpiod_lookup_table bk3_spi_cs_gpio_table = { 269static struct gpiod_lookup_table bk3_spi_cs_gpio_table = {
270 .dev_id = "ep93xx-spi.0", 270 .dev_id = "spi0",
271 .table = { 271 .table = {
272 GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW), 272 GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW),
273 { }, 273 { },
@@ -316,7 +316,7 @@ static struct spi_board_info ts72xx_spi_devices[] __initdata = {
316}; 316};
317 317
318static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table = { 318static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table = {
319 .dev_id = "ep93xx-spi.0", 319 .dev_id = "spi0",
320 .table = { 320 .table = {
321 /* DIO_17 */ 321 /* DIO_17 */
322 GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW), 322 GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW),
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index a88a1d807b32..cbcba3136d74 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -242,7 +242,7 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
242}; 242};
243 243
244static struct gpiod_lookup_table vision_spi_cs_gpio_table = { 244static struct gpiod_lookup_table vision_spi_cs_gpio_table = {
245 .dev_id = "ep93xx-spi.0", 245 .dev_id = "spi0",
246 .table = { 246 .table = {
247 GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW), 247 GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW),
248 GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW), 248 GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW),
diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 8101ff2f05c1..67100e4e1083 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -37,10 +37,19 @@
37#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 37#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
38#define BCM2835_DMA_CHAN_NAME_SIZE 8 38#define BCM2835_DMA_CHAN_NAME_SIZE 8
39 39
40/**
41 * struct bcm2835_dmadev - BCM2835 DMA controller
42 * @ddev: DMA device
43 * @base: base address of register map
44 * @dma_parms: DMA parameters (to convey 1 GByte max segment size to clients)
45 * @zero_page: bus address of zero page (to detect transactions copying from
46 * zero page and avoid accessing memory if so)
47 */
40struct bcm2835_dmadev { 48struct bcm2835_dmadev {
41 struct dma_device ddev; 49 struct dma_device ddev;
42 void __iomem *base; 50 void __iomem *base;
43 struct device_dma_parameters dma_parms; 51 struct device_dma_parameters dma_parms;
52 dma_addr_t zero_page;
44}; 53};
45 54
46struct bcm2835_dma_cb { 55struct bcm2835_dma_cb {
@@ -687,11 +696,12 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
687 size_t period_len, enum dma_transfer_direction direction, 696 size_t period_len, enum dma_transfer_direction direction,
688 unsigned long flags) 697 unsigned long flags)
689{ 698{
699 struct bcm2835_dmadev *od = to_bcm2835_dma_dev(chan->device);
690 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 700 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
691 struct bcm2835_desc *d; 701 struct bcm2835_desc *d;
692 dma_addr_t src, dst; 702 dma_addr_t src, dst;
693 u32 info = BCM2835_DMA_WAIT_RESP; 703 u32 info = BCM2835_DMA_WAIT_RESP;
694 u32 extra = BCM2835_DMA_INT_EN; 704 u32 extra = 0;
695 size_t max_len = bcm2835_dma_max_frame_length(c); 705 size_t max_len = bcm2835_dma_max_frame_length(c);
696 size_t frames; 706 size_t frames;
697 707
@@ -707,6 +717,11 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
707 return NULL; 717 return NULL;
708 } 718 }
709 719
720 if (flags & DMA_PREP_INTERRUPT)
721 extra |= BCM2835_DMA_INT_EN;
722 else
723 period_len = buf_len;
724
710 /* 725 /*
711 * warn if buf_len is not a multiple of period_len - this may leed 726 * warn if buf_len is not a multiple of period_len - this may leed
712 * to unexpected latencies for interrupts and thus audiable clicks 727 * to unexpected latencies for interrupts and thus audiable clicks
@@ -732,6 +747,10 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
732 dst = c->cfg.dst_addr; 747 dst = c->cfg.dst_addr;
733 src = buf_addr; 748 src = buf_addr;
734 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; 749 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
750
751 /* non-lite channels can write zeroes w/o accessing memory */
752 if (buf_addr == od->zero_page && !c->is_lite_channel)
753 info |= BCM2835_DMA_S_IGNORE;
735 } 754 }
736 755
737 /* calculate number of frames */ 756 /* calculate number of frames */
@@ -778,7 +797,10 @@ static int bcm2835_dma_terminate_all(struct dma_chan *chan)
778 797
779 /* stop DMA activity */ 798 /* stop DMA activity */
780 if (c->desc) { 799 if (c->desc) {
781 vchan_terminate_vdesc(&c->desc->vd); 800 if (c->desc->vd.tx.flags & DMA_PREP_INTERRUPT)
801 vchan_terminate_vdesc(&c->desc->vd);
802 else
803 vchan_vdesc_fini(&c->desc->vd);
782 c->desc = NULL; 804 c->desc = NULL;
783 bcm2835_dma_abort(c); 805 bcm2835_dma_abort(c);
784 } 806 }
@@ -831,6 +853,9 @@ static void bcm2835_dma_free(struct bcm2835_dmadev *od)
831 list_del(&c->vc.chan.device_node); 853 list_del(&c->vc.chan.device_node);
832 tasklet_kill(&c->vc.task); 854 tasklet_kill(&c->vc.task);
833 } 855 }
856
857 dma_unmap_page_attrs(od->ddev.dev, od->zero_page, PAGE_SIZE,
858 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
834} 859}
835 860
836static const struct of_device_id bcm2835_dma_of_match[] = { 861static const struct of_device_id bcm2835_dma_of_match[] = {
@@ -907,11 +932,20 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
907 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 932 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
908 BIT(DMA_MEM_TO_MEM); 933 BIT(DMA_MEM_TO_MEM);
909 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 934 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
935 od->ddev.descriptor_reuse = true;
910 od->ddev.dev = &pdev->dev; 936 od->ddev.dev = &pdev->dev;
911 INIT_LIST_HEAD(&od->ddev.channels); 937 INIT_LIST_HEAD(&od->ddev.channels);
912 938
913 platform_set_drvdata(pdev, od); 939 platform_set_drvdata(pdev, od);
914 940
941 od->zero_page = dma_map_page_attrs(od->ddev.dev, ZERO_PAGE(0), 0,
942 PAGE_SIZE, DMA_TO_DEVICE,
943 DMA_ATTR_SKIP_CPU_SYNC);
944 if (dma_mapping_error(od->ddev.dev, od->zero_page)) {
945 dev_err(&pdev->dev, "Failed to map zero page\n");
946 return -ENOMEM;
947 }
948
915 /* Request DMA channel mask from device tree */ 949 /* Request DMA channel mask from device tree */
916 if (of_property_read_u32(pdev->dev.of_node, 950 if (of_property_read_u32(pdev->dev.of_node,
917 "brcm,dma-channel-mask", 951 "brcm,dma-channel-mask",
diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrome/cros_ec_spi.c
index 006a8ff64057..714306bc3f79 100644
--- a/drivers/platform/chrome/cros_ec_spi.c
+++ b/drivers/platform/chrome/cros_ec_spi.c
@@ -706,7 +706,7 @@ static int cros_ec_spi_devm_high_pri_alloc(struct device *dev,
706 struct cros_ec_spi *ec_spi) 706 struct cros_ec_spi *ec_spi)
707{ 707{
708 struct sched_param sched_priority = { 708 struct sched_param sched_priority = {
709 .sched_priority = MAX_RT_PRIO - 1, 709 .sched_priority = MAX_RT_PRIO / 2,
710 }; 710 };
711 int err; 711 int err;
712 712
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3a1d8f1170de..6ee514fd0920 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -433,6 +433,16 @@ config SPI_MT7621
433 help 433 help
434 This selects a driver for the MediaTek MT7621 SPI Controller. 434 This selects a driver for the MediaTek MT7621 SPI Controller.
435 435
436config SPI_NPCM_FIU
437 tristate "Nuvoton NPCM FLASH Interface Unit"
438 depends on ARCH_NPCM || COMPILE_TEST
439 depends on OF && HAS_IOMEM
440 help
441 This enables support for the Flash Interface Unit SPI controller
442 in master mode.
443 This driver does not support generic SPI. The implementation only
444 supports spi-mem interface.
445
436config SPI_NPCM_PSPI 446config SPI_NPCM_PSPI
437 tristate "Nuvoton NPCM PSPI Controller" 447 tristate "Nuvoton NPCM PSPI Controller"
438 depends on ARCH_NPCM || COMPILE_TEST 448 depends on ARCH_NPCM || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 63dcab552bcb..adbebee93a75 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
63obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o 63obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
64obj-$(CONFIG_SPI_MXIC) += spi-mxic.o 64obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
65obj-$(CONFIG_SPI_MXS) += spi-mxs.o 65obj-$(CONFIG_SPI_MXS) += spi-mxs.o
66obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o
66obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o 67obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o
67obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o 68obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
68obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o 69obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 6a7d7b553d95..fd8007ebb145 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -526,7 +526,6 @@ static int atmel_qspi_probe(struct platform_device *pdev)
526 /* Request the IRQ */ 526 /* Request the IRQ */
527 irq = platform_get_irq(pdev, 0); 527 irq = platform_get_irq(pdev, 0);
528 if (irq < 0) { 528 if (irq < 0) {
529 dev_err(&pdev->dev, "missing IRQ\n");
530 err = irq; 529 err = irq;
531 goto disable_qspick; 530 goto disable_qspick;
532 } 531 }
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index ea160f117f88..41d71ba7fd32 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -170,7 +170,6 @@ static int altera_spi_probe(struct platform_device *pdev)
170{ 170{
171 struct altera_spi *hw; 171 struct altera_spi *hw;
172 struct spi_master *master; 172 struct spi_master *master;
173 struct resource *res;
174 int err = -ENODEV; 173 int err = -ENODEV;
175 174
176 master = spi_alloc_master(&pdev->dev, sizeof(struct altera_spi)); 175 master = spi_alloc_master(&pdev->dev, sizeof(struct altera_spi));
@@ -189,8 +188,7 @@ static int altera_spi_probe(struct platform_device *pdev)
189 hw = spi_master_get_devdata(master); 188 hw = spi_master_get_devdata(master);
190 189
191 /* find and map our resources */ 190 /* find and map our resources */
192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 191 hw->base = devm_platform_ioremap_resource(pdev, 0);
193 hw->base = devm_ioremap_resource(&pdev->dev, res);
194 if (IS_ERR(hw->base)) { 192 if (IS_ERR(hw->base)) {
195 err = PTR_ERR(hw->base); 193 err = PTR_ERR(hw->base);
196 goto exit; 194 goto exit;
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
index 032888344822..e450ee17787f 100644
--- a/drivers/spi/spi-armada-3700.c
+++ b/drivers/spi/spi-armada-3700.c
@@ -817,7 +817,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
817{ 817{
818 struct device *dev = &pdev->dev; 818 struct device *dev = &pdev->dev;
819 struct device_node *of_node = dev->of_node; 819 struct device_node *of_node = dev->of_node;
820 struct resource *res;
821 struct spi_master *master; 820 struct spi_master *master;
822 struct a3700_spi *spi; 821 struct a3700_spi *spi;
823 u32 num_cs = 0; 822 u32 num_cs = 0;
@@ -855,8 +854,7 @@ static int a3700_spi_probe(struct platform_device *pdev)
855 854
856 spi->master = master; 855 spi->master = master;
857 856
858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 857 spi->base = devm_platform_ioremap_resource(pdev, 0);
859 spi->base = devm_ioremap_resource(dev, res);
860 if (IS_ERR(spi->base)) { 858 if (IS_ERR(spi->base)) {
861 ret = PTR_ERR(spi->base); 859 ret = PTR_ERR(spi->base);
862 goto error; 860 goto error;
@@ -864,7 +862,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
864 862
865 irq = platform_get_irq(pdev, 0); 863 irq = platform_get_irq(pdev, 0);
866 if (irq < 0) { 864 if (irq < 0) {
867 dev_err(dev, "could not get irq: %d\n", irq);
868 ret = -ENXIO; 865 ret = -ENXIO;
869 goto error; 866 goto error;
870 } 867 }
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index 032a615e4ccd..eb9a243e9526 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -139,7 +139,6 @@ static int ath79_spi_probe(struct platform_device *pdev)
139 struct spi_master *master; 139 struct spi_master *master;
140 struct ath79_spi *sp; 140 struct ath79_spi *sp;
141 struct ath79_spi_platform_data *pdata; 141 struct ath79_spi_platform_data *pdata;
142 struct resource *r;
143 unsigned long rate; 142 unsigned long rate;
144 int ret; 143 int ret;
145 144
@@ -169,8 +168,7 @@ static int ath79_spi_probe(struct platform_device *pdev)
169 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; 168 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
170 sp->bitbang.flags = SPI_CS_HIGH; 169 sp->bitbang.flags = SPI_CS_HIGH;
171 170
172 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 171 sp->base = devm_platform_ioremap_resource(pdev, 0);
173 sp->base = devm_ioremap_resource(&pdev->dev, r);
174 if (IS_ERR(sp->base)) { 172 if (IS_ERR(sp->base)) {
175 ret = PTR_ERR(sp->base); 173 ret = PTR_ERR(sp->base);
176 goto err_put_master; 174 goto err_put_master;
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index f00b367523cd..acf318e7330c 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -23,6 +23,7 @@
23#include <linux/gpio/consumer.h> 23#include <linux/gpio/consumer.h>
24#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/consumer.h>
25#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
26#include <trace/events/spi.h>
26 27
27/* SPI register offsets */ 28/* SPI register offsets */
28#define SPI_CR 0x0000 29#define SPI_CR 0x0000
@@ -1409,9 +1410,13 @@ static int atmel_spi_transfer_one_message(struct spi_master *master,
1409 msg->actual_length = 0; 1410 msg->actual_length = 0;
1410 1411
1411 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 1412 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1413 trace_spi_transfer_start(msg, xfer);
1414
1412 ret = atmel_spi_one_transfer(master, msg, xfer); 1415 ret = atmel_spi_one_transfer(master, msg, xfer);
1413 if (ret) 1416 if (ret)
1414 goto msg_done; 1417 goto msg_done;
1418
1419 trace_spi_transfer_stop(msg, xfer);
1415 } 1420 }
1416 1421
1417 if (as->use_pdc) 1422 if (as->use_pdc)
diff --git a/drivers/spi/spi-axi-spi-engine.c b/drivers/spi/spi-axi-spi-engine.c
index 3b1833e6c7ad..74842f6019ed 100644
--- a/drivers/spi/spi-axi-spi-engine.c
+++ b/drivers/spi/spi-axi-spi-engine.c
@@ -460,7 +460,6 @@ static int spi_engine_probe(struct platform_device *pdev)
460 struct spi_engine *spi_engine; 460 struct spi_engine *spi_engine;
461 struct spi_master *master; 461 struct spi_master *master;
462 unsigned int version; 462 unsigned int version;
463 struct resource *res;
464 int irq; 463 int irq;
465 int ret; 464 int ret;
466 465
@@ -480,8 +479,7 @@ static int spi_engine_probe(struct platform_device *pdev)
480 479
481 spin_lock_init(&spi_engine->lock); 480 spin_lock_init(&spi_engine->lock);
482 481
483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 482 spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
484 spi_engine->base = devm_ioremap_resource(&pdev->dev, res);
485 if (IS_ERR(spi_engine->base)) { 483 if (IS_ERR(spi_engine->base)) {
486 ret = PTR_ERR(spi_engine->base); 484 ret = PTR_ERR(spi_engine->base);
487 goto err_put_master; 485 goto err_put_master;
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 0dbfd2496ab8..7a3531856491 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -897,6 +897,7 @@ static int bcm_qspi_transfer_one(struct spi_master *master,
897 897
898 read_from_hw(qspi, slots); 898 read_from_hw(qspi, slots);
899 } 899 }
900 bcm_qspi_enable_bspi(qspi);
900 901
901 return 0; 902 return 0;
902} 903}
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index dfdcebb38830..b4070c0de3df 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -25,7 +25,9 @@
25#include <linux/of.h> 25#include <linux/of.h>
26#include <linux/of_address.h> 26#include <linux/of_address.h>
27#include <linux/of_device.h> 27#include <linux/of_device.h>
28#include <linux/of_gpio.h> 28#include <linux/gpio/consumer.h>
29#include <linux/gpio/machine.h> /* FIXME: using chip internals */
30#include <linux/gpio/driver.h> /* FIXME: using chip internals */
29#include <linux/of_irq.h> 31#include <linux/of_irq.h>
30#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
31 33
@@ -66,6 +68,7 @@
66#define BCM2835_SPI_FIFO_SIZE 64 68#define BCM2835_SPI_FIFO_SIZE 64
67#define BCM2835_SPI_FIFO_SIZE_3_4 48 69#define BCM2835_SPI_FIFO_SIZE_3_4 48
68#define BCM2835_SPI_DMA_MIN_LENGTH 96 70#define BCM2835_SPI_DMA_MIN_LENGTH 96
71#define BCM2835_SPI_NUM_CS 3 /* raise as necessary */
69#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 72#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
70 | SPI_NO_CS | SPI_3WIRE) 73 | SPI_NO_CS | SPI_3WIRE)
71 74
@@ -92,7 +95,8 @@ MODULE_PARM_DESC(polling_limit_us,
92 * @rx_prologue: bytes received without DMA if first RX sglist entry's 95 * @rx_prologue: bytes received without DMA if first RX sglist entry's
93 * length is not a multiple of 4 (to overcome hardware limitation) 96 * length is not a multiple of 4 (to overcome hardware limitation)
94 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry 97 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
95 * @dma_pending: whether a DMA transfer is in progress 98 * @prepare_cs: precalculated CS register value for ->prepare_message()
99 * (uses slave-specific clock polarity and phase settings)
96 * @debugfs_dir: the debugfs directory - neede to remove debugfs when 100 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
97 * unloading the module 101 * unloading the module
98 * @count_transfer_polling: count of how often polling mode is used 102 * @count_transfer_polling: count of how often polling mode is used
@@ -102,6 +106,19 @@ MODULE_PARM_DESC(polling_limit_us,
102 * These are counted as well in @count_transfer_polling and 106 * These are counted as well in @count_transfer_polling and
103 * @count_transfer_irq 107 * @count_transfer_irq
104 * @count_transfer_dma: count how often dma mode is used 108 * @count_transfer_dma: count how often dma mode is used
109 * @chip_select: SPI slave currently selected
110 * (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs)
111 * @tx_dma_active: whether a TX DMA descriptor is in progress
112 * @rx_dma_active: whether a RX DMA descriptor is in progress
113 * (used by bcm2835_spi_dma_tx_done() to handle a race)
114 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
115 * (cyclically copies from zero page to TX FIFO)
116 * @fill_tx_addr: bus address of zero page
117 * @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
118 * (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
119 * @clear_rx_addr: bus address of @clear_rx_cs
120 * @clear_rx_cs: precalculated CS register value to clear RX FIFO
121 * (uses slave-specific clock polarity and phase settings)
105 */ 122 */
106struct bcm2835_spi { 123struct bcm2835_spi {
107 void __iomem *regs; 124 void __iomem *regs;
@@ -115,13 +132,22 @@ struct bcm2835_spi {
115 int tx_prologue; 132 int tx_prologue;
116 int rx_prologue; 133 int rx_prologue;
117 unsigned int tx_spillover; 134 unsigned int tx_spillover;
118 unsigned int dma_pending; 135 u32 prepare_cs[BCM2835_SPI_NUM_CS];
119 136
120 struct dentry *debugfs_dir; 137 struct dentry *debugfs_dir;
121 u64 count_transfer_polling; 138 u64 count_transfer_polling;
122 u64 count_transfer_irq; 139 u64 count_transfer_irq;
123 u64 count_transfer_irq_after_polling; 140 u64 count_transfer_irq_after_polling;
124 u64 count_transfer_dma; 141 u64 count_transfer_dma;
142
143 u8 chip_select;
144 unsigned int tx_dma_active;
145 unsigned int rx_dma_active;
146 struct dma_async_tx_descriptor *fill_tx_desc;
147 dma_addr_t fill_tx_addr;
148 struct dma_async_tx_descriptor *clear_rx_desc[BCM2835_SPI_NUM_CS];
149 dma_addr_t clear_rx_addr;
150 u32 clear_rx_cs[BCM2835_SPI_NUM_CS] ____cacheline_aligned;
125}; 151};
126 152
127#if defined(CONFIG_DEBUG_FS) 153#if defined(CONFIG_DEBUG_FS)
@@ -455,14 +481,14 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
455 bs->rx_prologue = 0; 481 bs->rx_prologue = 0;
456 bs->tx_spillover = false; 482 bs->tx_spillover = false;
457 483
458 if (!sg_is_last(&tfr->tx_sg.sgl[0])) 484 if (bs->tx_buf && !sg_is_last(&tfr->tx_sg.sgl[0]))
459 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3; 485 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
460 486
461 if (!sg_is_last(&tfr->rx_sg.sgl[0])) { 487 if (bs->rx_buf && !sg_is_last(&tfr->rx_sg.sgl[0])) {
462 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3; 488 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
463 489
464 if (bs->rx_prologue > bs->tx_prologue) { 490 if (bs->rx_prologue > bs->tx_prologue) {
465 if (sg_is_last(&tfr->tx_sg.sgl[0])) { 491 if (!bs->tx_buf || sg_is_last(&tfr->tx_sg.sgl[0])) {
466 bs->tx_prologue = bs->rx_prologue; 492 bs->tx_prologue = bs->rx_prologue;
467 } else { 493 } else {
468 bs->tx_prologue += 4; 494 bs->tx_prologue += 4;
@@ -496,6 +522,9 @@ static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
496 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue; 522 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
497 } 523 }
498 524
525 if (!bs->tx_buf)
526 return;
527
499 /* 528 /*
500 * Write remaining TX prologue. Adjust first entry in TX sglist. 529 * Write remaining TX prologue. Adjust first entry in TX sglist.
501 * Also adjust second entry if prologue spills over to it. 530 * Also adjust second entry if prologue spills over to it.
@@ -541,6 +570,9 @@ static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
541 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue; 570 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
542 } 571 }
543 572
573 if (!bs->tx_buf)
574 goto out;
575
544 if (likely(!bs->tx_spillover)) { 576 if (likely(!bs->tx_spillover)) {
545 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue; 577 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
546 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue; 578 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
@@ -549,32 +581,85 @@ static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
549 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4; 581 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
550 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4; 582 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
551 } 583 }
584out:
585 bs->tx_prologue = 0;
552} 586}
553 587
554static void bcm2835_spi_dma_done(void *data) 588/**
589 * bcm2835_spi_dma_rx_done() - callback for DMA RX channel
590 * @data: SPI master controller
591 *
592 * Used for bidirectional and RX-only transfers.
593 */
594static void bcm2835_spi_dma_rx_done(void *data)
555{ 595{
556 struct spi_controller *ctlr = data; 596 struct spi_controller *ctlr = data;
557 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 597 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
558 598
559 /* reset fifo and HW */ 599 /* terminate tx-dma as we do not have an irq for it
560 bcm2835_spi_reset_hw(ctlr);
561
562 /* and terminate tx-dma as we do not have an irq for it
563 * because when the rx dma will terminate and this callback 600 * because when the rx dma will terminate and this callback
564 * is called the tx-dma must have finished - can't get to this 601 * is called the tx-dma must have finished - can't get to this
565 * situation otherwise... 602 * situation otherwise...
566 */ 603 */
567 if (cmpxchg(&bs->dma_pending, true, false)) { 604 dmaengine_terminate_async(ctlr->dma_tx);
568 dmaengine_terminate_async(ctlr->dma_tx); 605 bs->tx_dma_active = false;
569 bcm2835_spi_undo_prologue(bs); 606 bs->rx_dma_active = false;
570 } 607 bcm2835_spi_undo_prologue(bs);
608
609 /* reset fifo and HW */
610 bcm2835_spi_reset_hw(ctlr);
571 611
572 /* and mark as completed */; 612 /* and mark as completed */;
573 complete(&ctlr->xfer_completion); 613 complete(&ctlr->xfer_completion);
574} 614}
575 615
616/**
617 * bcm2835_spi_dma_tx_done() - callback for DMA TX channel
618 * @data: SPI master controller
619 *
620 * Used for TX-only transfers.
621 */
622static void bcm2835_spi_dma_tx_done(void *data)
623{
624 struct spi_controller *ctlr = data;
625 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
626
627 /* busy-wait for TX FIFO to empty */
628 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
629 bcm2835_wr(bs, BCM2835_SPI_CS,
630 bs->clear_rx_cs[bs->chip_select]);
631
632 bs->tx_dma_active = false;
633 smp_wmb();
634
635 /*
636 * In case of a very short transfer, RX DMA may not have been
637 * issued yet. The onus is then on bcm2835_spi_transfer_one_dma()
638 * to terminate it immediately after issuing.
639 */
640 if (cmpxchg(&bs->rx_dma_active, true, false))
641 dmaengine_terminate_async(ctlr->dma_rx);
642
643 bcm2835_spi_undo_prologue(bs);
644 bcm2835_spi_reset_hw(ctlr);
645 complete(&ctlr->xfer_completion);
646}
647
648/**
649 * bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist
650 * @ctlr: SPI master controller
651 * @spi: SPI slave
652 * @tfr: SPI transfer
653 * @bs: BCM2835 SPI controller
654 * @is_tx: whether to submit DMA descriptor for TX or RX sglist
655 *
656 * Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr.
657 * Return 0 on success or a negative error number.
658 */
576static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr, 659static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
660 struct spi_device *spi,
577 struct spi_transfer *tfr, 661 struct spi_transfer *tfr,
662 struct bcm2835_spi *bs,
578 bool is_tx) 663 bool is_tx)
579{ 664{
580 struct dma_chan *chan; 665 struct dma_chan *chan;
@@ -591,8 +676,7 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
591 chan = ctlr->dma_tx; 676 chan = ctlr->dma_tx;
592 nents = tfr->tx_sg.nents; 677 nents = tfr->tx_sg.nents;
593 sgl = tfr->tx_sg.sgl; 678 sgl = tfr->tx_sg.sgl;
594 flags = 0 /* no tx interrupt */; 679 flags = tfr->rx_buf ? 0 : DMA_PREP_INTERRUPT;
595
596 } else { 680 } else {
597 dir = DMA_DEV_TO_MEM; 681 dir = DMA_DEV_TO_MEM;
598 chan = ctlr->dma_rx; 682 chan = ctlr->dma_rx;
@@ -605,10 +689,17 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
605 if (!desc) 689 if (!desc)
606 return -EINVAL; 690 return -EINVAL;
607 691
608 /* set callback for rx */ 692 /*
693 * Completion is signaled by the RX channel for bidirectional and
694 * RX-only transfers; else by the TX channel for TX-only transfers.
695 */
609 if (!is_tx) { 696 if (!is_tx) {
610 desc->callback = bcm2835_spi_dma_done; 697 desc->callback = bcm2835_spi_dma_rx_done;
611 desc->callback_param = ctlr; 698 desc->callback_param = ctlr;
699 } else if (!tfr->rx_buf) {
700 desc->callback = bcm2835_spi_dma_tx_done;
701 desc->callback_param = ctlr;
702 bs->chip_select = spi->chip_select;
612 } 703 }
613 704
614 /* submit it to DMA-engine */ 705 /* submit it to DMA-engine */
@@ -617,12 +708,60 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
617 return dma_submit_error(cookie); 708 return dma_submit_error(cookie);
618} 709}
619 710
711/**
712 * bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine
713 * @ctlr: SPI master controller
714 * @spi: SPI slave
715 * @tfr: SPI transfer
716 * @cs: CS register
717 *
718 * For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up
719 * the TX and RX DMA channel to copy between memory and FIFO register.
720 *
721 * For *TX-only* transfers (rx_buf is %NULL), copying the RX FIFO's contents to
722 * memory is pointless. However not reading the RX FIFO isn't an option either
723 * because transmission is halted once it's full. As a workaround, cyclically
724 * clear the RX FIFO by setting the CLEAR_RX bit in the CS register.
725 *
726 * The CS register value is precalculated in bcm2835_spi_setup(). Normally
727 * this is called only once, on slave registration. A DMA descriptor to write
728 * this value is preallocated in bcm2835_dma_init(). All that's left to do
729 * when performing a TX-only transfer is to submit this descriptor to the RX
730 * DMA channel. Latency is thereby minimized. The descriptor does not
731 * generate any interrupts while running. It must be terminated once the
732 * TX DMA channel is done.
733 *
734 * Clearing the RX FIFO is paced by the DREQ signal. The signal is asserted
735 * when the RX FIFO becomes half full, i.e. 32 bytes. (Tuneable with the DC
736 * register.) Reading 32 bytes from the RX FIFO would normally require 8 bus
737 * accesses, whereas clearing it requires only 1 bus access. So an 8-fold
738 * reduction in bus traffic and thus energy consumption is achieved.
739 *
740 * For *RX-only* transfers (tx_buf is %NULL), fill the TX FIFO by cyclically
741 * copying from the zero page. The DMA descriptor to do this is preallocated
742 * in bcm2835_dma_init(). It must be terminated once the RX DMA channel is
743 * done and can then be reused.
744 *
745 * The BCM2835 DMA driver autodetects when a transaction copies from the zero
746 * page and utilizes the DMA controller's ability to synthesize zeroes instead
747 * of copying them from memory. This reduces traffic on the memory bus. The
748 * feature is not available on so-called "lite" channels, but normally TX DMA
749 * is backed by a full-featured channel.
750 *
751 * Zero-filling the TX FIFO is paced by the DREQ signal. Unfortunately the
752 * BCM2835 SPI controller continues to assert DREQ even after the DLEN register
753 * has been counted down to zero (hardware erratum). Thus, when the transfer
754 * has finished, the DMA engine zero-fills the TX FIFO until it is half full.
755 * (Tuneable with the DC register.) So up to 9 gratuitous bus accesses are
756 * performed at the end of an RX-only transfer.
757 */
620static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr, 758static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
621 struct spi_device *spi, 759 struct spi_device *spi,
622 struct spi_transfer *tfr, 760 struct spi_transfer *tfr,
623 u32 cs) 761 u32 cs)
624{ 762{
625 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 763 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
764 dma_cookie_t cookie;
626 int ret; 765 int ret;
627 766
628 /* update usage statistics */ 767 /* update usage statistics */
@@ -635,16 +774,15 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
635 bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs); 774 bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
636 775
637 /* setup tx-DMA */ 776 /* setup tx-DMA */
638 ret = bcm2835_spi_prepare_sg(ctlr, tfr, true); 777 if (bs->tx_buf) {
778 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true);
779 } else {
780 cookie = dmaengine_submit(bs->fill_tx_desc);
781 ret = dma_submit_error(cookie);
782 }
639 if (ret) 783 if (ret)
640 goto err_reset_hw; 784 goto err_reset_hw;
641 785
642 /* start TX early */
643 dma_async_issue_pending(ctlr->dma_tx);
644
645 /* mark as dma pending */
646 bs->dma_pending = 1;
647
648 /* set the DMA length */ 786 /* set the DMA length */
649 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len); 787 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
650 788
@@ -652,20 +790,43 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
652 bcm2835_wr(bs, BCM2835_SPI_CS, 790 bcm2835_wr(bs, BCM2835_SPI_CS,
653 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); 791 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
654 792
793 bs->tx_dma_active = true;
794 smp_wmb();
795
796 /* start TX early */
797 dma_async_issue_pending(ctlr->dma_tx);
798
655 /* setup rx-DMA late - to run transfers while 799 /* setup rx-DMA late - to run transfers while
656 * mapping of the rx buffers still takes place 800 * mapping of the rx buffers still takes place
657 * this saves 10us or more. 801 * this saves 10us or more.
658 */ 802 */
659 ret = bcm2835_spi_prepare_sg(ctlr, tfr, false); 803 if (bs->rx_buf) {
804 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false);
805 } else {
806 cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]);
807 ret = dma_submit_error(cookie);
808 }
660 if (ret) { 809 if (ret) {
661 /* need to reset on errors */ 810 /* need to reset on errors */
662 dmaengine_terminate_sync(ctlr->dma_tx); 811 dmaengine_terminate_sync(ctlr->dma_tx);
663 bs->dma_pending = false; 812 bs->tx_dma_active = false;
664 goto err_reset_hw; 813 goto err_reset_hw;
665 } 814 }
666 815
667 /* start rx dma late */ 816 /* start rx dma late */
668 dma_async_issue_pending(ctlr->dma_rx); 817 dma_async_issue_pending(ctlr->dma_rx);
818 bs->rx_dma_active = true;
819 smp_mb();
820
821 /*
822 * In case of a very short TX-only transfer, bcm2835_spi_dma_tx_done()
823 * may run before RX DMA is issued. Terminate RX DMA if so.
824 */
825 if (!bs->rx_buf && !bs->tx_dma_active &&
826 cmpxchg(&bs->rx_dma_active, true, false)) {
827 dmaengine_terminate_async(ctlr->dma_rx);
828 bcm2835_spi_reset_hw(ctlr);
829 }
669 830
670 /* wait for wakeup in framework */ 831 /* wait for wakeup in framework */
671 return 1; 832 return 1;
@@ -688,26 +849,52 @@ static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
688 return true; 849 return true;
689} 850}
690 851
691static void bcm2835_dma_release(struct spi_controller *ctlr) 852static void bcm2835_dma_release(struct spi_controller *ctlr,
853 struct bcm2835_spi *bs)
692{ 854{
855 int i;
856
693 if (ctlr->dma_tx) { 857 if (ctlr->dma_tx) {
694 dmaengine_terminate_sync(ctlr->dma_tx); 858 dmaengine_terminate_sync(ctlr->dma_tx);
859
860 if (bs->fill_tx_desc)
861 dmaengine_desc_free(bs->fill_tx_desc);
862
863 if (bs->fill_tx_addr)
864 dma_unmap_page_attrs(ctlr->dma_tx->device->dev,
865 bs->fill_tx_addr, sizeof(u32),
866 DMA_TO_DEVICE,
867 DMA_ATTR_SKIP_CPU_SYNC);
868
695 dma_release_channel(ctlr->dma_tx); 869 dma_release_channel(ctlr->dma_tx);
696 ctlr->dma_tx = NULL; 870 ctlr->dma_tx = NULL;
697 } 871 }
872
698 if (ctlr->dma_rx) { 873 if (ctlr->dma_rx) {
699 dmaengine_terminate_sync(ctlr->dma_rx); 874 dmaengine_terminate_sync(ctlr->dma_rx);
875
876 for (i = 0; i < BCM2835_SPI_NUM_CS; i++)
877 if (bs->clear_rx_desc[i])
878 dmaengine_desc_free(bs->clear_rx_desc[i]);
879
880 if (bs->clear_rx_addr)
881 dma_unmap_single(ctlr->dma_rx->device->dev,
882 bs->clear_rx_addr,
883 sizeof(bs->clear_rx_cs),
884 DMA_TO_DEVICE);
885
700 dma_release_channel(ctlr->dma_rx); 886 dma_release_channel(ctlr->dma_rx);
701 ctlr->dma_rx = NULL; 887 ctlr->dma_rx = NULL;
702 } 888 }
703} 889}
704 890
705static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev) 891static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev,
892 struct bcm2835_spi *bs)
706{ 893{
707 struct dma_slave_config slave_config; 894 struct dma_slave_config slave_config;
708 const __be32 *addr; 895 const __be32 *addr;
709 dma_addr_t dma_reg_base; 896 dma_addr_t dma_reg_base;
710 int ret; 897 int ret, i;
711 898
712 /* base address in dma-space */ 899 /* base address in dma-space */
713 addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL); 900 addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
@@ -729,7 +916,11 @@ static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev)
729 goto err_release; 916 goto err_release;
730 } 917 }
731 918
732 /* configure DMAs */ 919 /*
920 * The TX DMA channel either copies a transfer's TX buffer to the FIFO
921 * or, in case of an RX-only transfer, cyclically copies from the zero
922 * page to the FIFO using a preallocated, reusable descriptor.
923 */
733 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 924 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
734 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 925 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
735 926
@@ -737,17 +928,74 @@ static void bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev)
737 if (ret) 928 if (ret)
738 goto err_config; 929 goto err_config;
739 930
931 bs->fill_tx_addr = dma_map_page_attrs(ctlr->dma_tx->device->dev,
932 ZERO_PAGE(0), 0, sizeof(u32),
933 DMA_TO_DEVICE,
934 DMA_ATTR_SKIP_CPU_SYNC);
935 if (dma_mapping_error(ctlr->dma_tx->device->dev, bs->fill_tx_addr)) {
936 dev_err(dev, "cannot map zero page - not using DMA mode\n");
937 bs->fill_tx_addr = 0;
938 goto err_release;
939 }
940
941 bs->fill_tx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_tx,
942 bs->fill_tx_addr,
943 sizeof(u32), 0,
944 DMA_MEM_TO_DEV, 0);
945 if (!bs->fill_tx_desc) {
946 dev_err(dev, "cannot prepare fill_tx_desc - not using DMA mode\n");
947 goto err_release;
948 }
949
950 ret = dmaengine_desc_set_reuse(bs->fill_tx_desc);
951 if (ret) {
952 dev_err(dev, "cannot reuse fill_tx_desc - not using DMA mode\n");
953 goto err_release;
954 }
955
956 /*
957 * The RX DMA channel is used bidirectionally: It either reads the
958 * RX FIFO or, in case of a TX-only transfer, cyclically writes a
959 * precalculated value to the CS register to clear the RX FIFO.
960 */
740 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 961 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
741 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 962 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
963 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_CS);
964 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
742 965
743 ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config); 966 ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config);
744 if (ret) 967 if (ret)
745 goto err_config; 968 goto err_config;
746 969
970 bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
971 bs->clear_rx_cs,
972 sizeof(bs->clear_rx_cs),
973 DMA_TO_DEVICE);
974 if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) {
975 dev_err(dev, "cannot map clear_rx_cs - not using DMA mode\n");
976 bs->clear_rx_addr = 0;
977 goto err_release;
978 }
979
980 for (i = 0; i < BCM2835_SPI_NUM_CS; i++) {
981 bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
982 bs->clear_rx_addr + i * sizeof(u32),
983 sizeof(u32), 0,
984 DMA_MEM_TO_DEV, 0);
985 if (!bs->clear_rx_desc[i]) {
986 dev_err(dev, "cannot prepare clear_rx_desc - not using DMA mode\n");
987 goto err_release;
988 }
989
990 ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]);
991 if (ret) {
992 dev_err(dev, "cannot reuse clear_rx_desc - not using DMA mode\n");
993 goto err_release;
994 }
995 }
996
747 /* all went well, so set can_dma */ 997 /* all went well, so set can_dma */
748 ctlr->can_dma = bcm2835_spi_can_dma; 998 ctlr->can_dma = bcm2835_spi_can_dma;
749 /* need to do TX AND RX DMA, so we need dummy buffers */
750 ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
751 999
752 return; 1000 return;
753 1001
@@ -755,7 +1003,7 @@ err_config:
755 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", 1003 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
756 ret); 1004 ret);
757err_release: 1005err_release:
758 bcm2835_dma_release(ctlr); 1006 bcm2835_dma_release(ctlr, bs);
759err: 1007err:
760 return; 1008 return;
761} 1009}
@@ -822,7 +1070,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
822 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 1070 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
823 unsigned long spi_hz, clk_hz, cdiv, spi_used_hz; 1071 unsigned long spi_hz, clk_hz, cdiv, spi_used_hz;
824 unsigned long hz_per_byte, byte_limit; 1072 unsigned long hz_per_byte, byte_limit;
825 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 1073 u32 cs = bs->prepare_cs[spi->chip_select];
826 1074
827 /* set clock */ 1075 /* set clock */
828 spi_hz = tfr->speed_hz; 1076 spi_hz = tfr->speed_hz;
@@ -844,18 +1092,8 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
844 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); 1092 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
845 1093
846 /* handle all the 3-wire mode */ 1094 /* handle all the 3-wire mode */
847 if (spi->mode & SPI_3WIRE && tfr->rx_buf && 1095 if (spi->mode & SPI_3WIRE && tfr->rx_buf)
848 tfr->rx_buf != ctlr->dummy_rx)
849 cs |= BCM2835_SPI_CS_REN; 1096 cs |= BCM2835_SPI_CS_REN;
850 else
851 cs &= ~BCM2835_SPI_CS_REN;
852
853 /*
854 * The driver always uses software-controlled GPIO Chip Select.
855 * Set the hardware-controlled native Chip Select to an invalid
856 * value to prevent it from interfering.
857 */
858 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
859 1097
860 /* set transmit buffers and length */ 1098 /* set transmit buffers and length */
861 bs->tx_buf = tfr->tx_buf; 1099 bs->tx_buf = tfr->tx_buf;
@@ -892,7 +1130,6 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
892{ 1130{
893 struct spi_device *spi = msg->spi; 1131 struct spi_device *spi = msg->spi;
894 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 1132 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
895 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
896 int ret; 1133 int ret;
897 1134
898 if (ctlr->can_dma) { 1135 if (ctlr->can_dma) {
@@ -907,14 +1144,11 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
907 return ret; 1144 return ret;
908 } 1145 }
909 1146
910 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); 1147 /*
911 1148 * Set up clock polarity before spi_transfer_one_message() asserts
912 if (spi->mode & SPI_CPOL) 1149 * chip select to avoid a gratuitous clock signal edge.
913 cs |= BCM2835_SPI_CS_CPOL; 1150 */
914 if (spi->mode & SPI_CPHA) 1151 bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]);
915 cs |= BCM2835_SPI_CS_CPHA;
916
917 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
918 1152
919 return 0; 1153 return 0;
920} 1154}
@@ -925,11 +1159,12 @@ static void bcm2835_spi_handle_err(struct spi_controller *ctlr,
925 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr); 1159 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
926 1160
927 /* if an error occurred and we have an active dma, then terminate */ 1161 /* if an error occurred and we have an active dma, then terminate */
928 if (cmpxchg(&bs->dma_pending, true, false)) { 1162 dmaengine_terminate_sync(ctlr->dma_tx);
929 dmaengine_terminate_sync(ctlr->dma_tx); 1163 bs->tx_dma_active = false;
930 dmaengine_terminate_sync(ctlr->dma_rx); 1164 dmaengine_terminate_sync(ctlr->dma_rx);
931 bcm2835_spi_undo_prologue(bs); 1165 bs->rx_dma_active = false;
932 } 1166 bcm2835_spi_undo_prologue(bs);
1167
933 /* and reset */ 1168 /* and reset */
934 bcm2835_spi_reset_hw(ctlr); 1169 bcm2835_spi_reset_hw(ctlr);
935} 1170}
@@ -941,14 +1176,50 @@ static int chip_match_name(struct gpio_chip *chip, void *data)
941 1176
942static int bcm2835_spi_setup(struct spi_device *spi) 1177static int bcm2835_spi_setup(struct spi_device *spi)
943{ 1178{
944 int err; 1179 struct spi_controller *ctlr = spi->controller;
1180 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
945 struct gpio_chip *chip; 1181 struct gpio_chip *chip;
1182 enum gpio_lookup_flags lflags;
1183 u32 cs;
1184
1185 /*
1186 * Precalculate SPI slave's CS register value for ->prepare_message():
1187 * The driver always uses software-controlled GPIO chip select, hence
1188 * set the hardware-controlled native chip select to an invalid value
1189 * to prevent it from interfering.
1190 */
1191 cs = BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
1192 if (spi->mode & SPI_CPOL)
1193 cs |= BCM2835_SPI_CS_CPOL;
1194 if (spi->mode & SPI_CPHA)
1195 cs |= BCM2835_SPI_CS_CPHA;
1196 bs->prepare_cs[spi->chip_select] = cs;
1197
1198 /*
1199 * Precalculate SPI slave's CS register value to clear RX FIFO
1200 * in case of a TX-only DMA transfer.
1201 */
1202 if (ctlr->dma_rx) {
1203 bs->clear_rx_cs[spi->chip_select] = cs |
1204 BCM2835_SPI_CS_TA |
1205 BCM2835_SPI_CS_DMAEN |
1206 BCM2835_SPI_CS_CLEAR_RX;
1207 dma_sync_single_for_device(ctlr->dma_rx->device->dev,
1208 bs->clear_rx_addr,
1209 sizeof(bs->clear_rx_cs),
1210 DMA_TO_DEVICE);
1211 }
1212
946 /* 1213 /*
947 * sanity checking the native-chipselects 1214 * sanity checking the native-chipselects
948 */ 1215 */
949 if (spi->mode & SPI_NO_CS) 1216 if (spi->mode & SPI_NO_CS)
950 return 0; 1217 return 0;
951 if (gpio_is_valid(spi->cs_gpio)) 1218 /*
1219 * The SPI core has successfully requested the CS GPIO line from the
1220 * device tree, so we are done.
1221 */
1222 if (spi->cs_gpiod)
952 return 0; 1223 return 0;
953 if (spi->chip_select > 1) { 1224 if (spi->chip_select > 1) {
954 /* error in the case of native CS requested with CS > 1 1225 /* error in the case of native CS requested with CS > 1
@@ -959,29 +1230,43 @@ static int bcm2835_spi_setup(struct spi_device *spi)
959 "setup: only two native chip-selects are supported\n"); 1230 "setup: only two native chip-selects are supported\n");
960 return -EINVAL; 1231 return -EINVAL;
961 } 1232 }
962 /* now translate native cs to GPIO */ 1233
1234 /*
1235 * Translate native CS to GPIO
1236 *
1237 * FIXME: poking around in the gpiolib internals like this is
1238 * not very good practice. Find a way to locate the real problem
1239 * and fix it. Why is the GPIO descriptor in spi->cs_gpiod
1240 * sometimes not assigned correctly? Erroneous device trees?
1241 */
963 1242
964 /* get the gpio chip for the base */ 1243 /* get the gpio chip for the base */
965 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); 1244 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
966 if (!chip) 1245 if (!chip)
967 return 0; 1246 return 0;
968 1247
969 /* and calculate the real CS */ 1248 /*
970 spi->cs_gpio = chip->base + 8 - spi->chip_select; 1249 * Retrieve the corresponding GPIO line used for CS.
1250 * The inversion semantics will be handled by the GPIO core
1251 * code, so we pass GPIOS_OUT_LOW for "unasserted" and
1252 * the correct flag for inversion semantics. The SPI_CS_HIGH
1253 * on spi->mode cannot be checked for polarity in this case
1254 * as the flag use_gpio_descriptors enforces SPI_CS_HIGH.
1255 */
1256 if (of_property_read_bool(spi->dev.of_node, "spi-cs-high"))
1257 lflags = GPIO_ACTIVE_HIGH;
1258 else
1259 lflags = GPIO_ACTIVE_LOW;
1260 spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
1261 DRV_NAME,
1262 lflags,
1263 GPIOD_OUT_LOW);
1264 if (IS_ERR(spi->cs_gpiod))
1265 return PTR_ERR(spi->cs_gpiod);
971 1266
972 /* and set up the "mode" and level */ 1267 /* and set up the "mode" and level */
973 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", 1268 dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
974 spi->chip_select, spi->cs_gpio); 1269 spi->chip_select);
975
976 /* set up GPIO as output and pull to the correct level */
977 err = gpio_direction_output(spi->cs_gpio,
978 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
979 if (err) {
980 dev_err(&spi->dev,
981 "could not set CS%i gpio %i as output: %i",
982 spi->chip_select, spi->cs_gpio, err);
983 return err;
984 }
985 1270
986 return 0; 1271 return 0;
987} 1272}
@@ -990,18 +1275,19 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
990{ 1275{
991 struct spi_controller *ctlr; 1276 struct spi_controller *ctlr;
992 struct bcm2835_spi *bs; 1277 struct bcm2835_spi *bs;
993 struct resource *res;
994 int err; 1278 int err;
995 1279
996 ctlr = spi_alloc_master(&pdev->dev, sizeof(*bs)); 1280 ctlr = spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),
1281 dma_get_cache_alignment()));
997 if (!ctlr) 1282 if (!ctlr)
998 return -ENOMEM; 1283 return -ENOMEM;
999 1284
1000 platform_set_drvdata(pdev, ctlr); 1285 platform_set_drvdata(pdev, ctlr);
1001 1286
1287 ctlr->use_gpio_descriptors = true;
1002 ctlr->mode_bits = BCM2835_SPI_MODE_BITS; 1288 ctlr->mode_bits = BCM2835_SPI_MODE_BITS;
1003 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 1289 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1004 ctlr->num_chipselect = 3; 1290 ctlr->num_chipselect = BCM2835_SPI_NUM_CS;
1005 ctlr->setup = bcm2835_spi_setup; 1291 ctlr->setup = bcm2835_spi_setup;
1006 ctlr->transfer_one = bcm2835_spi_transfer_one; 1292 ctlr->transfer_one = bcm2835_spi_transfer_one;
1007 ctlr->handle_err = bcm2835_spi_handle_err; 1293 ctlr->handle_err = bcm2835_spi_handle_err;
@@ -1010,8 +1296,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
1010 1296
1011 bs = spi_controller_get_devdata(ctlr); 1297 bs = spi_controller_get_devdata(ctlr);
1012 1298
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1299 bs->regs = devm_platform_ioremap_resource(pdev, 0);
1014 bs->regs = devm_ioremap_resource(&pdev->dev, res);
1015 if (IS_ERR(bs->regs)) { 1300 if (IS_ERR(bs->regs)) {
1016 err = PTR_ERR(bs->regs); 1301 err = PTR_ERR(bs->regs);
1017 goto out_controller_put; 1302 goto out_controller_put;
@@ -1026,14 +1311,13 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
1026 1311
1027 bs->irq = platform_get_irq(pdev, 0); 1312 bs->irq = platform_get_irq(pdev, 0);
1028 if (bs->irq <= 0) { 1313 if (bs->irq <= 0) {
1029 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
1030 err = bs->irq ? bs->irq : -ENODEV; 1314 err = bs->irq ? bs->irq : -ENODEV;
1031 goto out_controller_put; 1315 goto out_controller_put;
1032 } 1316 }
1033 1317
1034 clk_prepare_enable(bs->clk); 1318 clk_prepare_enable(bs->clk);
1035 1319
1036 bcm2835_dma_init(ctlr, &pdev->dev); 1320 bcm2835_dma_init(ctlr, &pdev->dev, bs);
1037 1321
1038 /* initialise the hardware with the default polarities */ 1322 /* initialise the hardware with the default polarities */
1039 bcm2835_wr(bs, BCM2835_SPI_CS, 1323 bcm2835_wr(bs, BCM2835_SPI_CS,
@@ -1077,7 +1361,7 @@ static int bcm2835_spi_remove(struct platform_device *pdev)
1077 1361
1078 clk_disable_unprepare(bs->clk); 1362 clk_disable_unprepare(bs->clk);
1079 1363
1080 bcm2835_dma_release(ctlr); 1364 bcm2835_dma_release(ctlr, bs);
1081 1365
1082 return 0; 1366 return 0;
1083} 1367}
diff --git a/drivers/spi/spi-bcm2835aux.c b/drivers/spi/spi-bcm2835aux.c
index bb57035c5770..a2162ff56a12 100644
--- a/drivers/spi/spi-bcm2835aux.c
+++ b/drivers/spi/spi-bcm2835aux.c
@@ -491,7 +491,6 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
491{ 491{
492 struct spi_master *master; 492 struct spi_master *master;
493 struct bcm2835aux_spi *bs; 493 struct bcm2835aux_spi *bs;
494 struct resource *res;
495 unsigned long clk_hz; 494 unsigned long clk_hz;
496 int err; 495 int err;
497 496
@@ -524,8 +523,7 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
524 bs = spi_master_get_devdata(master); 523 bs = spi_master_get_devdata(master);
525 524
526 /* the main area */ 525 /* the main area */
527 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 526 bs->regs = devm_platform_ioremap_resource(pdev, 0);
528 bs->regs = devm_ioremap_resource(&pdev->dev, res);
529 if (IS_ERR(bs->regs)) { 527 if (IS_ERR(bs->regs)) {
530 err = PTR_ERR(bs->regs); 528 err = PTR_ERR(bs->regs);
531 goto out_master_put; 529 goto out_master_put;
@@ -540,7 +538,6 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
540 538
541 bs->irq = platform_get_irq(pdev, 0); 539 bs->irq = platform_get_irq(pdev, 0);
542 if (bs->irq <= 0) { 540 if (bs->irq <= 0) {
543 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
544 err = bs->irq ? bs->irq : -ENODEV; 541 err = bs->irq ? bs->irq : -ENODEV;
545 goto out_master_put; 542 goto out_master_put;
546 } 543 }
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
index 9a06ffdb73b8..c6836a931dbf 100644
--- a/drivers/spi/spi-bcm63xx-hsspi.c
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -330,7 +330,6 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
330{ 330{
331 struct spi_master *master; 331 struct spi_master *master;
332 struct bcm63xx_hsspi *bs; 332 struct bcm63xx_hsspi *bs;
333 struct resource *res_mem;
334 void __iomem *regs; 333 void __iomem *regs;
335 struct device *dev = &pdev->dev; 334 struct device *dev = &pdev->dev;
336 struct clk *clk, *pll_clk = NULL; 335 struct clk *clk, *pll_clk = NULL;
@@ -338,13 +337,10 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
338 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; 337 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
339 338
340 irq = platform_get_irq(pdev, 0); 339 irq = platform_get_irq(pdev, 0);
341 if (irq < 0) { 340 if (irq < 0)
342 dev_err(dev, "no irq: %d\n", irq);
343 return irq; 341 return irq;
344 }
345 342
346 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 343 regs = devm_platform_ioremap_resource(pdev, 0);
347 regs = devm_ioremap_resource(dev, res_mem);
348 if (IS_ERR(regs)) 344 if (IS_ERR(regs))
349 return PTR_ERR(regs); 345 return PTR_ERR(regs);
350 346
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index df1c94a131e6..fdd7eaa0b8ed 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -520,10 +520,8 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
520 } 520 }
521 521
522 irq = platform_get_irq(pdev, 0); 522 irq = platform_get_irq(pdev, 0);
523 if (irq < 0) { 523 if (irq < 0)
524 dev_err(dev, "no irq: %d\n", irq);
525 return irq; 524 return irq;
526 }
527 525
528 clk = devm_clk_get(dev, "spi"); 526 clk = devm_clk_get(dev, "spi");
529 if (IS_ERR(clk)) { 527 if (IS_ERR(clk)) {
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 7c41e4e82849..c36587b42e95 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -474,7 +474,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
474 int ret = 0, irq; 474 int ret = 0, irq;
475 struct spi_master *master; 475 struct spi_master *master;
476 struct cdns_spi *xspi; 476 struct cdns_spi *xspi;
477 struct resource *res;
478 u32 num_cs; 477 u32 num_cs;
479 478
480 master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); 479 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
@@ -485,8 +484,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
485 master->dev.of_node = pdev->dev.of_node; 484 master->dev.of_node = pdev->dev.of_node;
486 platform_set_drvdata(pdev, master); 485 platform_set_drvdata(pdev, master);
487 486
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 487 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
489 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
490 if (IS_ERR(xspi->regs)) { 488 if (IS_ERR(xspi->regs)) {
491 ret = PTR_ERR(xspi->regs); 489 ret = PTR_ERR(xspi->regs);
492 goto remove_master; 490 goto remove_master;
@@ -540,7 +538,6 @@ static int cdns_spi_probe(struct platform_device *pdev)
540 irq = platform_get_irq(pdev, 0); 538 irq = platform_get_irq(pdev, 0);
541 if (irq <= 0) { 539 if (irq <= 0) {
542 ret = -ENXIO; 540 ret = -ENXIO;
543 dev_err(&pdev->dev, "irq number is invalid\n");
544 goto clk_dis_all; 541 goto clk_dis_all;
545 } 542 }
546 543
diff --git a/drivers/spi/spi-cavium-octeon.c b/drivers/spi/spi-cavium-octeon.c
index ee4703e84622..1a2de6ce9064 100644
--- a/drivers/spi/spi-cavium-octeon.c
+++ b/drivers/spi/spi-cavium-octeon.c
@@ -18,7 +18,6 @@
18 18
19static int octeon_spi_probe(struct platform_device *pdev) 19static int octeon_spi_probe(struct platform_device *pdev)
20{ 20{
21 struct resource *res_mem;
22 void __iomem *reg_base; 21 void __iomem *reg_base;
23 struct spi_master *master; 22 struct spi_master *master;
24 struct octeon_spi *p; 23 struct octeon_spi *p;
@@ -30,8 +29,7 @@ static int octeon_spi_probe(struct platform_device *pdev)
30 p = spi_master_get_devdata(master); 29 p = spi_master_get_devdata(master);
31 platform_set_drvdata(pdev, master); 30 platform_set_drvdata(pdev, master);
32 31
33 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 32 reg_base = devm_platform_ioremap_resource(pdev, 0);
34 reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
35 if (IS_ERR(reg_base)) { 33 if (IS_ERR(reg_base)) {
36 err = PTR_ERR(reg_base); 34 err = PTR_ERR(reg_base);
37 goto fail; 35 goto fail;
diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c
index 4daba12ec843..5e900f228919 100644
--- a/drivers/spi/spi-clps711x.c
+++ b/drivers/spi/spi-clps711x.c
@@ -91,7 +91,6 @@ static int spi_clps711x_probe(struct platform_device *pdev)
91{ 91{
92 struct spi_clps711x_data *hw; 92 struct spi_clps711x_data *hw;
93 struct spi_master *master; 93 struct spi_master *master;
94 struct resource *res;
95 int irq, ret; 94 int irq, ret;
96 95
97 irq = platform_get_irq(pdev, 0); 96 irq = platform_get_irq(pdev, 0);
@@ -125,8 +124,7 @@ static int spi_clps711x_probe(struct platform_device *pdev)
125 goto err_out; 124 goto err_out;
126 } 125 }
127 126
128 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 127 hw->syncio = devm_platform_ioremap_resource(pdev, 0);
129 hw->syncio = devm_ioremap_resource(&pdev->dev, res);
130 if (IS_ERR(hw->syncio)) { 128 if (IS_ERR(hw->syncio)) {
131 ret = PTR_ERR(hw->syncio); 129 ret = PTR_ERR(hw->syncio);
132 goto err_out; 130 goto err_out;
diff --git a/drivers/spi/spi-coldfire-qspi.c b/drivers/spi/spi-coldfire-qspi.c
index 5ff48ab2f534..f80e06c87fbe 100644
--- a/drivers/spi/spi-coldfire-qspi.c
+++ b/drivers/spi/spi-coldfire-qspi.c
@@ -339,7 +339,6 @@ static int mcfqspi_probe(struct platform_device *pdev)
339{ 339{
340 struct spi_master *master; 340 struct spi_master *master;
341 struct mcfqspi *mcfqspi; 341 struct mcfqspi *mcfqspi;
342 struct resource *res;
343 struct mcfqspi_platform_data *pdata; 342 struct mcfqspi_platform_data *pdata;
344 int status; 343 int status;
345 344
@@ -362,8 +361,7 @@ static int mcfqspi_probe(struct platform_device *pdev)
362 361
363 mcfqspi = spi_master_get_devdata(master); 362 mcfqspi = spi_master_get_devdata(master);
364 363
365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 364 mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
366 mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
367 if (IS_ERR(mcfqspi->iobase)) { 365 if (IS_ERR(mcfqspi->iobase)) {
368 status = PTR_ERR(mcfqspi->iobase); 366 status = PTR_ERR(mcfqspi->iobase);
369 goto fail0; 367 goto fail0;
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 18c06568805e..bd46fca3f094 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -79,14 +79,12 @@ static int dw_spi_mscc_init(struct platform_device *pdev,
79 const char *cpu_syscon, u32 if_si_owner_offset) 79 const char *cpu_syscon, u32 if_si_owner_offset)
80{ 80{
81 struct dw_spi_mscc *dwsmscc; 81 struct dw_spi_mscc *dwsmscc;
82 struct resource *res;
83 82
84 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); 83 dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
85 if (!dwsmscc) 84 if (!dwsmscc)
86 return -ENOMEM; 85 return -ENOMEM;
87 86
88 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 87 dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
89 dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
90 if (IS_ERR(dwsmscc->spi_mst)) { 88 if (IS_ERR(dwsmscc->spi_mst)) {
91 dev_err(&pdev->dev, "SPI_MST region map failed\n"); 89 dev_err(&pdev->dev, "SPI_MST region map failed\n");
92 return PTR_ERR(dwsmscc->spi_mst); 90 return PTR_ERR(dwsmscc->spi_mst);
@@ -138,7 +136,6 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
138 struct dw_spi_mmio *dwsmmio); 136 struct dw_spi_mmio *dwsmmio);
139 struct dw_spi_mmio *dwsmmio; 137 struct dw_spi_mmio *dwsmmio;
140 struct dw_spi *dws; 138 struct dw_spi *dws;
141 struct resource *mem;
142 int ret; 139 int ret;
143 int num_cs; 140 int num_cs;
144 141
@@ -150,18 +147,15 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
150 dws = &dwsmmio->dws; 147 dws = &dwsmmio->dws;
151 148
152 /* Get basic io resource and map it */ 149 /* Get basic io resource and map it */
153 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 150 dws->regs = devm_platform_ioremap_resource(pdev, 0);
154 dws->regs = devm_ioremap_resource(&pdev->dev, mem);
155 if (IS_ERR(dws->regs)) { 151 if (IS_ERR(dws->regs)) {
156 dev_err(&pdev->dev, "SPI region map failed\n"); 152 dev_err(&pdev->dev, "SPI region map failed\n");
157 return PTR_ERR(dws->regs); 153 return PTR_ERR(dws->regs);
158 } 154 }
159 155
160 dws->irq = platform_get_irq(pdev, 0); 156 dws->irq = platform_get_irq(pdev, 0);
161 if (dws->irq < 0) { 157 if (dws->irq < 0)
162 dev_err(&pdev->dev, "no irq resource?\n");
163 return dws->irq; /* -ENXIO */ 158 return dws->irq; /* -ENXIO */
164 }
165 159
166 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL); 160 dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
167 if (IS_ERR(dwsmmio->clk)) 161 if (IS_ERR(dwsmmio->clk))
@@ -172,8 +166,10 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
172 166
173 /* Optional clock needed to access the registers */ 167 /* Optional clock needed to access the registers */
174 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); 168 dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
175 if (IS_ERR(dwsmmio->pclk)) 169 if (IS_ERR(dwsmmio->pclk)) {
176 return PTR_ERR(dwsmmio->pclk); 170 ret = PTR_ERR(dwsmmio->pclk);
171 goto out_clk;
172 }
177 ret = clk_prepare_enable(dwsmmio->pclk); 173 ret = clk_prepare_enable(dwsmmio->pclk);
178 if (ret) 174 if (ret)
179 goto out_clk; 175 goto out_clk;
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c
index 90e7b789da3b..140644913e6c 100644
--- a/drivers/spi/spi-dw-pci.c
+++ b/drivers/spi/spi-dw-pci.c
@@ -106,16 +106,14 @@ static void spi_pci_remove(struct pci_dev *pdev)
106#ifdef CONFIG_PM_SLEEP 106#ifdef CONFIG_PM_SLEEP
107static int spi_suspend(struct device *dev) 107static int spi_suspend(struct device *dev)
108{ 108{
109 struct pci_dev *pdev = to_pci_dev(dev); 109 struct dw_spi *dws = dev_get_drvdata(dev);
110 struct dw_spi *dws = pci_get_drvdata(pdev);
111 110
112 return dw_spi_suspend_host(dws); 111 return dw_spi_suspend_host(dws);
113} 112}
114 113
115static int spi_resume(struct device *dev) 114static int spi_resume(struct device *dev)
116{ 115{
117 struct pci_dev *pdev = to_pci_dev(dev); 116 struct dw_spi *dws = dev_get_drvdata(dev);
118 struct dw_spi *dws = pci_get_drvdata(pdev);
119 117
120 return dw_spi_resume_host(dws); 118 return dw_spi_resume_host(dws);
121} 119}
diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c
index eb1f2142a335..64d4c441b641 100644
--- a/drivers/spi/spi-efm32.c
+++ b/drivers/spi/spi-efm32.c
@@ -400,10 +400,8 @@ static int efm32_spi_probe(struct platform_device *pdev)
400 } 400 }
401 401
402 ret = platform_get_irq(pdev, 0); 402 ret = platform_get_irq(pdev, 0);
403 if (ret <= 0) { 403 if (ret <= 0)
404 dev_err(&pdev->dev, "failed to get rx irq (%d)\n", ret);
405 goto err; 404 goto err;
406 }
407 405
408 ddata->rxirq = ret; 406 ddata->rxirq = ret;
409 407
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 4034e3ec0ba2..4e1ccd4e52b6 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -656,10 +656,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
656 } 656 }
657 657
658 irq = platform_get_irq(pdev, 0); 658 irq = platform_get_irq(pdev, 0);
659 if (irq < 0) { 659 if (irq < 0)
660 dev_err(&pdev->dev, "failed to get irq resources\n");
661 return -EBUSY; 660 return -EBUSY;
662 }
663 661
664 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
665 if (!res) { 663 if (!res) {
diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c
index e967ac564761..858f0544289e 100644
--- a/drivers/spi/spi-fsl-cpm.c
+++ b/drivers/spi/spi-fsl-cpm.c
@@ -305,12 +305,10 @@ int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
305 } 305 }
306 306
307 if (mspi->flags & SPI_CPM1) { 307 if (mspi->flags & SPI_CPM1) {
308 struct resource *res;
309 void *pram; 308 void *pram;
310 309
311 res = platform_get_resource(to_platform_device(dev), 310 pram = devm_platform_ioremap_resource(to_platform_device(dev),
312 IORESOURCE_MEM, 1); 311 1);
313 pram = devm_ioremap_resource(dev, res);
314 if (IS_ERR(pram)) 312 if (IS_ERR(pram))
315 mspi->pram = NULL; 313 mspi->pram = NULL;
316 else 314 else
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 545fc8189fb0..bec758e978fb 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -9,26 +9,16 @@
9#include <linux/delay.h> 9#include <linux/delay.h>
10#include <linux/dmaengine.h> 10#include <linux/dmaengine.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/errno.h>
14#include <linux/interrupt.h> 12#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/kernel.h> 13#include <linux/kernel.h>
17#include <linux/math64.h>
18#include <linux/module.h> 14#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h> 15#include <linux/of_device.h>
21#include <linux/pinctrl/consumer.h> 16#include <linux/pinctrl/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h> 17#include <linux/regmap.h>
25#include <linux/sched.h>
26#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
27#include <linux/spi/spi-fsl-dspi.h> 19#include <linux/spi/spi-fsl-dspi.h>
28#include <linux/spi/spi_bitbang.h>
29#include <linux/time.h>
30 20
31#define DRIVER_NAME "fsl-dspi" 21#define DRIVER_NAME "fsl-dspi"
32 22
33#ifdef CONFIG_M5441x 23#ifdef CONFIG_M5441x
34#define DSPI_FIFO_SIZE 16 24#define DSPI_FIFO_SIZE 16
@@ -37,101 +27,97 @@
37#endif 27#endif
38#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) 28#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
39 29
40#define SPI_MCR 0x00 30#define SPI_MCR 0x00
41#define SPI_MCR_MASTER (1 << 31) 31#define SPI_MCR_MASTER BIT(31)
42#define SPI_MCR_PCSIS (0x3F << 16) 32#define SPI_MCR_PCSIS (0x3F << 16)
43#define SPI_MCR_CLR_TXF (1 << 11) 33#define SPI_MCR_CLR_TXF BIT(11)
44#define SPI_MCR_CLR_RXF (1 << 10) 34#define SPI_MCR_CLR_RXF BIT(10)
45#define SPI_MCR_XSPI (1 << 3) 35#define SPI_MCR_XSPI BIT(3)
46 36
47#define SPI_TCR 0x08 37#define SPI_TCR 0x08
48#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) 38#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
49 39
50#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) 40#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
51#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) 41#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
52#define SPI_CTAR_CPOL(x) ((x) << 26) 42#define SPI_CTAR_CPOL BIT(26)
53#define SPI_CTAR_CPHA(x) ((x) << 25) 43#define SPI_CTAR_CPHA BIT(25)
54#define SPI_CTAR_LSBFE(x) ((x) << 24) 44#define SPI_CTAR_LSBFE BIT(24)
55#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) 45#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
56#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) 46#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
57#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) 47#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
58#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) 48#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
59#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) 49#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
60#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) 50#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
61#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) 51#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
62#define SPI_CTAR_BR(x) ((x) & 0x0000000f) 52#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
63#define SPI_CTAR_SCALE_BITS 0xf 53#define SPI_CTAR_SCALE_BITS 0xf
64 54
65#define SPI_CTAR0_SLAVE 0x0c 55#define SPI_CTAR0_SLAVE 0x0c
66 56
67#define SPI_SR 0x2c 57#define SPI_SR 0x2c
68#define SPI_SR_EOQF 0x10000000 58#define SPI_SR_TCFQF BIT(31)
69#define SPI_SR_TCFQF 0x80000000 59#define SPI_SR_EOQF BIT(28)
70#define SPI_SR_CLEAR 0x9aaf0000 60#define SPI_SR_TFUF BIT(27)
71 61#define SPI_SR_TFFF BIT(25)
72#define SPI_RSER_TFFFE BIT(25) 62#define SPI_SR_CMDTCF BIT(23)
73#define SPI_RSER_TFFFD BIT(24) 63#define SPI_SR_SPEF BIT(21)
74#define SPI_RSER_RFDFE BIT(17) 64#define SPI_SR_RFOF BIT(19)
75#define SPI_RSER_RFDFD BIT(16) 65#define SPI_SR_TFIWF BIT(18)
76 66#define SPI_SR_RFDF BIT(17)
77#define SPI_RSER 0x30 67#define SPI_SR_CMDFFF BIT(16)
78#define SPI_RSER_EOQFE 0x10000000 68#define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \
79#define SPI_RSER_TCFQE 0x80000000 69 SPI_SR_TFUF | SPI_SR_TFFF | \
80 70 SPI_SR_CMDTCF | SPI_SR_SPEF | \
81#define SPI_PUSHR 0x34 71 SPI_SR_RFOF | SPI_SR_TFIWF | \
82#define SPI_PUSHR_CMD_CONT (1 << 15) 72 SPI_SR_RFDF | SPI_SR_CMDFFF)
83#define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16) 73
84#define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12) 74#define SPI_RSER_TFFFE BIT(25)
85#define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16) 75#define SPI_RSER_TFFFD BIT(24)
86#define SPI_PUSHR_CMD_EOQ (1 << 11) 76#define SPI_RSER_RFDFE BIT(17)
87#define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16) 77#define SPI_RSER_RFDFD BIT(16)
88#define SPI_PUSHR_CMD_CTCNT (1 << 10) 78
89#define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16) 79#define SPI_RSER 0x30
90#define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f) 80#define SPI_RSER_TCFQE BIT(31)
91#define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16) 81#define SPI_RSER_EOQFE BIT(28)
92#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) 82
93 83#define SPI_PUSHR 0x34
94#define SPI_PUSHR_SLAVE 0x34 84#define SPI_PUSHR_CMD_CONT BIT(15)
95 85#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
96#define SPI_POPR 0x38 86#define SPI_PUSHR_CMD_EOQ BIT(11)
97#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) 87#define SPI_PUSHR_CMD_CTCNT BIT(10)
98 88#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
99#define SPI_TXFR0 0x3c 89
100#define SPI_TXFR1 0x40 90#define SPI_PUSHR_SLAVE 0x34
101#define SPI_TXFR2 0x44 91
102#define SPI_TXFR3 0x48 92#define SPI_POPR 0x38
103#define SPI_RXFR0 0x7c 93
104#define SPI_RXFR1 0x80 94#define SPI_TXFR0 0x3c
105#define SPI_RXFR2 0x84 95#define SPI_TXFR1 0x40
106#define SPI_RXFR3 0x88 96#define SPI_TXFR2 0x44
107 97#define SPI_TXFR3 0x48
108#define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4)) 98#define SPI_RXFR0 0x7c
109#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) 99#define SPI_RXFR1 0x80
110#define SPI_CTARE_DTCP(x) ((x) & 0x7ff) 100#define SPI_RXFR2 0x84
111 101#define SPI_RXFR3 0x88
112#define SPI_SREX 0x13c 102
113 103#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
114#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) 104#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
115#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) 105#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
116#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) 106
117#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) 107#define SPI_SREX 0x13c
118 108
119#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) 109#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
120#define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1) 110#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
121 111
122/* Register offsets for regmap_pushr */ 112/* Register offsets for regmap_pushr */
123#define PUSHR_CMD 0x0 113#define PUSHR_CMD 0x0
124#define PUSHR_TX 0x2 114#define PUSHR_TX 0x2
125 115
126#define SPI_CS_INIT 0x01 116#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
127#define SPI_CS_ASSERT 0x02
128#define SPI_CS_DROP 0x04
129
130#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
131 117
132struct chip_data { 118struct chip_data {
133 u32 ctar_val; 119 u32 ctar_val;
134 u16 void_write_data; 120 u16 void_write_data;
135}; 121};
136 122
137enum dspi_trans_mode { 123enum dspi_trans_mode {
@@ -141,75 +127,75 @@ enum dspi_trans_mode {
141}; 127};
142 128
143struct fsl_dspi_devtype_data { 129struct fsl_dspi_devtype_data {
144 enum dspi_trans_mode trans_mode; 130 enum dspi_trans_mode trans_mode;
145 u8 max_clock_factor; 131 u8 max_clock_factor;
146 bool xspi_mode; 132 bool xspi_mode;
147}; 133};
148 134
149static const struct fsl_dspi_devtype_data vf610_data = { 135static const struct fsl_dspi_devtype_data vf610_data = {
150 .trans_mode = DSPI_DMA_MODE, 136 .trans_mode = DSPI_DMA_MODE,
151 .max_clock_factor = 2, 137 .max_clock_factor = 2,
152}; 138};
153 139
154static const struct fsl_dspi_devtype_data ls1021a_v1_data = { 140static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
155 .trans_mode = DSPI_TCFQ_MODE, 141 .trans_mode = DSPI_TCFQ_MODE,
156 .max_clock_factor = 8, 142 .max_clock_factor = 8,
157 .xspi_mode = true, 143 .xspi_mode = true,
158}; 144};
159 145
160static const struct fsl_dspi_devtype_data ls2085a_data = { 146static const struct fsl_dspi_devtype_data ls2085a_data = {
161 .trans_mode = DSPI_TCFQ_MODE, 147 .trans_mode = DSPI_TCFQ_MODE,
162 .max_clock_factor = 8, 148 .max_clock_factor = 8,
163}; 149};
164 150
165static const struct fsl_dspi_devtype_data coldfire_data = { 151static const struct fsl_dspi_devtype_data coldfire_data = {
166 .trans_mode = DSPI_EOQ_MODE, 152 .trans_mode = DSPI_EOQ_MODE,
167 .max_clock_factor = 8, 153 .max_clock_factor = 8,
168}; 154};
169 155
170struct fsl_dspi_dma { 156struct fsl_dspi_dma {
171 /* Length of transfer in words of DSPI_FIFO_SIZE */ 157 /* Length of transfer in words of DSPI_FIFO_SIZE */
172 u32 curr_xfer_len; 158 u32 curr_xfer_len;
173 159
174 u32 *tx_dma_buf; 160 u32 *tx_dma_buf;
175 struct dma_chan *chan_tx; 161 struct dma_chan *chan_tx;
176 dma_addr_t tx_dma_phys; 162 dma_addr_t tx_dma_phys;
177 struct completion cmd_tx_complete; 163 struct completion cmd_tx_complete;
178 struct dma_async_tx_descriptor *tx_desc; 164 struct dma_async_tx_descriptor *tx_desc;
179 165
180 u32 *rx_dma_buf; 166 u32 *rx_dma_buf;
181 struct dma_chan *chan_rx; 167 struct dma_chan *chan_rx;
182 dma_addr_t rx_dma_phys; 168 dma_addr_t rx_dma_phys;
183 struct completion cmd_rx_complete; 169 struct completion cmd_rx_complete;
184 struct dma_async_tx_descriptor *rx_desc; 170 struct dma_async_tx_descriptor *rx_desc;
185}; 171};
186 172
187struct fsl_dspi { 173struct fsl_dspi {
188 struct spi_master *master; 174 struct spi_controller *ctlr;
189 struct platform_device *pdev; 175 struct platform_device *pdev;
190 176
191 struct regmap *regmap; 177 struct regmap *regmap;
192 struct regmap *regmap_pushr; 178 struct regmap *regmap_pushr;
193 int irq; 179 int irq;
194 struct clk *clk; 180 struct clk *clk;
195 181
196 struct spi_transfer *cur_transfer; 182 struct spi_transfer *cur_transfer;
197 struct spi_message *cur_msg; 183 struct spi_message *cur_msg;
198 struct chip_data *cur_chip; 184 struct chip_data *cur_chip;
199 size_t len; 185 size_t len;
200 const void *tx; 186 const void *tx;
201 void *rx; 187 void *rx;
202 void *rx_end; 188 void *rx_end;
203 u16 void_write_data; 189 u16 void_write_data;
204 u16 tx_cmd; 190 u16 tx_cmd;
205 u8 bits_per_word; 191 u8 bits_per_word;
206 u8 bytes_per_word; 192 u8 bytes_per_word;
207 const struct fsl_dspi_devtype_data *devtype_data; 193 const struct fsl_dspi_devtype_data *devtype_data;
208 194
209 wait_queue_head_t waitq; 195 wait_queue_head_t waitq;
210 u32 waitflags; 196 u32 waitflags;
211 197
212 struct fsl_dspi_dma *dma; 198 struct fsl_dspi_dma *dma;
213}; 199};
214 200
215static u32 dspi_pop_tx(struct fsl_dspi *dspi) 201static u32 dspi_pop_tx(struct fsl_dspi *dspi)
@@ -233,7 +219,7 @@ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
233{ 219{
234 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); 220 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
235 221
236 if (spi_controller_is_slave(dspi->master)) 222 if (spi_controller_is_slave(dspi->ctlr))
237 return data; 223 return data;
238 224
239 if (dspi->len > 0) 225 if (dspi->len > 0)
@@ -246,7 +232,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
246 if (!dspi->rx) 232 if (!dspi->rx)
247 return; 233 return;
248 234
249 /* Mask of undefined bits */ 235 /* Mask off undefined bits */
250 rxdata &= (1 << dspi->bits_per_word) - 1; 236 rxdata &= (1 << dspi->bits_per_word) - 1;
251 237
252 if (dspi->bytes_per_word == 1) 238 if (dspi->bytes_per_word == 1)
@@ -282,8 +268,8 @@ static void dspi_rx_dma_callback(void *arg)
282 268
283static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) 269static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
284{ 270{
285 struct fsl_dspi_dma *dma = dspi->dma;
286 struct device *dev = &dspi->pdev->dev; 271 struct device *dev = &dspi->pdev->dev;
272 struct fsl_dspi_dma *dma = dspi->dma;
287 int time_left; 273 int time_left;
288 int i; 274 int i;
289 275
@@ -332,13 +318,13 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
332 dma_async_issue_pending(dma->chan_rx); 318 dma_async_issue_pending(dma->chan_rx);
333 dma_async_issue_pending(dma->chan_tx); 319 dma_async_issue_pending(dma->chan_tx);
334 320
335 if (spi_controller_is_slave(dspi->master)) { 321 if (spi_controller_is_slave(dspi->ctlr)) {
336 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); 322 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
337 return 0; 323 return 0;
338 } 324 }
339 325
340 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, 326 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
341 DMA_COMPLETION_TIMEOUT); 327 DMA_COMPLETION_TIMEOUT);
342 if (time_left == 0) { 328 if (time_left == 0) {
343 dev_err(dev, "DMA tx timeout\n"); 329 dev_err(dev, "DMA tx timeout\n");
344 dmaengine_terminate_all(dma->chan_tx); 330 dmaengine_terminate_all(dma->chan_tx);
@@ -347,7 +333,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
347 } 333 }
348 334
349 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, 335 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
350 DMA_COMPLETION_TIMEOUT); 336 DMA_COMPLETION_TIMEOUT);
351 if (time_left == 0) { 337 if (time_left == 0) {
352 dev_err(dev, "DMA rx timeout\n"); 338 dev_err(dev, "DMA rx timeout\n");
353 dmaengine_terminate_all(dma->chan_tx); 339 dmaengine_terminate_all(dma->chan_tx);
@@ -360,9 +346,9 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
360 346
361static int dspi_dma_xfer(struct fsl_dspi *dspi) 347static int dspi_dma_xfer(struct fsl_dspi *dspi)
362{ 348{
363 struct fsl_dspi_dma *dma = dspi->dma;
364 struct device *dev = &dspi->pdev->dev;
365 struct spi_message *message = dspi->cur_msg; 349 struct spi_message *message = dspi->cur_msg;
350 struct device *dev = &dspi->pdev->dev;
351 struct fsl_dspi_dma *dma = dspi->dma;
366 int curr_remaining_bytes; 352 int curr_remaining_bytes;
367 int bytes_per_buffer; 353 int bytes_per_buffer;
368 int ret = 0; 354 int ret = 0;
@@ -397,9 +383,9 @@ exit:
397 383
398static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 384static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
399{ 385{
400 struct fsl_dspi_dma *dma;
401 struct dma_slave_config cfg;
402 struct device *dev = &dspi->pdev->dev; 386 struct device *dev = &dspi->pdev->dev;
387 struct dma_slave_config cfg;
388 struct fsl_dspi_dma *dma;
403 int ret; 389 int ret;
404 390
405 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 391 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
@@ -421,14 +407,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
421 } 407 }
422 408
423 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, 409 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
424 &dma->tx_dma_phys, GFP_KERNEL); 410 &dma->tx_dma_phys, GFP_KERNEL);
425 if (!dma->tx_dma_buf) { 411 if (!dma->tx_dma_buf) {
426 ret = -ENOMEM; 412 ret = -ENOMEM;
427 goto err_tx_dma_buf; 413 goto err_tx_dma_buf;
428 } 414 }
429 415
430 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, 416 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
431 &dma->rx_dma_phys, GFP_KERNEL); 417 &dma->rx_dma_phys, GFP_KERNEL);
432 if (!dma->rx_dma_buf) { 418 if (!dma->rx_dma_buf) {
433 ret = -ENOMEM; 419 ret = -ENOMEM;
434 goto err_rx_dma_buf; 420 goto err_rx_dma_buf;
@@ -485,30 +471,31 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
485 struct fsl_dspi_dma *dma = dspi->dma; 471 struct fsl_dspi_dma *dma = dspi->dma;
486 struct device *dev = &dspi->pdev->dev; 472 struct device *dev = &dspi->pdev->dev;
487 473
488 if (dma) { 474 if (!dma)
489 if (dma->chan_tx) { 475 return;
490 dma_unmap_single(dev, dma->tx_dma_phys,
491 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
492 dma_release_channel(dma->chan_tx);
493 }
494 476
495 if (dma->chan_rx) { 477 if (dma->chan_tx) {
496 dma_unmap_single(dev, dma->rx_dma_phys, 478 dma_unmap_single(dev, dma->tx_dma_phys,
497 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); 479 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
498 dma_release_channel(dma->chan_rx); 480 dma_release_channel(dma->chan_tx);
499 } 481 }
482
483 if (dma->chan_rx) {
484 dma_unmap_single(dev, dma->rx_dma_phys,
485 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
486 dma_release_channel(dma->chan_rx);
500 } 487 }
501} 488}
502 489
503static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 490static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
504 unsigned long clkrate) 491 unsigned long clkrate)
505{ 492{
506 /* Valid baud rate pre-scaler values */ 493 /* Valid baud rate pre-scaler values */
507 int pbr_tbl[4] = {2, 3, 5, 7}; 494 int pbr_tbl[4] = {2, 3, 5, 7};
508 int brs[16] = { 2, 4, 6, 8, 495 int brs[16] = { 2, 4, 6, 8,
509 16, 32, 64, 128, 496 16, 32, 64, 128,
510 256, 512, 1024, 2048, 497 256, 512, 1024, 2048,
511 4096, 8192, 16384, 32768 }; 498 4096, 8192, 16384, 32768 };
512 int scale_needed, scale, minscale = INT_MAX; 499 int scale_needed, scale, minscale = INT_MAX;
513 int i, j; 500 int i, j;
514 501
@@ -538,15 +525,15 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
538} 525}
539 526
540static void ns_delay_scale(char *psc, char *sc, int delay_ns, 527static void ns_delay_scale(char *psc, char *sc, int delay_ns,
541 unsigned long clkrate) 528 unsigned long clkrate)
542{ 529{
543 int pscale_tbl[4] = {1, 3, 5, 7};
544 int scale_needed, scale, minscale = INT_MAX; 530 int scale_needed, scale, minscale = INT_MAX;
545 int i, j; 531 int pscale_tbl[4] = {1, 3, 5, 7};
546 u32 remainder; 532 u32 remainder;
533 int i, j;
547 534
548 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, 535 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
549 &remainder); 536 &remainder);
550 if (remainder) 537 if (remainder)
551 scale_needed++; 538 scale_needed++;
552 539
@@ -601,7 +588,7 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi)
601 */ 588 */
602 u32 data = dspi_pop_tx(dspi); 589 u32 data = dspi_pop_tx(dspi);
603 590
604 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) { 591 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
605 /* LSB */ 592 /* LSB */
606 tx_fifo_write(dspi, data & 0xFFFF); 593 tx_fifo_write(dspi, data & 0xFFFF);
607 tx_fifo_write(dspi, data >> 16); 594 tx_fifo_write(dspi, data >> 16);
@@ -655,19 +642,90 @@ static void dspi_eoq_read(struct fsl_dspi *dspi)
655{ 642{
656 int fifo_size = DSPI_FIFO_SIZE; 643 int fifo_size = DSPI_FIFO_SIZE;
657 644
658 /* Read one FIFO entry at and push to rx buffer */ 645 /* Read one FIFO entry and push to rx buffer */
659 while ((dspi->rx < dspi->rx_end) && fifo_size--) 646 while ((dspi->rx < dspi->rx_end) && fifo_size--)
660 dspi_push_rx(dspi, fifo_read(dspi)); 647 dspi_push_rx(dspi, fifo_read(dspi));
661} 648}
662 649
663static int dspi_transfer_one_message(struct spi_master *master, 650static int dspi_rxtx(struct fsl_dspi *dspi)
664 struct spi_message *message) 651{
652 struct spi_message *msg = dspi->cur_msg;
653 enum dspi_trans_mode trans_mode;
654 u16 spi_tcnt;
655 u32 spi_tcr;
656
657 /* Get transfer counter (in number of SPI transfers). It was
658 * reset to 0 when transfer(s) were started.
659 */
660 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
661 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
662 /* Update total number of bytes that were transferred */
663 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
664
665 trans_mode = dspi->devtype_data->trans_mode;
666 if (trans_mode == DSPI_EOQ_MODE)
667 dspi_eoq_read(dspi);
668 else if (trans_mode == DSPI_TCFQ_MODE)
669 dspi_tcfq_read(dspi);
670
671 if (!dspi->len)
672 /* Success! */
673 return 0;
674
675 if (trans_mode == DSPI_EOQ_MODE)
676 dspi_eoq_write(dspi);
677 else if (trans_mode == DSPI_TCFQ_MODE)
678 dspi_tcfq_write(dspi);
679
680 return -EINPROGRESS;
681}
682
683static int dspi_poll(struct fsl_dspi *dspi)
684{
685 int tries = 1000;
686 u32 spi_sr;
687
688 do {
689 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
690 regmap_write(dspi->regmap, SPI_SR, spi_sr);
691
692 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF))
693 break;
694 } while (--tries);
695
696 if (!tries)
697 return -ETIMEDOUT;
698
699 return dspi_rxtx(dspi);
700}
701
702static irqreturn_t dspi_interrupt(int irq, void *dev_id)
703{
704 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
705 u32 spi_sr;
706
707 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
708 regmap_write(dspi->regmap, SPI_SR, spi_sr);
709
710 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)))
711 return IRQ_NONE;
712
713 if (dspi_rxtx(dspi) == 0) {
714 dspi->waitflags = 1;
715 wake_up_interruptible(&dspi->waitq);
716 }
717
718 return IRQ_HANDLED;
719}
720
721static int dspi_transfer_one_message(struct spi_controller *ctlr,
722 struct spi_message *message)
665{ 723{
666 struct fsl_dspi *dspi = spi_master_get_devdata(master); 724 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
667 struct spi_device *spi = message->spi; 725 struct spi_device *spi = message->spi;
726 enum dspi_trans_mode trans_mode;
668 struct spi_transfer *transfer; 727 struct spi_transfer *transfer;
669 int status = 0; 728 int status = 0;
670 enum dspi_trans_mode trans_mode;
671 729
672 message->actual_length = 0; 730 message->actual_length = 0;
673 731
@@ -677,7 +735,7 @@ static int dspi_transfer_one_message(struct spi_master *master,
677 dspi->cur_chip = spi_get_ctldata(spi); 735 dspi->cur_chip = spi_get_ctldata(spi);
678 /* Prepare command word for CMD FIFO */ 736 /* Prepare command word for CMD FIFO */
679 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | 737 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
680 SPI_PUSHR_CMD_PCS(spi->chip_select); 738 SPI_PUSHR_CMD_PCS(spi->chip_select);
681 if (list_is_last(&dspi->cur_transfer->transfer_list, 739 if (list_is_last(&dspi->cur_transfer->transfer_list,
682 &dspi->cur_msg->transfers)) { 740 &dspi->cur_msg->transfers)) {
683 /* Leave PCS activated after last transfer when 741 /* Leave PCS activated after last transfer when
@@ -718,8 +776,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
718 SPI_FRAME_BITS(transfer->bits_per_word)); 776 SPI_FRAME_BITS(transfer->bits_per_word));
719 if (dspi->devtype_data->xspi_mode) 777 if (dspi->devtype_data->xspi_mode)
720 regmap_write(dspi->regmap, SPI_CTARE(0), 778 regmap_write(dspi->regmap, SPI_CTARE(0),
721 SPI_FRAME_EBITS(transfer->bits_per_word) 779 SPI_FRAME_EBITS(transfer->bits_per_word) |
722 | SPI_CTARE_DTCP(1)); 780 SPI_CTARE_DTCP(1));
723 781
724 trans_mode = dspi->devtype_data->trans_mode; 782 trans_mode = dspi->devtype_data->trans_mode;
725 switch (trans_mode) { 783 switch (trans_mode) {
@@ -733,8 +791,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
733 break; 791 break;
734 case DSPI_DMA_MODE: 792 case DSPI_DMA_MODE:
735 regmap_write(dspi->regmap, SPI_RSER, 793 regmap_write(dspi->regmap, SPI_RSER,
736 SPI_RSER_TFFFE | SPI_RSER_TFFFD | 794 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
737 SPI_RSER_RFDFE | SPI_RSER_RFDFD); 795 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
738 status = dspi_dma_xfer(dspi); 796 status = dspi_dma_xfer(dspi);
739 break; 797 break;
740 default: 798 default:
@@ -744,13 +802,18 @@ static int dspi_transfer_one_message(struct spi_master *master,
744 goto out; 802 goto out;
745 } 803 }
746 804
747 if (trans_mode != DSPI_DMA_MODE) { 805 if (!dspi->irq) {
748 if (wait_event_interruptible(dspi->waitq, 806 do {
749 dspi->waitflags)) 807 status = dspi_poll(dspi);
750 dev_err(&dspi->pdev->dev, 808 } while (status == -EINPROGRESS);
751 "wait transfer complete fail!\n"); 809 } else if (trans_mode != DSPI_DMA_MODE) {
810 status = wait_event_interruptible(dspi->waitq,
811 dspi->waitflags);
752 dspi->waitflags = 0; 812 dspi->waitflags = 0;
753 } 813 }
814 if (status)
815 dev_err(&dspi->pdev->dev,
816 "Waiting for transfer to complete failed!\n");
754 817
755 if (transfer->delay_usecs) 818 if (transfer->delay_usecs)
756 udelay(transfer->delay_usecs); 819 udelay(transfer->delay_usecs);
@@ -758,19 +821,19 @@ static int dspi_transfer_one_message(struct spi_master *master,
758 821
759out: 822out:
760 message->status = status; 823 message->status = status;
761 spi_finalize_current_message(master); 824 spi_finalize_current_message(ctlr);
762 825
763 return status; 826 return status;
764} 827}
765 828
766static int dspi_setup(struct spi_device *spi) 829static int dspi_setup(struct spi_device *spi)
767{ 830{
768 struct chip_data *chip; 831 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
769 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
770 struct fsl_dspi_platform_data *pdata;
771 u32 cs_sck_delay = 0, sck_cs_delay = 0;
772 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; 832 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
833 u32 cs_sck_delay = 0, sck_cs_delay = 0;
834 struct fsl_dspi_platform_data *pdata;
773 unsigned char pasc = 0, asc = 0; 835 unsigned char pasc = 0, asc = 0;
836 struct chip_data *chip;
774 unsigned long clkrate; 837 unsigned long clkrate;
775 838
776 /* Only alloc on first setup */ 839 /* Only alloc on first setup */
@@ -785,10 +848,10 @@ static int dspi_setup(struct spi_device *spi)
785 848
786 if (!pdata) { 849 if (!pdata) {
787 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", 850 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
788 &cs_sck_delay); 851 &cs_sck_delay);
789 852
790 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", 853 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
791 &sck_cs_delay); 854 &sck_cs_delay);
792 } else { 855 } else {
793 cs_sck_delay = pdata->cs_sck_delay; 856 cs_sck_delay = pdata->cs_sck_delay;
794 sck_cs_delay = pdata->sck_cs_delay; 857 sck_cs_delay = pdata->sck_cs_delay;
@@ -805,18 +868,22 @@ static int dspi_setup(struct spi_device *spi)
805 /* Set After SCK delay scale values */ 868 /* Set After SCK delay scale values */
806 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); 869 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
807 870
808 chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) 871 chip->ctar_val = 0;
809 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0); 872 if (spi->mode & SPI_CPOL)
810 873 chip->ctar_val |= SPI_CTAR_CPOL;
811 if (!spi_controller_is_slave(dspi->master)) { 874 if (spi->mode & SPI_CPHA)
812 chip->ctar_val |= SPI_CTAR_LSBFE(spi->mode & 875 chip->ctar_val |= SPI_CTAR_CPHA;
813 SPI_LSB_FIRST ? 1 : 0) 876
814 | SPI_CTAR_PCSSCK(pcssck) 877 if (!spi_controller_is_slave(dspi->ctlr)) {
815 | SPI_CTAR_CSSCK(cssck) 878 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
816 | SPI_CTAR_PASC(pasc) 879 SPI_CTAR_CSSCK(cssck) |
817 | SPI_CTAR_ASC(asc) 880 SPI_CTAR_PASC(pasc) |
818 | SPI_CTAR_PBR(pbr) 881 SPI_CTAR_ASC(asc) |
819 | SPI_CTAR_BR(br); 882 SPI_CTAR_PBR(pbr) |
883 SPI_CTAR_BR(br);
884
885 if (spi->mode & SPI_LSB_FIRST)
886 chip->ctar_val |= SPI_CTAR_LSBFE;
820 } 887 }
821 888
822 spi_set_ctldata(spi, chip); 889 spi_set_ctldata(spi, chip);
@@ -829,70 +896,11 @@ static void dspi_cleanup(struct spi_device *spi)
829 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 896 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
830 897
831 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", 898 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
832 spi->master->bus_num, spi->chip_select); 899 spi->controller->bus_num, spi->chip_select);
833 900
834 kfree(chip); 901 kfree(chip);
835} 902}
836 903
837static irqreturn_t dspi_interrupt(int irq, void *dev_id)
838{
839 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
840 struct spi_message *msg = dspi->cur_msg;
841 enum dspi_trans_mode trans_mode;
842 u32 spi_sr, spi_tcr;
843 u16 spi_tcnt;
844
845 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
846 regmap_write(dspi->regmap, SPI_SR, spi_sr);
847
848
849 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
850 /* Get transfer counter (in number of SPI transfers). It was
851 * reset to 0 when transfer(s) were started.
852 */
853 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
854 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
855 /* Update total number of bytes that were transferred */
856 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
857
858 trans_mode = dspi->devtype_data->trans_mode;
859 switch (trans_mode) {
860 case DSPI_EOQ_MODE:
861 dspi_eoq_read(dspi);
862 break;
863 case DSPI_TCFQ_MODE:
864 dspi_tcfq_read(dspi);
865 break;
866 default:
867 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
868 trans_mode);
869 return IRQ_HANDLED;
870 }
871
872 if (!dspi->len) {
873 dspi->waitflags = 1;
874 wake_up_interruptible(&dspi->waitq);
875 } else {
876 switch (trans_mode) {
877 case DSPI_EOQ_MODE:
878 dspi_eoq_write(dspi);
879 break;
880 case DSPI_TCFQ_MODE:
881 dspi_tcfq_write(dspi);
882 break;
883 default:
884 dev_err(&dspi->pdev->dev,
885 "unsupported trans_mode %u\n",
886 trans_mode);
887 }
888 }
889
890 return IRQ_HANDLED;
891 }
892
893 return IRQ_NONE;
894}
895
896static const struct of_device_id fsl_dspi_dt_ids[] = { 904static const struct of_device_id fsl_dspi_dt_ids[] = {
897 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, 905 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
898 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, 906 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
@@ -904,10 +912,10 @@ MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
904#ifdef CONFIG_PM_SLEEP 912#ifdef CONFIG_PM_SLEEP
905static int dspi_suspend(struct device *dev) 913static int dspi_suspend(struct device *dev)
906{ 914{
907 struct spi_master *master = dev_get_drvdata(dev); 915 struct spi_controller *ctlr = dev_get_drvdata(dev);
908 struct fsl_dspi *dspi = spi_master_get_devdata(master); 916 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
909 917
910 spi_master_suspend(master); 918 spi_controller_suspend(ctlr);
911 clk_disable_unprepare(dspi->clk); 919 clk_disable_unprepare(dspi->clk);
912 920
913 pinctrl_pm_select_sleep_state(dev); 921 pinctrl_pm_select_sleep_state(dev);
@@ -917,8 +925,8 @@ static int dspi_suspend(struct device *dev)
917 925
918static int dspi_resume(struct device *dev) 926static int dspi_resume(struct device *dev)
919{ 927{
920 struct spi_master *master = dev_get_drvdata(dev); 928 struct spi_controller *ctlr = dev_get_drvdata(dev);
921 struct fsl_dspi *dspi = spi_master_get_devdata(master); 929 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
922 int ret; 930 int ret;
923 931
924 pinctrl_pm_select_default_state(dev); 932 pinctrl_pm_select_default_state(dev);
@@ -926,7 +934,7 @@ static int dspi_resume(struct device *dev)
926 ret = clk_prepare_enable(dspi->clk); 934 ret = clk_prepare_enable(dspi->clk);
927 if (ret) 935 if (ret)
928 return ret; 936 return ret;
929 spi_master_resume(master); 937 spi_controller_resume(ctlr);
930 938
931 return 0; 939 return 0;
932} 940}
@@ -941,16 +949,16 @@ static const struct regmap_range dspi_volatile_ranges[] = {
941}; 949};
942 950
943static const struct regmap_access_table dspi_volatile_table = { 951static const struct regmap_access_table dspi_volatile_table = {
944 .yes_ranges = dspi_volatile_ranges, 952 .yes_ranges = dspi_volatile_ranges,
945 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), 953 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
946}; 954};
947 955
948static const struct regmap_config dspi_regmap_config = { 956static const struct regmap_config dspi_regmap_config = {
949 .reg_bits = 32, 957 .reg_bits = 32,
950 .val_bits = 32, 958 .val_bits = 32,
951 .reg_stride = 4, 959 .reg_stride = 4,
952 .max_register = 0x88, 960 .max_register = 0x88,
953 .volatile_table = &dspi_volatile_table, 961 .volatile_table = &dspi_volatile_table,
954}; 962};
955 963
956static const struct regmap_range dspi_xspi_volatile_ranges[] = { 964static const struct regmap_range dspi_xspi_volatile_ranges[] = {
@@ -961,33 +969,34 @@ static const struct regmap_range dspi_xspi_volatile_ranges[] = {
961}; 969};
962 970
963static const struct regmap_access_table dspi_xspi_volatile_table = { 971static const struct regmap_access_table dspi_xspi_volatile_table = {
964 .yes_ranges = dspi_xspi_volatile_ranges, 972 .yes_ranges = dspi_xspi_volatile_ranges,
965 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), 973 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
966}; 974};
967 975
968static const struct regmap_config dspi_xspi_regmap_config[] = { 976static const struct regmap_config dspi_xspi_regmap_config[] = {
969 { 977 {
970 .reg_bits = 32, 978 .reg_bits = 32,
971 .val_bits = 32, 979 .val_bits = 32,
972 .reg_stride = 4, 980 .reg_stride = 4,
973 .max_register = 0x13c, 981 .max_register = 0x13c,
974 .volatile_table = &dspi_xspi_volatile_table, 982 .volatile_table = &dspi_xspi_volatile_table,
975 }, 983 },
976 { 984 {
977 .name = "pushr", 985 .name = "pushr",
978 .reg_bits = 16, 986 .reg_bits = 16,
979 .val_bits = 16, 987 .val_bits = 16,
980 .reg_stride = 2, 988 .reg_stride = 2,
981 .max_register = 0x2, 989 .max_register = 0x2,
982 }, 990 },
983}; 991};
984 992
985static void dspi_init(struct fsl_dspi *dspi) 993static void dspi_init(struct fsl_dspi *dspi)
986{ 994{
987 unsigned int mcr = SPI_MCR_PCSIS | 995 unsigned int mcr = SPI_MCR_PCSIS;
988 (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0);
989 996
990 if (!spi_controller_is_slave(dspi->master)) 997 if (dspi->devtype_data->xspi_mode)
998 mcr |= SPI_MCR_XSPI;
999 if (!spi_controller_is_slave(dspi->ctlr))
991 mcr |= SPI_MCR_MASTER; 1000 mcr |= SPI_MCR_MASTER;
992 1001
993 regmap_write(dspi->regmap, SPI_MCR, mcr); 1002 regmap_write(dspi->regmap, SPI_MCR, mcr);
@@ -1000,34 +1009,33 @@ static void dspi_init(struct fsl_dspi *dspi)
1000static int dspi_probe(struct platform_device *pdev) 1009static int dspi_probe(struct platform_device *pdev)
1001{ 1010{
1002 struct device_node *np = pdev->dev.of_node; 1011 struct device_node *np = pdev->dev.of_node;
1003 struct spi_master *master; 1012 const struct regmap_config *regmap_config;
1013 struct fsl_dspi_platform_data *pdata;
1014 struct spi_controller *ctlr;
1015 int ret, cs_num, bus_num;
1004 struct fsl_dspi *dspi; 1016 struct fsl_dspi *dspi;
1005 struct resource *res; 1017 struct resource *res;
1006 const struct regmap_config *regmap_config;
1007 void __iomem *base; 1018 void __iomem *base;
1008 struct fsl_dspi_platform_data *pdata;
1009 int ret = 0, cs_num, bus_num;
1010 1019
1011 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); 1020 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
1012 if (!master) 1021 if (!ctlr)
1013 return -ENOMEM; 1022 return -ENOMEM;
1014 1023
1015 dspi = spi_master_get_devdata(master); 1024 dspi = spi_controller_get_devdata(ctlr);
1016 dspi->pdev = pdev; 1025 dspi->pdev = pdev;
1017 dspi->master = master; 1026 dspi->ctlr = ctlr;
1018 1027
1019 master->transfer = NULL; 1028 ctlr->setup = dspi_setup;
1020 master->setup = dspi_setup; 1029 ctlr->transfer_one_message = dspi_transfer_one_message;
1021 master->transfer_one_message = dspi_transfer_one_message; 1030 ctlr->dev.of_node = pdev->dev.of_node;
1022 master->dev.of_node = pdev->dev.of_node;
1023 1031
1024 master->cleanup = dspi_cleanup; 1032 ctlr->cleanup = dspi_cleanup;
1025 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1033 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1026 1034
1027 pdata = dev_get_platdata(&pdev->dev); 1035 pdata = dev_get_platdata(&pdev->dev);
1028 if (pdata) { 1036 if (pdata) {
1029 master->num_chipselect = pdata->cs_num; 1037 ctlr->num_chipselect = pdata->cs_num;
1030 master->bus_num = pdata->bus_num; 1038 ctlr->bus_num = pdata->bus_num;
1031 1039
1032 dspi->devtype_data = &coldfire_data; 1040 dspi->devtype_data = &coldfire_data;
1033 } else { 1041 } else {
@@ -1035,38 +1043,38 @@ static int dspi_probe(struct platform_device *pdev)
1035 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); 1043 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1036 if (ret < 0) { 1044 if (ret < 0) {
1037 dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); 1045 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1038 goto out_master_put; 1046 goto out_ctlr_put;
1039 } 1047 }
1040 master->num_chipselect = cs_num; 1048 ctlr->num_chipselect = cs_num;
1041 1049
1042 ret = of_property_read_u32(np, "bus-num", &bus_num); 1050 ret = of_property_read_u32(np, "bus-num", &bus_num);
1043 if (ret < 0) { 1051 if (ret < 0) {
1044 dev_err(&pdev->dev, "can't get bus-num\n"); 1052 dev_err(&pdev->dev, "can't get bus-num\n");
1045 goto out_master_put; 1053 goto out_ctlr_put;
1046 } 1054 }
1047 master->bus_num = bus_num; 1055 ctlr->bus_num = bus_num;
1048 1056
1049 if (of_property_read_bool(np, "spi-slave")) 1057 if (of_property_read_bool(np, "spi-slave"))
1050 master->slave = true; 1058 ctlr->slave = true;
1051 1059
1052 dspi->devtype_data = of_device_get_match_data(&pdev->dev); 1060 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1053 if (!dspi->devtype_data) { 1061 if (!dspi->devtype_data) {
1054 dev_err(&pdev->dev, "can't get devtype_data\n"); 1062 dev_err(&pdev->dev, "can't get devtype_data\n");
1055 ret = -EFAULT; 1063 ret = -EFAULT;
1056 goto out_master_put; 1064 goto out_ctlr_put;
1057 } 1065 }
1058 } 1066 }
1059 1067
1060 if (dspi->devtype_data->xspi_mode) 1068 if (dspi->devtype_data->xspi_mode)
1061 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1069 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1062 else 1070 else
1063 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1071 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1064 1072
1065 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1066 base = devm_ioremap_resource(&pdev->dev, res); 1074 base = devm_ioremap_resource(&pdev->dev, res);
1067 if (IS_ERR(base)) { 1075 if (IS_ERR(base)) {
1068 ret = PTR_ERR(base); 1076 ret = PTR_ERR(base);
1069 goto out_master_put; 1077 goto out_ctlr_put;
1070 } 1078 }
1071 1079
1072 if (dspi->devtype_data->xspi_mode) 1080 if (dspi->devtype_data->xspi_mode)
@@ -1078,7 +1086,7 @@ static int dspi_probe(struct platform_device *pdev)
1078 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 1086 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1079 PTR_ERR(dspi->regmap)); 1087 PTR_ERR(dspi->regmap));
1080 ret = PTR_ERR(dspi->regmap); 1088 ret = PTR_ERR(dspi->regmap);
1081 goto out_master_put; 1089 goto out_ctlr_put;
1082 } 1090 }
1083 1091
1084 if (dspi->devtype_data->xspi_mode) { 1092 if (dspi->devtype_data->xspi_mode) {
@@ -1090,7 +1098,7 @@ static int dspi_probe(struct platform_device *pdev)
1090 "failed to init pushr regmap: %ld\n", 1098 "failed to init pushr regmap: %ld\n",
1091 PTR_ERR(dspi->regmap_pushr)); 1099 PTR_ERR(dspi->regmap_pushr));
1092 ret = PTR_ERR(dspi->regmap_pushr); 1100 ret = PTR_ERR(dspi->regmap_pushr);
1093 goto out_master_put; 1101 goto out_ctlr_put;
1094 } 1102 }
1095 } 1103 }
1096 1104
@@ -1098,18 +1106,20 @@ static int dspi_probe(struct platform_device *pdev)
1098 if (IS_ERR(dspi->clk)) { 1106 if (IS_ERR(dspi->clk)) {
1099 ret = PTR_ERR(dspi->clk); 1107 ret = PTR_ERR(dspi->clk);
1100 dev_err(&pdev->dev, "unable to get clock\n"); 1108 dev_err(&pdev->dev, "unable to get clock\n");
1101 goto out_master_put; 1109 goto out_ctlr_put;
1102 } 1110 }
1103 ret = clk_prepare_enable(dspi->clk); 1111 ret = clk_prepare_enable(dspi->clk);
1104 if (ret) 1112 if (ret)
1105 goto out_master_put; 1113 goto out_ctlr_put;
1106 1114
1107 dspi_init(dspi); 1115 dspi_init(dspi);
1116
1108 dspi->irq = platform_get_irq(pdev, 0); 1117 dspi->irq = platform_get_irq(pdev, 0);
1109 if (dspi->irq < 0) { 1118 if (dspi->irq <= 0) {
1110 dev_err(&pdev->dev, "can't get platform irq\n"); 1119 dev_info(&pdev->dev,
1111 ret = dspi->irq; 1120 "can't get platform irq, using poll mode\n");
1112 goto out_clk_put; 1121 dspi->irq = 0;
1122 goto poll_mode;
1113 } 1123 }
1114 1124
1115 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 1125 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
@@ -1119,6 +1129,9 @@ static int dspi_probe(struct platform_device *pdev)
1119 goto out_clk_put; 1129 goto out_clk_put;
1120 } 1130 }
1121 1131
1132 init_waitqueue_head(&dspi->waitq);
1133
1134poll_mode:
1122 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1135 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1123 ret = dspi_request_dma(dspi, res->start); 1136 ret = dspi_request_dma(dspi, res->start);
1124 if (ret < 0) { 1137 if (ret < 0) {
@@ -1127,15 +1140,14 @@ static int dspi_probe(struct platform_device *pdev)
1127 } 1140 }
1128 } 1141 }
1129 1142
1130 master->max_speed_hz = 1143 ctlr->max_speed_hz =
1131 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; 1144 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1132 1145
1133 init_waitqueue_head(&dspi->waitq); 1146 platform_set_drvdata(pdev, ctlr);
1134 platform_set_drvdata(pdev, master);
1135 1147
1136 ret = spi_register_master(master); 1148 ret = spi_register_controller(ctlr);
1137 if (ret != 0) { 1149 if (ret != 0) {
1138 dev_err(&pdev->dev, "Problem registering DSPI master\n"); 1150 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1139 goto out_clk_put; 1151 goto out_clk_put;
1140 } 1152 }
1141 1153
@@ -1143,32 +1155,32 @@ static int dspi_probe(struct platform_device *pdev)
1143 1155
1144out_clk_put: 1156out_clk_put:
1145 clk_disable_unprepare(dspi->clk); 1157 clk_disable_unprepare(dspi->clk);
1146out_master_put: 1158out_ctlr_put:
1147 spi_master_put(master); 1159 spi_controller_put(ctlr);
1148 1160
1149 return ret; 1161 return ret;
1150} 1162}
1151 1163
1152static int dspi_remove(struct platform_device *pdev) 1164static int dspi_remove(struct platform_device *pdev)
1153{ 1165{
1154 struct spi_master *master = platform_get_drvdata(pdev); 1166 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1155 struct fsl_dspi *dspi = spi_master_get_devdata(master); 1167 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1156 1168
1157 /* Disconnect from the SPI framework */ 1169 /* Disconnect from the SPI framework */
1158 dspi_release_dma(dspi); 1170 dspi_release_dma(dspi);
1159 clk_disable_unprepare(dspi->clk); 1171 clk_disable_unprepare(dspi->clk);
1160 spi_unregister_master(dspi->master); 1172 spi_unregister_controller(dspi->ctlr);
1161 1173
1162 return 0; 1174 return 0;
1163} 1175}
1164 1176
1165static struct platform_driver fsl_dspi_driver = { 1177static struct platform_driver fsl_dspi_driver = {
1166 .driver.name = DRIVER_NAME, 1178 .driver.name = DRIVER_NAME,
1167 .driver.of_match_table = fsl_dspi_dt_ids, 1179 .driver.of_match_table = fsl_dspi_dt_ids,
1168 .driver.owner = THIS_MODULE, 1180 .driver.owner = THIS_MODULE,
1169 .driver.pm = &dspi_pm, 1181 .driver.pm = &dspi_pm,
1170 .probe = dspi_probe, 1182 .probe = dspi_probe,
1171 .remove = dspi_remove, 1183 .remove = dspi_remove,
1172}; 1184};
1173module_platform_driver(fsl_dspi_driver); 1185module_platform_driver(fsl_dspi_driver);
1174 1186
diff --git a/drivers/spi/spi-fsl-lib.h b/drivers/spi/spi-fsl-lib.h
index 3576167283dc..015a1abb6a84 100644
--- a/drivers/spi/spi-fsl-lib.h
+++ b/drivers/spi/spi-fsl-lib.h
@@ -91,9 +91,6 @@ static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
91 91
92struct mpc8xxx_spi_probe_info { 92struct mpc8xxx_spi_probe_info {
93 struct fsl_spi_platform_data pdata; 93 struct fsl_spi_platform_data pdata;
94 int ngpios;
95 int *gpios;
96 bool *alow_flags;
97 __be32 __iomem *immr_spi_cs; 94 __be32 __iomem *immr_spi_cs;
98}; 95};
99 96
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index 448c00e4065b..c02e24c01136 100644
--- a/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@ -860,10 +860,8 @@ static int fsl_qspi_probe(struct platform_device *pdev)
860 860
861 /* find the irq */ 861 /* find the irq */
862 ret = platform_get_irq(pdev, 0); 862 ret = platform_get_irq(pdev, 0);
863 if (ret < 0) { 863 if (ret < 0)
864 dev_err(dev, "failed to get the irq: %d\n", ret);
865 goto err_disable_clk; 864 goto err_disable_clk;
866 }
867 865
868 ret = devm_request_irq(dev, ret, 866 ret = devm_request_irq(dev, ret,
869 fsl_qspi_irq_handler, 0, pdev->name, q); 867 fsl_qspi_irq_handler, 0, pdev->name, q);
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 1d9b33aa1a3b..4b80ace1d137 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -18,7 +18,7 @@
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/fsl_devices.h> 20#include <linux/fsl_devices.h>
21#include <linux/gpio.h> 21#include <linux/gpio/consumer.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -28,7 +28,6 @@
28#include <linux/of.h> 28#include <linux/of.h>
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/of_irq.h> 30#include <linux/of_irq.h>
31#include <linux/of_gpio.h>
32#include <linux/of_platform.h> 31#include <linux/of_platform.h>
33#include <linux/platform_device.h> 32#include <linux/platform_device.h>
34#include <linux/spi/spi.h> 33#include <linux/spi/spi.h>
@@ -481,32 +480,6 @@ static int fsl_spi_setup(struct spi_device *spi)
481 return retval; 480 return retval;
482 } 481 }
483 482
484 if (mpc8xxx_spi->type == TYPE_GRLIB) {
485 if (gpio_is_valid(spi->cs_gpio)) {
486 int desel;
487
488 retval = gpio_request(spi->cs_gpio,
489 dev_name(&spi->dev));
490 if (retval)
491 return retval;
492
493 desel = !(spi->mode & SPI_CS_HIGH);
494 retval = gpio_direction_output(spi->cs_gpio, desel);
495 if (retval) {
496 gpio_free(spi->cs_gpio);
497 return retval;
498 }
499 } else if (spi->cs_gpio != -ENOENT) {
500 if (spi->cs_gpio < 0)
501 return spi->cs_gpio;
502 return -EINVAL;
503 }
504 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
505 * indicates to use native chipselect if present, or allow for
506 * an always selected chip
507 */
508 }
509
510 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 483 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
511 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 484 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
512 485
@@ -515,12 +488,8 @@ static int fsl_spi_setup(struct spi_device *spi)
515 488
516static void fsl_spi_cleanup(struct spi_device *spi) 489static void fsl_spi_cleanup(struct spi_device *spi)
517{ 490{
518 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
519 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 491 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
520 492
521 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
522 gpio_free(spi->cs_gpio);
523
524 kfree(cs); 493 kfree(cs);
525 spi_set_ctldata(spi, NULL); 494 spi_set_ctldata(spi, NULL);
526} 495}
@@ -586,8 +555,8 @@ static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
586 u32 slvsel; 555 u32 slvsel;
587 u16 cs = spi->chip_select; 556 u16 cs = spi->chip_select;
588 557
589 if (gpio_is_valid(spi->cs_gpio)) { 558 if (spi->cs_gpiod) {
590 gpio_set_value(spi->cs_gpio, on); 559 gpiod_set_value(spi->cs_gpiod, on);
591 } else if (cs < mpc8xxx_spi->native_chipselects) { 560 } else if (cs < mpc8xxx_spi->native_chipselects) {
592 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel); 561 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
593 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 562 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
@@ -718,139 +687,19 @@ err:
718 687
719static void fsl_spi_cs_control(struct spi_device *spi, bool on) 688static void fsl_spi_cs_control(struct spi_device *spi, bool on)
720{ 689{
721 struct device *dev = spi->dev.parent->parent; 690 if (spi->cs_gpiod) {
722 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 691 gpiod_set_value(spi->cs_gpiod, on);
723 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
724 u16 cs = spi->chip_select;
725
726 if (cs < pinfo->ngpios) {
727 int gpio = pinfo->gpios[cs];
728 bool alow = pinfo->alow_flags[cs];
729
730 gpio_set_value(gpio, on ^ alow);
731 } else { 692 } else {
732 if (WARN_ON_ONCE(cs > pinfo->ngpios || !pinfo->immr_spi_cs)) 693 struct device *dev = spi->dev.parent->parent;
694 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
695 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
696
697 if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
733 return; 698 return;
734 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs); 699 iowrite32be(on ? SPI_BOOT_SEL_BIT : 0, pinfo->immr_spi_cs);
735 } 700 }
736} 701}
737 702
738static int of_fsl_spi_get_chipselects(struct device *dev)
739{
740 struct device_node *np = dev->of_node;
741 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
742 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
743 bool spisel_boot = IS_ENABLED(CONFIG_FSL_SOC) &&
744 of_property_read_bool(np, "fsl,spisel_boot");
745 int ngpios;
746 int i = 0;
747 int ret;
748
749 ngpios = of_gpio_count(np);
750 ngpios = max(ngpios, 0);
751 if (ngpios == 0 && !spisel_boot) {
752 /*
753 * SPI w/o chip-select line. One SPI device is still permitted
754 * though.
755 */
756 pdata->max_chipselect = 1;
757 return 0;
758 }
759
760 pinfo->ngpios = ngpios;
761 pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios),
762 GFP_KERNEL);
763 if (!pinfo->gpios)
764 return -ENOMEM;
765 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
766
767 pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags),
768 GFP_KERNEL);
769 if (!pinfo->alow_flags) {
770 ret = -ENOMEM;
771 goto err_alloc_flags;
772 }
773
774 for (; i < ngpios; i++) {
775 int gpio;
776 enum of_gpio_flags flags;
777
778 gpio = of_get_gpio_flags(np, i, &flags);
779 if (!gpio_is_valid(gpio)) {
780 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
781 ret = gpio;
782 goto err_loop;
783 }
784
785 ret = gpio_request(gpio, dev_name(dev));
786 if (ret) {
787 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
788 goto err_loop;
789 }
790
791 pinfo->gpios[i] = gpio;
792 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
793
794 ret = gpio_direction_output(pinfo->gpios[i],
795 pinfo->alow_flags[i]);
796 if (ret) {
797 dev_err(dev,
798 "can't set output direction for gpio #%d: %d\n",
799 i, ret);
800 goto err_loop;
801 }
802 }
803
804#if IS_ENABLED(CONFIG_FSL_SOC)
805 if (spisel_boot) {
806 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
807 if (!pinfo->immr_spi_cs) {
808 ret = -ENOMEM;
809 i = ngpios - 1;
810 goto err_loop;
811 }
812 }
813#endif
814
815 pdata->max_chipselect = ngpios + spisel_boot;
816 pdata->cs_control = fsl_spi_cs_control;
817
818 return 0;
819
820err_loop:
821 while (i >= 0) {
822 if (gpio_is_valid(pinfo->gpios[i]))
823 gpio_free(pinfo->gpios[i]);
824 i--;
825 }
826
827 kfree(pinfo->alow_flags);
828 pinfo->alow_flags = NULL;
829err_alloc_flags:
830 kfree(pinfo->gpios);
831 pinfo->gpios = NULL;
832 return ret;
833}
834
835static int of_fsl_spi_free_chipselects(struct device *dev)
836{
837 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
838 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
839 int i;
840
841 if (!pinfo->gpios)
842 return 0;
843
844 for (i = 0; i < pdata->max_chipselect; i++) {
845 if (gpio_is_valid(pinfo->gpios[i]))
846 gpio_free(pinfo->gpios[i]);
847 }
848
849 kfree(pinfo->gpios);
850 kfree(pinfo->alow_flags);
851 return 0;
852}
853
854static int of_fsl_spi_probe(struct platform_device *ofdev) 703static int of_fsl_spi_probe(struct platform_device *ofdev)
855{ 704{
856 struct device *dev = &ofdev->dev; 705 struct device *dev = &ofdev->dev;
@@ -866,9 +715,21 @@ static int of_fsl_spi_probe(struct platform_device *ofdev)
866 715
867 type = fsl_spi_get_type(&ofdev->dev); 716 type = fsl_spi_get_type(&ofdev->dev);
868 if (type == TYPE_FSL) { 717 if (type == TYPE_FSL) {
869 ret = of_fsl_spi_get_chipselects(dev); 718 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
870 if (ret) 719#if IS_ENABLED(CONFIG_FSL_SOC)
871 goto err; 720 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
721 bool spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
722
723 if (spisel_boot) {
724 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
725 if (!pinfo->immr_spi_cs) {
726 ret = -ENOMEM;
727 goto err;
728 }
729 }
730#endif
731
732 pdata->cs_control = fsl_spi_cs_control;
872 } 733 }
873 734
874 ret = of_address_to_resource(np, 0, &mem); 735 ret = of_address_to_resource(np, 0, &mem);
@@ -891,8 +752,6 @@ static int of_fsl_spi_probe(struct platform_device *ofdev)
891 752
892err: 753err:
893 irq_dispose_mapping(irq); 754 irq_dispose_mapping(irq);
894 if (type == TYPE_FSL)
895 of_fsl_spi_free_chipselects(dev);
896 return ret; 755 return ret;
897} 756}
898 757
@@ -902,8 +761,6 @@ static int of_fsl_spi_remove(struct platform_device *ofdev)
902 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 761 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
903 762
904 fsl_spi_cpm_free(mpc8xxx_spi); 763 fsl_spi_cpm_free(mpc8xxx_spi);
905 if (mpc8xxx_spi->type == TYPE_FSL)
906 of_fsl_spi_free_chipselects(&ofdev->dev);
907 return 0; 764 return 0;
908} 765}
909 766
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index 5f0b0d5bfef4..6f3d64a1a2b3 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -534,18 +534,14 @@ static int spi_geni_probe(struct platform_device *pdev)
534 int ret, irq; 534 int ret, irq;
535 struct spi_master *spi; 535 struct spi_master *spi;
536 struct spi_geni_master *mas; 536 struct spi_geni_master *mas;
537 struct resource *res;
538 void __iomem *base; 537 void __iomem *base;
539 struct clk *clk; 538 struct clk *clk;
540 539
541 irq = platform_get_irq(pdev, 0); 540 irq = platform_get_irq(pdev, 0);
542 if (irq < 0) { 541 if (irq < 0)
543 dev_err(&pdev->dev, "Err getting IRQ %d\n", irq);
544 return irq; 542 return irq;
545 }
546 543
547 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 544 base = devm_platform_ioremap_resource(pdev, 0);
548 base = devm_ioremap_resource(&pdev->dev, res);
549 if (IS_ERR(base)) 545 if (IS_ERR(base))
550 return PTR_ERR(base); 546 return PTR_ERR(base);
551 547
diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
index 9eb82150666e..1d3e23ec20a6 100644
--- a/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@ -290,10 +290,7 @@ static int spi_gpio_request(struct device *dev, struct spi_gpio *spi_gpio)
290 return PTR_ERR(spi_gpio->miso); 290 return PTR_ERR(spi_gpio->miso);
291 291
292 spi_gpio->sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW); 292 spi_gpio->sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW);
293 if (IS_ERR(spi_gpio->sck)) 293 return PTR_ERR_OR_ZERO(spi_gpio->sck);
294 return PTR_ERR(spi_gpio->sck);
295
296 return 0;
297} 294}
298 295
299#ifdef CONFIG_OF 296#ifdef CONFIG_OF
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
index 8f01858c0ae6..9dfe8b04e688 100644
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -819,22 +819,16 @@ static int lantiq_ssc_probe(struct platform_device *pdev)
819 } 819 }
820 820
821 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); 821 rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
822 if (rx_irq < 0) { 822 if (rx_irq < 0)
823 dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
824 return -ENXIO; 823 return -ENXIO;
825 }
826 824
827 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); 825 tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
828 if (tx_irq < 0) { 826 if (tx_irq < 0)
829 dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
830 return -ENXIO; 827 return -ENXIO;
831 }
832 828
833 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); 829 err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
834 if (err_irq < 0) { 830 if (err_irq < 0)
835 dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
836 return -ENXIO; 831 return -ENXIO;
837 }
838 832
839 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi)); 833 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
840 if (!master) 834 if (!master)
diff --git a/drivers/spi/spi-lp8841-rtc.c b/drivers/spi/spi-lp8841-rtc.c
index f50779fd329c..2d436541d6c2 100644
--- a/drivers/spi/spi-lp8841-rtc.c
+++ b/drivers/spi/spi-lp8841-rtc.c
@@ -185,7 +185,6 @@ spi_lp8841_rtc_probe(struct platform_device *pdev)
185 int ret; 185 int ret;
186 struct spi_master *master; 186 struct spi_master *master;
187 struct spi_lp8841_rtc *data; 187 struct spi_lp8841_rtc *data;
188 void *iomem;
189 188
190 master = spi_alloc_master(&pdev->dev, sizeof(*data)); 189 master = spi_alloc_master(&pdev->dev, sizeof(*data));
191 if (!master) 190 if (!master)
@@ -207,8 +206,7 @@ spi_lp8841_rtc_probe(struct platform_device *pdev)
207 206
208 data = spi_master_get_devdata(master); 207 data = spi_master_get_devdata(master);
209 208
210 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 209 data->iomem = devm_platform_ioremap_resource(pdev, 0);
211 data->iomem = devm_ioremap_resource(&pdev->dev, iomem);
212 ret = PTR_ERR_OR_ZERO(data->iomem); 210 ret = PTR_ERR_OR_ZERO(data->iomem);
213 if (ret) { 211 if (ret) {
214 dev_err(&pdev->dev, "failed to get IO address\n"); 212 dev_err(&pdev->dev, "failed to get IO address\n");
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 7fe4488ace57..f3f10443f9e2 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -503,7 +503,6 @@ static int meson_spicc_probe(struct platform_device *pdev)
503{ 503{
504 struct spi_master *master; 504 struct spi_master *master;
505 struct meson_spicc_device *spicc; 505 struct meson_spicc_device *spicc;
506 struct resource *res;
507 int ret, irq, rate; 506 int ret, irq, rate;
508 507
509 master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); 508 master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
@@ -517,8 +516,7 @@ static int meson_spicc_probe(struct platform_device *pdev)
517 spicc->pdev = pdev; 516 spicc->pdev = pdev;
518 platform_set_drvdata(pdev, spicc); 517 platform_set_drvdata(pdev, spicc);
519 518
520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 519 spicc->base = devm_platform_ioremap_resource(pdev, 0);
521 spicc->base = devm_ioremap_resource(&pdev->dev, res);
522 if (IS_ERR(spicc->base)) { 520 if (IS_ERR(spicc->base)) {
523 dev_err(&pdev->dev, "io resource mapping failed\n"); 521 dev_err(&pdev->dev, "io resource mapping failed\n");
524 ret = PTR_ERR(spicc->base); 522 ret = PTR_ERR(spicc->base);
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
index f7fe9b13d122..c7b039980291 100644
--- a/drivers/spi/spi-meson-spifc.c
+++ b/drivers/spi/spi-meson-spifc.c
@@ -286,7 +286,6 @@ static int meson_spifc_probe(struct platform_device *pdev)
286{ 286{
287 struct spi_master *master; 287 struct spi_master *master;
288 struct meson_spifc *spifc; 288 struct meson_spifc *spifc;
289 struct resource *res;
290 void __iomem *base; 289 void __iomem *base;
291 unsigned int rate; 290 unsigned int rate;
292 int ret = 0; 291 int ret = 0;
@@ -300,8 +299,7 @@ static int meson_spifc_probe(struct platform_device *pdev)
300 spifc = spi_master_get_devdata(master); 299 spifc = spi_master_get_devdata(master);
301 spifc->dev = &pdev->dev; 300 spifc->dev = &pdev->dev;
302 301
303 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 302 base = devm_platform_ioremap_resource(pdev, 0);
304 base = devm_ioremap_resource(spifc->dev, res);
305 if (IS_ERR(base)) { 303 if (IS_ERR(base)) {
306 ret = PTR_ERR(base); 304 ret = PTR_ERR(base);
307 goto out_err; 305 goto out_err;
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 45d8a7048b6c..6888a4dcff6d 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -17,6 +17,7 @@
17#include <linux/platform_data/spi-mt65xx.h> 17#include <linux/platform_data/spi-mt65xx.h>
18#include <linux/pm_runtime.h> 18#include <linux/pm_runtime.h>
19#include <linux/spi/spi.h> 19#include <linux/spi/spi.h>
20#include <linux/dma-mapping.h>
20 21
21#define SPI_CFG0_REG 0x0000 22#define SPI_CFG0_REG 0x0000
22#define SPI_CFG1_REG 0x0004 23#define SPI_CFG1_REG 0x0004
@@ -28,6 +29,8 @@
28#define SPI_STATUS0_REG 0x001c 29#define SPI_STATUS0_REG 0x001c
29#define SPI_PAD_SEL_REG 0x0024 30#define SPI_PAD_SEL_REG 0x0024
30#define SPI_CFG2_REG 0x0028 31#define SPI_CFG2_REG 0x0028
32#define SPI_TX_SRC_REG_64 0x002c
33#define SPI_RX_DST_REG_64 0x0030
31 34
32#define SPI_CFG0_SCK_HIGH_OFFSET 0 35#define SPI_CFG0_SCK_HIGH_OFFSET 0
33#define SPI_CFG0_SCK_LOW_OFFSET 8 36#define SPI_CFG0_SCK_LOW_OFFSET 8
@@ -73,6 +76,10 @@
73 76
74#define MTK_SPI_MAX_FIFO_SIZE 32U 77#define MTK_SPI_MAX_FIFO_SIZE 32U
75#define MTK_SPI_PACKET_SIZE 1024 78#define MTK_SPI_PACKET_SIZE 1024
79#define MTK_SPI_32BITS_MASK (0xffffffff)
80
81#define DMA_ADDR_EXT_BITS (36)
82#define DMA_ADDR_DEF_BITS (32)
76 83
77struct mtk_spi_compatible { 84struct mtk_spi_compatible {
78 bool need_pad_sel; 85 bool need_pad_sel;
@@ -80,6 +87,8 @@ struct mtk_spi_compatible {
80 bool must_tx; 87 bool must_tx;
81 /* some IC design adjust cfg register to enhance time accuracy */ 88 /* some IC design adjust cfg register to enhance time accuracy */
82 bool enhance_timing; 89 bool enhance_timing;
90 /* some IC support DMA addr extension */
91 bool dma_ext;
83}; 92};
84 93
85struct mtk_spi { 94struct mtk_spi {
@@ -102,6 +111,13 @@ static const struct mtk_spi_compatible mt2712_compat = {
102 .must_tx = true, 111 .must_tx = true,
103}; 112};
104 113
114static const struct mtk_spi_compatible mt6765_compat = {
115 .need_pad_sel = true,
116 .must_tx = true,
117 .enhance_timing = true,
118 .dma_ext = true,
119};
120
105static const struct mtk_spi_compatible mt7622_compat = { 121static const struct mtk_spi_compatible mt7622_compat = {
106 .must_tx = true, 122 .must_tx = true,
107 .enhance_timing = true, 123 .enhance_timing = true,
@@ -137,6 +153,9 @@ static const struct of_device_id mtk_spi_of_match[] = {
137 { .compatible = "mediatek,mt6589-spi", 153 { .compatible = "mediatek,mt6589-spi",
138 .data = (void *)&mtk_common_compat, 154 .data = (void *)&mtk_common_compat,
139 }, 155 },
156 { .compatible = "mediatek,mt6765-spi",
157 .data = (void *)&mt6765_compat,
158 },
140 { .compatible = "mediatek,mt7622-spi", 159 { .compatible = "mediatek,mt7622-spi",
141 .data = (void *)&mt7622_compat, 160 .data = (void *)&mt7622_compat,
142 }, 161 },
@@ -371,10 +390,25 @@ static void mtk_spi_setup_dma_addr(struct spi_master *master,
371{ 390{
372 struct mtk_spi *mdata = spi_master_get_devdata(master); 391 struct mtk_spi *mdata = spi_master_get_devdata(master);
373 392
374 if (mdata->tx_sgl) 393 if (mdata->tx_sgl) {
375 writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG); 394 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
376 if (mdata->rx_sgl) 395 mdata->base + SPI_TX_SRC_REG);
377 writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG); 396#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
397 if (mdata->dev_comp->dma_ext)
398 writel((u32)(xfer->tx_dma >> 32),
399 mdata->base + SPI_TX_SRC_REG_64);
400#endif
401 }
402
403 if (mdata->rx_sgl) {
404 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
405 mdata->base + SPI_RX_DST_REG);
406#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
407 if (mdata->dev_comp->dma_ext)
408 writel((u32)(xfer->rx_dma >> 32),
409 mdata->base + SPI_RX_DST_REG_64);
410#endif
411 }
378} 412}
379 413
380static int mtk_spi_fifo_transfer(struct spi_master *master, 414static int mtk_spi_fifo_transfer(struct spi_master *master,
@@ -586,7 +620,7 @@ static int mtk_spi_probe(struct platform_device *pdev)
586 struct mtk_spi *mdata; 620 struct mtk_spi *mdata;
587 const struct of_device_id *of_id; 621 const struct of_device_id *of_id;
588 struct resource *res; 622 struct resource *res;
589 int i, irq, ret; 623 int i, irq, ret, addr_bits;
590 624
591 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 625 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
592 if (!master) { 626 if (!master) {
@@ -664,7 +698,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
664 698
665 irq = platform_get_irq(pdev, 0); 699 irq = platform_get_irq(pdev, 0);
666 if (irq < 0) { 700 if (irq < 0) {
667 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
668 ret = irq; 701 ret = irq;
669 goto err_put_master; 702 goto err_put_master;
670 } 703 }
@@ -753,6 +786,15 @@ static int mtk_spi_probe(struct platform_device *pdev)
753 } 786 }
754 } 787 }
755 788
789 if (mdata->dev_comp->dma_ext)
790 addr_bits = DMA_ADDR_EXT_BITS;
791 else
792 addr_bits = DMA_ADDR_DEF_BITS;
793 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
794 if (ret)
795 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
796 addr_bits, ret);
797
756 return 0; 798 return 0;
757 799
758err_disable_runtime_pm: 800err_disable_runtime_pm:
diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
index ff85982464d2..2c3b7a2a1ec7 100644
--- a/drivers/spi/spi-mt7621.c
+++ b/drivers/spi/spi-mt7621.c
@@ -327,7 +327,6 @@ static int mt7621_spi_probe(struct platform_device *pdev)
327 struct spi_controller *master; 327 struct spi_controller *master;
328 struct mt7621_spi *rs; 328 struct mt7621_spi *rs;
329 void __iomem *base; 329 void __iomem *base;
330 struct resource *r;
331 int status = 0; 330 int status = 0;
332 struct clk *clk; 331 struct clk *clk;
333 int ret; 332 int ret;
@@ -336,8 +335,7 @@ static int mt7621_spi_probe(struct platform_device *pdev)
336 if (!match) 335 if (!match)
337 return -EINVAL; 336 return -EINVAL;
338 337
339 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 338 base = devm_platform_ioremap_resource(pdev, 0);
340 base = devm_ioremap_resource(&pdev->dev, r);
341 if (IS_ERR(base)) 339 if (IS_ERR(base))
342 return PTR_ERR(base); 340 return PTR_ERR(base);
343 341
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 7bf53cfc25d6..996c1c8a9c71 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -532,7 +532,6 @@ static int mxs_spi_probe(struct platform_device *pdev)
532 struct spi_master *master; 532 struct spi_master *master;
533 struct mxs_spi *spi; 533 struct mxs_spi *spi;
534 struct mxs_ssp *ssp; 534 struct mxs_ssp *ssp;
535 struct resource *iores;
536 struct clk *clk; 535 struct clk *clk;
537 void __iomem *base; 536 void __iomem *base;
538 int devid, clk_freq; 537 int devid, clk_freq;
@@ -545,12 +544,11 @@ static int mxs_spi_probe(struct platform_device *pdev)
545 */ 544 */
546 const int clk_freq_default = 160000000; 545 const int clk_freq_default = 160000000;
547 546
548 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
549 irq_err = platform_get_irq(pdev, 0); 547 irq_err = platform_get_irq(pdev, 0);
550 if (irq_err < 0) 548 if (irq_err < 0)
551 return irq_err; 549 return irq_err;
552 550
553 base = devm_ioremap_resource(&pdev->dev, iores); 551 base = devm_platform_ioremap_resource(pdev, 0);
554 if (IS_ERR(base)) 552 if (IS_ERR(base))
555 return PTR_ERR(base); 553 return PTR_ERR(base);
556 554
diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c
new file mode 100644
index 000000000000..cb52fd8008d0
--- /dev/null
+++ b/drivers/spi/spi-npcm-fiu.c
@@ -0,0 +1,769 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2019 Nuvoton Technology corporation.
3
4#include <linux/init.h>
5#include <linux/kernel.h>
6#include <linux/device.h>
7#include <linux/module.h>
8#include <linux/ioport.h>
9#include <linux/clk.h>
10#include <linux/platform_device.h>
11#include <linux/io.h>
12#include <linux/vmalloc.h>
13#include <linux/regmap.h>
14#include <linux/of_device.h>
15#include <linux/spi/spi-mem.h>
16#include <linux/mfd/syscon.h>
17
18/* NPCM7xx GCR module */
19#define NPCM7XX_INTCR3_OFFSET 0x9C
20#define NPCM7XX_INTCR3_FIU_FIX BIT(6)
21
22/* Flash Interface Unit (FIU) Registers */
23#define NPCM_FIU_DRD_CFG 0x00
24#define NPCM_FIU_DWR_CFG 0x04
25#define NPCM_FIU_UMA_CFG 0x08
26#define NPCM_FIU_UMA_CTS 0x0C
27#define NPCM_FIU_UMA_CMD 0x10
28#define NPCM_FIU_UMA_ADDR 0x14
29#define NPCM_FIU_PRT_CFG 0x18
30#define NPCM_FIU_UMA_DW0 0x20
31#define NPCM_FIU_UMA_DW1 0x24
32#define NPCM_FIU_UMA_DW2 0x28
33#define NPCM_FIU_UMA_DW3 0x2C
34#define NPCM_FIU_UMA_DR0 0x30
35#define NPCM_FIU_UMA_DR1 0x34
36#define NPCM_FIU_UMA_DR2 0x38
37#define NPCM_FIU_UMA_DR3 0x3C
38#define NPCM_FIU_MAX_REG_LIMIT 0x80
39
40/* FIU Direct Read Configuration Register */
41#define NPCM_FIU_DRD_CFG_LCK BIT(31)
42#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)
43#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)
44#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)
45#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)
46#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)
47#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16
48#define NPCM_FIU_DRD_DBW_SHIFT 12
49#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8
50
51/* FIU Direct Write Configuration Register */
52#define NPCM_FIU_DWR_CFG_LCK BIT(31)
53#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)
54#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)
55#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)
56#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)
57#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)
58#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16
59#define NPCM_FIU_DWR_ABPCK_SHIFT 10
60#define NPCM_FIU_DWR_DBPCK_SHIFT 8
61
62/* FIU UMA Configuration Register */
63#define NPCM_FIU_UMA_CFG_LCK BIT(31)
64#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30)
65#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)
66#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)
67#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)
68#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)
69#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10)
70#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)
71#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)
72#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)
73#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)
74#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)
75#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2
76#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4
77#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6
78#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8
79#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11
80#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16
81#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21
82#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24
83
84/* FIU UMA Control and Status Register */
85#define NPCM_FIU_UMA_CTS_RDYIE BIT(25)
86#define NPCM_FIU_UMA_CTS_RDYST BIT(24)
87#define NPCM_FIU_UMA_CTS_SW_CS BIT(16)
88#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)
89#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0)
90#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8
91
92/* FIU UMA Command Register */
93#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)
94#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)
95#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)
96#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)
97
98/* FIU UMA Address Register */
99#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)
100#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)
101#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)
102#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)
103#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)
104
105/* FIU UMA Write Data Bytes 0-3 Register */
106#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)
107#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)
108#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)
109#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)
110
111/* FIU UMA Write Data Bytes 4-7 Register */
112#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)
113#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)
114#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)
115#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)
116
117/* FIU UMA Write Data Bytes 8-11 Register */
118#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)
119#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)
120#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)
121#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)
122
123/* FIU UMA Write Data Bytes 12-15 Register */
124#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)
125#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)
126#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)
127#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)
128
129/* FIU UMA Read Data Bytes 0-3 Register */
130#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)
131#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)
132#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)
133#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)
134
135/* FIU UMA Read Data Bytes 4-7 Register */
136#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)
137#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)
138#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)
139#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)
140
141/* FIU UMA Read Data Bytes 8-11 Register */
142#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)
143#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)
144#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)
145#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)
146
147/* FIU UMA Read Data Bytes 12-15 Register */
148#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)
149#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)
150#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)
151#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)
152
153/* FIU Read Mode */
154enum {
155 DRD_SINGLE_WIRE_MODE = 0,
156 DRD_DUAL_IO_MODE = 1,
157 DRD_QUAD_IO_MODE = 2,
158 DRD_SPI_X_MODE = 3,
159};
160
161enum {
162 DWR_ABPCK_BIT_PER_CLK = 0,
163 DWR_ABPCK_2_BIT_PER_CLK = 1,
164 DWR_ABPCK_4_BIT_PER_CLK = 2,
165};
166
167enum {
168 DWR_DBPCK_BIT_PER_CLK = 0,
169 DWR_DBPCK_2_BIT_PER_CLK = 1,
170 DWR_DBPCK_4_BIT_PER_CLK = 2,
171};
172
173#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000
174#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000
175
176#define MAP_SIZE_128MB 0x8000000
177#define MAP_SIZE_16MB 0x1000000
178#define MAP_SIZE_8MB 0x800000
179
180#define NUM_BITS_IN_BYTE 8
181#define FIU_DRD_MAX_DUMMY_NUMBER 3
182#define NPCM_MAX_CHIP_NUM 4
183#define CHUNK_SIZE 16
184#define UMA_MICRO_SEC_TIMEOUT 150
185
186enum {
187 FIU0 = 0,
188 FIU3,
189 FIUX,
190};
191
192struct npcm_fiu_info {
193 char *name;
194 u32 fiu_id;
195 u32 max_map_size;
196 u32 max_cs;
197};
198
199struct fiu_data {
200 const struct npcm_fiu_info *npcm_fiu_data_info;
201 int fiu_max;
202};
203
204static const struct npcm_fiu_info npxm7xx_fiu_info[] = {
205 {.name = "FIU0", .fiu_id = FIU0,
206 .max_map_size = MAP_SIZE_128MB, .max_cs = 2},
207 {.name = "FIU3", .fiu_id = FIU3,
208 .max_map_size = MAP_SIZE_128MB, .max_cs = 4},
209 {.name = "FIUX", .fiu_id = FIUX,
210 .max_map_size = MAP_SIZE_16MB, .max_cs = 2} };
211
212static const struct fiu_data npxm7xx_fiu_data = {
213 .npcm_fiu_data_info = npxm7xx_fiu_info,
214 .fiu_max = 3,
215};
216
217struct npcm_fiu_spi;
218
219struct npcm_fiu_chip {
220 void __iomem *flash_region_mapped_ptr;
221 struct npcm_fiu_spi *fiu;
222 unsigned long clkrate;
223 u32 chipselect;
224};
225
226struct npcm_fiu_spi {
227 struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM];
228 const struct npcm_fiu_info *info;
229 struct spi_mem_op drd_op;
230 struct resource *res_mem;
231 struct regmap *regmap;
232 unsigned long clkrate;
233 struct device *dev;
234 struct clk *clk;
235 bool spix_mode;
236};
237
238static const struct regmap_config npcm_mtd_regmap_config = {
239 .reg_bits = 32,
240 .val_bits = 32,
241 .reg_stride = 4,
242 .max_register = NPCM_FIU_MAX_REG_LIMIT,
243};
244
245static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
246 const struct spi_mem_op *op)
247{
248 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
249 NPCM_FIU_DRD_CFG_ACCTYPE,
250 ilog2(op->addr.buswidth) <<
251 NPCM_FIU_DRD_ACCTYPE_SHIFT);
252 fiu->drd_op.addr.buswidth = op->addr.buswidth;
253 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
254 NPCM_FIU_DRD_CFG_DBW,
255 ((op->dummy.nbytes * ilog2(op->addr.buswidth))
256 / NUM_BITS_IN_BYTE) << NPCM_FIU_DRD_DBW_SHIFT);
257 fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
258 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
259 NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);
260 fiu->drd_op.cmd.opcode = op->cmd.opcode;
261 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
262 NPCM_FIU_DRD_CFG_ADDSIZ,
263 (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT);
264 fiu->drd_op.addr.nbytes = op->addr.nbytes;
265}
266
267static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,
268 u64 offs, size_t len, void *buf)
269{
270 struct npcm_fiu_spi *fiu =
271 spi_controller_get_devdata(desc->mem->spi->master);
272 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
273 void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr +
274 offs);
275 u8 *buf_rx = buf;
276 u32 i;
277
278 if (fiu->spix_mode) {
279 for (i = 0 ; i < len ; i++)
280 *(buf_rx + i) = ioread8(src + i);
281 } else {
282 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
283 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
284 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
285 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
286 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
287
288 memcpy_fromio(buf_rx, src, len);
289 }
290
291 return len;
292}
293
294static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc,
295 u64 offs, size_t len, const void *buf)
296{
297 struct npcm_fiu_spi *fiu =
298 spi_controller_get_devdata(desc->mem->spi->master);
299 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
300 void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr +
301 offs);
302 const u8 *buf_tx = buf;
303 u32 i;
304
305 if (fiu->spix_mode)
306 for (i = 0 ; i < len ; i++)
307 iowrite8(*(buf_tx + i), dst + i);
308 else
309 memcpy_toio(dst, buf_tx, len);
310
311 return len;
312}
313
314static int npcm_fiu_uma_read(struct spi_mem *mem,
315 const struct spi_mem_op *op, u32 addr,
316 bool is_address_size, u8 *data, u32 data_size)
317{
318 struct npcm_fiu_spi *fiu =
319 spi_controller_get_devdata(mem->spi->master);
320 u32 uma_cfg = BIT(10);
321 u32 data_reg[4];
322 int ret;
323 u32 val;
324 u32 i;
325
326 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
327 NPCM_FIU_UMA_CTS_DEV_NUM,
328 (mem->spi->chip_select <<
329 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
330 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
331 NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode);
332
333 if (is_address_size) {
334 uma_cfg |= ilog2(op->cmd.buswidth);
335 uma_cfg |= ilog2(op->addr.buswidth)
336 << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
337 uma_cfg |= ilog2(op->dummy.buswidth)
338 << NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
339 uma_cfg |= ilog2(op->data.buswidth)
340 << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;
341 uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;
342 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
343 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);
344 } else {
345 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
346 }
347
348 uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT;
349 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
350 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
351 NPCM_FIU_UMA_CTS_EXEC_DONE,
352 NPCM_FIU_UMA_CTS_EXEC_DONE);
353 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
354 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
355 UMA_MICRO_SEC_TIMEOUT);
356 if (ret)
357 return ret;
358
359 if (data_size) {
360 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
361 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),
362 &data_reg[i]);
363 memcpy(data, data_reg, data_size);
364 }
365
366 return 0;
367}
368
369static int npcm_fiu_uma_write(struct spi_mem *mem,
370 const struct spi_mem_op *op, u8 cmd,
371 bool is_address_size, u8 *data, u32 data_size)
372{
373 struct npcm_fiu_spi *fiu =
374 spi_controller_get_devdata(mem->spi->master);
375 u32 uma_cfg = BIT(10);
376 u32 data_reg[4] = {0};
377 u32 val;
378 u32 i;
379
380 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
381 NPCM_FIU_UMA_CTS_DEV_NUM,
382 (mem->spi->chip_select <<
383 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
384
385 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
386 NPCM_FIU_UMA_CMD_CMD, cmd);
387
388 if (data_size) {
389 memcpy(data_reg, data, data_size);
390 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
391 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),
392 data_reg[i]);
393 }
394
395 if (is_address_size) {
396 uma_cfg |= ilog2(op->cmd.buswidth);
397 uma_cfg |= ilog2(op->addr.buswidth) <<
398 NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
399 uma_cfg |= ilog2(op->data.buswidth) <<
400 NPCM_FIU_UMA_CFG_WDBPCK_SHIFT;
401 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
402 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);
403 } else {
404 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
405 }
406
407 uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT);
408 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
409
410 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
411 NPCM_FIU_UMA_CTS_EXEC_DONE,
412 NPCM_FIU_UMA_CTS_EXEC_DONE);
413
414 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
415 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
416 UMA_MICRO_SEC_TIMEOUT);
417}
418
419static int npcm_fiu_manualwrite(struct spi_mem *mem,
420 const struct spi_mem_op *op)
421{
422 struct npcm_fiu_spi *fiu =
423 spi_controller_get_devdata(mem->spi->master);
424 u8 *data = (u8 *)op->data.buf.out;
425 u32 num_data_chunks;
426 u32 remain_data;
427 u32 idx = 0;
428 int ret;
429
430 num_data_chunks = op->data.nbytes / CHUNK_SIZE;
431 remain_data = op->data.nbytes % CHUNK_SIZE;
432
433 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
434 NPCM_FIU_UMA_CTS_DEV_NUM,
435 (mem->spi->chip_select <<
436 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
437 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
438 NPCM_FIU_UMA_CTS_SW_CS, 0);
439
440 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0);
441 if (ret)
442 return ret;
443
444 /* Starting the data writing loop in multiples of 8 */
445 for (idx = 0; idx < num_data_chunks; ++idx) {
446 ret = npcm_fiu_uma_write(mem, op, data[0], false,
447 &data[1], CHUNK_SIZE - 1);
448 if (ret)
449 return ret;
450
451 data += CHUNK_SIZE;
452 }
453
454 /* Handling chunk remains */
455 if (remain_data > 0) {
456 ret = npcm_fiu_uma_write(mem, op, data[0], false,
457 &data[1], remain_data - 1);
458 if (ret)
459 return ret;
460 }
461
462 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
463 NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS);
464
465 return 0;
466}
467
468static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op)
469{
470 u8 *data = op->data.buf.in;
471 int i, readlen, currlen;
472 u8 *buf_ptr;
473 u32 addr;
474 int ret;
475
476 i = 0;
477 currlen = op->data.nbytes;
478
479 do {
480 addr = ((u32)op->addr.val + i);
481 if (currlen < 16)
482 readlen = currlen;
483 else
484 readlen = 16;
485
486 buf_ptr = data + i;
487 ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr,
488 readlen);
489 if (ret)
490 return ret;
491
492 i += readlen;
493 currlen -= 16;
494 } while (currlen > 0);
495
496 return 0;
497}
498
499static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)
500{
501 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,
502 NPCM_FIU_DWR_16_BYTE_BURST);
503 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
504 NPCM_FIU_DWR_CFG_ABPCK,
505 DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT);
506 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
507 NPCM_FIU_DWR_CFG_DBPCK,
508 DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT);
509}
510
511static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
512{
513 u32 rx_dummy = 0;
514
515 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,
516 NPCM_FIU_DRD_16_BYTE_BURST);
517 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
518 NPCM_FIU_DRD_CFG_ACCTYPE,
519 DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT);
520 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
521 NPCM_FIU_DRD_CFG_DBW,
522 rx_dummy << NPCM_FIU_DRD_DBW_SHIFT);
523}
524
525static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
526{
527 struct npcm_fiu_spi *fiu =
528 spi_controller_get_devdata(mem->spi->master);
529 struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];
530 int ret = 0;
531 u8 *buf;
532
533 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
534 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
535 op->dummy.buswidth, op->data.buswidth, op->addr.val,
536 op->data.nbytes);
537
538 if (fiu->spix_mode || op->addr.nbytes > 4)
539 return -ENOTSUPP;
540
541 if (fiu->clkrate != chip->clkrate) {
542 ret = clk_set_rate(fiu->clk, chip->clkrate);
543 if (ret < 0)
544 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n",
545 chip->clkrate, fiu->clkrate);
546 else
547 fiu->clkrate = chip->clkrate;
548 }
549
550 if (op->data.dir == SPI_MEM_DATA_IN) {
551 if (!op->addr.nbytes) {
552 buf = op->data.buf.in;
553 ret = npcm_fiu_uma_read(mem, op, op->addr.val, false,
554 buf, op->data.nbytes);
555 } else {
556 ret = npcm_fiu_read(mem, op);
557 }
558 } else {
559 if (!op->addr.nbytes && !op->data.nbytes)
560 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
561 NULL, 0);
562 if (op->addr.nbytes && !op->data.nbytes) {
563 int i;
564 u8 buf_addr[4];
565 u32 addr = op->addr.val;
566
567 for (i = op->addr.nbytes - 1; i >= 0; i--) {
568 buf_addr[i] = addr & 0xff;
569 addr >>= 8;
570 }
571 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
572 buf_addr, op->addr.nbytes);
573 }
574 if (!op->addr.nbytes && op->data.nbytes)
575 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false,
576 (u8 *)op->data.buf.out,
577 op->data.nbytes);
578 if (op->addr.nbytes && op->data.nbytes)
579 ret = npcm_fiu_manualwrite(mem, op);
580 }
581
582 return ret;
583}
584
585static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
586{
587 struct npcm_fiu_spi *fiu =
588 spi_controller_get_devdata(desc->mem->spi->master);
589 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];
590 struct regmap *gcr_regmap;
591
592 if (!fiu->res_mem) {
593 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");
594 desc->nodirmap = true;
595 return 0;
596 }
597
598 if (!fiu->spix_mode &&
599 desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
600 desc->nodirmap = true;
601 return 0;
602 }
603
604 if (!chip->flash_region_mapped_ptr) {
605 chip->flash_region_mapped_ptr =
606 devm_ioremap_nocache(fiu->dev, (fiu->res_mem->start +
607 (fiu->info->max_map_size *
608 desc->mem->spi->chip_select)),
609 (u32)desc->info.length);
610 if (!chip->flash_region_mapped_ptr) {
611 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");
612 desc->nodirmap = true;
613 return 0;
614 }
615 }
616
617 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {
618 gcr_regmap =
619 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
620 if (IS_ERR(gcr_regmap)) {
621 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");
622 desc->nodirmap = true;
623 return 0;
624 }
625 regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,
626 NPCM7XX_INTCR3_FIU_FIX,
627 NPCM7XX_INTCR3_FIU_FIX);
628 }
629
630 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
631 if (!fiu->spix_mode)
632 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
633 else
634 npcm_fiux_set_direct_rd(fiu);
635
636 } else {
637 npcm_fiux_set_direct_wr(fiu);
638 }
639
640 return 0;
641}
642
643static int npcm_fiu_setup(struct spi_device *spi)
644{
645 struct spi_controller *ctrl = spi->master;
646 struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
647 struct npcm_fiu_chip *chip;
648
649 chip = &fiu->chip[spi->chip_select];
650 chip->fiu = fiu;
651 chip->chipselect = spi->chip_select;
652 chip->clkrate = spi->max_speed_hz;
653
654 fiu->clkrate = clk_get_rate(fiu->clk);
655
656 return 0;
657}
658
659static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
660 .exec_op = npcm_fiu_exec_op,
661 .dirmap_create = npcm_fiu_dirmap_create,
662 .dirmap_read = npcm_fiu_direct_read,
663 .dirmap_write = npcm_fiu_direct_write,
664};
665
666static const struct of_device_id npcm_fiu_dt_ids[] = {
667 { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },
668 { /* sentinel */ }
669};
670
671static int npcm_fiu_probe(struct platform_device *pdev)
672{
673 const struct fiu_data *fiu_data_match;
674 const struct of_device_id *match;
675 struct device *dev = &pdev->dev;
676 struct spi_controller *ctrl;
677 struct npcm_fiu_spi *fiu;
678 void __iomem *regbase;
679 struct resource *res;
680 int ret;
681 int id;
682
683 ctrl = spi_alloc_master(dev, sizeof(*fiu));
684 if (!ctrl)
685 return -ENOMEM;
686
687 fiu = spi_controller_get_devdata(ctrl);
688
689 match = of_match_device(npcm_fiu_dt_ids, dev);
690 if (!match || !match->data) {
691 dev_err(dev, "No compatible OF match\n");
692 return -ENODEV;
693 }
694
695 fiu_data_match = match->data;
696 id = of_alias_get_id(dev->of_node, "fiu");
697 if (id < 0 || id >= fiu_data_match->fiu_max) {
698 dev_err(dev, "Invalid platform device id: %d\n", id);
699 return -EINVAL;
700 }
701
702 fiu->info = &fiu_data_match->npcm_fiu_data_info[id];
703
704 platform_set_drvdata(pdev, fiu);
705 fiu->dev = dev;
706
707 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
708 regbase = devm_ioremap_resource(dev, res);
709 if (IS_ERR(regbase))
710 return PTR_ERR(regbase);
711
712 fiu->regmap = devm_regmap_init_mmio(dev, regbase,
713 &npcm_mtd_regmap_config);
714 if (IS_ERR(fiu->regmap)) {
715 dev_err(dev, "Failed to create regmap\n");
716 return PTR_ERR(fiu->regmap);
717 }
718
719 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
720 "memory");
721 fiu->clk = devm_clk_get(dev, NULL);
722 if (IS_ERR(fiu->clk))
723 return PTR_ERR(fiu->clk);
724
725 fiu->spix_mode = of_property_read_bool(dev->of_node,
726 "nuvoton,spix-mode");
727
728 platform_set_drvdata(pdev, fiu);
729 clk_prepare_enable(fiu->clk);
730
731 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
732 | SPI_TX_DUAL | SPI_TX_QUAD;
733 ctrl->setup = npcm_fiu_setup;
734 ctrl->bus_num = -1;
735 ctrl->mem_ops = &npcm_fiu_mem_ops;
736 ctrl->num_chipselect = fiu->info->max_cs;
737 ctrl->dev.of_node = dev->of_node;
738
739 ret = devm_spi_register_master(dev, ctrl);
740 if (ret)
741 return ret;
742
743 return 0;
744}
745
746static int npcm_fiu_remove(struct platform_device *pdev)
747{
748 struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);
749
750 clk_disable_unprepare(fiu->clk);
751 return 0;
752}
753
754MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids);
755
756static struct platform_driver npcm_fiu_driver = {
757 .driver = {
758 .name = "NPCM-FIU",
759 .bus = &platform_bus_type,
760 .of_match_table = npcm_fiu_dt_ids,
761 },
762 .probe = npcm_fiu_probe,
763 .remove = npcm_fiu_remove,
764};
765module_platform_driver(npcm_fiu_driver);
766
767MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver");
768MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
769MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-npcm-pspi.c b/drivers/spi/spi-npcm-pspi.c
index 734a2b956959..b191d57d1dc0 100644
--- a/drivers/spi/spi-npcm-pspi.c
+++ b/drivers/spi/spi-npcm-pspi.c
@@ -341,7 +341,6 @@ static int npcm_pspi_probe(struct platform_device *pdev)
341{ 341{
342 struct npcm_pspi *priv; 342 struct npcm_pspi *priv;
343 struct spi_master *master; 343 struct spi_master *master;
344 struct resource *res;
345 unsigned long clk_hz; 344 unsigned long clk_hz;
346 struct device_node *np = pdev->dev.of_node; 345 struct device_node *np = pdev->dev.of_node;
347 int num_cs, i; 346 int num_cs, i;
@@ -368,8 +367,7 @@ static int npcm_pspi_probe(struct platform_device *pdev)
368 priv->is_save_param = false; 367 priv->is_save_param = false;
369 priv->id = pdev->id; 368 priv->id = pdev->id;
370 369
371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 370 priv->base = devm_platform_ioremap_resource(pdev, 0);
372 priv->base = devm_ioremap_resource(&pdev->dev, res);
373 if (IS_ERR(priv->base)) { 371 if (IS_ERR(priv->base)) {
374 ret = PTR_ERR(priv->base); 372 ret = PTR_ERR(priv->base);
375 goto out_master_put; 373 goto out_master_put;
@@ -388,7 +386,6 @@ static int npcm_pspi_probe(struct platform_device *pdev)
388 386
389 irq = platform_get_irq(pdev, 0); 387 irq = platform_get_irq(pdev, 0);
390 if (irq < 0) { 388 if (irq < 0) {
391 dev_err(&pdev->dev, "failed to get IRQ\n");
392 ret = irq; 389 ret = irq;
393 goto out_disable_clk; 390 goto out_disable_clk;
394 } 391 }
diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c
index 37e2034ad4d5..61400358f4be 100644
--- a/drivers/spi/spi-nuc900.c
+++ b/drivers/spi/spi-nuc900.c
@@ -327,7 +327,6 @@ static int nuc900_spi_probe(struct platform_device *pdev)
327{ 327{
328 struct nuc900_spi *hw; 328 struct nuc900_spi *hw;
329 struct spi_master *master; 329 struct spi_master *master;
330 struct resource *res;
331 int err = 0; 330 int err = 0;
332 331
333 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi)); 332 master = spi_alloc_master(&pdev->dev, sizeof(struct nuc900_spi));
@@ -358,8 +357,7 @@ static int nuc900_spi_probe(struct platform_device *pdev)
358 hw->bitbang.chipselect = nuc900_spi_chipsel; 357 hw->bitbang.chipselect = nuc900_spi_chipsel;
359 hw->bitbang.txrx_bufs = nuc900_spi_txrx; 358 hw->bitbang.txrx_bufs = nuc900_spi_txrx;
360 359
361 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 360 hw->regs = devm_platform_ioremap_resource(pdev, 0);
362 hw->regs = devm_ioremap_resource(&pdev->dev, res);
363 if (IS_ERR(hw->regs)) { 361 if (IS_ERR(hw->regs)) {
364 err = PTR_ERR(hw->regs); 362 err = PTR_ERR(hw->regs);
365 goto err_pdata; 363 goto err_pdata;
@@ -367,7 +365,6 @@ static int nuc900_spi_probe(struct platform_device *pdev)
367 365
368 hw->irq = platform_get_irq(pdev, 0); 366 hw->irq = platform_get_irq(pdev, 0);
369 if (hw->irq < 0) { 367 if (hw->irq < 0) {
370 dev_err(&pdev->dev, "No IRQ specified\n");
371 err = -ENOENT; 368 err = -ENOENT;
372 goto err_pdata; 369 goto err_pdata;
373 } 370 }
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 8894f98cc99c..501b923f2c27 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -1007,10 +1007,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
1007 1007
1008 /* find the irq */ 1008 /* find the irq */
1009 ret = platform_get_irq(pdev, 0); 1009 ret = platform_get_irq(pdev, 0);
1010 if (ret < 0) { 1010 if (ret < 0)
1011 dev_err(dev, "failed to get the irq: %d\n", ret);
1012 goto err_disable_clk; 1011 goto err_disable_clk;
1013 }
1014 1012
1015 ret = devm_request_irq(dev, ret, 1013 ret = devm_request_irq(dev, ret,
1016 nxp_fspi_irq_handler, 0, pdev->name, f); 1014 nxp_fspi_irq_handler, 0, pdev->name, f);
diff --git a/drivers/spi/spi-oc-tiny.c b/drivers/spi/spi-oc-tiny.c
index bbc4ba66571f..e2331eb7b47a 100644
--- a/drivers/spi/spi-oc-tiny.c
+++ b/drivers/spi/spi-oc-tiny.c
@@ -240,7 +240,6 @@ static int tiny_spi_probe(struct platform_device *pdev)
240 struct tiny_spi_platform_data *platp = dev_get_platdata(&pdev->dev); 240 struct tiny_spi_platform_data *platp = dev_get_platdata(&pdev->dev);
241 struct tiny_spi *hw; 241 struct tiny_spi *hw;
242 struct spi_master *master; 242 struct spi_master *master;
243 struct resource *res;
244 unsigned int i; 243 unsigned int i;
245 int err = -ENODEV; 244 int err = -ENODEV;
246 245
@@ -264,8 +263,7 @@ static int tiny_spi_probe(struct platform_device *pdev)
264 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs; 263 hw->bitbang.txrx_bufs = tiny_spi_txrx_bufs;
265 264
266 /* find and map our resources */ 265 /* find and map our resources */
267 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 266 hw->base = devm_platform_ioremap_resource(pdev, 0);
268 hw->base = devm_ioremap_resource(&pdev->dev, res);
269 if (IS_ERR(hw->base)) { 267 if (IS_ERR(hw->base)) {
270 err = PTR_ERR(hw->base); 268 err = PTR_ERR(hw->base);
271 goto exit; 269 goto exit;
diff --git a/drivers/spi/spi-pic32-sqi.c b/drivers/spi/spi-pic32-sqi.c
index b635526ad414..86ad17597f5f 100644
--- a/drivers/spi/spi-pic32-sqi.c
+++ b/drivers/spi/spi-pic32-sqi.c
@@ -570,7 +570,6 @@ static int pic32_sqi_probe(struct platform_device *pdev)
570{ 570{
571 struct spi_master *master; 571 struct spi_master *master;
572 struct pic32_sqi *sqi; 572 struct pic32_sqi *sqi;
573 struct resource *reg;
574 int ret; 573 int ret;
575 574
576 master = spi_alloc_master(&pdev->dev, sizeof(*sqi)); 575 master = spi_alloc_master(&pdev->dev, sizeof(*sqi));
@@ -580,8 +579,7 @@ static int pic32_sqi_probe(struct platform_device *pdev)
580 sqi = spi_master_get_devdata(master); 579 sqi = spi_master_get_devdata(master);
581 sqi->master = master; 580 sqi->master = master;
582 581
583 reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 582 sqi->regs = devm_platform_ioremap_resource(pdev, 0);
584 sqi->regs = devm_ioremap_resource(&pdev->dev, reg);
585 if (IS_ERR(sqi->regs)) { 583 if (IS_ERR(sqi->regs)) {
586 ret = PTR_ERR(sqi->regs); 584 ret = PTR_ERR(sqi->regs);
587 goto err_free_master; 585 goto err_free_master;
@@ -590,7 +588,6 @@ static int pic32_sqi_probe(struct platform_device *pdev)
590 /* irq */ 588 /* irq */
591 sqi->irq = platform_get_irq(pdev, 0); 589 sqi->irq = platform_get_irq(pdev, 0);
592 if (sqi->irq < 0) { 590 if (sqi->irq < 0) {
593 dev_err(&pdev->dev, "no irq found\n");
594 ret = sqi->irq; 591 ret = sqi->irq;
595 goto err_free_master; 592 goto err_free_master;
596 } 593 }
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
index 10cebeaa1e6b..69f517ec59c6 100644
--- a/drivers/spi/spi-pic32.c
+++ b/drivers/spi/spi-pic32.c
@@ -711,22 +711,16 @@ static int pic32_spi_hw_probe(struct platform_device *pdev,
711 711
712 /* get irq resources: err-irq, rx-irq, tx-irq */ 712 /* get irq resources: err-irq, rx-irq, tx-irq */
713 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault"); 713 pic32s->fault_irq = platform_get_irq_byname(pdev, "fault");
714 if (pic32s->fault_irq < 0) { 714 if (pic32s->fault_irq < 0)
715 dev_err(&pdev->dev, "fault-irq not found\n");
716 return pic32s->fault_irq; 715 return pic32s->fault_irq;
717 }
718 716
719 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx"); 717 pic32s->rx_irq = platform_get_irq_byname(pdev, "rx");
720 if (pic32s->rx_irq < 0) { 718 if (pic32s->rx_irq < 0)
721 dev_err(&pdev->dev, "rx-irq not found\n");
722 return pic32s->rx_irq; 719 return pic32s->rx_irq;
723 }
724 720
725 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx"); 721 pic32s->tx_irq = platform_get_irq_byname(pdev, "tx");
726 if (pic32s->tx_irq < 0) { 722 if (pic32s->tx_irq < 0)
727 dev_err(&pdev->dev, "tx-irq not found\n");
728 return pic32s->tx_irq; 723 return pic32s->tx_irq;
729 }
730 724
731 /* get clock */ 725 /* get clock */
732 pic32s->clk = devm_clk_get(&pdev->dev, "mck0"); 726 pic32s->clk = devm_clk_get(&pdev->dev, "mck0");
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index e0f061139c8f..250fd60e1678 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -424,7 +424,6 @@ static int qcom_qspi_probe(struct platform_device *pdev)
424{ 424{
425 int ret; 425 int ret;
426 struct device *dev; 426 struct device *dev;
427 struct resource *res;
428 struct spi_master *master; 427 struct spi_master *master;
429 struct qcom_qspi *ctrl; 428 struct qcom_qspi *ctrl;
430 429
@@ -440,8 +439,7 @@ static int qcom_qspi_probe(struct platform_device *pdev)
440 439
441 spin_lock_init(&ctrl->lock); 440 spin_lock_init(&ctrl->lock);
442 ctrl->dev = dev; 441 ctrl->dev = dev;
443 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 442 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
444 ctrl->base = devm_ioremap_resource(dev, res);
445 if (IS_ERR(ctrl->base)) { 443 if (IS_ERR(ctrl->base)) {
446 ret = PTR_ERR(ctrl->base); 444 ret = PTR_ERR(ctrl->base);
447 goto exit_probe_master_put; 445 goto exit_probe_master_put;
@@ -454,10 +452,8 @@ static int qcom_qspi_probe(struct platform_device *pdev)
454 goto exit_probe_master_put; 452 goto exit_probe_master_put;
455 453
456 ret = platform_get_irq(pdev, 0); 454 ret = platform_get_irq(pdev, 0);
457 if (ret < 0) { 455 if (ret < 0)
458 dev_err(dev, "Failed to get irq %d\n", ret);
459 goto exit_probe_master_put; 456 goto exit_probe_master_put;
460 }
461 ret = devm_request_irq(dev, ret, qcom_qspi_irq, 457 ret = devm_request_irq(dev, ret, qcom_qspi_irq,
462 IRQF_TRIGGER_HIGH, dev_name(dev), ctrl); 458 IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
463 if (ret) { 459 if (ret) {
diff --git a/drivers/spi/spi-rb4xx.c b/drivers/spi/spi-rb4xx.c
index 51f03d977ad6..4c9620e0d18c 100644
--- a/drivers/spi/spi-rb4xx.c
+++ b/drivers/spi/spi-rb4xx.c
@@ -135,12 +135,10 @@ static int rb4xx_spi_probe(struct platform_device *pdev)
135 struct spi_master *master; 135 struct spi_master *master;
136 struct clk *ahb_clk; 136 struct clk *ahb_clk;
137 struct rb4xx_spi *rbspi; 137 struct rb4xx_spi *rbspi;
138 struct resource *r;
139 int err; 138 int err;
140 void __iomem *spi_base; 139 void __iomem *spi_base;
141 140
142 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 141 spi_base = devm_platform_ioremap_resource(pdev, 0);
143 spi_base = devm_ioremap_resource(&pdev->dev, r);
144 if (IS_ERR(spi_base)) 142 if (IS_ERR(spi_base))
145 return PTR_ERR(spi_base); 143 return PTR_ERR(spi_base);
146 144
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index 48d8dff05a3a..2d6e37f25e2d 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -487,7 +487,6 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
487 struct s3c2410_spi_info *pdata; 487 struct s3c2410_spi_info *pdata;
488 struct s3c24xx_spi *hw; 488 struct s3c24xx_spi *hw;
489 struct spi_master *master; 489 struct spi_master *master;
490 struct resource *res;
491 int err = 0; 490 int err = 0;
492 491
493 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); 492 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
@@ -536,8 +535,7 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
536 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); 535 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
537 536
538 /* find and map our resources */ 537 /* find and map our resources */
539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 538 hw->regs = devm_platform_ioremap_resource(pdev, 0);
540 hw->regs = devm_ioremap_resource(&pdev->dev, res);
541 if (IS_ERR(hw->regs)) { 539 if (IS_ERR(hw->regs)) {
542 err = PTR_ERR(hw->regs); 540 err = PTR_ERR(hw->regs);
543 goto err_no_pdata; 541 goto err_no_pdata;
@@ -545,7 +543,6 @@ static int s3c24xx_spi_probe(struct platform_device *pdev)
545 543
546 hw->irq = platform_get_irq(pdev, 0); 544 hw->irq = platform_get_irq(pdev, 0);
547 if (hw->irq < 0) { 545 if (hw->irq < 0) {
548 dev_err(&pdev->dev, "No IRQ specified\n");
549 err = -ENOENT; 546 err = -ENOENT;
550 goto err_no_pdata; 547 goto err_no_pdata;
551 } 548 }
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index b50bdbc27e58..8f134735291f 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1297,7 +1297,6 @@ static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1297 1297
1298static int sh_msiof_spi_probe(struct platform_device *pdev) 1298static int sh_msiof_spi_probe(struct platform_device *pdev)
1299{ 1299{
1300 struct resource *r;
1301 struct spi_controller *ctlr; 1300 struct spi_controller *ctlr;
1302 const struct sh_msiof_chipdata *chipdata; 1301 const struct sh_msiof_chipdata *chipdata;
1303 struct sh_msiof_spi_info *info; 1302 struct sh_msiof_spi_info *info;
@@ -1346,13 +1345,11 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1346 1345
1347 i = platform_get_irq(pdev, 0); 1346 i = platform_get_irq(pdev, 0);
1348 if (i < 0) { 1347 if (i < 0) {
1349 dev_err(&pdev->dev, "cannot get IRQ\n");
1350 ret = i; 1348 ret = i;
1351 goto err1; 1349 goto err1;
1352 } 1350 }
1353 1351
1354 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1352 p->mapbase = devm_platform_ioremap_resource(pdev, 0);
1355 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1356 if (IS_ERR(p->mapbase)) { 1353 if (IS_ERR(p->mapbase)) {
1357 ret = PTR_ERR(p->mapbase); 1354 ret = PTR_ERR(p->mapbase);
1358 goto err1; 1355 goto err1;
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index f1ee58208216..20bdae5fdf3b 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -437,10 +437,8 @@ static int spi_sh_probe(struct platform_device *pdev)
437 } 437 }
438 438
439 irq = platform_get_irq(pdev, 0); 439 irq = platform_get_irq(pdev, 0);
440 if (irq < 0) { 440 if (irq < 0)
441 dev_err(&pdev->dev, "platform_get_irq error: %d\n", irq);
442 return irq; 441 return irq;
443 }
444 442
445 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data)); 443 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
446 if (master == NULL) { 444 if (master == NULL) {
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index 93ec2c6cdbfd..35254bdc42c4 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -292,7 +292,6 @@ sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
292static int sifive_spi_probe(struct platform_device *pdev) 292static int sifive_spi_probe(struct platform_device *pdev)
293{ 293{
294 struct sifive_spi *spi; 294 struct sifive_spi *spi;
295 struct resource *res;
296 int ret, irq, num_cs; 295 int ret, irq, num_cs;
297 u32 cs_bits, max_bits_per_word; 296 u32 cs_bits, max_bits_per_word;
298 struct spi_master *master; 297 struct spi_master *master;
@@ -307,8 +306,7 @@ static int sifive_spi_probe(struct platform_device *pdev)
307 init_completion(&spi->done); 306 init_completion(&spi->done);
308 platform_set_drvdata(pdev, master); 307 platform_set_drvdata(pdev, master);
309 308
310 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 309 spi->regs = devm_platform_ioremap_resource(pdev, 0);
311 spi->regs = devm_ioremap_resource(&pdev->dev, res);
312 if (IS_ERR(spi->regs)) { 310 if (IS_ERR(spi->regs)) {
313 ret = PTR_ERR(spi->regs); 311 ret = PTR_ERR(spi->regs);
314 goto put_master; 312 goto put_master;
@@ -323,7 +321,6 @@ static int sifive_spi_probe(struct platform_device *pdev)
323 321
324 irq = platform_get_irq(pdev, 0); 322 irq = platform_get_irq(pdev, 0);
325 if (irq < 0) { 323 if (irq < 0) {
326 dev_err(&pdev->dev, "Unable to find interrupt\n");
327 ret = irq; 324 ret = irq;
328 goto put_master; 325 goto put_master;
329 } 326 }
diff --git a/drivers/spi/spi-sirf.c b/drivers/spi/spi-sirf.c
index 71b882ab31b9..e1e639191557 100644
--- a/drivers/spi/spi-sirf.c
+++ b/drivers/spi/spi-sirf.c
@@ -1070,7 +1070,6 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
1070{ 1070{
1071 struct sirfsoc_spi *sspi; 1071 struct sirfsoc_spi *sspi;
1072 struct spi_master *master; 1072 struct spi_master *master;
1073 struct resource *mem_res;
1074 const struct sirf_spi_comp_data *spi_comp_data; 1073 const struct sirf_spi_comp_data *spi_comp_data;
1075 int irq; 1074 int irq;
1076 int ret; 1075 int ret;
@@ -1097,8 +1096,7 @@ static int spi_sirfsoc_probe(struct platform_device *pdev)
1097 sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1; 1096 sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1;
1098 sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len; 1097 sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len;
1099 sspi->fifo_size = spi_comp_data->fifo_size; 1098 sspi->fifo_size = spi_comp_data->fifo_size;
1100 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1099 sspi->base = devm_platform_ioremap_resource(pdev, 0);
1101 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
1102 if (IS_ERR(sspi->base)) { 1100 if (IS_ERR(sspi->base)) {
1103 ret = PTR_ERR(sspi->base); 1101 ret = PTR_ERR(sspi->base);
1104 goto free_master; 1102 goto free_master;
diff --git a/drivers/spi/spi-slave-mt27xx.c b/drivers/spi/spi-slave-mt27xx.c
index d1075433f6a6..61bc43b0fe57 100644
--- a/drivers/spi/spi-slave-mt27xx.c
+++ b/drivers/spi/spi-slave-mt27xx.c
@@ -410,7 +410,6 @@ static int mtk_spi_slave_probe(struct platform_device *pdev)
410 410
411 irq = platform_get_irq(pdev, 0); 411 irq = platform_get_irq(pdev, 0);
412 if (irq < 0) { 412 if (irq < 0) {
413 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
414 ret = irq; 413 ret = irq;
415 goto err_put_ctlr; 414 goto err_put_ctlr;
416 } 415 }
diff --git a/drivers/spi/spi-sprd-adi.c b/drivers/spi/spi-sprd-adi.c
index df5960bddfe6..9a051286f120 100644
--- a/drivers/spi/spi-sprd-adi.c
+++ b/drivers/spi/spi-sprd-adi.c
@@ -86,6 +86,7 @@
86#define BIT_WDG_EN BIT(2) 86#define BIT_WDG_EN BIT(2)
87 87
88/* Definition of PMIC reset status register */ 88/* Definition of PMIC reset status register */
89#define HWRST_STATUS_SECURITY 0x02
89#define HWRST_STATUS_RECOVERY 0x20 90#define HWRST_STATUS_RECOVERY 0x20
90#define HWRST_STATUS_NORMAL 0x40 91#define HWRST_STATUS_NORMAL 0x40
91#define HWRST_STATUS_ALARM 0x50 92#define HWRST_STATUS_ALARM 0x50
@@ -97,6 +98,8 @@
97#define HWRST_STATUS_AUTODLOADER 0xa0 98#define HWRST_STATUS_AUTODLOADER 0xa0
98#define HWRST_STATUS_IQMODE 0xb0 99#define HWRST_STATUS_IQMODE 0xb0
99#define HWRST_STATUS_SPRDISK 0xc0 100#define HWRST_STATUS_SPRDISK 0xc0
101#define HWRST_STATUS_FACTORYTEST 0xe0
102#define HWRST_STATUS_WATCHDOG 0xf0
100 103
101/* Use default timeout 50 ms that converts to watchdog values */ 104/* Use default timeout 50 ms that converts to watchdog values */
102#define WDG_LOAD_VAL ((50 * 1000) / 32768) 105#define WDG_LOAD_VAL ((50 * 1000) / 32768)
@@ -162,14 +165,16 @@ static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
162 int read_timeout = ADI_READ_TIMEOUT; 165 int read_timeout = ADI_READ_TIMEOUT;
163 unsigned long flags; 166 unsigned long flags;
164 u32 val, rd_addr; 167 u32 val, rd_addr;
165 int ret; 168 int ret = 0;
166 169
167 ret = hwspin_lock_timeout_irqsave(sadi->hwlock, 170 if (sadi->hwlock) {
168 ADI_HWSPINLOCK_TIMEOUT, 171 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
169 &flags); 172 ADI_HWSPINLOCK_TIMEOUT,
170 if (ret) { 173 &flags);
171 dev_err(sadi->dev, "get the hw lock failed\n"); 174 if (ret) {
172 return ret; 175 dev_err(sadi->dev, "get the hw lock failed\n");
176 return ret;
177 }
173 } 178 }
174 179
175 /* 180 /*
@@ -216,7 +221,8 @@ static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
216 *read_val = val & RD_VALUE_MASK; 221 *read_val = val & RD_VALUE_MASK;
217 222
218out: 223out:
219 hwspin_unlock_irqrestore(sadi->hwlock, &flags); 224 if (sadi->hwlock)
225 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
220 return ret; 226 return ret;
221} 227}
222 228
@@ -227,12 +233,14 @@ static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
227 unsigned long flags; 233 unsigned long flags;
228 int ret; 234 int ret;
229 235
230 ret = hwspin_lock_timeout_irqsave(sadi->hwlock, 236 if (sadi->hwlock) {
231 ADI_HWSPINLOCK_TIMEOUT, 237 ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
232 &flags); 238 ADI_HWSPINLOCK_TIMEOUT,
233 if (ret) { 239 &flags);
234 dev_err(sadi->dev, "get the hw lock failed\n"); 240 if (ret) {
235 return ret; 241 dev_err(sadi->dev, "get the hw lock failed\n");
242 return ret;
243 }
236 } 244 }
237 245
238 ret = sprd_adi_drain_fifo(sadi); 246 ret = sprd_adi_drain_fifo(sadi);
@@ -258,7 +266,8 @@ static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
258 } 266 }
259 267
260out: 268out:
261 hwspin_unlock_irqrestore(sadi->hwlock, &flags); 269 if (sadi->hwlock)
270 hwspin_unlock_irqrestore(sadi->hwlock, &flags);
262 return ret; 271 return ret;
263} 272}
264 273
@@ -307,6 +316,18 @@ static int sprd_adi_transfer_one(struct spi_controller *ctlr,
307 return 0; 316 return 0;
308} 317}
309 318
319static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
320{
321#ifdef CONFIG_SPRD_WATCHDOG
322 u32 val;
323
324 /* Set default watchdog reboot mode */
325 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
326 val |= HWRST_STATUS_WATCHDOG;
327 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
328#endif
329}
330
310static int sprd_adi_restart_handler(struct notifier_block *this, 331static int sprd_adi_restart_handler(struct notifier_block *this,
311 unsigned long mode, void *cmd) 332 unsigned long mode, void *cmd)
312{ 333{
@@ -336,11 +357,16 @@ static int sprd_adi_restart_handler(struct notifier_block *this,
336 reboot_mode = HWRST_STATUS_IQMODE; 357 reboot_mode = HWRST_STATUS_IQMODE;
337 else if (!strncmp(cmd, "sprdisk", 7)) 358 else if (!strncmp(cmd, "sprdisk", 7))
338 reboot_mode = HWRST_STATUS_SPRDISK; 359 reboot_mode = HWRST_STATUS_SPRDISK;
360 else if (!strncmp(cmd, "tospanic", 8))
361 reboot_mode = HWRST_STATUS_SECURITY;
362 else if (!strncmp(cmd, "factorytest", 11))
363 reboot_mode = HWRST_STATUS_FACTORYTEST;
339 else 364 else
340 reboot_mode = HWRST_STATUS_NORMAL; 365 reboot_mode = HWRST_STATUS_NORMAL;
341 366
342 /* Record the reboot mode */ 367 /* Record the reboot mode */
343 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val); 368 sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
369 val &= ~HWRST_STATUS_WATCHDOG;
344 val |= reboot_mode; 370 val |= reboot_mode;
345 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val); 371 sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
346 372
@@ -380,9 +406,6 @@ static void sprd_adi_hw_init(struct sprd_adi *sadi)
380 const __be32 *list; 406 const __be32 *list;
381 u32 tmp; 407 u32 tmp;
382 408
383 /* Address bits select default 12 bits */
384 writel_relaxed(0, sadi->base + REG_ADI_CTRL0);
385
386 /* Set all channels as default priority */ 409 /* Set all channels as default priority */
387 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); 410 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
388 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH); 411 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
@@ -459,19 +482,30 @@ static int sprd_adi_probe(struct platform_device *pdev)
459 sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET; 482 sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
460 sadi->ctlr = ctlr; 483 sadi->ctlr = ctlr;
461 sadi->dev = &pdev->dev; 484 sadi->dev = &pdev->dev;
462 ret = of_hwspin_lock_get_id_byname(np, "adi"); 485 ret = of_hwspin_lock_get_id(np, 0);
463 if (ret < 0) { 486 if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
464 dev_err(&pdev->dev, "can not get the hardware spinlock\n"); 487 sadi->hwlock =
465 goto put_ctlr; 488 devm_hwspin_lock_request_specific(&pdev->dev, ret);
466 } 489 if (!sadi->hwlock) {
467 490 ret = -ENXIO;
468 sadi->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret); 491 goto put_ctlr;
469 if (!sadi->hwlock) { 492 }
470 ret = -ENXIO; 493 } else {
471 goto put_ctlr; 494 switch (ret) {
495 case -ENOENT:
496 dev_info(&pdev->dev, "no hardware spinlock supplied\n");
497 break;
498 default:
499 dev_err(&pdev->dev,
500 "failed to find hwlock id, %d\n", ret);
501 /* fall-through */
502 case -EPROBE_DEFER:
503 goto put_ctlr;
504 }
472 } 505 }
473 506
474 sprd_adi_hw_init(sadi); 507 sprd_adi_hw_init(sadi);
508 sprd_adi_set_wdt_rst_mode(sadi);
475 509
476 ctlr->dev.of_node = pdev->dev.of_node; 510 ctlr->dev.of_node = pdev->dev.of_node;
477 ctlr->bus_num = pdev->id; 511 ctlr->bus_num = pdev->id;
diff --git a/drivers/spi/spi-sprd.c b/drivers/spi/spi-sprd.c
index 1b7eebb72c07..8c9021b7f7a9 100644
--- a/drivers/spi/spi-sprd.c
+++ b/drivers/spi/spi-sprd.c
@@ -843,10 +843,8 @@ static int sprd_spi_irq_init(struct platform_device *pdev, struct sprd_spi *ss)
843 int ret; 843 int ret;
844 844
845 ss->irq = platform_get_irq(pdev, 0); 845 ss->irq = platform_get_irq(pdev, 0);
846 if (ss->irq < 0) { 846 if (ss->irq < 0)
847 dev_err(&pdev->dev, "failed to get irq resource\n");
848 return ss->irq; 847 return ss->irq;
849 }
850 848
851 ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq, 849 ret = devm_request_irq(&pdev->dev, ss->irq, sprd_spi_handle_irq,
852 0, pdev->name, ss); 850 0, pdev->name, ss);
diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index 840a6bf81336..0c24c494f386 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -298,7 +298,6 @@ static int spi_st_probe(struct platform_device *pdev)
298{ 298{
299 struct device_node *np = pdev->dev.of_node; 299 struct device_node *np = pdev->dev.of_node;
300 struct spi_master *master; 300 struct spi_master *master;
301 struct resource *res;
302 struct spi_st *spi_st; 301 struct spi_st *spi_st;
303 int irq, ret = 0; 302 int irq, ret = 0;
304 u32 var; 303 u32 var;
@@ -331,8 +330,7 @@ static int spi_st_probe(struct platform_device *pdev)
331 init_completion(&spi_st->done); 330 init_completion(&spi_st->done);
332 331
333 /* Get resources */ 332 /* Get resources */
334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 333 spi_st->base = devm_platform_ioremap_resource(pdev, 0);
335 spi_st->base = devm_ioremap_resource(&pdev->dev, res);
336 if (IS_ERR(spi_st->base)) { 334 if (IS_ERR(spi_st->base)) {
337 ret = PTR_ERR(spi_st->base); 335 ret = PTR_ERR(spi_st->base);
338 goto clk_disable; 336 goto clk_disable;
diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c
index 655e4afbfb2a..9ac6f9fe13cf 100644
--- a/drivers/spi/spi-stm32-qspi.c
+++ b/drivers/spi/spi-stm32-qspi.c
@@ -570,11 +570,8 @@ static int stm32_qspi_probe(struct platform_device *pdev)
570 } 570 }
571 571
572 irq = platform_get_irq(pdev, 0); 572 irq = platform_get_irq(pdev, 0);
573 if (irq < 0) { 573 if (irq < 0)
574 if (irq != -EPROBE_DEFER)
575 dev_err(dev, "IRQ error missing or invalid\n");
576 return irq; 574 return irq;
577 }
578 575
579 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, 576 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
580 dev_name(dev), qspi); 577 dev_name(dev), qspi);
diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index 5194bc07fd60..cbfac6596fad 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -428,7 +428,6 @@ static int sun4i_spi_probe(struct platform_device *pdev)
428{ 428{
429 struct spi_master *master; 429 struct spi_master *master;
430 struct sun4i_spi *sspi; 430 struct sun4i_spi *sspi;
431 struct resource *res;
432 int ret = 0, irq; 431 int ret = 0, irq;
433 432
434 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); 433 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi));
@@ -440,8 +439,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
440 platform_set_drvdata(pdev, master); 439 platform_set_drvdata(pdev, master);
441 sspi = spi_master_get_devdata(master); 440 sspi = spi_master_get_devdata(master);
442 441
443 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 442 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
444 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
445 if (IS_ERR(sspi->base_addr)) { 443 if (IS_ERR(sspi->base_addr)) {
446 ret = PTR_ERR(sspi->base_addr); 444 ret = PTR_ERR(sspi->base_addr);
447 goto err_free_master; 445 goto err_free_master;
@@ -449,7 +447,6 @@ static int sun4i_spi_probe(struct platform_device *pdev)
449 447
450 irq = platform_get_irq(pdev, 0); 448 irq = platform_get_irq(pdev, 0);
451 if (irq < 0) { 449 if (irq < 0) {
452 dev_err(&pdev->dev, "No spi IRQ specified\n");
453 ret = -ENXIO; 450 ret = -ENXIO;
454 goto err_free_master; 451 goto err_free_master;
455 } 452 }
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index ee2bdaf5b856..ec7967be9e2f 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -435,7 +435,6 @@ static int sun6i_spi_probe(struct platform_device *pdev)
435{ 435{
436 struct spi_master *master; 436 struct spi_master *master;
437 struct sun6i_spi *sspi; 437 struct sun6i_spi *sspi;
438 struct resource *res;
439 int ret = 0, irq; 438 int ret = 0, irq;
440 439
441 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 440 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
@@ -447,8 +446,7 @@ static int sun6i_spi_probe(struct platform_device *pdev)
447 platform_set_drvdata(pdev, master); 446 platform_set_drvdata(pdev, master);
448 sspi = spi_master_get_devdata(master); 447 sspi = spi_master_get_devdata(master);
449 448
450 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 449 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
451 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
452 if (IS_ERR(sspi->base_addr)) { 450 if (IS_ERR(sspi->base_addr)) {
453 ret = PTR_ERR(sspi->base_addr); 451 ret = PTR_ERR(sspi->base_addr);
454 goto err_free_master; 452 goto err_free_master;
@@ -456,7 +454,6 @@ static int sun6i_spi_probe(struct platform_device *pdev)
456 454
457 irq = platform_get_irq(pdev, 0); 455 irq = platform_get_irq(pdev, 0);
458 if (irq < 0) { 456 if (irq < 0) {
459 dev_err(&pdev->dev, "No spi IRQ specified\n");
460 ret = -ENXIO; 457 ret = -ENXIO;
461 goto err_free_master; 458 goto err_free_master;
462 } 459 }
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index f99abd85c50a..ae17c99cce03 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -670,7 +670,6 @@ static int synquacer_spi_probe(struct platform_device *pdev)
670 670
671 rx_irq = platform_get_irq(pdev, 0); 671 rx_irq = platform_get_irq(pdev, 0);
672 if (rx_irq <= 0) { 672 if (rx_irq <= 0) {
673 dev_err(&pdev->dev, "get rx_irq failed (%d)\n", rx_irq);
674 ret = rx_irq; 673 ret = rx_irq;
675 goto put_spi; 674 goto put_spi;
676 } 675 }
@@ -685,7 +684,6 @@ static int synquacer_spi_probe(struct platform_device *pdev)
685 684
686 tx_irq = platform_get_irq(pdev, 1); 685 tx_irq = platform_get_irq(pdev, 1);
687 if (tx_irq <= 0) { 686 if (tx_irq <= 0) {
688 dev_err(&pdev->dev, "get tx_irq failed (%d)\n", tx_irq);
689 ret = tx_irq; 687 ret = tx_irq;
690 goto put_spi; 688 goto put_spi;
691 } 689 }
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index cd714a4f52c6..a841a7250d14 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -419,7 +419,6 @@ static int tegra_sflash_probe(struct platform_device *pdev)
419{ 419{
420 struct spi_master *master; 420 struct spi_master *master;
421 struct tegra_sflash_data *tsd; 421 struct tegra_sflash_data *tsd;
422 struct resource *r;
423 int ret; 422 int ret;
424 const struct of_device_id *match; 423 const struct of_device_id *match;
425 424
@@ -451,8 +450,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
451 &master->max_speed_hz)) 450 &master->max_speed_hz))
452 master->max_speed_hz = 25000000; /* 25MHz */ 451 master->max_speed_hz = 25000000; /* 25MHz */
453 452
454 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 453 tsd->base = devm_platform_ioremap_resource(pdev, 0);
455 tsd->base = devm_ioremap_resource(&pdev->dev, r);
456 if (IS_ERR(tsd->base)) { 454 if (IS_ERR(tsd->base)) {
457 ret = PTR_ERR(tsd->base); 455 ret = PTR_ERR(tsd->base);
458 goto exit_free_master; 456 goto exit_free_master;
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 6ca600702470..3cb65371ae3b 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -717,7 +717,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
717 717
718 irq = platform_get_irq(pdev, 0); 718 irq = platform_get_irq(pdev, 0);
719 if (irq < 0) { 719 if (irq < 0) {
720 dev_err(&pdev->dev, "no irq resource?\n");
721 ret = irq; 720 ret = irq;
722 goto free_master; 721 goto free_master;
723 } 722 }
diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
index 4e99a0f25c29..47cde1864630 100644
--- a/drivers/spi/spi-uniphier.c
+++ b/drivers/spi/spi-uniphier.c
@@ -7,6 +7,7 @@
7#include <linux/bitfield.h> 7#include <linux/bitfield.h>
8#include <linux/bitops.h> 8#include <linux/bitops.h>
9#include <linux/clk.h> 9#include <linux/clk.h>
10#include <linux/delay.h>
10#include <linux/interrupt.h> 11#include <linux/interrupt.h>
11#include <linux/io.h> 12#include <linux/io.h>
12#include <linux/module.h> 13#include <linux/module.h>
@@ -16,6 +17,7 @@
16#include <asm/unaligned.h> 17#include <asm/unaligned.h>
17 18
18#define SSI_TIMEOUT_MS 2000 19#define SSI_TIMEOUT_MS 2000
20#define SSI_POLL_TIMEOUT_US 200
19#define SSI_MAX_CLK_DIVIDER 254 21#define SSI_MAX_CLK_DIVIDER 254
20#define SSI_MIN_CLK_DIVIDER 4 22#define SSI_MIN_CLK_DIVIDER 4
21 23
@@ -227,8 +229,7 @@ static void uniphier_spi_setup_transfer(struct spi_device *spi,
227 priv->speed_hz = t->speed_hz; 229 priv->speed_hz = t->speed_hz;
228 } 230 }
229 231
230 if (!priv->is_save_param) 232 priv->is_save_param = true;
231 priv->is_save_param = true;
232 233
233 /* reset FIFOs */ 234 /* reset FIFOs */
234 val = SSI_FC_TXFFL | SSI_FC_RXFFL; 235 val = SSI_FC_TXFFL | SSI_FC_RXFFL;
@@ -291,21 +292,23 @@ static void uniphier_spi_recv(struct uniphier_spi_priv *priv)
291 292
292static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv) 293static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)
293{ 294{
294 unsigned int tx_count; 295 unsigned int fifo_threshold, fill_bytes;
295 u32 val; 296 u32 val;
296 297
297 tx_count = DIV_ROUND_UP(priv->tx_bytes, 298 fifo_threshold = DIV_ROUND_UP(priv->rx_bytes,
298 bytes_per_word(priv->bits_per_word)); 299 bytes_per_word(priv->bits_per_word));
299 tx_count = min(tx_count, SSI_FIFO_DEPTH); 300 fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);
301
302 fill_bytes = fifo_threshold - (priv->rx_bytes - priv->tx_bytes);
300 303
301 /* set fifo threshold */ 304 /* set fifo threshold */
302 val = readl(priv->base + SSI_FC); 305 val = readl(priv->base + SSI_FC);
303 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); 306 val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
304 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, tx_count); 307 val |= FIELD_PREP(SSI_FC_TXFTH_MASK, fifo_threshold);
305 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, tx_count); 308 val |= FIELD_PREP(SSI_FC_RXFTH_MASK, fifo_threshold);
306 writel(val, priv->base + SSI_FC); 309 writel(val, priv->base + SSI_FC);
307 310
308 while (tx_count--) 311 while (fill_bytes--)
309 uniphier_spi_send(priv); 312 uniphier_spi_send(priv);
310} 313}
311 314
@@ -324,20 +327,14 @@ static void uniphier_spi_set_cs(struct spi_device *spi, bool enable)
324 writel(val, priv->base + SSI_FPS); 327 writel(val, priv->base + SSI_FPS);
325} 328}
326 329
327static int uniphier_spi_transfer_one(struct spi_master *master, 330static int uniphier_spi_transfer_one_irq(struct spi_master *master,
328 struct spi_device *spi, 331 struct spi_device *spi,
329 struct spi_transfer *t) 332 struct spi_transfer *t)
330{ 333{
331 struct uniphier_spi_priv *priv = spi_master_get_devdata(master); 334 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
332 struct device *dev = master->dev.parent; 335 struct device *dev = master->dev.parent;
333 unsigned long time_left; 336 unsigned long time_left;
334 337
335 /* Terminate and return success for 0 byte length transfer */
336 if (!t->len)
337 return 0;
338
339 uniphier_spi_setup_transfer(spi, t);
340
341 reinit_completion(&priv->xfer_done); 338 reinit_completion(&priv->xfer_done);
342 339
343 uniphier_spi_fill_tx_fifo(priv); 340 uniphier_spi_fill_tx_fifo(priv);
@@ -357,6 +354,59 @@ static int uniphier_spi_transfer_one(struct spi_master *master,
357 return priv->error; 354 return priv->error;
358} 355}
359 356
357static int uniphier_spi_transfer_one_poll(struct spi_master *master,
358 struct spi_device *spi,
359 struct spi_transfer *t)
360{
361 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
362 int loop = SSI_POLL_TIMEOUT_US * 10;
363
364 while (priv->tx_bytes) {
365 uniphier_spi_fill_tx_fifo(priv);
366
367 while ((priv->rx_bytes - priv->tx_bytes) > 0) {
368 while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE)
369 && loop--)
370 ndelay(100);
371
372 if (loop == -1)
373 goto irq_transfer;
374
375 uniphier_spi_recv(priv);
376 }
377 }
378
379 return 0;
380
381irq_transfer:
382 return uniphier_spi_transfer_one_irq(master, spi, t);
383}
384
385static int uniphier_spi_transfer_one(struct spi_master *master,
386 struct spi_device *spi,
387 struct spi_transfer *t)
388{
389 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
390 unsigned long threshold;
391
392 /* Terminate and return success for 0 byte length transfer */
393 if (!t->len)
394 return 0;
395
396 uniphier_spi_setup_transfer(spi, t);
397
398 /*
399 * If the transfer operation will take longer than
400 * SSI_POLL_TIMEOUT_US, it should use irq.
401 */
402 threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz,
403 USEC_PER_SEC * BITS_PER_BYTE);
404 if (t->len > threshold)
405 return uniphier_spi_transfer_one_irq(master, spi, t);
406 else
407 return uniphier_spi_transfer_one_poll(master, spi, t);
408}
409
360static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master) 410static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master)
361{ 411{
362 struct uniphier_spi_priv *priv = spi_master_get_devdata(master); 412 struct uniphier_spi_priv *priv = spi_master_get_devdata(master);
@@ -420,7 +470,6 @@ static int uniphier_spi_probe(struct platform_device *pdev)
420{ 470{
421 struct uniphier_spi_priv *priv; 471 struct uniphier_spi_priv *priv;
422 struct spi_master *master; 472 struct spi_master *master;
423 struct resource *res;
424 unsigned long clk_rate; 473 unsigned long clk_rate;
425 int irq; 474 int irq;
426 int ret; 475 int ret;
@@ -435,8 +484,7 @@ static int uniphier_spi_probe(struct platform_device *pdev)
435 priv->master = master; 484 priv->master = master;
436 priv->is_save_param = false; 485 priv->is_save_param = false;
437 486
438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 487 priv->base = devm_platform_ioremap_resource(pdev, 0);
439 priv->base = devm_ioremap_resource(&pdev->dev, res);
440 if (IS_ERR(priv->base)) { 488 if (IS_ERR(priv->base)) {
441 ret = PTR_ERR(priv->base); 489 ret = PTR_ERR(priv->base);
442 goto out_master_put; 490 goto out_master_put;
@@ -455,7 +503,6 @@ static int uniphier_spi_probe(struct platform_device *pdev)
455 503
456 irq = platform_get_irq(pdev, 0); 504 irq = platform_get_irq(pdev, 0);
457 if (irq < 0) { 505 if (irq < 0) {
458 dev_err(&pdev->dev, "failed to get IRQ\n");
459 ret = irq; 506 ret = irq;
460 goto out_disable_clk; 507 goto out_disable_clk;
461 } 508 }
diff --git a/drivers/spi/spi-xlp.c b/drivers/spi/spi-xlp.c
index 1dc479fab98c..797ac0ea8fa3 100644
--- a/drivers/spi/spi-xlp.c
+++ b/drivers/spi/spi-xlp.c
@@ -370,7 +370,6 @@ static int xlp_spi_probe(struct platform_device *pdev)
370{ 370{
371 struct spi_master *master; 371 struct spi_master *master;
372 struct xlp_spi_priv *xspi; 372 struct xlp_spi_priv *xspi;
373 struct resource *res;
374 struct clk *clk; 373 struct clk *clk;
375 int irq, err; 374 int irq, err;
376 375
@@ -378,16 +377,13 @@ static int xlp_spi_probe(struct platform_device *pdev)
378 if (!xspi) 377 if (!xspi)
379 return -ENOMEM; 378 return -ENOMEM;
380 379
381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 380 xspi->base = devm_platform_ioremap_resource(pdev, 0);
382 xspi->base = devm_ioremap_resource(&pdev->dev, res);
383 if (IS_ERR(xspi->base)) 381 if (IS_ERR(xspi->base))
384 return PTR_ERR(xspi->base); 382 return PTR_ERR(xspi->base);
385 383
386 irq = platform_get_irq(pdev, 0); 384 irq = platform_get_irq(pdev, 0);
387 if (irq < 0) { 385 if (irq < 0)
388 dev_err(&pdev->dev, "no IRQ resource found: %d\n", irq);
389 return irq; 386 return irq;
390 }
391 err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0, 387 err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
392 pdev->name, xspi); 388 pdev->name, xspi);
393 if (err) { 389 if (err) {
diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index d812a215ae5c..5cf6993ddce5 100644
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -620,7 +620,6 @@ static int zynq_qspi_probe(struct platform_device *pdev)
620 struct device *dev = &pdev->dev; 620 struct device *dev = &pdev->dev;
621 struct device_node *np = dev->of_node; 621 struct device_node *np = dev->of_node;
622 struct zynq_qspi *xqspi; 622 struct zynq_qspi *xqspi;
623 struct resource *res;
624 u32 num_cs; 623 u32 num_cs;
625 624
626 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); 625 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
@@ -630,8 +629,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
630 xqspi = spi_controller_get_devdata(ctlr); 629 xqspi = spi_controller_get_devdata(ctlr);
631 xqspi->dev = dev; 630 xqspi->dev = dev;
632 platform_set_drvdata(pdev, xqspi); 631 platform_set_drvdata(pdev, xqspi);
633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 632 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
634 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
635 if (IS_ERR(xqspi->regs)) { 633 if (IS_ERR(xqspi->regs)) {
636 ret = PTR_ERR(xqspi->regs); 634 ret = PTR_ERR(xqspi->regs);
637 goto remove_master; 635 goto remove_master;
@@ -671,7 +669,6 @@ static int zynq_qspi_probe(struct platform_device *pdev)
671 xqspi->irq = platform_get_irq(pdev, 0); 669 xqspi->irq = platform_get_irq(pdev, 0);
672 if (xqspi->irq <= 0) { 670 if (xqspi->irq <= 0) {
673 ret = -ENXIO; 671 ret = -ENXIO;
674 dev_err(&pdev->dev, "irq resource not found\n");
675 goto remove_master; 672 goto remove_master;
676 } 673 }
677 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, 674 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 07a83ca164c2..60c4de4e4485 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -1016,7 +1016,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
1016 int ret = 0; 1016 int ret = 0;
1017 struct spi_master *master; 1017 struct spi_master *master;
1018 struct zynqmp_qspi *xqspi; 1018 struct zynqmp_qspi *xqspi;
1019 struct resource *res;
1020 struct device *dev = &pdev->dev; 1019 struct device *dev = &pdev->dev;
1021 1020
1022 eemi_ops = zynqmp_pm_get_eemi_ops(); 1021 eemi_ops = zynqmp_pm_get_eemi_ops();
@@ -1031,8 +1030,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
1031 master->dev.of_node = pdev->dev.of_node; 1030 master->dev.of_node = pdev->dev.of_node;
1032 platform_set_drvdata(pdev, master); 1031 platform_set_drvdata(pdev, master);
1033 1032
1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1033 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1035 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1036 if (IS_ERR(xqspi->regs)) { 1034 if (IS_ERR(xqspi->regs)) {
1037 ret = PTR_ERR(xqspi->regs); 1035 ret = PTR_ERR(xqspi->regs);
1038 goto remove_master; 1036 goto remove_master;
@@ -1077,7 +1075,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
1077 xqspi->irq = platform_get_irq(pdev, 0); 1075 xqspi->irq = platform_get_irq(pdev, 0);
1078 if (xqspi->irq <= 0) { 1076 if (xqspi->irq <= 0) {
1079 ret = -ENXIO; 1077 ret = -ENXIO;
1080 dev_err(dev, "irq resource not found\n");
1081 goto clk_dis_all; 1078 goto clk_dis_all;
1082 } 1079 }
1083 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq, 1080 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 75ac046cae52..f8b4654a57d3 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1265,8 +1265,9 @@ EXPORT_SYMBOL_GPL(spi_finalize_current_transfer);
1265 */ 1265 */
1266static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread) 1266static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread)
1267{ 1267{
1268 unsigned long flags; 1268 struct spi_message *msg;
1269 bool was_busy = false; 1269 bool was_busy = false;
1270 unsigned long flags;
1270 int ret; 1271 int ret;
1271 1272
1272 /* Lock queue */ 1273 /* Lock queue */
@@ -1325,10 +1326,10 @@ static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread)
1325 } 1326 }
1326 1327
1327 /* Extract head of queue */ 1328 /* Extract head of queue */
1328 ctlr->cur_msg = 1329 msg = list_first_entry(&ctlr->queue, struct spi_message, queue);
1329 list_first_entry(&ctlr->queue, struct spi_message, queue); 1330 ctlr->cur_msg = msg;
1330 1331
1331 list_del_init(&ctlr->cur_msg->queue); 1332 list_del_init(&msg->queue);
1332 if (ctlr->busy) 1333 if (ctlr->busy)
1333 was_busy = true; 1334 was_busy = true;
1334 else 1335 else
@@ -1361,7 +1362,7 @@ static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread)
1361 if (ctlr->auto_runtime_pm) 1362 if (ctlr->auto_runtime_pm)
1362 pm_runtime_put(ctlr->dev.parent); 1363 pm_runtime_put(ctlr->dev.parent);
1363 1364
1364 ctlr->cur_msg->status = ret; 1365 msg->status = ret;
1365 spi_finalize_current_message(ctlr); 1366 spi_finalize_current_message(ctlr);
1366 1367
1367 mutex_unlock(&ctlr->io_mutex); 1368 mutex_unlock(&ctlr->io_mutex);
@@ -1369,28 +1370,28 @@ static void __spi_pump_messages(struct spi_controller *ctlr, bool in_kthread)
1369 } 1370 }
1370 } 1371 }
1371 1372
1372 trace_spi_message_start(ctlr->cur_msg); 1373 trace_spi_message_start(msg);
1373 1374
1374 if (ctlr->prepare_message) { 1375 if (ctlr->prepare_message) {
1375 ret = ctlr->prepare_message(ctlr, ctlr->cur_msg); 1376 ret = ctlr->prepare_message(ctlr, msg);
1376 if (ret) { 1377 if (ret) {
1377 dev_err(&ctlr->dev, "failed to prepare message: %d\n", 1378 dev_err(&ctlr->dev, "failed to prepare message: %d\n",
1378 ret); 1379 ret);
1379 ctlr->cur_msg->status = ret; 1380 msg->status = ret;
1380 spi_finalize_current_message(ctlr); 1381 spi_finalize_current_message(ctlr);
1381 goto out; 1382 goto out;
1382 } 1383 }
1383 ctlr->cur_msg_prepared = true; 1384 ctlr->cur_msg_prepared = true;
1384 } 1385 }
1385 1386
1386 ret = spi_map_msg(ctlr, ctlr->cur_msg); 1387 ret = spi_map_msg(ctlr, msg);
1387 if (ret) { 1388 if (ret) {
1388 ctlr->cur_msg->status = ret; 1389 msg->status = ret;
1389 spi_finalize_current_message(ctlr); 1390 spi_finalize_current_message(ctlr);
1390 goto out; 1391 goto out;
1391 } 1392 }
1392 1393
1393 ret = ctlr->transfer_one_message(ctlr, ctlr->cur_msg); 1394 ret = ctlr->transfer_one_message(ctlr, msg);
1394 if (ret) { 1395 if (ret) {
1395 dev_err(&ctlr->dev, 1396 dev_err(&ctlr->dev,
1396 "failed to transfer one message from queue\n"); 1397 "failed to transfer one message from queue\n");
@@ -1434,7 +1435,7 @@ static void spi_pump_messages(struct kthread_work *work)
1434 */ 1435 */
1435static void spi_set_thread_rt(struct spi_controller *ctlr) 1436static void spi_set_thread_rt(struct spi_controller *ctlr)
1436{ 1437{
1437 struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; 1438 struct sched_param param = { .sched_priority = MAX_RT_PRIO / 2 };
1438 1439
1439 dev_info(&ctlr->dev, 1440 dev_info(&ctlr->dev,
1440 "will run message pump with realtime priority\n"); 1441 "will run message pump with realtime priority\n");
@@ -2105,8 +2106,8 @@ static int match_true(struct device *dev, void *data)
2105 return 1; 2106 return 1;
2106} 2107}
2107 2108
2108static ssize_t spi_slave_show(struct device *dev, 2109static ssize_t slave_show(struct device *dev, struct device_attribute *attr,
2109 struct device_attribute *attr, char *buf) 2110 char *buf)
2110{ 2111{
2111 struct spi_controller *ctlr = container_of(dev, struct spi_controller, 2112 struct spi_controller *ctlr = container_of(dev, struct spi_controller,
2112 dev); 2113 dev);
@@ -2117,9 +2118,8 @@ static ssize_t spi_slave_show(struct device *dev,
2117 child ? to_spi_device(child)->modalias : NULL); 2118 child ? to_spi_device(child)->modalias : NULL);
2118} 2119}
2119 2120
2120static ssize_t spi_slave_store(struct device *dev, 2121static ssize_t slave_store(struct device *dev, struct device_attribute *attr,
2121 struct device_attribute *attr, const char *buf, 2122 const char *buf, size_t count)
2122 size_t count)
2123{ 2123{
2124 struct spi_controller *ctlr = container_of(dev, struct spi_controller, 2124 struct spi_controller *ctlr = container_of(dev, struct spi_controller,
2125 dev); 2125 dev);
@@ -2157,7 +2157,7 @@ static ssize_t spi_slave_store(struct device *dev,
2157 return count; 2157 return count;
2158} 2158}
2159 2159
2160static DEVICE_ATTR(slave, 0644, spi_slave_show, spi_slave_store); 2160static DEVICE_ATTR_RW(slave);
2161 2161
2162static struct attribute *spi_slave_attrs[] = { 2162static struct attribute *spi_slave_attrs[] = {
2163 &dev_attr_slave.attr, 2163 &dev_attr_slave.attr,
@@ -2188,8 +2188,10 @@ extern struct class spi_slave_class; /* dummy */
2188 * __spi_alloc_controller - allocate an SPI master or slave controller 2188 * __spi_alloc_controller - allocate an SPI master or slave controller
2189 * @dev: the controller, possibly using the platform_bus 2189 * @dev: the controller, possibly using the platform_bus
2190 * @size: how much zeroed driver-private data to allocate; the pointer to this 2190 * @size: how much zeroed driver-private data to allocate; the pointer to this
2191 * memory is in the driver_data field of the returned device, 2191 * memory is in the driver_data field of the returned device, accessible
2192 * accessible with spi_controller_get_devdata(). 2192 * with spi_controller_get_devdata(); the memory is cacheline aligned;
2193 * drivers granting DMA access to portions of their private data need to
2194 * round up @size using ALIGN(size, dma_get_cache_alignment()).
2193 * @slave: flag indicating whether to allocate an SPI master (false) or SPI 2195 * @slave: flag indicating whether to allocate an SPI master (false) or SPI
2194 * slave (true) controller 2196 * slave (true) controller
2195 * Context: can sleep 2197 * Context: can sleep
@@ -2211,11 +2213,12 @@ struct spi_controller *__spi_alloc_controller(struct device *dev,
2211 unsigned int size, bool slave) 2213 unsigned int size, bool slave)
2212{ 2214{
2213 struct spi_controller *ctlr; 2215 struct spi_controller *ctlr;
2216 size_t ctlr_size = ALIGN(sizeof(*ctlr), dma_get_cache_alignment());
2214 2217
2215 if (!dev) 2218 if (!dev)
2216 return NULL; 2219 return NULL;
2217 2220
2218 ctlr = kzalloc(size + sizeof(*ctlr), GFP_KERNEL); 2221 ctlr = kzalloc(size + ctlr_size, GFP_KERNEL);
2219 if (!ctlr) 2222 if (!ctlr)
2220 return NULL; 2223 return NULL;
2221 2224
@@ -2229,14 +2232,14 @@ struct spi_controller *__spi_alloc_controller(struct device *dev,
2229 ctlr->dev.class = &spi_master_class; 2232 ctlr->dev.class = &spi_master_class;
2230 ctlr->dev.parent = dev; 2233 ctlr->dev.parent = dev;
2231 pm_suspend_ignore_children(&ctlr->dev, true); 2234 pm_suspend_ignore_children(&ctlr->dev, true);
2232 spi_controller_set_devdata(ctlr, &ctlr[1]); 2235 spi_controller_set_devdata(ctlr, (void *)ctlr + ctlr_size);
2233 2236
2234 return ctlr; 2237 return ctlr;
2235} 2238}
2236EXPORT_SYMBOL_GPL(__spi_alloc_controller); 2239EXPORT_SYMBOL_GPL(__spi_alloc_controller);
2237 2240
2238#ifdef CONFIG_OF 2241#ifdef CONFIG_OF
2239static int of_spi_register_master(struct spi_controller *ctlr) 2242static int of_spi_get_gpio_numbers(struct spi_controller *ctlr)
2240{ 2243{
2241 int nb, i, *cs; 2244 int nb, i, *cs;
2242 struct device_node *np = ctlr->dev.of_node; 2245 struct device_node *np = ctlr->dev.of_node;
@@ -2269,7 +2272,7 @@ static int of_spi_register_master(struct spi_controller *ctlr)
2269 return 0; 2272 return 0;
2270} 2273}
2271#else 2274#else
2272static int of_spi_register_master(struct spi_controller *ctlr) 2275static int of_spi_get_gpio_numbers(struct spi_controller *ctlr)
2273{ 2276{
2274 return 0; 2277 return 0;
2275} 2278}
@@ -2456,7 +2459,7 @@ int spi_register_controller(struct spi_controller *ctlr)
2456 ctlr->mode_bits |= SPI_CS_HIGH; 2459 ctlr->mode_bits |= SPI_CS_HIGH;
2457 } else { 2460 } else {
2458 /* Legacy code path for GPIOs from DT */ 2461 /* Legacy code path for GPIOs from DT */
2459 status = of_spi_register_master(ctlr); 2462 status = of_spi_get_gpio_numbers(ctlr);
2460 if (status) 2463 if (status)
2461 return status; 2464 return status;
2462 } 2465 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 00:41:34 -0400