diff options
author | Nicolin Chen <nicoleotsuka@gmail.com> | 2017-12-17 21:52:04 -0500 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2017-12-19 04:24:41 -0500 |
commit | af4f7f388242d5e63e3026a03a12e18ef4d8f62c (patch) | |
tree | c3a6ae1fd05e294ba53f8b6bc8a9315960780b84 | |
parent | a818aa5f967ba60522ee0ad181a0c5a96b65d999 (diff) |
ASoC: fsl_ssi: Refine indentations and wrappings
This patch just simply unifies the coding style.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Reviewed-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Acked-by: Timur Tabi <timur@tabi.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 239 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_ssi.h | 2 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_ssi_dbg.c | 3 |
3 files changed, 118 insertions, 126 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 24d96956b53a..ed9ac758e35d 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c | |||
@@ -69,21 +69,35 @@ | |||
69 | * samples will be written to STX properly. | 69 | * samples will be written to STX properly. |
70 | */ | 70 | */ |
71 | #ifdef __BIG_ENDIAN | 71 | #ifdef __BIG_ENDIAN |
72 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | 72 | #define FSLSSI_I2S_FORMATS \ |
73 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | 73 | (SNDRV_PCM_FMTBIT_S8 | \ |
74 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | 74 | SNDRV_PCM_FMTBIT_S16_BE | \ |
75 | SNDRV_PCM_FMTBIT_S18_3BE | \ | ||
76 | SNDRV_PCM_FMTBIT_S20_3BE | \ | ||
77 | SNDRV_PCM_FMTBIT_S24_3BE | \ | ||
78 | SNDRV_PCM_FMTBIT_S24_BE) | ||
75 | #else | 79 | #else |
76 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | 80 | #define FSLSSI_I2S_FORMATS \ |
77 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | 81 | (SNDRV_PCM_FMTBIT_S8 | \ |
78 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | 82 | SNDRV_PCM_FMTBIT_S16_LE | \ |
83 | SNDRV_PCM_FMTBIT_S18_3LE | \ | ||
84 | SNDRV_PCM_FMTBIT_S20_3LE | \ | ||
85 | SNDRV_PCM_FMTBIT_S24_3LE | \ | ||
86 | SNDRV_PCM_FMTBIT_S24_LE) | ||
79 | #endif | 87 | #endif |
80 | 88 | ||
81 | #define FSLSSI_SIER_DBG_RX_FLAGS (SSI_SIER_RFF0_EN | \ | 89 | #define FSLSSI_SIER_DBG_RX_FLAGS \ |
82 | SSI_SIER_RLS_EN | SSI_SIER_RFS_EN | \ | 90 | (SSI_SIER_RFF0_EN | \ |
83 | SSI_SIER_ROE0_EN | SSI_SIER_RFRC_EN) | 91 | SSI_SIER_RLS_EN | \ |
84 | #define FSLSSI_SIER_DBG_TX_FLAGS (SSI_SIER_TFE0_EN | \ | 92 | SSI_SIER_RFS_EN | \ |
85 | SSI_SIER_TLS_EN | SSI_SIER_TFS_EN | \ | 93 | SSI_SIER_ROE0_EN | \ |
86 | SSI_SIER_TUE0_EN | SSI_SIER_TFRC_EN) | 94 | SSI_SIER_RFRC_EN) |
95 | #define FSLSSI_SIER_DBG_TX_FLAGS \ | ||
96 | (SSI_SIER_TFE0_EN | \ | ||
97 | SSI_SIER_TLS_EN | \ | ||
98 | SSI_SIER_TFS_EN | \ | ||
99 | SSI_SIER_TUE0_EN | \ | ||
100 | SSI_SIER_TFRC_EN) | ||
87 | 101 | ||
88 | enum fsl_ssi_type { | 102 | enum fsl_ssi_type { |
89 | FSL_SSI_MCP8610, | 103 | FSL_SSI_MCP8610, |
@@ -291,8 +305,8 @@ static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { | |||
291 | .imx = false, | 305 | .imx = false, |
292 | .offline_config = true, | 306 | .offline_config = true, |
293 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | | 307 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
294 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | | 308 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
295 | SSI_SISR_TUE0 | SSI_SISR_TUE1, | 309 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
296 | }; | 310 | }; |
297 | 311 | ||
298 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { | 312 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { |
@@ -306,15 +320,15 @@ static struct fsl_ssi_soc_data fsl_ssi_imx35 = { | |||
306 | .imx = true, | 320 | .imx = true, |
307 | .offline_config = true, | 321 | .offline_config = true, |
308 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | | 322 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
309 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | | 323 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
310 | SSI_SISR_TUE0 | SSI_SISR_TUE1, | 324 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
311 | }; | 325 | }; |
312 | 326 | ||
313 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { | 327 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { |
314 | .imx = true, | 328 | .imx = true, |
315 | .offline_config = false, | 329 | .offline_config = false, |
316 | .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | | 330 | .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
317 | SSI_SISR_TUE0 | SSI_SISR_TUE1, | 331 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
318 | }; | 332 | }; |
319 | 333 | ||
320 | static const struct of_device_id fsl_ssi_ids[] = { | 334 | static const struct of_device_id fsl_ssi_ids[] = { |
@@ -376,21 +390,21 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable) | |||
376 | 390 | ||
377 | if (enable) { | 391 | if (enable) { |
378 | regmap_update_bits(regs, REG_SSI_SIER, | 392 | regmap_update_bits(regs, REG_SSI_SIER, |
379 | vals->rx.sier | vals->tx.sier, | 393 | vals->rx.sier | vals->tx.sier, |
380 | vals->rx.sier | vals->tx.sier); | 394 | vals->rx.sier | vals->tx.sier); |
381 | regmap_update_bits(regs, REG_SSI_SRCR, | 395 | regmap_update_bits(regs, REG_SSI_SRCR, |
382 | vals->rx.srcr | vals->tx.srcr, | 396 | vals->rx.srcr | vals->tx.srcr, |
383 | vals->rx.srcr | vals->tx.srcr); | 397 | vals->rx.srcr | vals->tx.srcr); |
384 | regmap_update_bits(regs, REG_SSI_STCR, | 398 | regmap_update_bits(regs, REG_SSI_STCR, |
385 | vals->rx.stcr | vals->tx.stcr, | 399 | vals->rx.stcr | vals->tx.stcr, |
386 | vals->rx.stcr | vals->tx.stcr); | 400 | vals->rx.stcr | vals->tx.stcr); |
387 | } else { | 401 | } else { |
388 | regmap_update_bits(regs, REG_SSI_SRCR, | 402 | regmap_update_bits(regs, REG_SSI_SRCR, |
389 | vals->rx.srcr | vals->tx.srcr, 0); | 403 | vals->rx.srcr | vals->tx.srcr, 0); |
390 | regmap_update_bits(regs, REG_SSI_STCR, | 404 | regmap_update_bits(regs, REG_SSI_STCR, |
391 | vals->rx.stcr | vals->tx.stcr, 0); | 405 | vals->rx.stcr | vals->tx.stcr, 0); |
392 | regmap_update_bits(regs, REG_SSI_SIER, | 406 | regmap_update_bits(regs, REG_SSI_SIER, |
393 | vals->rx.sier | vals->tx.sier, 0); | 407 | vals->rx.sier | vals->tx.sier, 0); |
394 | } | 408 | } |
395 | } | 409 | } |
396 | 410 | ||
@@ -401,10 +415,10 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) | |||
401 | { | 415 | { |
402 | if (is_rx) { | 416 | if (is_rx) { |
403 | regmap_update_bits(ssi->regs, REG_SSI_SOR, | 417 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
404 | SSI_SOR_RX_CLR, SSI_SOR_RX_CLR); | 418 | SSI_SOR_RX_CLR, SSI_SOR_RX_CLR); |
405 | } else { | 419 | } else { |
406 | regmap_update_bits(ssi->regs, REG_SSI_SOR, | 420 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
407 | SSI_SOR_TX_CLR, SSI_SOR_TX_CLR); | 421 | SSI_SOR_TX_CLR, SSI_SOR_TX_CLR); |
408 | } | 422 | } |
409 | } | 423 | } |
410 | 424 | ||
@@ -432,7 +446,7 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) | |||
432 | * Enable or disable SSI configuration. | 446 | * Enable or disable SSI configuration. |
433 | */ | 447 | */ |
434 | static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, | 448 | static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, |
435 | struct fsl_ssi_reg_val *vals) | 449 | struct fsl_ssi_reg_val *vals) |
436 | { | 450 | { |
437 | struct regmap *regs = ssi->regs; | 451 | struct regmap *regs = ssi->regs; |
438 | struct fsl_ssi_reg_val *avals; | 452 | struct fsl_ssi_reg_val *avals; |
@@ -442,8 +456,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, | |||
442 | 456 | ||
443 | regmap_read(regs, REG_SSI_SCR, &scr_val); | 457 | regmap_read(regs, REG_SSI_SCR, &scr_val); |
444 | 458 | ||
445 | nr_active_streams = !!(scr_val & SSI_SCR_TE) + | 459 | nr_active_streams = !!(scr_val & SSI_SCR_TE) + !!(scr_val & SSI_SCR_RE); |
446 | !!(scr_val & SSI_SCR_RE); | ||
447 | 460 | ||
448 | if (nr_active_streams - 1 > 0) | 461 | if (nr_active_streams - 1 > 0) |
449 | keep_active = 1; | 462 | keep_active = 1; |
@@ -462,7 +475,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, | |||
462 | * both streams, and get safe bits to disable current stream | 475 | * both streams, and get safe bits to disable current stream |
463 | */ | 476 | */ |
464 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, | 477 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
465 | keep_active); | 478 | keep_active); |
466 | /* Safely disable SCR register for the stream */ | 479 | /* Safely disable SCR register for the stream */ |
467 | regmap_update_bits(regs, REG_SSI_SCR, scr, 0); | 480 | regmap_update_bits(regs, REG_SSI_SCR, scr, 0); |
468 | } | 481 | } |
@@ -474,8 +487,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, | |||
474 | * 2) Disable all remaining bits of both streams when last stream ends | 487 | * 2) Disable all remaining bits of both streams when last stream ends |
475 | */ | 488 | */ |
476 | if (ssi->soc->offline_config) { | 489 | if (ssi->soc->offline_config) { |
477 | if ((enable && !nr_active_streams) || | 490 | if ((enable && !nr_active_streams) || (!enable && !keep_active)) |
478 | (!enable && !keep_active)) | ||
479 | fsl_ssi_rxtx_config(ssi, enable); | 491 | fsl_ssi_rxtx_config(ssi, enable); |
480 | 492 | ||
481 | goto config_done; | 493 | goto config_done; |
@@ -498,11 +510,11 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, | |||
498 | * both streams, and get safe bits to disable current stream | 510 | * both streams, and get safe bits to disable current stream |
499 | */ | 511 | */ |
500 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, | 512 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
501 | keep_active); | 513 | keep_active); |
502 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | 514 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, |
503 | keep_active); | 515 | keep_active); |
504 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | 516 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, |
505 | keep_active); | 517 | keep_active); |
506 | 518 | ||
507 | /* Safely disable other control registers for the stream */ | 519 | /* Safely disable other control registers for the stream */ |
508 | regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0); | 520 | regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0); |
@@ -525,7 +537,7 @@ config_done: | |||
525 | 537 | ||
526 | /* Enable SSI first to send TX DMA request */ | 538 | /* Enable SSI first to send TX DMA request */ |
527 | regmap_update_bits(regs, REG_SSI_SCR, | 539 | regmap_update_bits(regs, REG_SSI_SCR, |
528 | SSI_SCR_SSIEN, SSI_SCR_SSIEN); | 540 | SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
529 | 541 | ||
530 | /* Busy wait until TX FIFO not empty -- DMA working */ | 542 | /* Busy wait until TX FIFO not empty -- DMA working */ |
531 | for (i = 0; i < max_loop; i++) { | 543 | for (i = 0; i < max_loop; i++) { |
@@ -544,7 +556,6 @@ config_done: | |||
544 | } | 556 | } |
545 | } | 557 | } |
546 | 558 | ||
547 | |||
548 | static void fsl_ssi_rx_config(struct fsl_ssi *ssi, bool enable) | 559 | static void fsl_ssi_rx_config(struct fsl_ssi *ssi, bool enable) |
549 | { | 560 | { |
550 | fsl_ssi_config(ssi, enable, &ssi->rxtx_reg_val.rx); | 561 | fsl_ssi_config(ssi, enable, &ssi->rxtx_reg_val.rx); |
@@ -615,19 +626,16 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) | |||
615 | struct regmap *regs = ssi->regs; | 626 | struct regmap *regs = ssi->regs; |
616 | 627 | ||
617 | /* Setup the clock control register */ | 628 | /* Setup the clock control register */ |
618 | regmap_write(regs, REG_SSI_STCCR, | 629 | regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
619 | SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); | 630 | regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
620 | regmap_write(regs, REG_SSI_SRCCR, | ||
621 | SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); | ||
622 | 631 | ||
623 | /* Enable AC97 mode and startup the SSI */ | 632 | /* Enable AC97 mode and startup the SSI */ |
624 | regmap_write(regs, REG_SSI_SACNT, | 633 | regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); |
625 | SSI_SACNT_AC97EN | SSI_SACNT_FV); | ||
626 | 634 | ||
627 | /* AC97 has to communicate with codec before starting a stream */ | 635 | /* AC97 has to communicate with codec before starting a stream */ |
628 | regmap_update_bits(regs, REG_SSI_SCR, | 636 | regmap_update_bits(regs, REG_SSI_SCR, |
629 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, | 637 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, |
630 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); | 638 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); |
631 | 639 | ||
632 | regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); | 640 | regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); |
633 | } | 641 | } |
@@ -651,19 +659,18 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream, | |||
651 | */ | 659 | */ |
652 | if (ssi->use_dual_fifo) | 660 | if (ssi->use_dual_fifo) |
653 | snd_pcm_hw_constraint_step(substream->runtime, 0, | 661 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
654 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | 662 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
655 | 663 | ||
656 | return 0; | 664 | return 0; |
657 | } | 665 | } |
658 | 666 | ||
659 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, | 667 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
660 | struct snd_soc_dai *dai) | 668 | struct snd_soc_dai *dai) |
661 | { | 669 | { |
662 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 670 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
663 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); | 671 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
664 | 672 | ||
665 | clk_disable_unprepare(ssi->clk); | 673 | clk_disable_unprepare(ssi->clk); |
666 | |||
667 | } | 674 | } |
668 | 675 | ||
669 | /** | 676 | /** |
@@ -676,8 +683,8 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, | |||
676 | * (In 2-channel I2S Master mode, slot_width is fixed 32) | 683 | * (In 2-channel I2S Master mode, slot_width is fixed 32) |
677 | */ | 684 | */ |
678 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, | 685 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
679 | struct snd_soc_dai *cpu_dai, | 686 | struct snd_soc_dai *cpu_dai, |
680 | struct snd_pcm_hw_params *hw_params) | 687 | struct snd_pcm_hw_params *hw_params) |
681 | { | 688 | { |
682 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); | 689 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); |
683 | struct regmap *regs = ssi->regs; | 690 | struct regmap *regs = ssi->regs; |
@@ -764,8 +771,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, | |||
764 | 771 | ||
765 | stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | | 772 | stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | |
766 | (psr ? SSI_SxCCR_PSR : 0); | 773 | (psr ? SSI_SxCCR_PSR : 0); |
767 | mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | | 774 | mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; |
768 | SSI_SxCCR_PSR; | ||
769 | 775 | ||
770 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) | 776 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) |
771 | regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr); | 777 | regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr); |
@@ -795,7 +801,8 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, | |||
795 | * fsl_ssi_set_bclk() if SSI is the DAI clock master. | 801 | * fsl_ssi_set_bclk() if SSI is the DAI clock master. |
796 | */ | 802 | */ |
797 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, | 803 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
798 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | 804 | struct snd_pcm_hw_params *hw_params, |
805 | struct snd_soc_dai *cpu_dai) | ||
799 | { | 806 | { |
800 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); | 807 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); |
801 | struct regmap *regs = ssi->regs; | 808 | struct regmap *regs = ssi->regs; |
@@ -837,36 +844,33 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, | |||
837 | u8 i2smode; | 844 | u8 i2smode; |
838 | /* Normal + Network mode to send 16-bit data in 32-bit frames */ | 845 | /* Normal + Network mode to send 16-bit data in 32-bit frames */ |
839 | if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) | 846 | if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) |
840 | i2smode = SSI_SCR_I2S_MODE_NORMAL | | 847 | i2smode = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; |
841 | SSI_SCR_NET; | ||
842 | else | 848 | else |
843 | i2smode = ssi->i2s_mode; | 849 | i2smode = ssi->i2s_mode; |
844 | 850 | ||
845 | regmap_update_bits(regs, REG_SSI_SCR, | 851 | regmap_update_bits(regs, REG_SSI_SCR, |
846 | SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK, | 852 | SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK, |
847 | channels == 1 ? 0 : i2smode); | 853 | channels == 1 ? 0 : i2smode); |
848 | } | 854 | } |
849 | 855 | ||
850 | /* In synchronous mode, the SSI uses STCCR for capture */ | 856 | /* In synchronous mode, the SSI uses STCCR for capture */ |
851 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | 857 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || |
852 | ssi->cpu_dai_drv.symmetric_rates) | 858 | ssi->cpu_dai_drv.symmetric_rates) |
853 | regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, | 859 | regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK, wl); |
854 | wl); | ||
855 | else | 860 | else |
856 | regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, | 861 | regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK, wl); |
857 | wl); | ||
858 | 862 | ||
859 | return 0; | 863 | return 0; |
860 | } | 864 | } |
861 | 865 | ||
862 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, | 866 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
863 | struct snd_soc_dai *cpu_dai) | 867 | struct snd_soc_dai *cpu_dai) |
864 | { | 868 | { |
865 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | 869 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
866 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); | 870 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
867 | 871 | ||
868 | if (fsl_ssi_is_i2s_master(ssi) && | 872 | if (fsl_ssi_is_i2s_master(ssi) && |
869 | ssi->baudclk_streams & BIT(substream->stream)) { | 873 | ssi->baudclk_streams & BIT(substream->stream)) { |
870 | clk_disable_unprepare(ssi->baudclk); | 874 | clk_disable_unprepare(ssi->baudclk); |
871 | ssi->baudclk_streams &= ~BIT(substream->stream); | 875 | ssi->baudclk_streams &= ~BIT(substream->stream); |
872 | } | 876 | } |
@@ -896,8 +900,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, | |||
896 | scr |= SSI_SCR_SYNC_TX_FS; | 900 | scr |= SSI_SCR_SYNC_TX_FS; |
897 | 901 | ||
898 | mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR | | 902 | mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR | |
899 | SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL | | 903 | SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL | SSI_STCR_TEFS; |
900 | SSI_STCR_TEFS; | ||
901 | regmap_read(regs, REG_SSI_STCR, &stcr); | 904 | regmap_read(regs, REG_SSI_STCR, &stcr); |
902 | regmap_read(regs, REG_SSI_SRCR, &srcr); | 905 | regmap_read(regs, REG_SSI_SRCR, &srcr); |
903 | stcr &= ~mask; | 906 | stcr &= ~mask; |
@@ -908,11 +911,9 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, | |||
908 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | 911 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
909 | case SND_SOC_DAIFMT_I2S: | 912 | case SND_SOC_DAIFMT_I2S: |
910 | regmap_update_bits(regs, REG_SSI_STCCR, | 913 | regmap_update_bits(regs, REG_SSI_STCCR, |
911 | SSI_SxCCR_DC_MASK, | 914 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); |
912 | SSI_SxCCR_DC(2)); | ||
913 | regmap_update_bits(regs, REG_SSI_SRCCR, | 915 | regmap_update_bits(regs, REG_SSI_SRCCR, |
914 | SSI_SxCCR_DC_MASK, | 916 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); |
915 | SSI_SxCCR_DC(2)); | ||
916 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | 917 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
917 | case SND_SOC_DAIFMT_CBM_CFS: | 918 | case SND_SOC_DAIFMT_CBM_CFS: |
918 | case SND_SOC_DAIFMT_CBS_CFS: | 919 | case SND_SOC_DAIFMT_CBS_CFS: |
@@ -927,7 +928,7 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, | |||
927 | 928 | ||
928 | /* Data on rising edge of bclk, frame low, 1clk before data */ | 929 | /* Data on rising edge of bclk, frame low, 1clk before data */ |
929 | strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | | 930 | strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | |
930 | SSI_STCR_TXBIT0 | SSI_STCR_TEFS; | 931 | SSI_STCR_TXBIT0 | SSI_STCR_TEFS; |
931 | break; | 932 | break; |
932 | case SND_SOC_DAIFMT_LEFT_J: | 933 | case SND_SOC_DAIFMT_LEFT_J: |
933 | /* Data on rising edge of bclk, frame high */ | 934 | /* Data on rising edge of bclk, frame high */ |
@@ -936,12 +937,11 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, | |||
936 | case SND_SOC_DAIFMT_DSP_A: | 937 | case SND_SOC_DAIFMT_DSP_A: |
937 | /* Data on rising edge of bclk, frame high, 1clk before data */ | 938 | /* Data on rising edge of bclk, frame high, 1clk before data */ |
938 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | | 939 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | |
939 | SSI_STCR_TXBIT0 | SSI_STCR_TEFS; | 940 | SSI_STCR_TXBIT0 | SSI_STCR_TEFS; |
940 | break; | 941 | break; |
941 | case SND_SOC_DAIFMT_DSP_B: | 942 | case SND_SOC_DAIFMT_DSP_B: |
942 | /* Data on rising edge of bclk, frame high */ | 943 | /* Data on rising edge of bclk, frame high */ |
943 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | | 944 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TXBIT0; |
944 | SSI_STCR_TXBIT0; | ||
945 | break; | 945 | break; |
946 | case SND_SOC_DAIFMT_AC97: | 946 | case SND_SOC_DAIFMT_AC97: |
947 | /* Data on falling edge of bclk, frame high, 1clk before data */ | 947 | /* Data on falling edge of bclk, frame high, 1clk before data */ |
@@ -1012,23 +1012,22 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev, | |||
1012 | wm = ssi->fifo_watermark; | 1012 | wm = ssi->fifo_watermark; |
1013 | 1013 | ||
1014 | regmap_write(regs, REG_SSI_SFCSR, | 1014 | regmap_write(regs, REG_SSI_SFCSR, |
1015 | SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | | 1015 | SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | |
1016 | SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); | 1016 | SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); |
1017 | 1017 | ||
1018 | if (ssi->use_dual_fifo) { | 1018 | if (ssi->use_dual_fifo) { |
1019 | regmap_update_bits(regs, REG_SSI_SRCR, SSI_SRCR_RFEN1, | 1019 | regmap_update_bits(regs, REG_SSI_SRCR, |
1020 | SSI_SRCR_RFEN1); | 1020 | SSI_SRCR_RFEN1, SSI_SRCR_RFEN1); |
1021 | regmap_update_bits(regs, REG_SSI_STCR, SSI_STCR_TFEN1, | 1021 | regmap_update_bits(regs, REG_SSI_STCR, |
1022 | SSI_STCR_TFEN1); | 1022 | SSI_STCR_TFEN1, SSI_STCR_TFEN1); |
1023 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_TCH_EN, | 1023 | regmap_update_bits(regs, REG_SSI_SCR, |
1024 | SSI_SCR_TCH_EN); | 1024 | SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); |
1025 | } | 1025 | } |
1026 | 1026 | ||
1027 | if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) | 1027 | if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) |
1028 | fsl_ssi_setup_ac97(ssi); | 1028 | fsl_ssi_setup_ac97(ssi); |
1029 | 1029 | ||
1030 | return 0; | 1030 | return 0; |
1031 | |||
1032 | } | 1031 | } |
1033 | 1032 | ||
1034 | /** | 1033 | /** |
@@ -1049,7 +1048,7 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |||
1049 | * Set TDM slot number and slot width | 1048 | * Set TDM slot number and slot width |
1050 | */ | 1049 | */ |
1051 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | 1050 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
1052 | u32 rx_mask, int slots, int slot_width) | 1051 | u32 rx_mask, int slots, int slot_width) |
1053 | { | 1052 | { |
1054 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); | 1053 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); |
1055 | struct regmap *regs = ssi->regs; | 1054 | struct regmap *regs = ssi->regs; |
@@ -1069,17 +1068,16 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |||
1069 | return -EINVAL; | 1068 | return -EINVAL; |
1070 | } | 1069 | } |
1071 | 1070 | ||
1072 | regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_DC_MASK, | 1071 | regmap_update_bits(regs, REG_SSI_STCCR, |
1073 | SSI_SxCCR_DC(slots)); | 1072 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
1074 | regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_DC_MASK, | 1073 | regmap_update_bits(regs, REG_SSI_SRCCR, |
1075 | SSI_SxCCR_DC(slots)); | 1074 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
1076 | 1075 | ||
1077 | /* Save SSIEN bit of the SCR register */ | 1076 | /* Save SSIEN bit of the SCR register */ |
1078 | regmap_read(regs, REG_SSI_SCR, &val); | 1077 | regmap_read(regs, REG_SSI_SCR, &val); |
1079 | val &= SSI_SCR_SSIEN; | 1078 | val &= SSI_SCR_SSIEN; |
1080 | /* Temporarily enable SSI to allow SxMSKs to be configurable */ | 1079 | /* Temporarily enable SSI to allow SxMSKs to be configurable */ |
1081 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, | 1080 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
1082 | SSI_SCR_SSIEN); | ||
1083 | 1081 | ||
1084 | regmap_write(regs, REG_SSI_STMSK, ~tx_mask); | 1082 | regmap_write(regs, REG_SSI_STMSK, ~tx_mask); |
1085 | regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); | 1083 | regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); |
@@ -1153,13 +1151,13 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) | |||
1153 | } | 1151 | } |
1154 | 1152 | ||
1155 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { | 1153 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
1156 | .startup = fsl_ssi_startup, | 1154 | .startup = fsl_ssi_startup, |
1157 | .shutdown = fsl_ssi_shutdown, | 1155 | .shutdown = fsl_ssi_shutdown, |
1158 | .hw_params = fsl_ssi_hw_params, | 1156 | .hw_params = fsl_ssi_hw_params, |
1159 | .hw_free = fsl_ssi_hw_free, | 1157 | .hw_free = fsl_ssi_hw_free, |
1160 | .set_fmt = fsl_ssi_set_dai_fmt, | 1158 | .set_fmt = fsl_ssi_set_dai_fmt, |
1161 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | 1159 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, |
1162 | .trigger = fsl_ssi_trigger, | 1160 | .trigger = fsl_ssi_trigger, |
1163 | }; | 1161 | }; |
1164 | 1162 | ||
1165 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | 1163 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { |
@@ -1182,7 +1180,7 @@ static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |||
1182 | }; | 1180 | }; |
1183 | 1181 | ||
1184 | static const struct snd_soc_component_driver fsl_ssi_component = { | 1182 | static const struct snd_soc_component_driver fsl_ssi_component = { |
1185 | .name = "fsl-ssi", | 1183 | .name = "fsl-ssi", |
1186 | }; | 1184 | }; |
1187 | 1185 | ||
1188 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { | 1186 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
@@ -1206,11 +1204,10 @@ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { | |||
1206 | .ops = &fsl_ssi_dai_ops, | 1204 | .ops = &fsl_ssi_dai_ops, |
1207 | }; | 1205 | }; |
1208 | 1206 | ||
1209 | |||
1210 | static struct fsl_ssi *fsl_ac97_data; | 1207 | static struct fsl_ssi *fsl_ac97_data; |
1211 | 1208 | ||
1212 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | 1209 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
1213 | unsigned short val) | 1210 | unsigned short val) |
1214 | { | 1211 | { |
1215 | struct regmap *regs = fsl_ac97_data->regs; | 1212 | struct regmap *regs = fsl_ac97_data->regs; |
1216 | unsigned int lreg; | 1213 | unsigned int lreg; |
@@ -1235,8 +1232,8 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |||
1235 | lval = val << 4; | 1232 | lval = val << 4; |
1236 | regmap_write(regs, REG_SSI_SACDAT, lval); | 1233 | regmap_write(regs, REG_SSI_SACDAT, lval); |
1237 | 1234 | ||
1238 | regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK, | 1235 | regmap_update_bits(regs, REG_SSI_SACNT, |
1239 | SSI_SACNT_WR); | 1236 | SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); |
1240 | udelay(100); | 1237 | udelay(100); |
1241 | 1238 | ||
1242 | clk_disable_unprepare(fsl_ac97_data->clk); | 1239 | clk_disable_unprepare(fsl_ac97_data->clk); |
@@ -1246,10 +1243,9 @@ ret_unlock: | |||
1246 | } | 1243 | } |
1247 | 1244 | ||
1248 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, | 1245 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
1249 | unsigned short reg) | 1246 | unsigned short reg) |
1250 | { | 1247 | { |
1251 | struct regmap *regs = fsl_ac97_data->regs; | 1248 | struct regmap *regs = fsl_ac97_data->regs; |
1252 | |||
1253 | unsigned short val = 0; | 1249 | unsigned short val = 0; |
1254 | u32 reg_val; | 1250 | u32 reg_val; |
1255 | unsigned int lreg; | 1251 | unsigned int lreg; |
@@ -1259,15 +1255,14 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, | |||
1259 | 1255 | ||
1260 | ret = clk_prepare_enable(fsl_ac97_data->clk); | 1256 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
1261 | if (ret) { | 1257 | if (ret) { |
1262 | pr_err("ac97 read clk_prepare_enable failed: %d\n", | 1258 | pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); |
1263 | ret); | ||
1264 | goto ret_unlock; | 1259 | goto ret_unlock; |
1265 | } | 1260 | } |
1266 | 1261 | ||
1267 | lreg = (reg & 0x7f) << 12; | 1262 | lreg = (reg & 0x7f) << 12; |
1268 | regmap_write(regs, REG_SSI_SACADD, lreg); | 1263 | regmap_write(regs, REG_SSI_SACADD, lreg); |
1269 | regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK, | 1264 | regmap_update_bits(regs, REG_SSI_SACNT, |
1270 | SSI_SACNT_RD); | 1265 | SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); |
1271 | 1266 | ||
1272 | udelay(100); | 1267 | udelay(100); |
1273 | 1268 | ||
@@ -1282,8 +1277,8 @@ ret_unlock: | |||
1282 | } | 1277 | } |
1283 | 1278 | ||
1284 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | 1279 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { |
1285 | .read = fsl_ssi_ac97_read, | 1280 | .read = fsl_ssi_ac97_read, |
1286 | .write = fsl_ssi_ac97_write, | 1281 | .write = fsl_ssi_ac97_write, |
1287 | }; | 1282 | }; |
1288 | 1283 | ||
1289 | /** | 1284 | /** |
@@ -1298,7 +1293,7 @@ static void make_lowercase(char *s) | |||
1298 | } | 1293 | } |
1299 | 1294 | ||
1300 | static int fsl_ssi_imx_probe(struct platform_device *pdev, | 1295 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
1301 | struct fsl_ssi *ssi, void __iomem *iomem) | 1296 | struct fsl_ssi *ssi, void __iomem *iomem) |
1302 | { | 1297 | { |
1303 | struct device_node *np = pdev->dev.of_node; | 1298 | struct device_node *np = pdev->dev.of_node; |
1304 | struct device *dev = &pdev->dev; | 1299 | struct device *dev = &pdev->dev; |
@@ -1370,14 +1365,13 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, | |||
1370 | return 0; | 1365 | return 0; |
1371 | 1366 | ||
1372 | error_pcm: | 1367 | error_pcm: |
1373 | |||
1374 | if (!ssi->has_ipg_clk_name) | 1368 | if (!ssi->has_ipg_clk_name) |
1375 | clk_disable_unprepare(ssi->clk); | 1369 | clk_disable_unprepare(ssi->clk); |
1370 | |||
1376 | return ret; | 1371 | return ret; |
1377 | } | 1372 | } |
1378 | 1373 | ||
1379 | static void fsl_ssi_imx_clean(struct platform_device *pdev, | 1374 | static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) |
1380 | struct fsl_ssi *ssi) | ||
1381 | { | 1375 | { |
1382 | if (!ssi->use_dma) | 1376 | if (!ssi->use_dma) |
1383 | imx_pcm_fiq_exit(pdev); | 1377 | imx_pcm_fiq_exit(pdev); |
@@ -1422,8 +1416,7 @@ static int fsl_ssi_probe(struct platform_device *pdev) | |||
1422 | 1416 | ||
1423 | if (fsl_ssi_is_ac97(ssi)) { | 1417 | if (fsl_ssi_is_ac97(ssi)) { |
1424 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, | 1418 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, |
1425 | sizeof(fsl_ssi_ac97_dai)); | 1419 | sizeof(fsl_ssi_ac97_dai)); |
1426 | |||
1427 | fsl_ac97_data = ssi; | 1420 | fsl_ac97_data = ssi; |
1428 | } else { | 1421 | } else { |
1429 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, | 1422 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, |
@@ -1582,8 +1575,8 @@ done: | |||
1582 | goto error_sound_card; | 1575 | goto error_sound_card; |
1583 | } | 1576 | } |
1584 | 1577 | ||
1585 | ssi->pdev = platform_device_register_data(NULL, | 1578 | ssi->pdev = platform_device_register_data(NULL, "ac97-codec", |
1586 | "ac97-codec", ssi_idx, NULL, 0); | 1579 | ssi_idx, NULL, 0); |
1587 | if (IS_ERR(ssi->pdev)) { | 1580 | if (IS_ERR(ssi->pdev)) { |
1588 | ret = PTR_ERR(ssi->pdev); | 1581 | ret = PTR_ERR(ssi->pdev); |
1589 | dev_err(dev, | 1582 | dev_err(dev, |
@@ -1597,11 +1590,9 @@ done: | |||
1597 | 1590 | ||
1598 | error_sound_card: | 1591 | error_sound_card: |
1599 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); | 1592 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
1600 | |||
1601 | error_asoc_register: | 1593 | error_asoc_register: |
1602 | if (fsl_ssi_is_ac97(ssi)) | 1594 | if (fsl_ssi_is_ac97(ssi)) |
1603 | snd_soc_set_ac97_ops(NULL); | 1595 | snd_soc_set_ac97_ops(NULL); |
1604 | |||
1605 | error_ac97_ops: | 1596 | error_ac97_ops: |
1606 | if (fsl_ssi_is_ac97(ssi)) | 1597 | if (fsl_ssi_is_ac97(ssi)) |
1607 | mutex_destroy(&ssi->ac97_reg_lock); | 1598 | mutex_destroy(&ssi->ac97_reg_lock); |
@@ -1655,9 +1646,9 @@ static int fsl_ssi_resume(struct device *dev) | |||
1655 | regcache_cache_only(regs, false); | 1646 | regcache_cache_only(regs, false); |
1656 | 1647 | ||
1657 | regmap_update_bits(regs, REG_SSI_SFCSR, | 1648 | regmap_update_bits(regs, REG_SSI_SFCSR, |
1658 | SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | | 1649 | SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | |
1659 | SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, | 1650 | SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, |
1660 | ssi->regcache_sfcsr); | 1651 | ssi->regcache_sfcsr); |
1661 | regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); | 1652 | regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); |
1662 | 1653 | ||
1663 | return regcache_sync(regs); | 1654 | return regcache_sync(regs); |
diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h index cdcf3d23873e..fe38e6913f96 100644 --- a/sound/soc/fsl/fsl_ssi.h +++ b/sound/soc/fsl/fsl_ssi.h | |||
@@ -310,7 +310,7 @@ static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr) | |||
310 | } | 310 | } |
311 | 311 | ||
312 | static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, | 312 | static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, |
313 | struct device *dev) | 313 | struct device *dev) |
314 | { | 314 | { |
315 | return 0; | 315 | return 0; |
316 | } | 316 | } |
diff --git a/sound/soc/fsl/fsl_ssi_dbg.c b/sound/soc/fsl/fsl_ssi_dbg.c index 362df91420f6..7aac63e2c561 100644 --- a/sound/soc/fsl/fsl_ssi_dbg.c +++ b/sound/soc/fsl/fsl_ssi_dbg.c | |||
@@ -147,7 +147,8 @@ int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev) | |||
147 | return -ENOMEM; | 147 | return -ENOMEM; |
148 | 148 | ||
149 | ssi_dbg->dbg_stats = debugfs_create_file("stats", S_IRUGO, | 149 | ssi_dbg->dbg_stats = debugfs_create_file("stats", S_IRUGO, |
150 | ssi_dbg->dbg_dir, ssi_dbg, &fsl_ssi_stats_ops); | 150 | ssi_dbg->dbg_dir, ssi_dbg, |
151 | &fsl_ssi_stats_ops); | ||
151 | if (!ssi_dbg->dbg_stats) { | 152 | if (!ssi_dbg->dbg_stats) { |
152 | debugfs_remove(ssi_dbg->dbg_dir); | 153 | debugfs_remove(ssi_dbg->dbg_dir); |
153 | return -ENOMEM; | 154 | return -ENOMEM; |