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authorNicolin Chen <nicoleotsuka@gmail.com>2017-12-17 21:52:03 -0500
committerMark Brown <broonie@kernel.org>2017-12-19 04:24:36 -0500
commita818aa5f967ba60522ee0ad181a0c5a96b65d999 (patch)
tree163d61b8ab6315a5d9b3e82f4e79b89b3d57eabc
parent7a8fceb74de407f65201f3eaaee35377c2b71dbb (diff)
ASoC: fsl_ssi: Rename registers and fields macros
This patch renames CCSR_SSI_xxx to REG_SSI_xxx and SSI_xxx_yyy style. It also slightly reduces the length of them to save some space. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Reviewed-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Acked-by: Timur Tabi <timur@tabi.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--sound/soc/fsl/fsl_ssi.c374
-rw-r--r--sound/soc/fsl/fsl_ssi.h376
-rw-r--r--sound/soc/fsl/fsl_ssi_dbg.c44
3 files changed, 397 insertions, 397 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index ff1827a074be..24d96956b53a 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -78,12 +78,12 @@
78 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 78 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
79#endif 79#endif
80 80
81#define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 81#define FSLSSI_SIER_DBG_RX_FLAGS (SSI_SIER_RFF0_EN | \
82 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 82 SSI_SIER_RLS_EN | SSI_SIER_RFS_EN | \
83 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 83 SSI_SIER_ROE0_EN | SSI_SIER_RFRC_EN)
84#define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 84#define FSLSSI_SIER_DBG_TX_FLAGS (SSI_SIER_TFE0_EN | \
85 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 85 SSI_SIER_TLS_EN | SSI_SIER_TFS_EN | \
86 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 86 SSI_SIER_TUE0_EN | SSI_SIER_TFRC_EN)
87 87
88enum fsl_ssi_type { 88enum fsl_ssi_type {
89 FSL_SSI_MCP8610, 89 FSL_SSI_MCP8610,
@@ -107,8 +107,8 @@ struct fsl_ssi_rxtx_reg_val {
107static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 107static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
108{ 108{
109 switch (reg) { 109 switch (reg) {
110 case CCSR_SSI_SACCEN: 110 case REG_SSI_SACCEN:
111 case CCSR_SSI_SACCDIS: 111 case REG_SSI_SACCDIS:
112 return false; 112 return false;
113 default: 113 default:
114 return true; 114 return true;
@@ -118,18 +118,18 @@ static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
118static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 118static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
119{ 119{
120 switch (reg) { 120 switch (reg) {
121 case CCSR_SSI_STX0: 121 case REG_SSI_STX0:
122 case CCSR_SSI_STX1: 122 case REG_SSI_STX1:
123 case CCSR_SSI_SRX0: 123 case REG_SSI_SRX0:
124 case CCSR_SSI_SRX1: 124 case REG_SSI_SRX1:
125 case CCSR_SSI_SISR: 125 case REG_SSI_SISR:
126 case CCSR_SSI_SFCSR: 126 case REG_SSI_SFCSR:
127 case CCSR_SSI_SACNT: 127 case REG_SSI_SACNT:
128 case CCSR_SSI_SACADD: 128 case REG_SSI_SACADD:
129 case CCSR_SSI_SACDAT: 129 case REG_SSI_SACDAT:
130 case CCSR_SSI_SATAG: 130 case REG_SSI_SATAG:
131 case CCSR_SSI_SACCST: 131 case REG_SSI_SACCST:
132 case CCSR_SSI_SOR: 132 case REG_SSI_SOR:
133 return true; 133 return true;
134 default: 134 default:
135 return false; 135 return false;
@@ -139,12 +139,12 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
139static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 139static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
140{ 140{
141 switch (reg) { 141 switch (reg) {
142 case CCSR_SSI_SRX0: 142 case REG_SSI_SRX0:
143 case CCSR_SSI_SRX1: 143 case REG_SSI_SRX1:
144 case CCSR_SSI_SISR: 144 case REG_SSI_SISR:
145 case CCSR_SSI_SACADD: 145 case REG_SSI_SACADD:
146 case CCSR_SSI_SACDAT: 146 case REG_SSI_SACDAT:
147 case CCSR_SSI_SATAG: 147 case REG_SSI_SATAG:
148 return true; 148 return true;
149 default: 149 default:
150 return false; 150 return false;
@@ -154,9 +154,9 @@ static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
154static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 154static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
155{ 155{
156 switch (reg) { 156 switch (reg) {
157 case CCSR_SSI_SRX0: 157 case REG_SSI_SRX0:
158 case CCSR_SSI_SRX1: 158 case REG_SSI_SRX1:
159 case CCSR_SSI_SACCST: 159 case REG_SSI_SACCST:
160 return false; 160 return false;
161 default: 161 default:
162 return true; 162 return true;
@@ -164,12 +164,12 @@ static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
164} 164}
165 165
166static const struct regmap_config fsl_ssi_regconfig = { 166static const struct regmap_config fsl_ssi_regconfig = {
167 .max_register = CCSR_SSI_SACCDIS, 167 .max_register = REG_SSI_SACCDIS,
168 .reg_bits = 32, 168 .reg_bits = 32,
169 .val_bits = 32, 169 .val_bits = 32,
170 .reg_stride = 4, 170 .reg_stride = 4,
171 .val_format_endian = REGMAP_ENDIAN_NATIVE, 171 .val_format_endian = REGMAP_ENDIAN_NATIVE,
172 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1, 172 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1,
173 .readable_reg = fsl_ssi_readable_reg, 173 .readable_reg = fsl_ssi_readable_reg,
174 .volatile_reg = fsl_ssi_volatile_reg, 174 .volatile_reg = fsl_ssi_volatile_reg,
175 .precious_reg = fsl_ssi_precious_reg, 175 .precious_reg = fsl_ssi_precious_reg,
@@ -290,9 +290,9 @@ struct fsl_ssi {
290static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 290static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
291 .imx = false, 291 .imx = false,
292 .offline_config = true, 292 .offline_config = true,
293 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 293 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
294 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 294 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
295 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 295 SSI_SISR_TUE0 | SSI_SISR_TUE1,
296}; 296};
297 297
298static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 298static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
@@ -305,16 +305,16 @@ static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
305static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 305static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
306 .imx = true, 306 .imx = true,
307 .offline_config = true, 307 .offline_config = true,
308 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 308 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC |
309 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 309 SSI_SISR_ROE0 | SSI_SISR_ROE1 |
310 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 310 SSI_SISR_TUE0 | SSI_SISR_TUE1,
311}; 311};
312 312
313static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 313static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
314 .imx = true, 314 .imx = true,
315 .offline_config = false, 315 .offline_config = false,
316 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 316 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 |
317 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 317 SSI_SISR_TUE0 | SSI_SISR_TUE1,
318}; 318};
319 319
320static const struct of_device_id fsl_ssi_ids[] = { 320static const struct of_device_id fsl_ssi_ids[] = {
@@ -354,12 +354,12 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
354 __be32 sisr; 354 __be32 sisr;
355 __be32 sisr2; 355 __be32 sisr2;
356 356
357 regmap_read(regs, CCSR_SSI_SISR, &sisr); 357 regmap_read(regs, REG_SSI_SISR, &sisr);
358 358
359 sisr2 = sisr & ssi->soc->sisr_write_mask; 359 sisr2 = sisr & ssi->soc->sisr_write_mask;
360 /* Clear the bits that we set */ 360 /* Clear the bits that we set */
361 if (sisr2) 361 if (sisr2)
362 regmap_write(regs, CCSR_SSI_SISR, sisr2); 362 regmap_write(regs, REG_SSI_SISR, sisr2);
363 363
364 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); 364 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr);
365 365
@@ -375,21 +375,21 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable)
375 struct fsl_ssi_rxtx_reg_val *vals = &ssi->rxtx_reg_val; 375 struct fsl_ssi_rxtx_reg_val *vals = &ssi->rxtx_reg_val;
376 376
377 if (enable) { 377 if (enable) {
378 regmap_update_bits(regs, CCSR_SSI_SIER, 378 regmap_update_bits(regs, REG_SSI_SIER,
379 vals->rx.sier | vals->tx.sier, 379 vals->rx.sier | vals->tx.sier,
380 vals->rx.sier | vals->tx.sier); 380 vals->rx.sier | vals->tx.sier);
381 regmap_update_bits(regs, CCSR_SSI_SRCR, 381 regmap_update_bits(regs, REG_SSI_SRCR,
382 vals->rx.srcr | vals->tx.srcr, 382 vals->rx.srcr | vals->tx.srcr,
383 vals->rx.srcr | vals->tx.srcr); 383 vals->rx.srcr | vals->tx.srcr);
384 regmap_update_bits(regs, CCSR_SSI_STCR, 384 regmap_update_bits(regs, REG_SSI_STCR,
385 vals->rx.stcr | vals->tx.stcr, 385 vals->rx.stcr | vals->tx.stcr,
386 vals->rx.stcr | vals->tx.stcr); 386 vals->rx.stcr | vals->tx.stcr);
387 } else { 387 } else {
388 regmap_update_bits(regs, CCSR_SSI_SRCR, 388 regmap_update_bits(regs, REG_SSI_SRCR,
389 vals->rx.srcr | vals->tx.srcr, 0); 389 vals->rx.srcr | vals->tx.srcr, 0);
390 regmap_update_bits(regs, CCSR_SSI_STCR, 390 regmap_update_bits(regs, REG_SSI_STCR,
391 vals->rx.stcr | vals->tx.stcr, 0); 391 vals->rx.stcr | vals->tx.stcr, 0);
392 regmap_update_bits(regs, CCSR_SSI_SIER, 392 regmap_update_bits(regs, REG_SSI_SIER,
393 vals->rx.sier | vals->tx.sier, 0); 393 vals->rx.sier | vals->tx.sier, 0);
394 } 394 }
395} 395}
@@ -400,11 +400,11 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable)
400static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) 400static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
401{ 401{
402 if (is_rx) { 402 if (is_rx) {
403 regmap_update_bits(ssi->regs, CCSR_SSI_SOR, 403 regmap_update_bits(ssi->regs, REG_SSI_SOR,
404 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR); 404 SSI_SOR_RX_CLR, SSI_SOR_RX_CLR);
405 } else { 405 } else {
406 regmap_update_bits(ssi->regs, CCSR_SSI_SOR, 406 regmap_update_bits(ssi->regs, REG_SSI_SOR,
407 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR); 407 SSI_SOR_TX_CLR, SSI_SOR_TX_CLR);
408 } 408 }
409} 409}
410 410
@@ -440,10 +440,10 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
440 u32 scr_val; 440 u32 scr_val;
441 int keep_active; 441 int keep_active;
442 442
443 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 443 regmap_read(regs, REG_SSI_SCR, &scr_val);
444 444
445 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 445 nr_active_streams = !!(scr_val & SSI_SCR_TE) +
446 !!(scr_val & CCSR_SSI_SCR_RE); 446 !!(scr_val & SSI_SCR_RE);
447 447
448 if (nr_active_streams - 1 > 0) 448 if (nr_active_streams - 1 > 0)
449 keep_active = 1; 449 keep_active = 1;
@@ -464,7 +464,7 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
464 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 464 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
465 keep_active); 465 keep_active);
466 /* Safely disable SCR register for the stream */ 466 /* Safely disable SCR register for the stream */
467 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 467 regmap_update_bits(regs, REG_SSI_SCR, scr, 0);
468 } 468 }
469 469
470 /* 470 /*
@@ -483,11 +483,11 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
483 483
484 /* Online configure single direction while SSI is running */ 484 /* Online configure single direction while SSI is running */
485 if (enable) { 485 if (enable) {
486 fsl_ssi_fifo_clear(ssi, vals->scr & CCSR_SSI_SCR_RE); 486 fsl_ssi_fifo_clear(ssi, vals->scr & SSI_SCR_RE);
487 487
488 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 488 regmap_update_bits(regs, REG_SSI_SRCR, vals->srcr, vals->srcr);
489 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 489 regmap_update_bits(regs, REG_SSI_STCR, vals->stcr, vals->stcr);
490 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 490 regmap_update_bits(regs, REG_SSI_SIER, vals->sier, vals->sier);
491 } else { 491 } else {
492 u32 sier; 492 u32 sier;
493 u32 srcr; 493 u32 srcr;
@@ -505,9 +505,9 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
505 keep_active); 505 keep_active);
506 506
507 /* Safely disable other control registers for the stream */ 507 /* Safely disable other control registers for the stream */
508 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 508 regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0);
509 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 509 regmap_update_bits(regs, REG_SSI_STCR, stcr, 0);
510 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 510 regmap_update_bits(regs, REG_SSI_SIER, sier, 0);
511 } 511 }
512 512
513config_done: 513config_done:
@@ -519,19 +519,19 @@ config_done:
519 * 519 *
520 * TODO: FIQ cases might also need this upon testing 520 * TODO: FIQ cases might also need this upon testing
521 */ 521 */
522 if (ssi->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { 522 if (ssi->use_dma && (vals->scr & SSI_SCR_TE)) {
523 int i; 523 int i;
524 int max_loop = 100; 524 int max_loop = 100;
525 525
526 /* Enable SSI first to send TX DMA request */ 526 /* Enable SSI first to send TX DMA request */
527 regmap_update_bits(regs, CCSR_SSI_SCR, 527 regmap_update_bits(regs, REG_SSI_SCR,
528 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); 528 SSI_SCR_SSIEN, SSI_SCR_SSIEN);
529 529
530 /* Busy wait until TX FIFO not empty -- DMA working */ 530 /* Busy wait until TX FIFO not empty -- DMA working */
531 for (i = 0; i < max_loop; i++) { 531 for (i = 0; i < max_loop; i++) {
532 u32 sfcsr; 532 u32 sfcsr;
533 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); 533 regmap_read(regs, REG_SSI_SFCSR, &sfcsr);
534 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) 534 if (SSI_SFCSR_TFCNT0(sfcsr))
535 break; 535 break;
536 } 536 }
537 if (i == max_loop) { 537 if (i == max_loop) {
@@ -540,7 +540,7 @@ config_done:
540 } 540 }
541 } 541 }
542 /* Enable all remaining bits */ 542 /* Enable all remaining bits */
543 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 543 regmap_update_bits(regs, REG_SSI_SCR, vals->scr, vals->scr);
544 } 544 }
545} 545}
546 546
@@ -557,9 +557,9 @@ static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi)
557 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 557 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
558 if (!ssi->soc->imx21regs) { 558 if (!ssi->soc->imx21regs) {
559 /* Disable all channel slots */ 559 /* Disable all channel slots */
560 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 560 regmap_write(regs, REG_SSI_SACCDIS, 0xff);
561 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ 561 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */
562 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 562 regmap_write(regs, REG_SSI_SACCEN, 0x300);
563 } 563 }
564} 564}
565 565
@@ -585,25 +585,25 @@ static void fsl_ssi_setup_reg_vals(struct fsl_ssi *ssi)
585{ 585{
586 struct fsl_ssi_rxtx_reg_val *reg = &ssi->rxtx_reg_val; 586 struct fsl_ssi_rxtx_reg_val *reg = &ssi->rxtx_reg_val;
587 587
588 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 588 reg->rx.sier = SSI_SIER_RFF0_EN;
589 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 589 reg->rx.srcr = SSI_SRCR_RFEN0;
590 reg->rx.scr = 0; 590 reg->rx.scr = 0;
591 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 591 reg->tx.sier = SSI_SIER_TFE0_EN;
592 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 592 reg->tx.stcr = SSI_STCR_TFEN0;
593 reg->tx.scr = 0; 593 reg->tx.scr = 0;
594 594
595 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ 595 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */
596 if (!fsl_ssi_is_ac97(ssi)) { 596 if (!fsl_ssi_is_ac97(ssi)) {
597 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 597 reg->rx.scr = SSI_SCR_SSIEN | SSI_SCR_RE;
598 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 598 reg->tx.scr = SSI_SCR_SSIEN | SSI_SCR_TE;
599 } 599 }
600 600
601 if (ssi->use_dma) { 601 if (ssi->use_dma) {
602 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 602 reg->rx.sier |= SSI_SIER_RDMAE;
603 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 603 reg->tx.sier |= SSI_SIER_TDMAE;
604 } else { 604 } else {
605 reg->rx.sier |= CCSR_SSI_SIER_RIE; 605 reg->rx.sier |= SSI_SIER_RIE;
606 reg->tx.sier |= CCSR_SSI_SIER_TIE; 606 reg->tx.sier |= SSI_SIER_TIE;
607 } 607 }
608 608
609 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 609 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
@@ -615,21 +615,21 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi)
615 struct regmap *regs = ssi->regs; 615 struct regmap *regs = ssi->regs;
616 616
617 /* Setup the clock control register */ 617 /* Setup the clock control register */
618 regmap_write(regs, CCSR_SSI_STCCR, 618 regmap_write(regs, REG_SSI_STCCR,
619 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 619 SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
620 regmap_write(regs, CCSR_SSI_SRCCR, 620 regmap_write(regs, REG_SSI_SRCCR,
621 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 621 SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13));
622 622
623 /* Enable AC97 mode and startup the SSI */ 623 /* Enable AC97 mode and startup the SSI */
624 regmap_write(regs, CCSR_SSI_SACNT, 624 regmap_write(regs, REG_SSI_SACNT,
625 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 625 SSI_SACNT_AC97EN | SSI_SACNT_FV);
626 626
627 /* AC97 has to communicate with codec before starting a stream */ 627 /* AC97 has to communicate with codec before starting a stream */
628 regmap_update_bits(regs, CCSR_SSI_SCR, 628 regmap_update_bits(regs, REG_SSI_SCR,
629 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 629 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE,
630 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 630 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE);
631 631
632 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 632 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3));
633} 633}
634 634
635static int fsl_ssi_startup(struct snd_pcm_substream *substream, 635static int fsl_ssi_startup(struct snd_pcm_substream *substream,
@@ -762,15 +762,15 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
762 return -EINVAL; 762 return -EINVAL;
763 } 763 }
764 764
765 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 765 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) |
766 (psr ? CCSR_SSI_SxCCR_PSR : 0); 766 (psr ? SSI_SxCCR_PSR : 0);
767 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 767 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 |
768 CCSR_SSI_SxCCR_PSR; 768 SSI_SxCCR_PSR;
769 769
770 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 770 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
771 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 771 regmap_update_bits(regs, REG_SSI_STCCR, mask, stccr);
772 else 772 else
773 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 773 regmap_update_bits(regs, REG_SSI_SRCCR, mask, stccr);
774 774
775 if (!baudclk_is_used) { 775 if (!baudclk_is_used) {
776 ret = clk_set_rate(ssi->baudclk, baudrate); 776 ret = clk_set_rate(ssi->baudclk, baudrate);
@@ -801,13 +801,13 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
801 struct regmap *regs = ssi->regs; 801 struct regmap *regs = ssi->regs;
802 unsigned int channels = params_channels(hw_params); 802 unsigned int channels = params_channels(hw_params);
803 unsigned int sample_size = params_width(hw_params); 803 unsigned int sample_size = params_width(hw_params);
804 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 804 u32 wl = SSI_SxCCR_WL(sample_size);
805 int ret; 805 int ret;
806 u32 scr_val; 806 u32 scr_val;
807 int enabled; 807 int enabled;
808 808
809 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 809 regmap_read(regs, REG_SSI_SCR, &scr_val);
810 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 810 enabled = scr_val & SSI_SCR_SSIEN;
811 811
812 /* 812 /*
813 * SSI is properly configured if it is enabled and running in 813 * SSI is properly configured if it is enabled and running in
@@ -837,23 +837,23 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
837 u8 i2smode; 837 u8 i2smode;
838 /* Normal + Network mode to send 16-bit data in 32-bit frames */ 838 /* Normal + Network mode to send 16-bit data in 32-bit frames */
839 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) 839 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16)
840 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 840 i2smode = SSI_SCR_I2S_MODE_NORMAL |
841 CCSR_SSI_SCR_NET; 841 SSI_SCR_NET;
842 else 842 else
843 i2smode = ssi->i2s_mode; 843 i2smode = ssi->i2s_mode;
844 844
845 regmap_update_bits(regs, CCSR_SSI_SCR, 845 regmap_update_bits(regs, REG_SSI_SCR,
846 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 846 SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK,
847 channels == 1 ? 0 : i2smode); 847 channels == 1 ? 0 : i2smode);
848 } 848 }
849 849
850 /* In synchronous mode, the SSI uses STCCR for capture */ 850 /* In synchronous mode, the SSI uses STCCR for capture */
851 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 851 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
852 ssi->cpu_dai_drv.symmetric_rates) 852 ssi->cpu_dai_drv.symmetric_rates)
853 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 853 regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_WL_MASK,
854 wl); 854 wl);
855 else 855 else
856 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 856 regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_WL_MASK,
857 wl); 857 wl);
858 858
859 return 0; 859 return 0;
@@ -890,62 +890,62 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
890 890
891 fsl_ssi_setup_reg_vals(ssi); 891 fsl_ssi_setup_reg_vals(ssi);
892 892
893 regmap_read(regs, CCSR_SSI_SCR, &scr); 893 regmap_read(regs, REG_SSI_SCR, &scr);
894 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 894 scr &= ~(SSI_SCR_SYN | SSI_SCR_I2S_MODE_MASK);
895 /* Synchronize frame sync clock for TE to avoid data slipping */ 895 /* Synchronize frame sync clock for TE to avoid data slipping */
896 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 896 scr |= SSI_SCR_SYNC_TX_FS;
897 897
898 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 898 mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR |
899 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 899 SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL |
900 CCSR_SSI_STCR_TEFS; 900 SSI_STCR_TEFS;
901 regmap_read(regs, CCSR_SSI_STCR, &stcr); 901 regmap_read(regs, REG_SSI_STCR, &stcr);
902 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 902 regmap_read(regs, REG_SSI_SRCR, &srcr);
903 stcr &= ~mask; 903 stcr &= ~mask;
904 srcr &= ~mask; 904 srcr &= ~mask;
905 905
906 /* Use Network mode as default */ 906 /* Use Network mode as default */
907 ssi->i2s_mode = CCSR_SSI_SCR_NET; 907 ssi->i2s_mode = SSI_SCR_NET;
908 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 908 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
909 case SND_SOC_DAIFMT_I2S: 909 case SND_SOC_DAIFMT_I2S:
910 regmap_update_bits(regs, CCSR_SSI_STCCR, 910 regmap_update_bits(regs, REG_SSI_STCCR,
911 CCSR_SSI_SxCCR_DC_MASK, 911 SSI_SxCCR_DC_MASK,
912 CCSR_SSI_SxCCR_DC(2)); 912 SSI_SxCCR_DC(2));
913 regmap_update_bits(regs, CCSR_SSI_SRCCR, 913 regmap_update_bits(regs, REG_SSI_SRCCR,
914 CCSR_SSI_SxCCR_DC_MASK, 914 SSI_SxCCR_DC_MASK,
915 CCSR_SSI_SxCCR_DC(2)); 915 SSI_SxCCR_DC(2));
916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
917 case SND_SOC_DAIFMT_CBM_CFS: 917 case SND_SOC_DAIFMT_CBM_CFS:
918 case SND_SOC_DAIFMT_CBS_CFS: 918 case SND_SOC_DAIFMT_CBS_CFS:
919 ssi->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 919 ssi->i2s_mode |= SSI_SCR_I2S_MODE_MASTER;
920 break; 920 break;
921 case SND_SOC_DAIFMT_CBM_CFM: 921 case SND_SOC_DAIFMT_CBM_CFM:
922 ssi->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 922 ssi->i2s_mode |= SSI_SCR_I2S_MODE_SLAVE;
923 break; 923 break;
924 default: 924 default:
925 return -EINVAL; 925 return -EINVAL;
926 } 926 }
927 927
928 /* Data on rising edge of bclk, frame low, 1clk before data */ 928 /* Data on rising edge of bclk, frame low, 1clk before data */
929 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 929 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP |
930 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 930 SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
931 break; 931 break;
932 case SND_SOC_DAIFMT_LEFT_J: 932 case SND_SOC_DAIFMT_LEFT_J:
933 /* Data on rising edge of bclk, frame high */ 933 /* Data on rising edge of bclk, frame high */
934 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 934 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP;
935 break; 935 break;
936 case SND_SOC_DAIFMT_DSP_A: 936 case SND_SOC_DAIFMT_DSP_A:
937 /* Data on rising edge of bclk, frame high, 1clk before data */ 937 /* Data on rising edge of bclk, frame high, 1clk before data */
938 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 938 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP |
939 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 939 SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
940 break; 940 break;
941 case SND_SOC_DAIFMT_DSP_B: 941 case SND_SOC_DAIFMT_DSP_B:
942 /* Data on rising edge of bclk, frame high */ 942 /* Data on rising edge of bclk, frame high */
943 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 943 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP |
944 CCSR_SSI_STCR_TXBIT0; 944 SSI_STCR_TXBIT0;
945 break; 945 break;
946 case SND_SOC_DAIFMT_AC97: 946 case SND_SOC_DAIFMT_AC97:
947 /* Data on falling edge of bclk, frame high, 1clk before data */ 947 /* Data on falling edge of bclk, frame high, 1clk before data */
948 ssi->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 948 ssi->i2s_mode |= SSI_SCR_I2S_MODE_NORMAL;
949 break; 949 break;
950 default: 950 default:
951 return -EINVAL; 951 return -EINVAL;
@@ -959,16 +959,16 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
959 break; 959 break;
960 case SND_SOC_DAIFMT_IB_NF: 960 case SND_SOC_DAIFMT_IB_NF:
961 /* Invert bit clock */ 961 /* Invert bit clock */
962 strcr ^= CCSR_SSI_STCR_TSCKP; 962 strcr ^= SSI_STCR_TSCKP;
963 break; 963 break;
964 case SND_SOC_DAIFMT_NB_IF: 964 case SND_SOC_DAIFMT_NB_IF:
965 /* Invert frame clock */ 965 /* Invert frame clock */
966 strcr ^= CCSR_SSI_STCR_TFSI; 966 strcr ^= SSI_STCR_TFSI;
967 break; 967 break;
968 case SND_SOC_DAIFMT_IB_IF: 968 case SND_SOC_DAIFMT_IB_IF:
969 /* Invert both clocks */ 969 /* Invert both clocks */
970 strcr ^= CCSR_SSI_STCR_TSCKP; 970 strcr ^= SSI_STCR_TSCKP;
971 strcr ^= CCSR_SSI_STCR_TFSI; 971 strcr ^= SSI_STCR_TFSI;
972 break; 972 break;
973 default: 973 default:
974 return -EINVAL; 974 return -EINVAL;
@@ -978,18 +978,18 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
978 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 978 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
979 case SND_SOC_DAIFMT_CBS_CFS: 979 case SND_SOC_DAIFMT_CBS_CFS:
980 /* Output bit and frame sync clocks */ 980 /* Output bit and frame sync clocks */
981 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 981 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR;
982 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 982 scr |= SSI_SCR_SYS_CLK_EN;
983 break; 983 break;
984 case SND_SOC_DAIFMT_CBM_CFM: 984 case SND_SOC_DAIFMT_CBM_CFM:
985 /* Input bit or frame sync clocks */ 985 /* Input bit or frame sync clocks */
986 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 986 scr &= ~SSI_SCR_SYS_CLK_EN;
987 break; 987 break;
988 case SND_SOC_DAIFMT_CBM_CFS: 988 case SND_SOC_DAIFMT_CBM_CFS:
989 /* Input bit clock but output frame sync clock */ 989 /* Input bit clock but output frame sync clock */
990 strcr &= ~CCSR_SSI_STCR_TXDIR; 990 strcr &= ~SSI_STCR_TXDIR;
991 strcr |= CCSR_SSI_STCR_TFDIR; 991 strcr |= SSI_STCR_TFDIR;
992 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 992 scr &= ~SSI_SCR_SYS_CLK_EN;
993 break; 993 break;
994 default: 994 default:
995 if (!fsl_ssi_is_ac97(ssi)) 995 if (!fsl_ssi_is_ac97(ssi))
@@ -1001,27 +1001,27 @@ static int _fsl_ssi_set_dai_fmt(struct device *dev,
1001 1001
1002 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ 1002 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */
1003 if (ssi->cpu_dai_drv.symmetric_rates || fsl_ssi_is_ac97(ssi)) { 1003 if (ssi->cpu_dai_drv.symmetric_rates || fsl_ssi_is_ac97(ssi)) {
1004 srcr &= ~CCSR_SSI_SRCR_RXDIR; 1004 srcr &= ~SSI_SRCR_RXDIR;
1005 scr |= CCSR_SSI_SCR_SYN; 1005 scr |= SSI_SCR_SYN;
1006 } 1006 }
1007 1007
1008 regmap_write(regs, CCSR_SSI_STCR, stcr); 1008 regmap_write(regs, REG_SSI_STCR, stcr);
1009 regmap_write(regs, CCSR_SSI_SRCR, srcr); 1009 regmap_write(regs, REG_SSI_SRCR, srcr);
1010 regmap_write(regs, CCSR_SSI_SCR, scr); 1010 regmap_write(regs, REG_SSI_SCR, scr);
1011 1011
1012 wm = ssi->fifo_watermark; 1012 wm = ssi->fifo_watermark;
1013 1013
1014 regmap_write(regs, CCSR_SSI_SFCSR, 1014 regmap_write(regs, REG_SSI_SFCSR,
1015 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 1015 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) |
1016 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 1016 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));
1017 1017
1018 if (ssi->use_dual_fifo) { 1018 if (ssi->use_dual_fifo) {
1019 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 1019 regmap_update_bits(regs, REG_SSI_SRCR, SSI_SRCR_RFEN1,
1020 CCSR_SSI_SRCR_RFEN1); 1020 SSI_SRCR_RFEN1);
1021 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 1021 regmap_update_bits(regs, REG_SSI_STCR, SSI_STCR_TFEN1,
1022 CCSR_SSI_STCR_TFEN1); 1022 SSI_STCR_TFEN1);
1023 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 1023 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_TCH_EN,
1024 CCSR_SSI_SCR_TCH_EN); 1024 SSI_SCR_TCH_EN);
1025 } 1025 }
1026 1026
1027 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1027 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
@@ -1062,30 +1062,30 @@ static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1062 } 1062 }
1063 1063
1064 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1064 /* The slot number should be >= 2 if using Network mode or I2S mode */
1065 regmap_read(regs, CCSR_SSI_SCR, &val); 1065 regmap_read(regs, REG_SSI_SCR, &val);
1066 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 1066 val &= SSI_SCR_I2S_MODE_MASK | SSI_SCR_NET;
1067 if (val && slots < 2) { 1067 if (val && slots < 2) {
1068 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1068 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1069 return -EINVAL; 1069 return -EINVAL;
1070 } 1070 }
1071 1071
1072 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 1072 regmap_update_bits(regs, REG_SSI_STCCR, SSI_SxCCR_DC_MASK,
1073 CCSR_SSI_SxCCR_DC(slots)); 1073 SSI_SxCCR_DC(slots));
1074 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 1074 regmap_update_bits(regs, REG_SSI_SRCCR, SSI_SxCCR_DC_MASK,
1075 CCSR_SSI_SxCCR_DC(slots)); 1075 SSI_SxCCR_DC(slots));
1076 1076
1077 /* Save SSIEN bit of the SCR register */ 1077 /* Save SSIEN bit of the SCR register */
1078 regmap_read(regs, CCSR_SSI_SCR, &val); 1078 regmap_read(regs, REG_SSI_SCR, &val);
1079 val &= CCSR_SSI_SCR_SSIEN; 1079 val &= SSI_SCR_SSIEN;
1080 /* Temporarily enable SSI to allow SxMSKs to be configurable */ 1080 /* Temporarily enable SSI to allow SxMSKs to be configurable */
1081 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 1081 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN,
1082 CCSR_SSI_SCR_SSIEN); 1082 SSI_SCR_SSIEN);
1083 1083
1084 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1084 regmap_write(regs, REG_SSI_STMSK, ~tx_mask);
1085 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1085 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask);
1086 1086
1087 /* Restore the value of SSIEN bit */ 1087 /* Restore the value of SSIEN bit */
1088 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1088 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val);
1089 1089
1090 ssi->slot_width = slot_width; 1090 ssi->slot_width = slot_width;
1091 ssi->slots = slots; 1091 ssi->slots = slots;
@@ -1132,9 +1132,9 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1132 /* Clear corresponding FIFO */ 1132 /* Clear corresponding FIFO */
1133 if (fsl_ssi_is_ac97(ssi)) { 1133 if (fsl_ssi_is_ac97(ssi)) {
1134 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1134 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1135 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1135 regmap_write(regs, REG_SSI_SOR, SSI_SOR_TX_CLR);
1136 else 1136 else
1137 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1137 regmap_write(regs, REG_SSI_SOR, SSI_SOR_RX_CLR);
1138 } 1138 }
1139 1139
1140 return 0; 1140 return 0;
@@ -1230,13 +1230,13 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1230 } 1230 }
1231 1231
1232 lreg = reg << 12; 1232 lreg = reg << 12;
1233 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1233 regmap_write(regs, REG_SSI_SACADD, lreg);
1234 1234
1235 lval = val << 4; 1235 lval = val << 4;
1236 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1236 regmap_write(regs, REG_SSI_SACDAT, lval);
1237 1237
1238 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1238 regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,
1239 CCSR_SSI_SACNT_WR); 1239 SSI_SACNT_WR);
1240 udelay(100); 1240 udelay(100);
1241 1241
1242 clk_disable_unprepare(fsl_ac97_data->clk); 1242 clk_disable_unprepare(fsl_ac97_data->clk);
@@ -1265,13 +1265,13 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1265 } 1265 }
1266 1266
1267 lreg = (reg & 0x7f) << 12; 1267 lreg = (reg & 0x7f) << 12;
1268 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1268 regmap_write(regs, REG_SSI_SACADD, lreg);
1269 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1269 regmap_update_bits(regs, REG_SSI_SACNT, SSI_SACNT_RDWR_MASK,
1270 CCSR_SSI_SACNT_RD); 1270 SSI_SACNT_RD);
1271 1271
1272 udelay(100); 1272 udelay(100);
1273 1273
1274 regmap_read(regs, CCSR_SSI_SACDAT, &reg_val); 1274 regmap_read(regs, REG_SSI_SACDAT, &reg_val);
1275 val = (reg_val >> 4) & 0xffff; 1275 val = (reg_val >> 4) & 0xffff;
1276 1276
1277 clk_disable_unprepare(fsl_ac97_data->clk); 1277 clk_disable_unprepare(fsl_ac97_data->clk);
@@ -1333,8 +1333,8 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
1333 1333
1334 ssi->dma_params_tx.maxburst = ssi->dma_maxburst; 1334 ssi->dma_params_tx.maxburst = ssi->dma_maxburst;
1335 ssi->dma_params_rx.maxburst = ssi->dma_maxburst; 1335 ssi->dma_params_rx.maxburst = ssi->dma_maxburst;
1336 ssi->dma_params_tx.addr = ssi->ssi_phys + CCSR_SSI_STX0; 1336 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0;
1337 ssi->dma_params_rx.addr = ssi->ssi_phys + CCSR_SSI_SRX0; 1337 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0;
1338 1338
1339 /* Set to dual FIFO mode according to the SDMA sciprt */ 1339 /* Set to dual FIFO mode according to the SDMA sciprt */
1340 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1340 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
@@ -1439,9 +1439,9 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1439 1439
1440 if (ssi->soc->imx21regs) { 1440 if (ssi->soc->imx21regs) {
1441 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ 1441 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */
1442 regconfig.max_register = CCSR_SSI_SRMSK; 1442 regconfig.max_register = REG_SSI_SRMSK;
1443 regconfig.num_reg_defaults_raw = 1443 regconfig.num_reg_defaults_raw =
1444 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1; 1444 REG_SSI_SRMSK / sizeof(uint32_t) + 1;
1445 } 1445 }
1446 1446
1447 ret = of_property_match_string(np, "clock-names", "ipg"); 1447 ret = of_property_match_string(np, "clock-names", "ipg");
@@ -1638,8 +1638,8 @@ static int fsl_ssi_suspend(struct device *dev)
1638 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1638 struct fsl_ssi *ssi = dev_get_drvdata(dev);
1639 struct regmap *regs = ssi->regs; 1639 struct regmap *regs = ssi->regs;
1640 1640
1641 regmap_read(regs, CCSR_SSI_SFCSR, &ssi->regcache_sfcsr); 1641 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr);
1642 regmap_read(regs, CCSR_SSI_SACNT, &ssi->regcache_sacnt); 1642 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt);
1643 1643
1644 regcache_cache_only(regs, true); 1644 regcache_cache_only(regs, true);
1645 regcache_mark_dirty(regs); 1645 regcache_mark_dirty(regs);
@@ -1654,11 +1654,11 @@ static int fsl_ssi_resume(struct device *dev)
1654 1654
1655 regcache_cache_only(regs, false); 1655 regcache_cache_only(regs, false);
1656 1656
1657 regmap_update_bits(regs, CCSR_SSI_SFCSR, 1657 regmap_update_bits(regs, REG_SSI_SFCSR,
1658 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1658 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK |
1659 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1659 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK,
1660 ssi->regcache_sfcsr); 1660 ssi->regcache_sfcsr);
1661 regmap_write(regs, CCSR_SSI_SACNT, ssi->regcache_sacnt); 1661 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt);
1662 1662
1663 return regcache_sync(regs); 1663 return regcache_sync(regs);
1664} 1664}
diff --git a/sound/soc/fsl/fsl_ssi.h b/sound/soc/fsl/fsl_ssi.h
index 1ad3bde7f065..cdcf3d23873e 100644
--- a/sound/soc/fsl/fsl_ssi.h
+++ b/sound/soc/fsl/fsl_ssi.h
@@ -15,55 +15,55 @@
15/* -- SSI Register Map -- */ 15/* -- SSI Register Map -- */
16 16
17/* SSI Transmit Data Register 0 */ 17/* SSI Transmit Data Register 0 */
18#define CCSR_SSI_STX0 0x00 18#define REG_SSI_STX0 0x00
19/* SSI Transmit Data Register 1 */ 19/* SSI Transmit Data Register 1 */
20#define CCSR_SSI_STX1 0x04 20#define REG_SSI_STX1 0x04
21/* SSI Receive Data Register 0 */ 21/* SSI Receive Data Register 0 */
22#define CCSR_SSI_SRX0 0x08 22#define REG_SSI_SRX0 0x08
23/* SSI Receive Data Register 1 */ 23/* SSI Receive Data Register 1 */
24#define CCSR_SSI_SRX1 0x0c 24#define REG_SSI_SRX1 0x0c
25/* SSI Control Register */ 25/* SSI Control Register */
26#define CCSR_SSI_SCR 0x10 26#define REG_SSI_SCR 0x10
27/* SSI Interrupt Status Register */ 27/* SSI Interrupt Status Register */
28#define CCSR_SSI_SISR 0x14 28#define REG_SSI_SISR 0x14
29/* SSI Interrupt Enable Register */ 29/* SSI Interrupt Enable Register */
30#define CCSR_SSI_SIER 0x18 30#define REG_SSI_SIER 0x18
31/* SSI Transmit Configuration Register */ 31/* SSI Transmit Configuration Register */
32#define CCSR_SSI_STCR 0x1c 32#define REG_SSI_STCR 0x1c
33/* SSI Receive Configuration Register */ 33/* SSI Receive Configuration Register */
34#define CCSR_SSI_SRCR 0x20 34#define REG_SSI_SRCR 0x20
35/* SSI Transmit Clock Control Register */ 35/* SSI Transmit Clock Control Register */
36#define CCSR_SSI_STCCR 0x24 36#define REG_SSI_STCCR 0x24
37/* SSI Receive Clock Control Register */ 37/* SSI Receive Clock Control Register */
38#define CCSR_SSI_SRCCR 0x28 38#define REG_SSI_SRCCR 0x28
39/* SSI FIFO Control/Status Register */ 39/* SSI FIFO Control/Status Register */
40#define CCSR_SSI_SFCSR 0x2c 40#define REG_SSI_SFCSR 0x2c
41/* 41/*
42 * SSI Test Register (Intended for debugging purposes only) 42 * SSI Test Register (Intended for debugging purposes only)
43 * 43 *
44 * Note: STR is not documented in recent IMX datasheet, but 44 * Note: STR is not documented in recent IMX datasheet, but
45 * is described in IMX51 reference manual at section 56.3.3.14 45 * is described in IMX51 reference manual at section 56.3.3.14
46 */ 46 */
47#define CCSR_SSI_STR 0x30 47#define REG_SSI_STR 0x30
48/* 48/*
49 * SSI Option Register (Intended for internal use only) 49 * SSI Option Register (Intended for internal use only)
50 * 50 *
51 * Note: SOR is not documented in recent IMX datasheet, but 51 * Note: SOR is not documented in recent IMX datasheet, but
52 * is described in IMX51 reference manual at section 56.3.3.15 52 * is described in IMX51 reference manual at section 56.3.3.15
53 */ 53 */
54#define CCSR_SSI_SOR 0x34 54#define REG_SSI_SOR 0x34
55/* SSI AC97 Control Register */ 55/* SSI AC97 Control Register */
56#define CCSR_SSI_SACNT 0x38 56#define REG_SSI_SACNT 0x38
57/* SSI AC97 Command Address Register */ 57/* SSI AC97 Command Address Register */
58#define CCSR_SSI_SACADD 0x3c 58#define REG_SSI_SACADD 0x3c
59/* SSI AC97 Command Data Register */ 59/* SSI AC97 Command Data Register */
60#define CCSR_SSI_SACDAT 0x40 60#define REG_SSI_SACDAT 0x40
61/* SSI AC97 Tag Register */ 61/* SSI AC97 Tag Register */
62#define CCSR_SSI_SATAG 0x44 62#define REG_SSI_SATAG 0x44
63/* SSI Transmit Time Slot Mask Register */ 63/* SSI Transmit Time Slot Mask Register */
64#define CCSR_SSI_STMSK 0x48 64#define REG_SSI_STMSK 0x48
65/* SSI Receive Time Slot Mask Register */ 65/* SSI Receive Time Slot Mask Register */
66#define CCSR_SSI_SRMSK 0x4c 66#define REG_SSI_SRMSK 0x4c
67/* 67/*
68 * SSI AC97 Channel Status Register 68 * SSI AC97 Channel Status Register
69 * 69 *
@@ -72,193 +72,193 @@
72 * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit 72 * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
73 * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link 73 * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
74 */ 74 */
75#define CCSR_SSI_SACCST 0x50 75#define REG_SSI_SACCST 0x50
76/* SSI AC97 Channel Enable Register -- Set bits in SACCST */ 76/* SSI AC97 Channel Enable Register -- Set bits in SACCST */
77#define CCSR_SSI_SACCEN 0x54 77#define REG_SSI_SACCEN 0x54
78/* SSI AC97 Channel Disable Register -- Clear bits in SACCST */ 78/* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
79#define CCSR_SSI_SACCDIS 0x58 79#define REG_SSI_SACCDIS 0x58
80 80
81/* -- SSI Register Field Maps -- */ 81/* -- SSI Register Field Maps -- */
82 82
83/* SSI Control Register -- CCSR_SSI_SCR 0x10 */ 83/* SSI Control Register -- REG_SSI_SCR 0x10 */
84#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000 84#define SSI_SCR_SYNC_TX_FS 0x00001000
85#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800 85#define SSI_SCR_RFR_CLK_DIS 0x00000800
86#define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400 86#define SSI_SCR_TFR_CLK_DIS 0x00000400
87#define CCSR_SSI_SCR_TCH_EN 0x00000100 87#define SSI_SCR_TCH_EN 0x00000100
88#define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080 88#define SSI_SCR_SYS_CLK_EN 0x00000080
89#define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060 89#define SSI_SCR_I2S_MODE_MASK 0x00000060
90#define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000 90#define SSI_SCR_I2S_MODE_NORMAL 0x00000000
91#define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020 91#define SSI_SCR_I2S_MODE_MASTER 0x00000020
92#define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040 92#define SSI_SCR_I2S_MODE_SLAVE 0x00000040
93#define CCSR_SSI_SCR_SYN 0x00000010 93#define SSI_SCR_SYN 0x00000010
94#define CCSR_SSI_SCR_NET 0x00000008 94#define SSI_SCR_NET 0x00000008
95#define CCSR_SSI_SCR_RE 0x00000004 95#define SSI_SCR_RE 0x00000004
96#define CCSR_SSI_SCR_TE 0x00000002 96#define SSI_SCR_TE 0x00000002
97#define CCSR_SSI_SCR_SSIEN 0x00000001 97#define SSI_SCR_SSIEN 0x00000001
98 98
99/* SSI Interrupt Status Register -- CCSR_SSI_SISR 0x14 */ 99/* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
100#define CCSR_SSI_SISR_RFRC 0x01000000 100#define SSI_SISR_RFRC 0x01000000
101#define CCSR_SSI_SISR_TFRC 0x00800000 101#define SSI_SISR_TFRC 0x00800000
102#define CCSR_SSI_SISR_CMDAU 0x00040000 102#define SSI_SISR_CMDAU 0x00040000
103#define CCSR_SSI_SISR_CMDDU 0x00020000 103#define SSI_SISR_CMDDU 0x00020000
104#define CCSR_SSI_SISR_RXT 0x00010000 104#define SSI_SISR_RXT 0x00010000
105#define CCSR_SSI_SISR_RDR1 0x00008000 105#define SSI_SISR_RDR1 0x00008000
106#define CCSR_SSI_SISR_RDR0 0x00004000 106#define SSI_SISR_RDR0 0x00004000
107#define CCSR_SSI_SISR_TDE1 0x00002000 107#define SSI_SISR_TDE1 0x00002000
108#define CCSR_SSI_SISR_TDE0 0x00001000 108#define SSI_SISR_TDE0 0x00001000
109#define CCSR_SSI_SISR_ROE1 0x00000800 109#define SSI_SISR_ROE1 0x00000800
110#define CCSR_SSI_SISR_ROE0 0x00000400 110#define SSI_SISR_ROE0 0x00000400
111#define CCSR_SSI_SISR_TUE1 0x00000200 111#define SSI_SISR_TUE1 0x00000200
112#define CCSR_SSI_SISR_TUE0 0x00000100 112#define SSI_SISR_TUE0 0x00000100
113#define CCSR_SSI_SISR_TFS 0x00000080 113#define SSI_SISR_TFS 0x00000080
114#define CCSR_SSI_SISR_RFS 0x00000040 114#define SSI_SISR_RFS 0x00000040
115#define CCSR_SSI_SISR_TLS 0x00000020 115#define SSI_SISR_TLS 0x00000020
116#define CCSR_SSI_SISR_RLS 0x00000010 116#define SSI_SISR_RLS 0x00000010
117#define CCSR_SSI_SISR_RFF1 0x00000008 117#define SSI_SISR_RFF1 0x00000008
118#define CCSR_SSI_SISR_RFF0 0x00000004 118#define SSI_SISR_RFF0 0x00000004
119#define CCSR_SSI_SISR_TFE1 0x00000002 119#define SSI_SISR_TFE1 0x00000002
120#define CCSR_SSI_SISR_TFE0 0x00000001 120#define SSI_SISR_TFE0 0x00000001
121 121
122/* SSI Interrupt Enable Register -- CCSR_SSI_SIER 0x18 */ 122/* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
123#define CCSR_SSI_SIER_RFRC_EN 0x01000000 123#define SSI_SIER_RFRC_EN 0x01000000
124#define CCSR_SSI_SIER_TFRC_EN 0x00800000 124#define SSI_SIER_TFRC_EN 0x00800000
125#define CCSR_SSI_SIER_RDMAE 0x00400000 125#define SSI_SIER_RDMAE 0x00400000
126#define CCSR_SSI_SIER_RIE 0x00200000 126#define SSI_SIER_RIE 0x00200000
127#define CCSR_SSI_SIER_TDMAE 0x00100000 127#define SSI_SIER_TDMAE 0x00100000
128#define CCSR_SSI_SIER_TIE 0x00080000 128#define SSI_SIER_TIE 0x00080000
129#define CCSR_SSI_SIER_CMDAU_EN 0x00040000 129#define SSI_SIER_CMDAU_EN 0x00040000
130#define CCSR_SSI_SIER_CMDDU_EN 0x00020000 130#define SSI_SIER_CMDDU_EN 0x00020000
131#define CCSR_SSI_SIER_RXT_EN 0x00010000 131#define SSI_SIER_RXT_EN 0x00010000
132#define CCSR_SSI_SIER_RDR1_EN 0x00008000 132#define SSI_SIER_RDR1_EN 0x00008000
133#define CCSR_SSI_SIER_RDR0_EN 0x00004000 133#define SSI_SIER_RDR0_EN 0x00004000
134#define CCSR_SSI_SIER_TDE1_EN 0x00002000 134#define SSI_SIER_TDE1_EN 0x00002000
135#define CCSR_SSI_SIER_TDE0_EN 0x00001000 135#define SSI_SIER_TDE0_EN 0x00001000
136#define CCSR_SSI_SIER_ROE1_EN 0x00000800 136#define SSI_SIER_ROE1_EN 0x00000800
137#define CCSR_SSI_SIER_ROE0_EN 0x00000400 137#define SSI_SIER_ROE0_EN 0x00000400
138#define CCSR_SSI_SIER_TUE1_EN 0x00000200 138#define SSI_SIER_TUE1_EN 0x00000200
139#define CCSR_SSI_SIER_TUE0_EN 0x00000100 139#define SSI_SIER_TUE0_EN 0x00000100
140#define CCSR_SSI_SIER_TFS_EN 0x00000080 140#define SSI_SIER_TFS_EN 0x00000080
141#define CCSR_SSI_SIER_RFS_EN 0x00000040 141#define SSI_SIER_RFS_EN 0x00000040
142#define CCSR_SSI_SIER_TLS_EN 0x00000020 142#define SSI_SIER_TLS_EN 0x00000020
143#define CCSR_SSI_SIER_RLS_EN 0x00000010 143#define SSI_SIER_RLS_EN 0x00000010
144#define CCSR_SSI_SIER_RFF1_EN 0x00000008 144#define SSI_SIER_RFF1_EN 0x00000008
145#define CCSR_SSI_SIER_RFF0_EN 0x00000004 145#define SSI_SIER_RFF0_EN 0x00000004
146#define CCSR_SSI_SIER_TFE1_EN 0x00000002 146#define SSI_SIER_TFE1_EN 0x00000002
147#define CCSR_SSI_SIER_TFE0_EN 0x00000001 147#define SSI_SIER_TFE0_EN 0x00000001
148 148
149/* SSI Transmit Configuration Register -- CCSR_SSI_STCR 0x1C */ 149/* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
150#define CCSR_SSI_STCR_TXBIT0 0x00000200 150#define SSI_STCR_TXBIT0 0x00000200
151#define CCSR_SSI_STCR_TFEN1 0x00000100 151#define SSI_STCR_TFEN1 0x00000100
152#define CCSR_SSI_STCR_TFEN0 0x00000080 152#define SSI_STCR_TFEN0 0x00000080
153#define CCSR_SSI_STCR_TFDIR 0x00000040 153#define SSI_STCR_TFDIR 0x00000040
154#define CCSR_SSI_STCR_TXDIR 0x00000020 154#define SSI_STCR_TXDIR 0x00000020
155#define CCSR_SSI_STCR_TSHFD 0x00000010 155#define SSI_STCR_TSHFD 0x00000010
156#define CCSR_SSI_STCR_TSCKP 0x00000008 156#define SSI_STCR_TSCKP 0x00000008
157#define CCSR_SSI_STCR_TFSI 0x00000004 157#define SSI_STCR_TFSI 0x00000004
158#define CCSR_SSI_STCR_TFSL 0x00000002 158#define SSI_STCR_TFSL 0x00000002
159#define CCSR_SSI_STCR_TEFS 0x00000001 159#define SSI_STCR_TEFS 0x00000001
160 160
161/* SSI Receive Configuration Register -- CCSR_SSI_SRCR 0x20 */ 161/* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
162#define CCSR_SSI_SRCR_RXEXT 0x00000400 162#define SSI_SRCR_RXEXT 0x00000400
163#define CCSR_SSI_SRCR_RXBIT0 0x00000200 163#define SSI_SRCR_RXBIT0 0x00000200
164#define CCSR_SSI_SRCR_RFEN1 0x00000100 164#define SSI_SRCR_RFEN1 0x00000100
165#define CCSR_SSI_SRCR_RFEN0 0x00000080 165#define SSI_SRCR_RFEN0 0x00000080
166#define CCSR_SSI_SRCR_RFDIR 0x00000040 166#define SSI_SRCR_RFDIR 0x00000040
167#define CCSR_SSI_SRCR_RXDIR 0x00000020 167#define SSI_SRCR_RXDIR 0x00000020
168#define CCSR_SSI_SRCR_RSHFD 0x00000010 168#define SSI_SRCR_RSHFD 0x00000010
169#define CCSR_SSI_SRCR_RSCKP 0x00000008 169#define SSI_SRCR_RSCKP 0x00000008
170#define CCSR_SSI_SRCR_RFSI 0x00000004 170#define SSI_SRCR_RFSI 0x00000004
171#define CCSR_SSI_SRCR_RFSL 0x00000002 171#define SSI_SRCR_RFSL 0x00000002
172#define CCSR_SSI_SRCR_REFS 0x00000001 172#define SSI_SRCR_REFS 0x00000001
173 173
174/* 174/*
175 * SSI Transmit Clock Control Register -- CCSR_SSI_STCCR 0x24 175 * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
176 * SSI Receive Clock Control Register -- CCSR_SSI_SRCCR 0x28 176 * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
177 */ 177 */
178#define CCSR_SSI_SxCCR_DIV2_SHIFT 18 178#define SSI_SxCCR_DIV2_SHIFT 18
179#define CCSR_SSI_SxCCR_DIV2 0x00040000 179#define SSI_SxCCR_DIV2 0x00040000
180#define CCSR_SSI_SxCCR_PSR_SHIFT 17 180#define SSI_SxCCR_PSR_SHIFT 17
181#define CCSR_SSI_SxCCR_PSR 0x00020000 181#define SSI_SxCCR_PSR 0x00020000
182#define CCSR_SSI_SxCCR_WL_SHIFT 13 182#define SSI_SxCCR_WL_SHIFT 13
183#define CCSR_SSI_SxCCR_WL_MASK 0x0001E000 183#define SSI_SxCCR_WL_MASK 0x0001E000
184#define CCSR_SSI_SxCCR_WL(x) \ 184#define SSI_SxCCR_WL(x) \
185 (((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK) 185 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
186#define CCSR_SSI_SxCCR_DC_SHIFT 8 186#define SSI_SxCCR_DC_SHIFT 8
187#define CCSR_SSI_SxCCR_DC_MASK 0x00001F00 187#define SSI_SxCCR_DC_MASK 0x00001F00
188#define CCSR_SSI_SxCCR_DC(x) \ 188#define SSI_SxCCR_DC(x) \
189 ((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK) 189 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
190#define CCSR_SSI_SxCCR_PM_SHIFT 0 190#define SSI_SxCCR_PM_SHIFT 0
191#define CCSR_SSI_SxCCR_PM_MASK 0x000000FF 191#define SSI_SxCCR_PM_MASK 0x000000FF
192#define CCSR_SSI_SxCCR_PM(x) \ 192#define SSI_SxCCR_PM(x) \
193 ((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK) 193 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
194 194
195/* 195/*
196 * SSI FIFO Control/Status Register -- CCSR_SSI_SFCSR 0x2c 196 * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
197 * 197 *
198 * Tx or Rx FIFO Counter -- CCSR_SSI_SFCSR_xFCNTy Read-Only 198 * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
199 * Tx or Rx FIFO Watermarks -- CCSR_SSI_SFCSR_xFWMy Read/Write 199 * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
200 */ 200 */
201#define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28 201#define SSI_SFCSR_RFCNT1_SHIFT 28
202#define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000 202#define SSI_SFCSR_RFCNT1_MASK 0xF0000000
203#define CCSR_SSI_SFCSR_RFCNT1(x) \ 203#define SSI_SFCSR_RFCNT1(x) \
204 (((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT) 204 (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
205#define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24 205#define SSI_SFCSR_TFCNT1_SHIFT 24
206#define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000 206#define SSI_SFCSR_TFCNT1_MASK 0x0F000000
207#define CCSR_SSI_SFCSR_TFCNT1(x) \ 207#define SSI_SFCSR_TFCNT1(x) \
208 (((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT) 208 (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
209#define CCSR_SSI_SFCSR_RFWM1_SHIFT 20 209#define SSI_SFCSR_RFWM1_SHIFT 20
210#define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000 210#define SSI_SFCSR_RFWM1_MASK 0x00F00000
211#define CCSR_SSI_SFCSR_RFWM1(x) \ 211#define SSI_SFCSR_RFWM1(x) \
212 (((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK) 212 (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
213#define CCSR_SSI_SFCSR_TFWM1_SHIFT 16 213#define SSI_SFCSR_TFWM1_SHIFT 16
214#define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000 214#define SSI_SFCSR_TFWM1_MASK 0x000F0000
215#define CCSR_SSI_SFCSR_TFWM1(x) \ 215#define SSI_SFCSR_TFWM1(x) \
216 (((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK) 216 (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
217#define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12 217#define SSI_SFCSR_RFCNT0_SHIFT 12
218#define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000 218#define SSI_SFCSR_RFCNT0_MASK 0x0000F000
219#define CCSR_SSI_SFCSR_RFCNT0(x) \ 219#define SSI_SFCSR_RFCNT0(x) \
220 (((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT) 220 (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
221#define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8 221#define SSI_SFCSR_TFCNT0_SHIFT 8
222#define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00 222#define SSI_SFCSR_TFCNT0_MASK 0x00000F00
223#define CCSR_SSI_SFCSR_TFCNT0(x) \ 223#define SSI_SFCSR_TFCNT0(x) \
224 (((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT) 224 (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
225#define CCSR_SSI_SFCSR_RFWM0_SHIFT 4 225#define SSI_SFCSR_RFWM0_SHIFT 4
226#define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0 226#define SSI_SFCSR_RFWM0_MASK 0x000000F0
227#define CCSR_SSI_SFCSR_RFWM0(x) \ 227#define SSI_SFCSR_RFWM0(x) \
228 (((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK) 228 (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
229#define CCSR_SSI_SFCSR_TFWM0_SHIFT 0 229#define SSI_SFCSR_TFWM0_SHIFT 0
230#define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F 230#define SSI_SFCSR_TFWM0_MASK 0x0000000F
231#define CCSR_SSI_SFCSR_TFWM0(x) \ 231#define SSI_SFCSR_TFWM0(x) \
232 (((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK) 232 (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
233 233
234/* SSI Test Register -- CCSR_SSI_STR 0x30 */ 234/* SSI Test Register -- REG_SSI_STR 0x30 */
235#define CCSR_SSI_STR_TEST 0x00008000 235#define SSI_STR_TEST 0x00008000
236#define CCSR_SSI_STR_RCK2TCK 0x00004000 236#define SSI_STR_RCK2TCK 0x00004000
237#define CCSR_SSI_STR_RFS2TFS 0x00002000 237#define SSI_STR_RFS2TFS 0x00002000
238#define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F) 238#define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
239#define CCSR_SSI_STR_TXD2RXD 0x00000080 239#define SSI_STR_TXD2RXD 0x00000080
240#define CCSR_SSI_STR_TCK2RCK 0x00000040 240#define SSI_STR_TCK2RCK 0x00000040
241#define CCSR_SSI_STR_TFS2RFS 0x00000020 241#define SSI_STR_TFS2RFS 0x00000020
242#define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F) 242#define SSI_STR_TXSTATE(x) ((x) & 0x1F)
243 243
244/* SSI Option Register -- CCSR_SSI_SOR 0x34 */ 244/* SSI Option Register -- REG_SSI_SOR 0x34 */
245#define CCSR_SSI_SOR_CLKOFF 0x00000040 245#define SSI_SOR_CLKOFF 0x00000040
246#define CCSR_SSI_SOR_RX_CLR 0x00000020 246#define SSI_SOR_RX_CLR 0x00000020
247#define CCSR_SSI_SOR_TX_CLR 0x00000010 247#define SSI_SOR_TX_CLR 0x00000010
248#define CCSR_SSI_SOR_INIT 0x00000008 248#define SSI_SOR_INIT 0x00000008
249#define CCSR_SSI_SOR_WAIT_SHIFT 1 249#define SSI_SOR_WAIT_SHIFT 1
250#define CCSR_SSI_SOR_WAIT_MASK 0x00000006 250#define SSI_SOR_WAIT_MASK 0x00000006
251#define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT) 251#define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
252#define CCSR_SSI_SOR_SYNRST 0x00000001 252#define SSI_SOR_SYNRST 0x00000001
253 253
254/* SSI AC97 Control Register -- CCSR_SSI_SACNT 0x38 */ 254/* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
255#define CCSR_SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) 255#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
256#define CCSR_SSI_SACNT_WR 0x00000010 256#define SSI_SACNT_WR 0x00000010
257#define CCSR_SSI_SACNT_RD 0x00000008 257#define SSI_SACNT_RD 0x00000008
258#define CCSR_SSI_SACNT_RDWR_MASK 0x00000018 258#define SSI_SACNT_RDWR_MASK 0x00000018
259#define CCSR_SSI_SACNT_TIF 0x00000004 259#define SSI_SACNT_TIF 0x00000004
260#define CCSR_SSI_SACNT_FV 0x00000002 260#define SSI_SACNT_FV 0x00000002
261#define CCSR_SSI_SACNT_AC97EN 0x00000001 261#define SSI_SACNT_AC97EN 0x00000001
262 262
263 263
264struct device; 264struct device;
diff --git a/sound/soc/fsl/fsl_ssi_dbg.c b/sound/soc/fsl/fsl_ssi_dbg.c
index 88d9e8e08905..362df91420f6 100644
--- a/sound/soc/fsl/fsl_ssi_dbg.c
+++ b/sound/soc/fsl/fsl_ssi_dbg.c
@@ -18,67 +18,67 @@
18 18
19void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr) 19void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
20{ 20{
21 if (sisr & CCSR_SSI_SISR_RFRC) 21 if (sisr & SSI_SISR_RFRC)
22 dbg->stats.rfrc++; 22 dbg->stats.rfrc++;
23 23
24 if (sisr & CCSR_SSI_SISR_TFRC) 24 if (sisr & SSI_SISR_TFRC)
25 dbg->stats.tfrc++; 25 dbg->stats.tfrc++;
26 26
27 if (sisr & CCSR_SSI_SISR_CMDAU) 27 if (sisr & SSI_SISR_CMDAU)
28 dbg->stats.cmdau++; 28 dbg->stats.cmdau++;
29 29
30 if (sisr & CCSR_SSI_SISR_CMDDU) 30 if (sisr & SSI_SISR_CMDDU)
31 dbg->stats.cmddu++; 31 dbg->stats.cmddu++;
32 32
33 if (sisr & CCSR_SSI_SISR_RXT) 33 if (sisr & SSI_SISR_RXT)
34 dbg->stats.rxt++; 34 dbg->stats.rxt++;
35 35
36 if (sisr & CCSR_SSI_SISR_RDR1) 36 if (sisr & SSI_SISR_RDR1)
37 dbg->stats.rdr1++; 37 dbg->stats.rdr1++;
38 38
39 if (sisr & CCSR_SSI_SISR_RDR0) 39 if (sisr & SSI_SISR_RDR0)
40 dbg->stats.rdr0++; 40 dbg->stats.rdr0++;
41 41
42 if (sisr & CCSR_SSI_SISR_TDE1) 42 if (sisr & SSI_SISR_TDE1)
43 dbg->stats.tde1++; 43 dbg->stats.tde1++;
44 44
45 if (sisr & CCSR_SSI_SISR_TDE0) 45 if (sisr & SSI_SISR_TDE0)
46 dbg->stats.tde0++; 46 dbg->stats.tde0++;
47 47
48 if (sisr & CCSR_SSI_SISR_ROE1) 48 if (sisr & SSI_SISR_ROE1)
49 dbg->stats.roe1++; 49 dbg->stats.roe1++;
50 50
51 if (sisr & CCSR_SSI_SISR_ROE0) 51 if (sisr & SSI_SISR_ROE0)
52 dbg->stats.roe0++; 52 dbg->stats.roe0++;
53 53
54 if (sisr & CCSR_SSI_SISR_TUE1) 54 if (sisr & SSI_SISR_TUE1)
55 dbg->stats.tue1++; 55 dbg->stats.tue1++;
56 56
57 if (sisr & CCSR_SSI_SISR_TUE0) 57 if (sisr & SSI_SISR_TUE0)
58 dbg->stats.tue0++; 58 dbg->stats.tue0++;
59 59
60 if (sisr & CCSR_SSI_SISR_TFS) 60 if (sisr & SSI_SISR_TFS)
61 dbg->stats.tfs++; 61 dbg->stats.tfs++;
62 62
63 if (sisr & CCSR_SSI_SISR_RFS) 63 if (sisr & SSI_SISR_RFS)
64 dbg->stats.rfs++; 64 dbg->stats.rfs++;
65 65
66 if (sisr & CCSR_SSI_SISR_TLS) 66 if (sisr & SSI_SISR_TLS)
67 dbg->stats.tls++; 67 dbg->stats.tls++;
68 68
69 if (sisr & CCSR_SSI_SISR_RLS) 69 if (sisr & SSI_SISR_RLS)
70 dbg->stats.rls++; 70 dbg->stats.rls++;
71 71
72 if (sisr & CCSR_SSI_SISR_RFF1) 72 if (sisr & SSI_SISR_RFF1)
73 dbg->stats.rff1++; 73 dbg->stats.rff1++;
74 74
75 if (sisr & CCSR_SSI_SISR_RFF0) 75 if (sisr & SSI_SISR_RFF0)
76 dbg->stats.rff0++; 76 dbg->stats.rff0++;
77 77
78 if (sisr & CCSR_SSI_SISR_TFE1) 78 if (sisr & SSI_SISR_TFE1)
79 dbg->stats.tfe1++; 79 dbg->stats.tfe1++;
80 80
81 if (sisr & CCSR_SSI_SISR_TFE0) 81 if (sisr & SSI_SISR_TFE0)
82 dbg->stats.tfe0++; 82 dbg->stats.tfe0++;
83} 83}
84 84
@@ -89,7 +89,7 @@ void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
89 */ 89 */
90#define SIER_SHOW(flag, name) \ 90#define SIER_SHOW(flag, name) \
91 do { \ 91 do { \
92 if (CCSR_SSI_SIER_##flag) \ 92 if (SSI_SIER_##flag) \
93 seq_printf(s, #name "=%u\n", ssi_dbg->stats.name); \ 93 seq_printf(s, #name "=%u\n", ssi_dbg->stats.name); \
94 } while (0) 94 } while (0)
95 95
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-14 06:38:50 -0400