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authorLinus Torvalds <torvalds@linux-foundation.org>2019-09-20 18:45:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-09-20 18:45:07 -0400
commita703d279c57e1bfe2b6536c3a17c1c498b416d24 (patch)
tree3b11cc5bf81720b3cd07b0c07d04d4724d65b972
parent1ddd00276fd5fbd14dd5e366d8777dcd5f2d1b65 (diff)
parentebd47c8434064687ab6641e837144e0a3ea3872d (diff)
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "We have a small collection of core framework updates this time, mostly around clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: Drop !clk checks in debugfs dumping clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: sprd: add missing kfree clk: at91: allow 24 Mhz clock as input for PLL clk: Make clk_bulk_get_all() return a valid "id" clk: actions: Fix factor clk struct member access clk: qcom: rcg: Return failure for RCG update clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt42
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml1
-rw-r--r--Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt7
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt (renamed from Documentation/devicetree/bindings/clock/emev2-clock.txt)0
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt60
-rw-r--r--Documentation/devicetree/bindings/clock/ti,cdce925.txt4
-rw-r--r--drivers/clk/Kconfig9
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/actions/owl-common.c5
-rw-r--r--drivers/clk/actions/owl-factor.c7
-rw-r--r--drivers/clk/at91/clk-main.c12
-rw-r--r--drivers/clk/at91/sama5d2.c2
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c138
-rw-r--r--drivers/clk/bcm/clk-bcm63xx-gate.c4
-rw-r--r--drivers/clk/clk-aspeed.c78
-rw-r--r--drivers/clk/clk-aspeed.h82
-rw-r--r--drivers/clk/clk-ast2600.c704
-rw-r--r--drivers/clk/clk-bulk.c5
-rw-r--r--drivers/clk/clk-cdce925.c34
-rw-r--r--drivers/clk/clk-composite.c1
-rw-r--r--drivers/clk/clk-lochnagar.c2
-rw-r--r--drivers/clk/clk-milbeaut.c2
-rw-r--r--drivers/clk/clk-qoriq.c2
-rw-r--r--drivers/clk/clk-si5341.c1
-rw-r--r--drivers/clk/clk.c169
-rw-r--r--drivers/clk/davinci/pll.c5
-rw-r--r--drivers/clk/imx/clk-imx7ulp.c31
-rw-r--r--drivers/clk/imx/clk-imx8mm.c124
-rw-r--r--drivers/clk/imx/clk-imx8mn.c86
-rw-r--r--drivers/clk/imx/clk-imx8mq.c131
-rw-r--r--drivers/clk/imx/clk-pll14xx.c27
-rw-r--r--drivers/clk/imx/clk.h25
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4740-cgu.c11
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4780-cgu.c2
-rw-r--r--drivers/clk/mediatek/Kconfig56
-rw-r--r--drivers/clk/mediatek/Makefile9
-rw-r--r--drivers/clk/mediatek/clk-gate.c5
-rw-r--r--drivers/clk/mediatek/clk-gate.h3
-rw-r--r--drivers/clk/mediatek/clk-mt6779-aud.c117
-rw-r--r--drivers/clk/mediatek/clk-mt6779-cam.c66
-rw-r--r--drivers/clk/mediatek/clk-mt6779-img.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779-ipe.c60
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mfg.c55
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mm.c113
-rw-r--r--drivers/clk/mediatek/clk-mt6779-vdec.c67
-rw-r--r--drivers/clk/mediatek/clk-mt6779-venc.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779.c1315
-rw-r--r--drivers/clk/mediatek/clk-mt8183-mfgcfg.c7
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c44
-rw-r--r--drivers/clk/mediatek/clk-mtk.c16
-rw-r--r--drivers/clk/mediatek/clk-mtk.h8
-rw-r--r--drivers/clk/mediatek/reset.c56
-rw-r--r--drivers/clk/meson/axg-audio.c114
-rw-r--r--drivers/clk/meson/axg-audio.h1
-rw-r--r--drivers/clk/meson/g12a.c544
-rw-r--r--drivers/clk/meson/g12a.h24
-rw-r--r--drivers/clk/mvebu/Kconfig8
-rw-r--r--drivers/clk/mvebu/Makefile2
-rw-r--r--drivers/clk/mvebu/ap-cpu-clk.c356
-rw-r--r--drivers/clk/mvebu/ap806-system-controller.c178
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.c30
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.h11
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c32
-rw-r--r--drivers/clk/qcom/Kconfig9
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c236
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h7
-rw-r--r--drivers/clk/qcom/clk-rcg2.c10
-rw-r--r--drivers/clk/qcom/clk-rpmh.c42
-rw-r--r--drivers/clk/qcom/common.c20
-rw-r--r--drivers/clk/qcom/common.h2
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c2
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c4
-rw-r--r--drivers/clk/qcom/gcc-qcs404.c34
-rw-r--r--drivers/clk/qcom/gcc-sdm660.c2
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c4
-rw-r--r--drivers/clk/qcom/gcc-sm8150.c3588
-rw-r--r--drivers/clk/qcom/lpasscc-sdm845.c23
-rw-r--r--drivers/clk/qcom/turingcc-qcs404.c2
-rw-r--r--drivers/clk/renesas/clk-mstp.c3
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c3
-rw-r--r--drivers/clk/renesas/rcar-usb2-clock-sel.c4
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c3
-rw-r--r--drivers/clk/rockchip/Makefile1
-rw-r--r--drivers/clk/rockchip/clk-rk3308.c955
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c1
-rw-r--r--drivers/clk/rockchip/clk.h13
-rw-r--r--drivers/clk/sirf/clk-common.c12
-rw-r--r--drivers/clk/socfpga/clk-gate.c24
-rw-r--r--drivers/clk/socfpga/clk-periph-a10.c7
-rw-r--r--drivers/clk/spear/spear1340_clock.c2
-rw-r--r--drivers/clk/sprd/common.c5
-rw-r--r--drivers/clk/sprd/pll.c2
-rw-r--r--drivers/clk/st/clk-flexgen.c1
-rw-r--r--drivers/clk/st/clkgen-fsyn.c1
-rw-r--r--drivers/clk/st/clkgen-pll.c13
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6.c8
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.c250
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.h6
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.c5
-rw-r--r--drivers/clk/ti/apll.c9
-rw-r--r--drivers/clk/ti/clk-814x.c1
-rw-r--r--drivers/clk/ti/dpll.c13
-rw-r--r--drivers/clk/versatile/clk-versatile.c1
-rw-r--r--drivers/clk/zte/clk-zx296718.c109
-rw-r--r--drivers/phy/ti/phy-am654-serdes.c4
-rw-r--r--drivers/rtc/rtc-sun6i.c2
-rw-r--r--include/dt-bindings/clock/ast2600-clock.h113
-rw-r--r--include/dt-bindings/clock/bcm2835.h2
-rw-r--r--include/dt-bindings/clock/imx8mn-clock.h3
-rw-r--r--include/dt-bindings/clock/mt6779-clk.h436
-rw-r--r--include/dt-bindings/clock/mt8183-clk.h4
-rw-r--r--include/dt-bindings/clock/qcom,gcc-qcs404.h3
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sm8150.h243
-rw-r--r--include/dt-bindings/clock/rk3308-cru.h387
-rw-r--r--include/dt-bindings/clock/sun8i-v3s-ccu.h4
-rw-r--r--include/dt-bindings/reset-controller/mt8183-resets.h81
-rw-r--r--include/dt-bindings/reset/sun8i-v3s-ccu.h3
-rw-r--r--include/linux/clk-provider.h3
-rw-r--r--include/linux/clk.h17
-rw-r--r--include/linux/clk/clk-conf.h5
137 files changed, 11399 insertions, 638 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 7b8b8eb0191f..26410fbb85be 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -18,17 +18,19 @@ Clocks:
18------- 18-------
19 19
20 20
21The Device Tree node representing the AP806 system controller provides 21The Device Tree node representing the AP806/AP807 system controller
22a number of clocks: 22provides a number of clocks:
23 23
24 - 0: clock of CPU cluster 0 24 - 0: reference clock of CPU cluster 0
25 - 1: clock of CPU cluster 1 25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz 26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL 27 - 3: MSS clock, derived from the fixed PLL
28 28
29Required properties: 29Required properties:
30 30
31 - compatible: must be: "marvell,ap806-clock" 31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
32 - #clock-cells: must be set to 1 34 - #clock-cells: must be set to 1
33 35
34Pinctrl: 36Pinctrl:
@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
143 #thermal-sensor-cells = <1>; 145 #thermal-sensor-cells = <1>;
144 }; 146 };
145}; 147};
148
149Cluster clocks:
150---------------
151
152Device Tree Clock bindings for cluster clock of Marvell
153AP806/AP807. Each cluster contain up to 2 CPUs running at the same
154frequency.
155
156Required properties:
157 - compatible: must be one of:
158 * "marvell,ap806-cpu-clock"
159 * "marvell,ap807-cpu-clock"
160- #clock-cells : should be set to 1.
161
162- clocks : shall be the input parent clock(s) phandle for the clock
163 (one per cluster)
164
165- reg: register range associated with the cluster clocks
166
167ap_syscon1: system-controller@6f8000 {
168 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
169 reg = <0x6f8000 0x1000>;
170
171 cpu_clk: clock-cpu@278 {
172 compatible = "marvell,ap806-cpu-clock";
173 clocks = <&ap_clk 0>, <&ap_clk 1>;
174 #clock-cells = <1>;
175 reg = <0x278 0xa30>;
176 };
177};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 161e63a6c254..ff000ccade78 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys" 9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon" 10 - "mediatek,mt2712-apmixedsys", "syscon"
11 - "mediatek,mt6779-apmixedsys", "syscon"
11 - "mediatek,mt6797-apmixedsys" 12 - "mediatek,mt6797-apmixedsys"
12 - "mediatek,mt7622-apmixedsys" 13 - "mediatek,mt7622-apmixedsys"
13 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" 14 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 07c9d813465c..e4ca7b703123 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-audsys", "syscon" 9 - "mediatek,mt2701-audsys", "syscon"
10 - "mediatek,mt6779-audio", "syscon"
10 - "mediatek,mt7622-audsys", "syscon" 11 - "mediatek,mt7622-audsys", "syscon"
11 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" 12 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
12 - "mediatek,mt8183-audiosys", "syscon" 13 - "mediatek,mt8183-audiosys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
index d8930f64aa98..1f4aaa15a37e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
6Required Properties: 6Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt6779-camsys", "syscon"
9 - "mediatek,mt8183-camsys", "syscon" 10 - "mediatek,mt8183-camsys", "syscon"
10- #clock-cells: Must be 1 11- #clock-cells: Must be 1
11 12
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index e3bc4a1e7a6e..2b693e343c56 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon" 9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon" 10 - "mediatek,mt2712-imgsys", "syscon"
11 - "mediatek,mt6779-imgsys", "syscon"
11 - "mediatek,mt6797-imgsys", "syscon" 12 - "mediatek,mt6797-imgsys", "syscon"
12 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" 13 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
13 - "mediatek,mt8173-imgsys", "syscon" 14 - "mediatek,mt8173-imgsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index a90913988d7e..db2f4fd754e7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -9,6 +9,7 @@ Required Properties:
9- compatible: Should be one of: 9- compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon" 10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon" 11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6779-infracfg_ao", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon" 13 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon" 14 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" 15 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
new file mode 100644
index 000000000000..2ce889b023d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
@@ -0,0 +1,22 @@
1Mediatek ipesys controller
2============================
3
4The Mediatek ipesys controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt6779-ipesys", "syscon"
10- #clock-cells: Must be 1
11
12The ipesys controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18ipesys: clock-controller@1b000000 {
19 compatible = "mediatek,mt6779-ipesys", "syscon";
20 reg = <0 0x1b000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index 72787e7dd227..ad5f9d2f6818 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon" 9 - "mediatek,mt2712-mfgcfg", "syscon"
10 - "mediatek,mt6779-mfgcfg", "syscon"
10 - "mediatek,mt8183-mfgcfg", "syscon" 11 - "mediatek,mt8183-mfgcfg", "syscon"
11- #clock-cells: Must be 1 12- #clock-cells: Must be 1
12 13
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 545eab717c96..301eefbe1618 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-mmsys", "syscon" 9 - "mediatek,mt2701-mmsys", "syscon"
10 - "mediatek,mt2712-mmsys", "syscon" 10 - "mediatek,mt2712-mmsys", "syscon"
11 - "mediatek,mt6779-mmsys", "syscon"
11 - "mediatek,mt6797-mmsys", "syscon" 12 - "mediatek,mt6797-mmsys", "syscon"
12 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" 13 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
13 - "mediatek,mt8173-mmsys", "syscon" 14 - "mediatek,mt8173-mmsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 4c7e478117a0..ecf027a9003a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -14,6 +14,7 @@ Required Properties:
14 - "mediatek,mt7629-pericfg", "syscon" 14 - "mediatek,mt7629-pericfg", "syscon"
15 - "mediatek,mt8135-pericfg", "syscon" 15 - "mediatek,mt8135-pericfg", "syscon"
16 - "mediatek,mt8173-pericfg", "syscon" 16 - "mediatek,mt8173-pericfg", "syscon"
17 - "mediatek,mt8183-pericfg", "syscon"
17- #clock-cells: Must be 1 18- #clock-cells: Must be 1
18- #reset-cells: Must be 1 19- #reset-cells: Must be 1
19 20
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index a023b8338960..0293d693ce0c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-topckgen" 9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon" 10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6779-topckgen", "syscon"
11 - "mediatek,mt6797-topckgen" 12 - "mediatek,mt6797-topckgen"
12 - "mediatek,mt7622-topckgen" 13 - "mediatek,mt7622-topckgen"
13 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" 14 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 57176bb8dbb5..7894558b7a1c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon" 9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon" 10 - "mediatek,mt2712-vdecsys", "syscon"
11 - "mediatek,mt6779-vdecsys", "syscon"
11 - "mediatek,mt6797-vdecsys", "syscon" 12 - "mediatek,mt6797-vdecsys", "syscon"
12 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" 13 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
13 - "mediatek,mt8173-vdecsys", "syscon" 14 - "mediatek,mt8173-vdecsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index c9faa6269087..6a6a14e15cd7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon" 9 - "mediatek,mt2712-vencsys", "syscon"
10 - "mediatek,mt6779-vencsys", "syscon"
10 - "mediatek,mt6797-vencsys", "syscon" 11 - "mediatek,mt6797-vencsys", "syscon"
11 - "mediatek,mt8173-vencsys", "syscon" 12 - "mediatek,mt8173-vencsys", "syscon"
12 - "mediatek,mt8183-vencsys", "syscon" 13 - "mediatek,mt8183-vencsys", "syscon"
diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index fa4d143a73de..64938fdaea55 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -31,6 +31,7 @@ properties:
31 - allwinner,sun8i-h3-ccu 31 - allwinner,sun8i-h3-ccu
32 - allwinner,sun8i-h3-r-ccu 32 - allwinner,sun8i-h3-r-ccu
33 - allwinner,sun8i-r40-ccu 33 - allwinner,sun8i-r40-ccu
34 - allwinner,sun8i-v3-ccu
34 - allwinner,sun8i-v3s-ccu 35 - allwinner,sun8i-v3s-ccu
35 - allwinner,sun9i-a80-ccu 36 - allwinner,sun9i-a80-ccu
36 - allwinner,sun50i-a64-ccu 37 - allwinner,sun50i-a64-ccu
diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
index dd906db34b32..9e0b03a6519b 100644
--- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
@@ -12,7 +12,9 @@ clock generators, but a few (like the ARM or HDMI) will source from
12the PLL dividers directly. 12the PLL dividers directly.
13 13
14Required properties: 14Required properties:
15- compatible: Should be "brcm,bcm2835-cprman" 15- compatible: should be one of the following,
16 "brcm,bcm2711-cprman"
17 "brcm,bcm2835-cprman"
16- #clock-cells: Should be <1>. The permitted clock-specifier values can be 18- #clock-cells: Should be <1>. The permitted clock-specifier values can be
17 found in include/dt-bindings/clock/bcm2835.h 19 found in include/dt-bindings/clock/bcm2835.h
18- reg: Specifies base physical address and size of the registers 20- reg: Specifies base physical address and size of the registers
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 8661c3cd3ccf..d14362ad4132 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,7 @@ Required properties :
23 "qcom,gcc-sdm630" 23 "qcom,gcc-sdm630"
24 "qcom,gcc-sdm660" 24 "qcom,gcc-sdm660"
25 "qcom,gcc-sdm845" 25 "qcom,gcc-sdm845"
26 "qcom,gcc-sm8150"
26 27
27- reg : shall contain base register location and length 28- reg : shall contain base register location and length
28- #clock-cells : shall contain 1 29- #clock-cells : shall contain 1
@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
38- protected-clocks : Protected clock specifier list as per common clock 39- protected-clocks : Protected clock specifier list as per common clock
39 binding. 40 binding.
40 41
42For SM8150 only:
43 - clocks: a list of phandles and clock-specifier pairs,
44 one for each entry in clock-names.
45 - clock-names: "bi_tcxo" (required)
46 "sleep_clk" (optional)
47 "aud_ref_clock" (optional)
48
41Example: 49Example:
42 clock-controller@900000 { 50 clock-controller@900000 {
43 compatible = "qcom,gcc-msm8960"; 51 compatible = "qcom,gcc-msm8960";
@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
71 <GCC_LPASS_Q6_AXI_CLK>, 79 <GCC_LPASS_Q6_AXI_CLK>,
72 <GCC_LPASS_SWAY_CLK>; 80 <GCC_LPASS_SWAY_CLK>;
73 }; 81 };
82
83Example of GCC with clocks
84 gcc: clock-controller@100000 {
85 compatible = "qcom,gcc-sm8150";
86 reg = <0x00100000 0x1f0000>;
87 #clock-cells = <1>;
88 #reset-cells = <1>;
89 #power-domain-cells = <1>;
90 clock-names = "bi_tcxo",
91 "sleep_clk";
92 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
93 <&sleep_clk>;
94 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
index 3c007653da31..365bbde599b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
6other hardware subsystems via RSC to control clocks. 6other hardware subsystems via RSC to control clocks.
7 7
8Required properties : 8Required properties :
9- compatible : shall contain "qcom,sdm845-rpmh-clk" 9- compatible : must be one of:
10 "qcom,sdm845-rpmh-clk"
11 "qcom,sm8150-rpmh-clk"
10 12
11- #clock-cells : must contain 1 13- #clock-cells : must contain 1
14- clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16- clock-names: Parent board clock: "xo".
12 17
13Example : 18Example :
14 19
diff --git a/Documentation/devicetree/bindings/clock/emev2-clock.txt b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
index 268ca615459e..268ca615459e 100644
--- a/Documentation/devicetree/bindings/clock/emev2-clock.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
new file mode 100644
index 000000000000..9b151c5b0c90
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt
@@ -0,0 +1,60 @@
1* Rockchip RK3308 Clock and Reset Unit
2
3The RK3308 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: CRU should be "rockchip,rk3308-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing, pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
34 "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",
35 "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,
36 - "mac_clkin" - external MAC clock - optional
37
38Example: Clock controller node:
39
40 cru: clock-controller@ff500000 {
41 compatible = "rockchip,rk3308-cru";
42 reg = <0x0 0xff500000 0x0 0x1000>;
43 rockchip,grf = <&grf>;
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 };
47
48Example: UART controller node that consumes the clock generated by the clock
49 controller:
50
51 uart0: serial@ff0a0000 {
52 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
53 reg = <0x0 0xff0a0000 0x0 0x100>;
54 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
56 clock-names = "baudclk", "apb_pclk";
57 reg-shift = <2>;
58 reg-io-width = <4>;
59 status = "disabled";
60 };
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce925.txt b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
index 0d01f2d5cc36..26544c85202a 100644
--- a/Documentation/devicetree/bindings/clock/ti,cdce925.txt
+++ b/Documentation/devicetree/bindings/clock/ti,cdce925.txt
@@ -24,6 +24,8 @@ Required properties:
24Optional properties: 24Optional properties:
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a 25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
26 board, or to compensate for external influences. 26 board, or to compensate for external influences.
27- vdd-supply: A regulator node for Vdd
28- vddout-supply: A regulator node for Vddout
27 29
28For all PLL1, PLL2, ... an optional child node can be used to specify spread 30For all PLL1, PLL2, ... an optional child node can be used to specify spread
29spectrum clocking parameters for a board. 31spectrum clocking parameters for a board.
@@ -41,6 +43,8 @@ Example:
41 clocks = <&xtal_27Mhz>; 43 clocks = <&xtal_27Mhz>;
42 #clock-cells = <1>; 44 #clock-cells = <1>;
43 xtal-load-pf = <5>; 45 xtal-load-pf = <5>;
46 vdd-supply = <&1v8-reg>;
47 vddout-supply = <&3v3-reg>;
44 /* PLL options to get SSC 1% centered */ 48 /* PLL options to get SSC 1% centered */
45 PLL2 { 49 PLL2 {
46 spread-spectrum = <4>; 50 spread-spectrum = <4>;
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 801fa1cd0321..c44247d0b83e 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -116,7 +116,6 @@ config COMMON_CLK_SI514
116 depends on OF 116 depends on OF
117 select REGMAP_I2C 117 select REGMAP_I2C
118 help 118 help
119 ---help---
120 This driver supports the Silicon Labs 514 programmable clock 119 This driver supports the Silicon Labs 514 programmable clock
121 generator. 120 generator.
122 121
@@ -125,7 +124,6 @@ config COMMON_CLK_SI544
125 depends on I2C 124 depends on I2C
126 select REGMAP_I2C 125 select REGMAP_I2C
127 help 126 help
128 ---help---
129 This driver supports the Silicon Labs 544 programmable clock 127 This driver supports the Silicon Labs 544 programmable clock
130 generator. 128 generator.
131 129
@@ -135,7 +133,6 @@ config COMMON_CLK_SI570
135 depends on OF 133 depends on OF
136 select REGMAP_I2C 134 select REGMAP_I2C
137 help 135 help
138 ---help---
139 This driver supports Silicon Labs 570/571/598/599 programmable 136 This driver supports Silicon Labs 570/571/598/599 programmable
140 clock generators. 137 clock generators.
141 138
@@ -153,7 +150,6 @@ config COMMON_CLK_CDCE925
153 depends on OF 150 depends on OF
154 select REGMAP_I2C 151 select REGMAP_I2C
155 help 152 help
156 ---help---
157 This driver supports the TI CDCE913/925/937/949 programmable clock 153 This driver supports the TI CDCE913/925/937/949 programmable clock
158 synthesizer. Each chip has different number of PLLs and outputs. 154 synthesizer. Each chip has different number of PLLs and outputs.
159 For example, the CDCE925 contains two PLLs with spread-spectrum 155 For example, the CDCE925 contains two PLLs with spread-spectrum
@@ -212,7 +208,6 @@ config COMMON_CLK_AXI_CLKGEN
212 tristate "AXI clkgen driver" 208 tristate "AXI clkgen driver"
213 depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST 209 depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
214 help 210 help
215 ---help---
216 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx 211 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
217 FPGAs. It is commonly used in Analog Devices' reference designs. 212 FPGAs. It is commonly used in Analog Devices' reference designs.
218 213
@@ -279,26 +274,22 @@ config COMMON_CLK_VC5
279 depends on OF 274 depends on OF
280 select REGMAP_I2C 275 select REGMAP_I2C
281 help 276 help
282 ---help---
283 This driver supports the IDT VersaClock 5 and VersaClock 6 277 This driver supports the IDT VersaClock 5 and VersaClock 6
284 programmable clock generators. 278 programmable clock generators.
285 279
286config COMMON_CLK_STM32MP157 280config COMMON_CLK_STM32MP157
287 def_bool COMMON_CLK && MACH_STM32MP157 281 def_bool COMMON_CLK && MACH_STM32MP157
288 help 282 help
289 ---help---
290 Support for stm32mp157 SoC family clocks 283 Support for stm32mp157 SoC family clocks
291 284
292config COMMON_CLK_STM32F 285config COMMON_CLK_STM32F
293 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) 286 def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
294 help 287 help
295 ---help---
296 Support for stm32f4 and stm32f7 SoC families clocks 288 Support for stm32f4 and stm32f7 SoC families clocks
297 289
298config COMMON_CLK_STM32H7 290config COMMON_CLK_STM32H7
299 def_bool COMMON_CLK && MACH_STM32H743 291 def_bool COMMON_CLK && MACH_STM32H743
300 help 292 help
301 ---help---
302 Support for stm32h7 SoC family clocks 293 Support for stm32h7 SoC family clocks
303 294
304config COMMON_CLK_BD718XX 295config COMMON_CLK_BD718XX
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o 30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o 31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o 32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
33obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
33obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 34obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
34obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o 35obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
35obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o 36obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c
index 32dd29e0a37e..4de97cc7cb54 100644
--- a/drivers/clk/actions/owl-common.c
+++ b/drivers/clk/actions/owl-common.c
@@ -68,16 +68,17 @@ int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
68 struct clk_hw *hw; 68 struct clk_hw *hw;
69 69
70 for (i = 0; i < hw_clks->num; i++) { 70 for (i = 0; i < hw_clks->num; i++) {
71 const char *name;
71 72
72 hw = hw_clks->hws[i]; 73 hw = hw_clks->hws[i];
73
74 if (IS_ERR_OR_NULL(hw)) 74 if (IS_ERR_OR_NULL(hw))
75 continue; 75 continue;
76 76
77 name = hw->init->name;
77 ret = devm_clk_hw_register(dev, hw); 78 ret = devm_clk_hw_register(dev, hw);
78 if (ret) { 79 if (ret) {
79 dev_err(dev, "Couldn't register clock %d - %s\n", 80 dev_err(dev, "Couldn't register clock %d - %s\n",
80 i, hw->init->name); 81 i, name);
81 return ret; 82 return ret;
82 } 83 }
83 } 84 }
diff --git a/drivers/clk/actions/owl-factor.c b/drivers/clk/actions/owl-factor.c
index 317d4a9e112e..f15e2621fa18 100644
--- a/drivers/clk/actions/owl-factor.c
+++ b/drivers/clk/actions/owl-factor.c
@@ -64,11 +64,10 @@ static unsigned int _get_table_val(const struct clk_factor_table *table,
64 return val; 64 return val;
65} 65}
66 66
67static int clk_val_best(struct clk_hw *hw, unsigned long rate, 67static int owl_clk_val_best(const struct owl_factor_hw *factor_hw,
68 struct clk_hw *hw, unsigned long rate,
68 unsigned long *best_parent_rate) 69 unsigned long *best_parent_rate)
69{ 70{
70 struct owl_factor *factor = hw_to_owl_factor(hw);
71 struct owl_factor_hw *factor_hw = &factor->factor_hw;
72 const struct clk_factor_table *clkt = factor_hw->table; 71 const struct clk_factor_table *clkt = factor_hw->table;
73 unsigned long parent_rate, try_parent_rate, best = 0, cur_rate; 72 unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
74 unsigned long parent_rate_saved = *best_parent_rate; 73 unsigned long parent_rate_saved = *best_parent_rate;
@@ -126,7 +125,7 @@ long owl_factor_helper_round_rate(struct owl_clk_common *common,
126 const struct clk_factor_table *clkt = factor_hw->table; 125 const struct clk_factor_table *clkt = factor_hw->table;
127 unsigned int val, mul = 0, div = 1; 126 unsigned int val, mul = 0, div = 1;
128 127
129 val = clk_val_best(&common->hw, rate, parent_rate); 128 val = owl_clk_val_best(factor_hw, &common->hw, rate, parent_rate);
130 _get_table_div_mul(clkt, val, &mul, &div); 129 _get_table_div_mul(clkt, val, &mul, &div);
131 130
132 return *parent_rate * mul / div; 131 return *parent_rate * mul / div;
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index f607ee702c83..87083b3a2769 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -21,6 +21,10 @@
21 21
22#define MOR_KEY_MASK (0xff << 16) 22#define MOR_KEY_MASK (0xff << 16)
23 23
24#define clk_main_parent_select(s) (((s) & \
25 (AT91_PMC_MOSCEN | \
26 AT91_PMC_OSCBYPASS)) ? 1 : 0)
27
24struct clk_main_osc { 28struct clk_main_osc {
25 struct clk_hw hw; 29 struct clk_hw hw;
26 struct regmap *regmap; 30 struct regmap *regmap;
@@ -113,7 +117,7 @@ static int clk_main_osc_is_prepared(struct clk_hw *hw)
113 117
114 regmap_read(regmap, AT91_PMC_SR, &status); 118 regmap_read(regmap, AT91_PMC_SR, &status);
115 119
116 return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN); 120 return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
117} 121}
118 122
119static const struct clk_ops main_osc_ops = { 123static const struct clk_ops main_osc_ops = {
@@ -152,7 +156,7 @@ at91_clk_register_main_osc(struct regmap *regmap,
152 if (bypass) 156 if (bypass)
153 regmap_update_bits(regmap, 157 regmap_update_bits(regmap,
154 AT91_CKGR_MOR, MOR_KEY_MASK | 158 AT91_CKGR_MOR, MOR_KEY_MASK |
155 AT91_PMC_MOSCEN, 159 AT91_PMC_OSCBYPASS,
156 AT91_PMC_OSCBYPASS | AT91_PMC_KEY); 160 AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
157 161
158 hw = &osc->hw; 162 hw = &osc->hw;
@@ -450,7 +454,7 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
450 454
451 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); 455 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
452 456
453 return status & AT91_PMC_MOSCEN ? 1 : 0; 457 return clk_main_parent_select(status);
454} 458}
455 459
456static const struct clk_ops sam9x5_main_ops = { 460static const struct clk_ops sam9x5_main_ops = {
@@ -492,7 +496,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
492 clkmain->hw.init = &init; 496 clkmain->hw.init = &init;
493 clkmain->regmap = regmap; 497 clkmain->regmap = regmap;
494 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); 498 regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
495 clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0; 499 clkmain->parent = clk_main_parent_select(status);
496 500
497 hw = &clkmain->hw; 501 hw = &clkmain->hw;
498 ret = clk_hw_register(NULL, &clkmain->hw); 502 ret = clk_hw_register(NULL, &clkmain->hw);
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 6509d0934804..0de1108737db 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
21}; 21};
22 22
23static const struct clk_pll_characteristics plla_characteristics = { 23static const struct clk_pll_characteristics plla_characteristics = {
24 .input = { .min = 12000000, .max = 12000000 }, 24 .input = { .min = 12000000, .max = 24000000 },
25 .num_output = ARRAY_SIZE(plla_outputs), 25 .num_output = ARRAY_SIZE(plla_outputs),
26 .output = plla_outputs, 26 .output = plla_outputs,
27 .icpll = plla_icpll, 27 .icpll = plla_icpll,
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 867ae3c20041..802e488fd3c3 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -31,7 +31,7 @@
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/module.h> 33#include <linux/module.h>
34#include <linux/of.h> 34#include <linux/of_device.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <dt-bindings/clock/bcm2835.h> 37#include <dt-bindings/clock/bcm2835.h>
@@ -114,6 +114,8 @@
114#define CM_AVEODIV 0x1bc 114#define CM_AVEODIV 0x1bc
115#define CM_EMMCCTL 0x1c0 115#define CM_EMMCCTL 0x1c0
116#define CM_EMMCDIV 0x1c4 116#define CM_EMMCDIV 0x1c4
117#define CM_EMMC2CTL 0x1d0
118#define CM_EMMC2DIV 0x1d4
117 119
118/* General bits for the CM_*CTL regs */ 120/* General bits for the CM_*CTL regs */
119# define CM_ENABLE BIT(4) 121# define CM_ENABLE BIT(4)
@@ -289,6 +291,10 @@
289#define LOCK_TIMEOUT_NS 100000000 291#define LOCK_TIMEOUT_NS 100000000
290#define BCM2835_MAX_FB_RATE 1750000000u 292#define BCM2835_MAX_FB_RATE 1750000000u
291 293
294#define SOC_BCM2835 BIT(0)
295#define SOC_BCM2711 BIT(1)
296#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
297
292/* 298/*
293 * Names of clocks used within the driver that need to be replaced 299 * Names of clocks used within the driver that need to be replaced
294 * with an external parent's name. This array is in the order that 300 * with an external parent's name. This array is in the order that
@@ -320,6 +326,10 @@ struct bcm2835_cprman {
320 struct clk_hw_onecell_data onecell; 326 struct clk_hw_onecell_data onecell;
321}; 327};
322 328
329struct cprman_plat_data {
330 unsigned int soc;
331};
332
323static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 333static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
324{ 334{
325 writel(CM_PASSWORD | val, cprman->regs + reg); 335 writel(CM_PASSWORD | val, cprman->regs + reg);
@@ -1451,22 +1461,28 @@ typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1451 const void *data); 1461 const void *data);
1452struct bcm2835_clk_desc { 1462struct bcm2835_clk_desc {
1453 bcm2835_clk_register clk_register; 1463 bcm2835_clk_register clk_register;
1464 unsigned int supported;
1454 const void *data; 1465 const void *data;
1455}; 1466};
1456 1467
1457/* assignment helper macros for different clock types */ 1468/* assignment helper macros for different clock types */
1458#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1469#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \
1459 .data = __VA_ARGS__ } 1470 .supported = s, \
1460#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1471 .data = __VA_ARGS__ }
1472#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1473 s, \
1461 &(struct bcm2835_pll_data) \ 1474 &(struct bcm2835_pll_data) \
1462 {__VA_ARGS__}) 1475 {__VA_ARGS__})
1463#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1476#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1464 &(struct bcm2835_pll_divider_data) \ 1477 s, \
1465 {__VA_ARGS__}) 1478 &(struct bcm2835_pll_divider_data) \
1466#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1479 {__VA_ARGS__})
1480#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1481 s, \
1467 &(struct bcm2835_clock_data) \ 1482 &(struct bcm2835_clock_data) \
1468 {__VA_ARGS__}) 1483 {__VA_ARGS__})
1469#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1484#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1485 s, \
1470 &(struct bcm2835_gate_data) \ 1486 &(struct bcm2835_gate_data) \
1471 {__VA_ARGS__}) 1487 {__VA_ARGS__})
1472 1488
@@ -1480,7 +1496,8 @@ static const char *const bcm2835_clock_osc_parents[] = {
1480 "testdebug1" 1496 "testdebug1"
1481}; 1497};
1482 1498
1483#define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1499#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1500 s, \
1484 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1501 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1485 .parents = bcm2835_clock_osc_parents, \ 1502 .parents = bcm2835_clock_osc_parents, \
1486 __VA_ARGS__) 1503 __VA_ARGS__)
@@ -1497,7 +1514,8 @@ static const char *const bcm2835_clock_per_parents[] = {
1497 "pllh_aux", 1514 "pllh_aux",
1498}; 1515};
1499 1516
1500#define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1517#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1518 s, \
1501 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1519 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1502 .parents = bcm2835_clock_per_parents, \ 1520 .parents = bcm2835_clock_per_parents, \
1503 __VA_ARGS__) 1521 __VA_ARGS__)
@@ -1522,7 +1540,8 @@ static const char *const bcm2835_pcm_per_parents[] = {
1522 "-", 1540 "-",
1523}; 1541};
1524 1542
1525#define REGISTER_PCM_CLK(...) REGISTER_CLK( \ 1543#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1544 s, \
1526 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ 1545 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1527 .parents = bcm2835_pcm_per_parents, \ 1546 .parents = bcm2835_pcm_per_parents, \
1528 __VA_ARGS__) 1547 __VA_ARGS__)
@@ -1541,7 +1560,8 @@ static const char *const bcm2835_clock_vpu_parents[] = {
1541 "pllc_core2", 1560 "pllc_core2",
1542}; 1561};
1543 1562
1544#define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1563#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1564 s, \
1545 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1565 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1546 .parents = bcm2835_clock_vpu_parents, \ 1566 .parents = bcm2835_clock_vpu_parents, \
1547 __VA_ARGS__) 1567 __VA_ARGS__)
@@ -1577,12 +1597,14 @@ static const char *const bcm2835_clock_dsi1_parents[] = {
1577 "dsi1_byte_inv", 1597 "dsi1_byte_inv",
1578}; 1598};
1579 1599
1580#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ 1600#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1601 s, \
1581 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ 1602 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1582 .parents = bcm2835_clock_dsi0_parents, \ 1603 .parents = bcm2835_clock_dsi0_parents, \
1583 __VA_ARGS__) 1604 __VA_ARGS__)
1584 1605
1585#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ 1606#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1607 s, \
1586 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ 1608 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1587 .parents = bcm2835_clock_dsi1_parents, \ 1609 .parents = bcm2835_clock_dsi1_parents, \
1588 __VA_ARGS__) 1610 __VA_ARGS__)
@@ -1602,6 +1624,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1602 * AUDIO domain is on. 1624 * AUDIO domain is on.
1603 */ 1625 */
1604 [BCM2835_PLLA] = REGISTER_PLL( 1626 [BCM2835_PLLA] = REGISTER_PLL(
1627 SOC_ALL,
1605 .name = "plla", 1628 .name = "plla",
1606 .cm_ctrl_reg = CM_PLLA, 1629 .cm_ctrl_reg = CM_PLLA,
1607 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1630 .a2w_ctrl_reg = A2W_PLLA_CTRL,
@@ -1616,6 +1639,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1616 .max_rate = 2400000000u, 1639 .max_rate = 2400000000u,
1617 .max_fb_rate = BCM2835_MAX_FB_RATE), 1640 .max_fb_rate = BCM2835_MAX_FB_RATE),
1618 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1641 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1642 SOC_ALL,
1619 .name = "plla_core", 1643 .name = "plla_core",
1620 .source_pll = "plla", 1644 .source_pll = "plla",
1621 .cm_reg = CM_PLLA, 1645 .cm_reg = CM_PLLA,
@@ -1625,6 +1649,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1625 .fixed_divider = 1, 1649 .fixed_divider = 1,
1626 .flags = CLK_SET_RATE_PARENT), 1650 .flags = CLK_SET_RATE_PARENT),
1627 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1651 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1652 SOC_ALL,
1628 .name = "plla_per", 1653 .name = "plla_per",
1629 .source_pll = "plla", 1654 .source_pll = "plla",
1630 .cm_reg = CM_PLLA, 1655 .cm_reg = CM_PLLA,
@@ -1634,6 +1659,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1634 .fixed_divider = 1, 1659 .fixed_divider = 1,
1635 .flags = CLK_SET_RATE_PARENT), 1660 .flags = CLK_SET_RATE_PARENT),
1636 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1661 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1662 SOC_ALL,
1637 .name = "plla_dsi0", 1663 .name = "plla_dsi0",
1638 .source_pll = "plla", 1664 .source_pll = "plla",
1639 .cm_reg = CM_PLLA, 1665 .cm_reg = CM_PLLA,
@@ -1642,6 +1668,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1642 .hold_mask = CM_PLLA_HOLDDSI0, 1668 .hold_mask = CM_PLLA_HOLDDSI0,
1643 .fixed_divider = 1), 1669 .fixed_divider = 1),
1644 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1670 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1671 SOC_ALL,
1645 .name = "plla_ccp2", 1672 .name = "plla_ccp2",
1646 .source_pll = "plla", 1673 .source_pll = "plla",
1647 .cm_reg = CM_PLLA, 1674 .cm_reg = CM_PLLA,
@@ -1663,6 +1690,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1663 * AUDIO domain is on. 1690 * AUDIO domain is on.
1664 */ 1691 */
1665 [BCM2835_PLLC] = REGISTER_PLL( 1692 [BCM2835_PLLC] = REGISTER_PLL(
1693 SOC_ALL,
1666 .name = "pllc", 1694 .name = "pllc",
1667 .cm_ctrl_reg = CM_PLLC, 1695 .cm_ctrl_reg = CM_PLLC,
1668 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1696 .a2w_ctrl_reg = A2W_PLLC_CTRL,
@@ -1677,6 +1705,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1677 .max_rate = 3000000000u, 1705 .max_rate = 3000000000u,
1678 .max_fb_rate = BCM2835_MAX_FB_RATE), 1706 .max_fb_rate = BCM2835_MAX_FB_RATE),
1679 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1707 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1708 SOC_ALL,
1680 .name = "pllc_core0", 1709 .name = "pllc_core0",
1681 .source_pll = "pllc", 1710 .source_pll = "pllc",
1682 .cm_reg = CM_PLLC, 1711 .cm_reg = CM_PLLC,
@@ -1686,6 +1715,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1686 .fixed_divider = 1, 1715 .fixed_divider = 1,
1687 .flags = CLK_SET_RATE_PARENT), 1716 .flags = CLK_SET_RATE_PARENT),
1688 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1717 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1718 SOC_ALL,
1689 .name = "pllc_core1", 1719 .name = "pllc_core1",
1690 .source_pll = "pllc", 1720 .source_pll = "pllc",
1691 .cm_reg = CM_PLLC, 1721 .cm_reg = CM_PLLC,
@@ -1695,6 +1725,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1695 .fixed_divider = 1, 1725 .fixed_divider = 1,
1696 .flags = CLK_SET_RATE_PARENT), 1726 .flags = CLK_SET_RATE_PARENT),
1697 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1727 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1728 SOC_ALL,
1698 .name = "pllc_core2", 1729 .name = "pllc_core2",
1699 .source_pll = "pllc", 1730 .source_pll = "pllc",
1700 .cm_reg = CM_PLLC, 1731 .cm_reg = CM_PLLC,
@@ -1704,6 +1735,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1704 .fixed_divider = 1, 1735 .fixed_divider = 1,
1705 .flags = CLK_SET_RATE_PARENT), 1736 .flags = CLK_SET_RATE_PARENT),
1706 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1737 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1738 SOC_ALL,
1707 .name = "pllc_per", 1739 .name = "pllc_per",
1708 .source_pll = "pllc", 1740 .source_pll = "pllc",
1709 .cm_reg = CM_PLLC, 1741 .cm_reg = CM_PLLC,
@@ -1720,6 +1752,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1720 * AUDIO domain is on. 1752 * AUDIO domain is on.
1721 */ 1753 */
1722 [BCM2835_PLLD] = REGISTER_PLL( 1754 [BCM2835_PLLD] = REGISTER_PLL(
1755 SOC_ALL,
1723 .name = "plld", 1756 .name = "plld",
1724 .cm_ctrl_reg = CM_PLLD, 1757 .cm_ctrl_reg = CM_PLLD,
1725 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1758 .a2w_ctrl_reg = A2W_PLLD_CTRL,
@@ -1734,6 +1767,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1734 .max_rate = 2400000000u, 1767 .max_rate = 2400000000u,
1735 .max_fb_rate = BCM2835_MAX_FB_RATE), 1768 .max_fb_rate = BCM2835_MAX_FB_RATE),
1736 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1769 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1770 SOC_ALL,
1737 .name = "plld_core", 1771 .name = "plld_core",
1738 .source_pll = "plld", 1772 .source_pll = "plld",
1739 .cm_reg = CM_PLLD, 1773 .cm_reg = CM_PLLD,
@@ -1742,7 +1776,13 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1742 .hold_mask = CM_PLLD_HOLDCORE, 1776 .hold_mask = CM_PLLD_HOLDCORE,
1743 .fixed_divider = 1, 1777 .fixed_divider = 1,
1744 .flags = CLK_SET_RATE_PARENT), 1778 .flags = CLK_SET_RATE_PARENT),
1779 /*
1780 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1781 * Otherwise this could cause firmware lookups. That's why we mark
1782 * it as critical.
1783 */
1745 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1784 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1785 SOC_ALL,
1746 .name = "plld_per", 1786 .name = "plld_per",
1747 .source_pll = "plld", 1787 .source_pll = "plld",
1748 .cm_reg = CM_PLLD, 1788 .cm_reg = CM_PLLD,
@@ -1750,8 +1790,9 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1750 .load_mask = CM_PLLD_LOADPER, 1790 .load_mask = CM_PLLD_LOADPER,
1751 .hold_mask = CM_PLLD_HOLDPER, 1791 .hold_mask = CM_PLLD_HOLDPER,
1752 .fixed_divider = 1, 1792 .fixed_divider = 1,
1753 .flags = CLK_SET_RATE_PARENT), 1793 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1754 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1794 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1795 SOC_ALL,
1755 .name = "plld_dsi0", 1796 .name = "plld_dsi0",
1756 .source_pll = "plld", 1797 .source_pll = "plld",
1757 .cm_reg = CM_PLLD, 1798 .cm_reg = CM_PLLD,
@@ -1760,6 +1801,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1760 .hold_mask = CM_PLLD_HOLDDSI0, 1801 .hold_mask = CM_PLLD_HOLDDSI0,
1761 .fixed_divider = 1), 1802 .fixed_divider = 1),
1762 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1803 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1804 SOC_ALL,
1763 .name = "plld_dsi1", 1805 .name = "plld_dsi1",
1764 .source_pll = "plld", 1806 .source_pll = "plld",
1765 .cm_reg = CM_PLLD, 1807 .cm_reg = CM_PLLD,
@@ -1775,6 +1817,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1775 * It is in the HDMI power domain. 1817 * It is in the HDMI power domain.
1776 */ 1818 */
1777 [BCM2835_PLLH] = REGISTER_PLL( 1819 [BCM2835_PLLH] = REGISTER_PLL(
1820 SOC_BCM2835,
1778 "pllh", 1821 "pllh",
1779 .cm_ctrl_reg = CM_PLLH, 1822 .cm_ctrl_reg = CM_PLLH,
1780 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1823 .a2w_ctrl_reg = A2W_PLLH_CTRL,
@@ -1789,6 +1832,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1789 .max_rate = 3000000000u, 1832 .max_rate = 3000000000u,
1790 .max_fb_rate = BCM2835_MAX_FB_RATE), 1833 .max_fb_rate = BCM2835_MAX_FB_RATE),
1791 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1834 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1835 SOC_BCM2835,
1792 .name = "pllh_rcal", 1836 .name = "pllh_rcal",
1793 .source_pll = "pllh", 1837 .source_pll = "pllh",
1794 .cm_reg = CM_PLLH, 1838 .cm_reg = CM_PLLH,
@@ -1798,6 +1842,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1798 .fixed_divider = 10, 1842 .fixed_divider = 10,
1799 .flags = CLK_SET_RATE_PARENT), 1843 .flags = CLK_SET_RATE_PARENT),
1800 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1844 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1845 SOC_BCM2835,
1801 .name = "pllh_aux", 1846 .name = "pllh_aux",
1802 .source_pll = "pllh", 1847 .source_pll = "pllh",
1803 .cm_reg = CM_PLLH, 1848 .cm_reg = CM_PLLH,
@@ -1807,6 +1852,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1807 .fixed_divider = 1, 1852 .fixed_divider = 1,
1808 .flags = CLK_SET_RATE_PARENT), 1853 .flags = CLK_SET_RATE_PARENT),
1809 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1854 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1855 SOC_BCM2835,
1810 .name = "pllh_pix", 1856 .name = "pllh_pix",
1811 .source_pll = "pllh", 1857 .source_pll = "pllh",
1812 .cm_reg = CM_PLLH, 1858 .cm_reg = CM_PLLH,
@@ -1822,6 +1868,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1822 1868
1823 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1869 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1824 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1870 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1871 SOC_ALL,
1825 .name = "otp", 1872 .name = "otp",
1826 .ctl_reg = CM_OTPCTL, 1873 .ctl_reg = CM_OTPCTL,
1827 .div_reg = CM_OTPDIV, 1874 .div_reg = CM_OTPDIV,
@@ -1833,6 +1880,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1833 * bythe watchdog timer and the camera pulse generator. 1880 * bythe watchdog timer and the camera pulse generator.
1834 */ 1881 */
1835 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1882 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1883 SOC_ALL,
1836 .name = "timer", 1884 .name = "timer",
1837 .ctl_reg = CM_TIMERCTL, 1885 .ctl_reg = CM_TIMERCTL,
1838 .div_reg = CM_TIMERDIV, 1886 .div_reg = CM_TIMERDIV,
@@ -1843,12 +1891,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1843 * Generally run at 2Mhz, max 5Mhz. 1891 * Generally run at 2Mhz, max 5Mhz.
1844 */ 1892 */
1845 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1893 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1894 SOC_ALL,
1846 .name = "tsens", 1895 .name = "tsens",
1847 .ctl_reg = CM_TSENSCTL, 1896 .ctl_reg = CM_TSENSCTL,
1848 .div_reg = CM_TSENSDIV, 1897 .div_reg = CM_TSENSDIV,
1849 .int_bits = 5, 1898 .int_bits = 5,
1850 .frac_bits = 0), 1899 .frac_bits = 0),
1851 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1900 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1901 SOC_ALL,
1852 .name = "tec", 1902 .name = "tec",
1853 .ctl_reg = CM_TECCTL, 1903 .ctl_reg = CM_TECCTL,
1854 .div_reg = CM_TECDIV, 1904 .div_reg = CM_TECDIV,
@@ -1857,6 +1907,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1857 1907
1858 /* clocks with vpu parent mux */ 1908 /* clocks with vpu parent mux */
1859 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1909 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1910 SOC_ALL,
1860 .name = "h264", 1911 .name = "h264",
1861 .ctl_reg = CM_H264CTL, 1912 .ctl_reg = CM_H264CTL,
1862 .div_reg = CM_H264DIV, 1913 .div_reg = CM_H264DIV,
@@ -1864,6 +1915,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1864 .frac_bits = 8, 1915 .frac_bits = 8,
1865 .tcnt_mux = 1), 1916 .tcnt_mux = 1),
1866 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1917 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1918 SOC_ALL,
1867 .name = "isp", 1919 .name = "isp",
1868 .ctl_reg = CM_ISPCTL, 1920 .ctl_reg = CM_ISPCTL,
1869 .div_reg = CM_ISPDIV, 1921 .div_reg = CM_ISPDIV,
@@ -1876,6 +1928,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1876 * in the SDRAM controller can't be used. 1928 * in the SDRAM controller can't be used.
1877 */ 1929 */
1878 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1930 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1931 SOC_ALL,
1879 .name = "sdram", 1932 .name = "sdram",
1880 .ctl_reg = CM_SDCCTL, 1933 .ctl_reg = CM_SDCCTL,
1881 .div_reg = CM_SDCDIV, 1934 .div_reg = CM_SDCDIV,
@@ -1883,6 +1936,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1883 .frac_bits = 0, 1936 .frac_bits = 0,
1884 .tcnt_mux = 3), 1937 .tcnt_mux = 3),
1885 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1938 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1939 SOC_ALL,
1886 .name = "v3d", 1940 .name = "v3d",
1887 .ctl_reg = CM_V3DCTL, 1941 .ctl_reg = CM_V3DCTL,
1888 .div_reg = CM_V3DDIV, 1942 .div_reg = CM_V3DDIV,
@@ -1896,6 +1950,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1896 * in various hardware documentation. 1950 * in various hardware documentation.
1897 */ 1951 */
1898 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1952 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
1953 SOC_ALL,
1899 .name = "vpu", 1954 .name = "vpu",
1900 .ctl_reg = CM_VPUCTL, 1955 .ctl_reg = CM_VPUCTL,
1901 .div_reg = CM_VPUDIV, 1956 .div_reg = CM_VPUDIV,
@@ -1907,6 +1962,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1907 1962
1908 /* clocks with per parent mux */ 1963 /* clocks with per parent mux */
1909 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1964 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
1965 SOC_ALL,
1910 .name = "aveo", 1966 .name = "aveo",
1911 .ctl_reg = CM_AVEOCTL, 1967 .ctl_reg = CM_AVEOCTL,
1912 .div_reg = CM_AVEODIV, 1968 .div_reg = CM_AVEODIV,
@@ -1914,6 +1970,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1914 .frac_bits = 0, 1970 .frac_bits = 0,
1915 .tcnt_mux = 38), 1971 .tcnt_mux = 38),
1916 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1972 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
1973 SOC_ALL,
1917 .name = "cam0", 1974 .name = "cam0",
1918 .ctl_reg = CM_CAM0CTL, 1975 .ctl_reg = CM_CAM0CTL,
1919 .div_reg = CM_CAM0DIV, 1976 .div_reg = CM_CAM0DIV,
@@ -1921,6 +1978,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1921 .frac_bits = 8, 1978 .frac_bits = 8,
1922 .tcnt_mux = 14), 1979 .tcnt_mux = 14),
1923 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1980 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
1981 SOC_ALL,
1924 .name = "cam1", 1982 .name = "cam1",
1925 .ctl_reg = CM_CAM1CTL, 1983 .ctl_reg = CM_CAM1CTL,
1926 .div_reg = CM_CAM1DIV, 1984 .div_reg = CM_CAM1DIV,
@@ -1928,12 +1986,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1928 .frac_bits = 8, 1986 .frac_bits = 8,
1929 .tcnt_mux = 15), 1987 .tcnt_mux = 15),
1930 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1988 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
1989 SOC_ALL,
1931 .name = "dft", 1990 .name = "dft",
1932 .ctl_reg = CM_DFTCTL, 1991 .ctl_reg = CM_DFTCTL,
1933 .div_reg = CM_DFTDIV, 1992 .div_reg = CM_DFTDIV,
1934 .int_bits = 5, 1993 .int_bits = 5,
1935 .frac_bits = 0), 1994 .frac_bits = 0),
1936 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1995 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
1996 SOC_ALL,
1937 .name = "dpi", 1997 .name = "dpi",
1938 .ctl_reg = CM_DPICTL, 1998 .ctl_reg = CM_DPICTL,
1939 .div_reg = CM_DPIDIV, 1999 .div_reg = CM_DPIDIV,
@@ -1943,6 +2003,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1943 2003
1944 /* Arasan EMMC clock */ 2004 /* Arasan EMMC clock */
1945 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 2005 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2006 SOC_ALL,
1946 .name = "emmc", 2007 .name = "emmc",
1947 .ctl_reg = CM_EMMCCTL, 2008 .ctl_reg = CM_EMMCCTL,
1948 .div_reg = CM_EMMCDIV, 2009 .div_reg = CM_EMMCDIV,
@@ -1950,8 +2011,19 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1950 .frac_bits = 8, 2011 .frac_bits = 8,
1951 .tcnt_mux = 39), 2012 .tcnt_mux = 39),
1952 2013
2014 /* EMMC2 clock (only available for BCM2711) */
2015 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2016 SOC_BCM2711,
2017 .name = "emmc2",
2018 .ctl_reg = CM_EMMC2CTL,
2019 .div_reg = CM_EMMC2DIV,
2020 .int_bits = 4,
2021 .frac_bits = 8,
2022 .tcnt_mux = 42),
2023
1953 /* General purpose (GPIO) clocks */ 2024 /* General purpose (GPIO) clocks */
1954 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 2025 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2026 SOC_ALL,
1955 .name = "gp0", 2027 .name = "gp0",
1956 .ctl_reg = CM_GP0CTL, 2028 .ctl_reg = CM_GP0CTL,
1957 .div_reg = CM_GP0DIV, 2029 .div_reg = CM_GP0DIV,
@@ -1960,6 +2032,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1960 .is_mash_clock = true, 2032 .is_mash_clock = true,
1961 .tcnt_mux = 20), 2033 .tcnt_mux = 20),
1962 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 2034 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2035 SOC_ALL,
1963 .name = "gp1", 2036 .name = "gp1",
1964 .ctl_reg = CM_GP1CTL, 2037 .ctl_reg = CM_GP1CTL,
1965 .div_reg = CM_GP1DIV, 2038 .div_reg = CM_GP1DIV,
@@ -1969,6 +2042,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1969 .is_mash_clock = true, 2042 .is_mash_clock = true,
1970 .tcnt_mux = 21), 2043 .tcnt_mux = 21),
1971 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 2044 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2045 SOC_ALL,
1972 .name = "gp2", 2046 .name = "gp2",
1973 .ctl_reg = CM_GP2CTL, 2047 .ctl_reg = CM_GP2CTL,
1974 .div_reg = CM_GP2DIV, 2048 .div_reg = CM_GP2DIV,
@@ -1978,6 +2052,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1978 2052
1979 /* HDMI state machine */ 2053 /* HDMI state machine */
1980 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 2054 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2055 SOC_ALL,
1981 .name = "hsm", 2056 .name = "hsm",
1982 .ctl_reg = CM_HSMCTL, 2057 .ctl_reg = CM_HSMCTL,
1983 .div_reg = CM_HSMDIV, 2058 .div_reg = CM_HSMDIV,
@@ -1985,6 +2060,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1985 .frac_bits = 8, 2060 .frac_bits = 8,
1986 .tcnt_mux = 22), 2061 .tcnt_mux = 22),
1987 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( 2062 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2063 SOC_ALL,
1988 .name = "pcm", 2064 .name = "pcm",
1989 .ctl_reg = CM_PCMCTL, 2065 .ctl_reg = CM_PCMCTL,
1990 .div_reg = CM_PCMDIV, 2066 .div_reg = CM_PCMDIV,
@@ -1994,6 +2070,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
1994 .low_jitter = true, 2070 .low_jitter = true,
1995 .tcnt_mux = 23), 2071 .tcnt_mux = 23),
1996 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 2072 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2073 SOC_ALL,
1997 .name = "pwm", 2074 .name = "pwm",
1998 .ctl_reg = CM_PWMCTL, 2075 .ctl_reg = CM_PWMCTL,
1999 .div_reg = CM_PWMDIV, 2076 .div_reg = CM_PWMDIV,
@@ -2002,6 +2079,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2002 .is_mash_clock = true, 2079 .is_mash_clock = true,
2003 .tcnt_mux = 24), 2080 .tcnt_mux = 24),
2004 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 2081 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2082 SOC_ALL,
2005 .name = "slim", 2083 .name = "slim",
2006 .ctl_reg = CM_SLIMCTL, 2084 .ctl_reg = CM_SLIMCTL,
2007 .div_reg = CM_SLIMDIV, 2085 .div_reg = CM_SLIMDIV,
@@ -2010,6 +2088,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2010 .is_mash_clock = true, 2088 .is_mash_clock = true,
2011 .tcnt_mux = 25), 2089 .tcnt_mux = 25),
2012 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 2090 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2091 SOC_ALL,
2013 .name = "smi", 2092 .name = "smi",
2014 .ctl_reg = CM_SMICTL, 2093 .ctl_reg = CM_SMICTL,
2015 .div_reg = CM_SMIDIV, 2094 .div_reg = CM_SMIDIV,
@@ -2017,6 +2096,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2017 .frac_bits = 8, 2096 .frac_bits = 8,
2018 .tcnt_mux = 27), 2097 .tcnt_mux = 27),
2019 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 2098 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2099 SOC_ALL,
2020 .name = "uart", 2100 .name = "uart",
2021 .ctl_reg = CM_UARTCTL, 2101 .ctl_reg = CM_UARTCTL,
2022 .div_reg = CM_UARTDIV, 2102 .div_reg = CM_UARTDIV,
@@ -2026,6 +2106,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2026 2106
2027 /* TV encoder clock. Only operating frequency is 108Mhz. */ 2107 /* TV encoder clock. Only operating frequency is 108Mhz. */
2028 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 2108 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2109 SOC_ALL,
2029 .name = "vec", 2110 .name = "vec",
2030 .ctl_reg = CM_VECCTL, 2111 .ctl_reg = CM_VECCTL,
2031 .div_reg = CM_VECDIV, 2112 .div_reg = CM_VECDIV,
@@ -2040,6 +2121,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2040 2121
2041 /* dsi clocks */ 2122 /* dsi clocks */
2042 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 2123 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2124 SOC_ALL,
2043 .name = "dsi0e", 2125 .name = "dsi0e",
2044 .ctl_reg = CM_DSI0ECTL, 2126 .ctl_reg = CM_DSI0ECTL,
2045 .div_reg = CM_DSI0EDIV, 2127 .div_reg = CM_DSI0EDIV,
@@ -2047,6 +2129,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2047 .frac_bits = 8, 2129 .frac_bits = 8,
2048 .tcnt_mux = 18), 2130 .tcnt_mux = 18),
2049 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 2131 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2132 SOC_ALL,
2050 .name = "dsi1e", 2133 .name = "dsi1e",
2051 .ctl_reg = CM_DSI1ECTL, 2134 .ctl_reg = CM_DSI1ECTL,
2052 .div_reg = CM_DSI1EDIV, 2135 .div_reg = CM_DSI1EDIV,
@@ -2054,6 +2137,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2054 .frac_bits = 8, 2137 .frac_bits = 8,
2055 .tcnt_mux = 19), 2138 .tcnt_mux = 19),
2056 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( 2139 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2140 SOC_ALL,
2057 .name = "dsi0p", 2141 .name = "dsi0p",
2058 .ctl_reg = CM_DSI0PCTL, 2142 .ctl_reg = CM_DSI0PCTL,
2059 .div_reg = CM_DSI0PDIV, 2143 .div_reg = CM_DSI0PDIV,
@@ -2061,6 +2145,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2061 .frac_bits = 0, 2145 .frac_bits = 0,
2062 .tcnt_mux = 12), 2146 .tcnt_mux = 12),
2063 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( 2147 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2148 SOC_ALL,
2064 .name = "dsi1p", 2149 .name = "dsi1p",
2065 .ctl_reg = CM_DSI1PCTL, 2150 .ctl_reg = CM_DSI1PCTL,
2066 .div_reg = CM_DSI1PDIV, 2151 .div_reg = CM_DSI1PDIV,
@@ -2077,6 +2162,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
2077 * non-stop vpu clock. 2162 * non-stop vpu clock.
2078 */ 2163 */
2079 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 2164 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2165 SOC_ALL,
2080 .name = "peri_image", 2166 .name = "peri_image",
2081 .parent = "vpu", 2167 .parent = "vpu",
2082 .ctl_reg = CM_PERIICTL), 2168 .ctl_reg = CM_PERIICTL),
@@ -2109,9 +2195,14 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
2109 struct resource *res; 2195 struct resource *res;
2110 const struct bcm2835_clk_desc *desc; 2196 const struct bcm2835_clk_desc *desc;
2111 const size_t asize = ARRAY_SIZE(clk_desc_array); 2197 const size_t asize = ARRAY_SIZE(clk_desc_array);
2198 const struct cprman_plat_data *pdata;
2112 size_t i; 2199 size_t i;
2113 int ret; 2200 int ret;
2114 2201
2202 pdata = of_device_get_match_data(&pdev->dev);
2203 if (!pdata)
2204 return -ENODEV;
2205
2115 cprman = devm_kzalloc(dev, 2206 cprman = devm_kzalloc(dev,
2116 struct_size(cprman, onecell.hws, asize), 2207 struct_size(cprman, onecell.hws, asize),
2117 GFP_KERNEL); 2208 GFP_KERNEL);
@@ -2147,8 +2238,10 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
2147 2238
2148 for (i = 0; i < asize; i++) { 2239 for (i = 0; i < asize; i++) {
2149 desc = &clk_desc_array[i]; 2240 desc = &clk_desc_array[i];
2150 if (desc->clk_register && desc->data) 2241 if (desc->clk_register && desc->data &&
2242 (desc->supported & pdata->soc)) {
2151 hws[i] = desc->clk_register(cprman, desc->data); 2243 hws[i] = desc->clk_register(cprman, desc->data);
2244 }
2152 } 2245 }
2153 2246
2154 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 2247 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
@@ -2159,8 +2252,17 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
2159 &cprman->onecell); 2252 &cprman->onecell);
2160} 2253}
2161 2254
2255static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2256 .soc = SOC_BCM2835,
2257};
2258
2259static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2260 .soc = SOC_BCM2711,
2261};
2262
2162static const struct of_device_id bcm2835_clk_of_match[] = { 2263static const struct of_device_id bcm2835_clk_of_match[] = {
2163 { .compatible = "brcm,bcm2835-cprman", }, 2264 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2265 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2164 {} 2266 {}
2165}; 2267};
2166MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 2268MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c
index 9e1dcd43258c..98e884957db8 100644
--- a/drivers/clk/bcm/clk-bcm63xx-gate.c
+++ b/drivers/clk/bcm/clk-bcm63xx-gate.c
@@ -146,7 +146,6 @@ static int clk_bcm63xx_probe(struct platform_device *pdev)
146{ 146{
147 const struct clk_bcm63xx_table_entry *entry, *table; 147 const struct clk_bcm63xx_table_entry *entry, *table;
148 struct clk_bcm63xx_hw *hw; 148 struct clk_bcm63xx_hw *hw;
149 struct resource *r;
150 u8 maxbit = 0; 149 u8 maxbit = 0;
151 int i, ret; 150 int i, ret;
152 151
@@ -170,8 +169,7 @@ static int clk_bcm63xx_probe(struct platform_device *pdev)
170 for (i = 0; i < maxbit; i++) 169 for (i = 0; i < maxbit; i++)
171 hw->data.hws[i] = ERR_PTR(-ENODEV); 170 hw->data.hws[i] = ERR_PTR(-ENODEV);
172 171
173 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 172 hw->regs = devm_platform_ioremap_resource(pdev, 0);
174 hw->regs = devm_ioremap_resource(&pdev->dev, r);
175 if (IS_ERR(hw->regs)) 173 if (IS_ERR(hw->regs))
176 return PTR_ERR(hw->regs); 174 return PTR_ERR(hw->regs);
177 175
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 42b4df6ba249..abf06fb6453e 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -1,19 +1,19 @@
1// SPDX-License-Identifier: GPL-2.0+ 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright IBM Corp
2 3
3#define pr_fmt(fmt) "clk-aspeed: " fmt 4#define pr_fmt(fmt) "clk-aspeed: " fmt
4 5
5#include <linux/clk-provider.h>
6#include <linux/mfd/syscon.h> 6#include <linux/mfd/syscon.h>
7#include <linux/of_address.h> 7#include <linux/of_address.h>
8#include <linux/of_device.h> 8#include <linux/of_device.h>
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/regmap.h> 10#include <linux/regmap.h>
11#include <linux/reset-controller.h>
12#include <linux/slab.h> 11#include <linux/slab.h>
13#include <linux/spinlock.h>
14 12
15#include <dt-bindings/clock/aspeed-clock.h> 13#include <dt-bindings/clock/aspeed-clock.h>
16 14
15#include "clk-aspeed.h"
16
17#define ASPEED_NUM_CLKS 36 17#define ASPEED_NUM_CLKS 36
18 18
19#define ASPEED_RESET2_OFFSET 32 19#define ASPEED_RESET2_OFFSET 32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
42 42
43static void __iomem *scu_base; 43static void __iomem *scu_base;
44 44
45/**
46 * struct aspeed_gate_data - Aspeed gated clocks
47 * @clock_idx: bit used to gate this clock in the clock register
48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
49 * reset is required when enabling the clock
50 * @name: the clock name
51 * @parent_name: the name of the parent clock
52 * @flags: standard clock framework flags
53 */
54struct aspeed_gate_data {
55 u8 clock_idx;
56 s8 reset_idx;
57 const char *name;
58 const char *parent_name;
59 unsigned long flags;
60};
61
62/**
63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
64 * @hw: handle between common and hardware-specific interfaces
65 * @reg: register controlling gate
66 * @clock_idx: bit used to gate this clock in the clock register
67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
68 * reset is required when enabling the clock
69 * @flags: hardware-specific flags
70 * @lock: register lock
71 *
72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
73 * This modified version of clk_gate allows an optional reset bit to be
74 * specified.
75 */
76struct aspeed_clk_gate {
77 struct clk_hw hw;
78 struct regmap *map;
79 u8 clock_idx;
80 s8 reset_idx;
81 u8 flags;
82 spinlock_t *lock;
83};
84
85#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
86
87/* TODO: ask Aspeed about the actual parent data */ 45/* TODO: ask Aspeed about the actual parent data */
88static const struct aspeed_gate_data aspeed_gates[] = { 46static const struct aspeed_gate_data aspeed_gates[] = {
89 /* clk rst name parent flags */ 47 /* clk rst name parent flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
208 mult, div); 166 mult, div);
209} 167}
210 168
211struct aspeed_clk_soc_data {
212 const struct clk_div_table *div_table;
213 const struct clk_div_table *eclk_div_table;
214 const struct clk_div_table *mac_div_table;
215 struct clk_hw *(*calc_pll)(const char *name, u32 val);
216};
217
218static const struct aspeed_clk_soc_data ast2500_data = { 169static const struct aspeed_clk_soc_data ast2500_data = {
219 .div_table = ast2500_div_table, 170 .div_table = ast2500_div_table,
220 .eclk_div_table = ast2500_eclk_div_table, 171 .eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
315 .is_enabled = aspeed_clk_is_enabled, 266 .is_enabled = aspeed_clk_is_enabled,
316}; 267};
317 268
318/**
319 * struct aspeed_reset - Aspeed reset controller
320 * @map: regmap to access the containing system controller
321 * @rcdev: reset controller device
322 */
323struct aspeed_reset {
324 struct regmap *map;
325 struct reset_controller_dev rcdev;
326};
327
328#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
329
330static const u8 aspeed_resets[] = { 269static const u8 aspeed_resets[] = {
331 /* SCU04 resets */ 270 /* SCU04 resets */
332 [ASPEED_RESET_XDMA] = 25, 271 [ASPEED_RESET_XDMA] = 25,
@@ -500,9 +439,14 @@ static int aspeed_clk_probe(struct platform_device *pdev)
500 return PTR_ERR(hw); 439 return PTR_ERR(hw);
501 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 440 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
502 441
503 /* SD/SDIO clock divider (TODO: There's a gate too) */ 442 /* SD/SDIO clock divider and gate */
504 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, 443 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
505 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 444 scu_base + ASPEED_CLK_SELECTION, 15, 0,
445 &aspeed_clk_lock);
446 if (IS_ERR(hw))
447 return PTR_ERR(hw);
448 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
449 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
506 soc_data->div_table, 450 soc_data->div_table,
507 &aspeed_clk_lock); 451 &aspeed_clk_lock);
508 if (IS_ERR(hw)) 452 if (IS_ERR(hw))
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..5296b15b1c88
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,82 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Structures used by ASPEED clock drivers
4 *
5 * Copyright 2019 IBM Corp.
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/kernel.h>
10#include <linux/reset-controller.h>
11#include <linux/spinlock.h>
12
13struct clk_div_table;
14struct regmap;
15
16/**
17 * struct aspeed_gate_data - Aspeed gated clocks
18 * @clock_idx: bit used to gate this clock in the clock register
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20 * reset is required when enabling the clock
21 * @name: the clock name
22 * @parent_name: the name of the parent clock
23 * @flags: standard clock framework flags
24 */
25struct aspeed_gate_data {
26 u8 clock_idx;
27 s8 reset_idx;
28 const char *name;
29 const char *parent_name;
30 unsigned long flags;
31};
32
33/**
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
36 * @reg: register controlling gate
37 * @clock_idx: bit used to gate this clock in the clock register
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
39 * reset is required when enabling the clock
40 * @flags: hardware-specific flags
41 * @lock: register lock
42 *
43 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
44 * This modified version of clk_gate allows an optional reset bit to be
45 * specified.
46 */
47struct aspeed_clk_gate {
48 struct clk_hw hw;
49 struct regmap *map;
50 u8 clock_idx;
51 s8 reset_idx;
52 u8 flags;
53 spinlock_t *lock;
54};
55
56#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
57
58/**
59 * struct aspeed_reset - Aspeed reset controller
60 * @map: regmap to access the containing system controller
61 * @rcdev: reset controller device
62 */
63struct aspeed_reset {
64 struct regmap *map;
65 struct reset_controller_dev rcdev;
66};
67
68#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
69
70/**
71 * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
72 * @div_table: Common divider lookup table
73 * @eclk_div_table: Divider lookup table for ECLK
74 * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
75 * @calc_pll: Callback to maculate common PLL settings
76 */
77struct aspeed_clk_soc_data {
78 const struct clk_div_table *div_table;
79 const struct clk_div_table *eclk_div_table;
80 const struct clk_div_table *mac_div_table;
81 struct clk_hw *(*calc_pll)(const char *name, u32 val);
82};
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..1c1bb39bb04e
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,704 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright IBM Corp
3// Copyright ASPEED Technology
4
5#define pr_fmt(fmt) "clk-ast2600: " fmt
6
7#include <linux/mfd/syscon.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include <dt-bindings/clock/ast2600-clock.h>
15
16#include "clk-aspeed.h"
17
18#define ASPEED_G6_NUM_CLKS 67
19
20#define ASPEED_G6_SILICON_REV 0x004
21
22#define ASPEED_G6_RESET_CTRL 0x040
23#define ASPEED_G6_RESET_CTRL2 0x050
24
25#define ASPEED_G6_CLK_STOP_CTRL 0x080
26#define ASPEED_G6_CLK_STOP_CTRL2 0x090
27
28#define ASPEED_G6_MISC_CTRL 0x0C0
29#define UART_DIV13_EN BIT(12)
30
31#define ASPEED_G6_CLK_SELECTION1 0x300
32#define ASPEED_G6_CLK_SELECTION2 0x304
33#define ASPEED_G6_CLK_SELECTION4 0x310
34
35#define ASPEED_HPLL_PARAM 0x200
36#define ASPEED_APLL_PARAM 0x210
37#define ASPEED_MPLL_PARAM 0x220
38#define ASPEED_EPLL_PARAM 0x240
39#define ASPEED_DPLL_PARAM 0x260
40
41#define ASPEED_G6_STRAP1 0x500
42
43/* Globally visible clocks */
44static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
45
46/* Keeps track of all clocks */
47static struct clk_hw_onecell_data *aspeed_g6_clk_data;
48
49static void __iomem *scu_g6_base;
50
51/*
52 * Clocks marked with CLK_IS_CRITICAL:
53 *
54 * ref0 and ref1 are essential for the SoC to operate
55 * mpll is required if SDRAM is used
56 */
57static const struct aspeed_gate_data aspeed_g6_gates[] = {
58 /* clk rst name parent flags */
59 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
60 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
61 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
62 /* vclk parent - dclk/d1clk/hclk/mclk */
63 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
64 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
65 /* From dpll */
66 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
67 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
68 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
69 /* Reserved 8 */
70 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
71 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
72 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
73 /* Reserved 11/12 */
74 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
75 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
76 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
77 /* Reserved 16/19 */
78 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
79 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
80 /* Reserved 22/23 */
81 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
82 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
83 /* Reserved 26 */
84 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
85 /* Reserved 28/29/30 */
86 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
87 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
88 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
89 /* Reserved 35 */
90 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
91 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
92 /* Reserved 38 RSA: no longer used */
93 /* Reserved 39 */
94 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
95 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
96 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
97 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
98 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
99 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
100 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
101 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
102 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
103 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
104 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
105 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
106 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
107 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
108 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
109 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
110 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
111 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
112 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
113 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
114 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
115 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
116 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
117};
118
119static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
120
121static const struct clk_div_table ast2600_eclk_div_table[] = {
122 { 0x0, 2 },
123 { 0x1, 2 },
124 { 0x2, 3 },
125 { 0x3, 4 },
126 { 0x4, 5 },
127 { 0x5, 6 },
128 { 0x6, 7 },
129 { 0x7, 8 },
130 { 0 }
131};
132
133static const struct clk_div_table ast2600_mac_div_table[] = {
134 { 0x0, 4 },
135 { 0x1, 4 },
136 { 0x2, 6 },
137 { 0x3, 8 },
138 { 0x4, 10 },
139 { 0x5, 12 },
140 { 0x6, 14 },
141 { 0x7, 16 },
142 { 0 }
143};
144
145static const struct clk_div_table ast2600_div_table[] = {
146 { 0x0, 4 },
147 { 0x1, 8 },
148 { 0x2, 12 },
149 { 0x3, 16 },
150 { 0x4, 20 },
151 { 0x5, 24 },
152 { 0x6, 28 },
153 { 0x7, 32 },
154 { 0 }
155};
156
157/* For hpll/dpll/epll/mpll */
158static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
159{
160 unsigned int mult, div;
161
162 if (val & BIT(24)) {
163 /* Pass through mode */
164 mult = div = 1;
165 } else {
166 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
167 u32 m = val & 0x1fff;
168 u32 n = (val >> 13) & 0x3f;
169 u32 p = (val >> 19) & 0xf;
170 mult = (m + 1) / (n + 1);
171 div = (p + 1);
172 }
173 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
174 mult, div);
175};
176
177static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
178{
179 unsigned int mult, div;
180
181 if (val & BIT(20)) {
182 /* Pass through mode */
183 mult = div = 1;
184 } else {
185 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
186 u32 m = (val >> 5) & 0x3f;
187 u32 od = (val >> 4) & 0x1;
188 u32 n = val & 0xf;
189
190 mult = (2 - od) * (m + 2);
191 div = n + 1;
192 }
193 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
194 mult, div);
195};
196
197static u32 get_bit(u8 idx)
198{
199 return BIT(idx % 32);
200}
201
202static u32 get_reset_reg(struct aspeed_clk_gate *gate)
203{
204 if (gate->reset_idx < 32)
205 return ASPEED_G6_RESET_CTRL;
206
207 return ASPEED_G6_RESET_CTRL2;
208}
209
210static u32 get_clock_reg(struct aspeed_clk_gate *gate)
211{
212 if (gate->clock_idx < 32)
213 return ASPEED_G6_CLK_STOP_CTRL;
214
215 return ASPEED_G6_CLK_STOP_CTRL2;
216}
217
218static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
219{
220 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
221 u32 clk = get_bit(gate->clock_idx);
222 u32 rst = get_bit(gate->reset_idx);
223 u32 reg;
224 u32 enval;
225
226 /*
227 * If the IP is in reset, treat the clock as not enabled,
228 * this happens with some clocks such as the USB one when
229 * coming from cold reset. Without this, aspeed_clk_enable()
230 * will fail to lift the reset.
231 */
232 if (gate->reset_idx >= 0) {
233 regmap_read(gate->map, get_reset_reg(gate), &reg);
234
235 if (reg & rst)
236 return 0;
237 }
238
239 regmap_read(gate->map, get_clock_reg(gate), &reg);
240
241 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
242
243 return ((reg & clk) == enval) ? 1 : 0;
244}
245
246static int aspeed_g6_clk_enable(struct clk_hw *hw)
247{
248 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
249 unsigned long flags;
250 u32 clk = get_bit(gate->clock_idx);
251 u32 rst = get_bit(gate->reset_idx);
252
253 spin_lock_irqsave(gate->lock, flags);
254
255 if (aspeed_g6_clk_is_enabled(hw)) {
256 spin_unlock_irqrestore(gate->lock, flags);
257 return 0;
258 }
259
260 if (gate->reset_idx >= 0) {
261 /* Put IP in reset */
262 regmap_write(gate->map, get_reset_reg(gate), rst);
263 /* Delay 100us */
264 udelay(100);
265 }
266
267 /* Enable clock */
268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
269 regmap_write(gate->map, get_clock_reg(gate), clk);
270 } else {
271 /* Use set to clear register */
272 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
273 }
274
275 if (gate->reset_idx >= 0) {
276 /* A delay of 10ms is specified by the ASPEED docs */
277 mdelay(10);
278 /* Take IP out of reset */
279 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
280 }
281
282 spin_unlock_irqrestore(gate->lock, flags);
283
284 return 0;
285}
286
287static void aspeed_g6_clk_disable(struct clk_hw *hw)
288{
289 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
290 unsigned long flags;
291 u32 clk = get_bit(gate->clock_idx);
292
293 spin_lock_irqsave(gate->lock, flags);
294
295 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
296 regmap_write(gate->map, get_clock_reg(gate), clk);
297 } else {
298 /* Use set to clear register */
299 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
300 }
301
302 spin_unlock_irqrestore(gate->lock, flags);
303}
304
305static const struct clk_ops aspeed_g6_clk_gate_ops = {
306 .enable = aspeed_g6_clk_enable,
307 .disable = aspeed_g6_clk_disable,
308 .is_enabled = aspeed_g6_clk_is_enabled,
309};
310
311static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
312 unsigned long id)
313{
314 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
315 u32 rst = get_bit(id);
316 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
317
318 /* Use set to clear register */
319 return regmap_write(ar->map, reg + 0x04, rst);
320}
321
322static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
323 unsigned long id)
324{
325 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
326 u32 rst = get_bit(id);
327 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
328
329 return regmap_write(ar->map, reg, rst);
330}
331
332static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
333 unsigned long id)
334{
335 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
336 int ret;
337 u32 val;
338 u32 rst = get_bit(id);
339 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
340
341 ret = regmap_read(ar->map, reg, &val);
342 if (ret)
343 return ret;
344
345 return !!(val & rst);
346}
347
348static const struct reset_control_ops aspeed_g6_reset_ops = {
349 .assert = aspeed_g6_reset_assert,
350 .deassert = aspeed_g6_reset_deassert,
351 .status = aspeed_g6_reset_status,
352};
353
354static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
355 const char *name, const char *parent_name, unsigned long flags,
356 struct regmap *map, u8 clock_idx, u8 reset_idx,
357 u8 clk_gate_flags, spinlock_t *lock)
358{
359 struct aspeed_clk_gate *gate;
360 struct clk_init_data init;
361 struct clk_hw *hw;
362 int ret;
363
364 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
365 if (!gate)
366 return ERR_PTR(-ENOMEM);
367
368 init.name = name;
369 init.ops = &aspeed_g6_clk_gate_ops;
370 init.flags = flags;
371 init.parent_names = parent_name ? &parent_name : NULL;
372 init.num_parents = parent_name ? 1 : 0;
373
374 gate->map = map;
375 gate->clock_idx = clock_idx;
376 gate->reset_idx = reset_idx;
377 gate->flags = clk_gate_flags;
378 gate->lock = lock;
379 gate->hw.init = &init;
380
381 hw = &gate->hw;
382 ret = clk_hw_register(dev, hw);
383 if (ret) {
384 kfree(gate);
385 hw = ERR_PTR(ret);
386 }
387
388 return hw;
389}
390
391static const char * const vclk_parent_names[] = {
392 "dpll",
393 "d1pll",
394 "hclk",
395 "mclk",
396};
397
398static const char * const d1clk_parent_names[] = {
399 "dpll",
400 "epll",
401 "usb-phy-40m",
402 "gpioc6_clkin",
403 "dp_phy_pll",
404};
405
406static int aspeed_g6_clk_probe(struct platform_device *pdev)
407{
408 struct device *dev = &pdev->dev;
409 struct aspeed_reset *ar;
410 struct regmap *map;
411 struct clk_hw *hw;
412 u32 val, rate;
413 int i, ret;
414
415 map = syscon_node_to_regmap(dev->of_node);
416 if (IS_ERR(map)) {
417 dev_err(dev, "no syscon regmap\n");
418 return PTR_ERR(map);
419 }
420
421 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
422 if (!ar)
423 return -ENOMEM;
424
425 ar->map = map;
426
427 ar->rcdev.owner = THIS_MODULE;
428 ar->rcdev.nr_resets = 64;
429 ar->rcdev.ops = &aspeed_g6_reset_ops;
430 ar->rcdev.of_node = dev->of_node;
431
432 ret = devm_reset_controller_register(dev, &ar->rcdev);
433 if (ret) {
434 dev_err(dev, "could not register reset controller\n");
435 return ret;
436 }
437
438 /* UART clock div13 setting */
439 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
440 if (val & UART_DIV13_EN)
441 rate = 24000000 / 13;
442 else
443 rate = 24000000;
444 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
445 if (IS_ERR(hw))
446 return PTR_ERR(hw);
447 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
448
449 /* UART6~13 clock div13 setting */
450 regmap_read(map, 0x80, &val);
451 if (val & BIT(31))
452 rate = 24000000 / 13;
453 else
454 rate = 24000000;
455 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
456 if (IS_ERR(hw))
457 return PTR_ERR(hw);
458 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
459
460 /* EMMC ext clock divider */
461 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
462 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
463 &aspeed_g6_clk_lock);
464 if (IS_ERR(hw))
465 return PTR_ERR(hw);
466 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
467 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
468 ast2600_div_table,
469 &aspeed_g6_clk_lock);
470 if (IS_ERR(hw))
471 return PTR_ERR(hw);
472 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
473
474 /* SD/SDIO clock divider and gate */
475 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
476 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
477 &aspeed_g6_clk_lock);
478 if (IS_ERR(hw))
479 return PTR_ERR(hw);
480 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
481 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
482 ast2600_div_table,
483 &aspeed_g6_clk_lock);
484 if (IS_ERR(hw))
485 return PTR_ERR(hw);
486 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
487
488 /* MAC1/2 AHB bus clock divider */
489 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
490 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
491 ast2600_mac_div_table,
492 &aspeed_g6_clk_lock);
493 if (IS_ERR(hw))
494 return PTR_ERR(hw);
495 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
496
497 /* MAC3/4 AHB bus clock divider */
498 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
499 scu_g6_base + 0x310, 24, 3, 0,
500 ast2600_mac_div_table,
501 &aspeed_g6_clk_lock);
502 if (IS_ERR(hw))
503 return PTR_ERR(hw);
504 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
505
506 /* LPC Host (LHCLK) clock divider */
507 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
508 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
509 ast2600_div_table,
510 &aspeed_g6_clk_lock);
511 if (IS_ERR(hw))
512 return PTR_ERR(hw);
513 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
514
515 /* gfx d1clk : use dp clk */
516 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
517 /* SoC Display clock selection */
518 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
519 ARRAY_SIZE(d1clk_parent_names), 0,
520 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
521 &aspeed_g6_clk_lock);
522 if (IS_ERR(hw))
523 return PTR_ERR(hw);
524 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
525
526 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
527 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
528
529 /* P-Bus (BCLK) clock divider */
530 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
531 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
532 ast2600_div_table,
533 &aspeed_g6_clk_lock);
534 if (IS_ERR(hw))
535 return PTR_ERR(hw);
536 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
537
538 /* Video Capture clock selection */
539 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
540 ARRAY_SIZE(vclk_parent_names), 0,
541 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
542 &aspeed_g6_clk_lock);
543 if (IS_ERR(hw))
544 return PTR_ERR(hw);
545 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
546
547 /* Video Engine clock divider */
548 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
549 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
550 ast2600_eclk_div_table,
551 &aspeed_g6_clk_lock);
552 if (IS_ERR(hw))
553 return PTR_ERR(hw);
554 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
555
556 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
557 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
558 u32 gate_flags;
559
560 /*
561 * Special case: the USB port 1 clock (bit 14) is always
562 * working the opposite way from the other ones.
563 */
564 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
565 hw = aspeed_g6_clk_hw_register_gate(dev,
566 gd->name,
567 gd->parent_name,
568 gd->flags,
569 map,
570 gd->clock_idx,
571 gd->reset_idx,
572 gate_flags,
573 &aspeed_g6_clk_lock);
574 if (IS_ERR(hw))
575 return PTR_ERR(hw);
576 aspeed_g6_clk_data->hws[i] = hw;
577 }
578
579 return 0;
580};
581
582static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
583 { .compatible = "aspeed,ast2600-scu" },
584 { }
585};
586
587static struct platform_driver aspeed_g6_clk_driver = {
588 .probe = aspeed_g6_clk_probe,
589 .driver = {
590 .name = "ast2600-clk",
591 .of_match_table = aspeed_g6_clk_dt_ids,
592 .suppress_bind_attrs = true,
593 },
594};
595builtin_platform_driver(aspeed_g6_clk_driver);
596
597static const u32 ast2600_a0_axi_ahb_div_table[] = {
598 2, 2, 3, 5,
599};
600
601static const u32 ast2600_a1_axi_ahb_div_table[] = {
602 4, 6, 2, 4,
603};
604
605static void __init aspeed_g6_cc(struct regmap *map)
606{
607 struct clk_hw *hw;
608 u32 val, div, chip_id, axi_div, ahb_div;
609
610 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
611
612 /*
613 * High-speed PLL clock derived from the crystal. This the CPU clock,
614 * and we assume that it is enabled
615 */
616 regmap_read(map, ASPEED_HPLL_PARAM, &val);
617 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
618
619 regmap_read(map, ASPEED_MPLL_PARAM, &val);
620 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
621
622 regmap_read(map, ASPEED_DPLL_PARAM, &val);
623 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
624
625 regmap_read(map, ASPEED_EPLL_PARAM, &val);
626 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
627
628 regmap_read(map, ASPEED_APLL_PARAM, &val);
629 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
630
631 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
632 regmap_read(map, ASPEED_G6_STRAP1, &val);
633 if (val & BIT(16))
634 axi_div = 1;
635 else
636 axi_div = 2;
637
638 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
639 if (chip_id & BIT(16))
640 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
641 else
642 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
643
644 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
645 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
646
647 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
648 val = (val >> 23) & 0x7;
649 div = 4 * (val + 1);
650 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
651 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
652
653 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
654 val = (val >> 9) & 0x7;
655 div = 2 * (val + 1);
656 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
657 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
658
659 /* USB 2.0 port1 phy 40MHz clock */
660 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
661 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
662};
663
664static void __init aspeed_g6_cc_init(struct device_node *np)
665{
666 struct regmap *map;
667 int ret;
668 int i;
669
670 scu_g6_base = of_iomap(np, 0);
671 if (!scu_g6_base)
672 return;
673
674 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
675 ASPEED_G6_NUM_CLKS), GFP_KERNEL);
676 if (!aspeed_g6_clk_data)
677 return;
678
679 /*
680 * This way all clocks fetched before the platform device probes,
681 * except those we assign here for early use, will be deferred.
682 */
683 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
684 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
685
686 /*
687 * We check that the regmap works on this very first access,
688 * but as this is an MMIO-backed regmap, subsequent regmap
689 * access is not going to fail and we skip error checks from
690 * this point.
691 */
692 map = syscon_node_to_regmap(np);
693 if (IS_ERR(map)) {
694 pr_err("no syscon regmap\n");
695 return;
696 }
697
698 aspeed_g6_cc(map);
699 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
700 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
701 if (ret)
702 pr_err("failed to add DT provider: %d\n", ret);
703};
704CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/drivers/clk/clk-bulk.c b/drivers/clk/clk-bulk.c
index 524bf9a53098..e9e16425c739 100644
--- a/drivers/clk/clk-bulk.c
+++ b/drivers/clk/clk-bulk.c
@@ -18,10 +18,13 @@ static int __must_check of_clk_bulk_get(struct device_node *np, int num_clks,
18 int ret; 18 int ret;
19 int i; 19 int i;
20 20
21 for (i = 0; i < num_clks; i++) 21 for (i = 0; i < num_clks; i++) {
22 clks[i].id = NULL;
22 clks[i].clk = NULL; 23 clks[i].clk = NULL;
24 }
23 25
24 for (i = 0; i < num_clks; i++) { 26 for (i = 0; i < num_clks; i++) {
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id);
25 clks[i].clk = of_clk_get(np, i); 28 clks[i].clk = of_clk_get(np, i);
26 if (IS_ERR(clks[i].clk)) { 29 if (IS_ERR(clks[i].clk)) {
27 ret = PTR_ERR(clks[i].clk); 30 ret = PTR_ERR(clks[i].clk);
diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index 23c9326ea48c..308b353815e1 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -16,6 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/regmap.h> 18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20#include <linux/gcd.h> 21#include <linux/gcd.h>
21 22
@@ -602,6 +603,30 @@ of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
602 return &data->clk[idx].hw; 603 return &data->clk[idx].hw;
603} 604}
604 605
606static void cdce925_regulator_disable(void *regulator)
607{
608 regulator_disable(regulator);
609}
610
611static int cdce925_regulator_enable(struct device *dev, const char *name)
612{
613 struct regulator *regulator;
614 int err;
615
616 regulator = devm_regulator_get(dev, name);
617 if (IS_ERR(regulator))
618 return PTR_ERR(regulator);
619
620 err = regulator_enable(regulator);
621 if (err) {
622 dev_err(dev, "Failed to enable %s: %d\n", name, err);
623 return err;
624 }
625
626 return devm_add_action_or_reset(dev, cdce925_regulator_disable,
627 regulator);
628}
629
605/* The CDCE925 uses a funky way to read/write registers. Bulk mode is 630/* The CDCE925 uses a funky way to read/write registers. Bulk mode is
606 * just weird, so just use the single byte mode exclusively. */ 631 * just weird, so just use the single byte mode exclusively. */
607static struct regmap_bus regmap_cdce925_bus = { 632static struct regmap_bus regmap_cdce925_bus = {
@@ -630,6 +655,15 @@ static int cdce925_probe(struct i2c_client *client,
630 }; 655 };
631 656
632 dev_dbg(&client->dev, "%s\n", __func__); 657 dev_dbg(&client->dev, "%s\n", __func__);
658
659 err = cdce925_regulator_enable(&client->dev, "vdd");
660 if (err)
661 return err;
662
663 err = cdce925_regulator_enable(&client->dev, "vddout");
664 if (err)
665 return err;
666
633 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 667 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
634 if (!data) 668 if (!data)
635 return -ENOMEM; 669 return -ENOMEM;
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b06038b8f658..4f13a681ddfc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -3,7 +3,6 @@
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. 3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
4 */ 4 */
5 5
6#include <linux/clk.h>
7#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
8#include <linux/err.h> 7#include <linux/err.h>
9#include <linux/slab.h> 8#include <linux/slab.h>
diff --git a/drivers/clk/clk-lochnagar.c b/drivers/clk/clk-lochnagar.c
index fa8c91758b1d..565bcd0cdde9 100644
--- a/drivers/clk/clk-lochnagar.c
+++ b/drivers/clk/clk-lochnagar.c
@@ -198,7 +198,7 @@ static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
198 if (ret < 0) { 198 if (ret < 0) {
199 dev_dbg(priv->dev, "Failed to read parent of %s: %d\n", 199 dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
200 lclk->name, ret); 200 lclk->name, ret);
201 return hw->init->num_parents; 201 return clk_hw_get_num_parents(hw);
202 } 202 }
203 203
204 val &= lclk->src_mask; 204 val &= lclk->src_mask;
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
index 5fc78faf820c..80b9d78493bc 100644
--- a/drivers/clk/clk-milbeaut.c
+++ b/drivers/clk/clk-milbeaut.c
@@ -437,7 +437,7 @@ static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
437 if (readl_poll_timeout(divider->write_valid_reg, val, 437 if (readl_poll_timeout(divider->write_valid_reg, val,
438 !val, M10V_UPOLL_RATE, M10V_UTIMEOUT)) 438 !val, M10V_UPOLL_RATE, M10V_UTIMEOUT))
439 pr_err("%s:%s couldn't stabilize\n", 439 pr_err("%s:%s couldn't stabilize\n",
440 __func__, divider->hw.init->name); 440 __func__, clk_hw_get_name(hw));
441 } 441 }
442 442
443 if (divider->lock) 443 if (divider->lock)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 07f3b252f3e0..bed140f7375f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -686,7 +686,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
686 .guts_compat = "fsl,qoriq-device-config-1.0", 686 .guts_compat = "fsl,qoriq-device-config-1.0",
687 .init_periph = p5020_init_periph, 687 .init_periph = p5020_init_periph,
688 .cmux_groups = { 688 .cmux_groups = {
689 &p2041_cmux_grp1, &p2041_cmux_grp2 689 &p5020_cmux_grp1, &p5020_cmux_grp2
690 }, 690 },
691 .cmux_to_group = { 691 .cmux_to_group = {
692 0, 1, -1 692 0, 1, -1
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 72424eb7e5f8..6e780c2a9e6b 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -547,7 +547,6 @@ static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
547 bool is_integer; 547 bool is_integer;
548 548
549 n_num = synth->data->freq_vco; 549 n_num = synth->data->freq_vco;
550 n_den = rate;
551 550
552 /* see if there's an integer solution */ 551 /* see if there's an integer solution */
553 r = do_div(n_num, rate); 552 r = do_div(n_num, rate);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ca99e9db6575..1c677d7f7f53 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -37,6 +37,12 @@ static HLIST_HEAD(clk_root_list);
37static HLIST_HEAD(clk_orphan_list); 37static HLIST_HEAD(clk_orphan_list);
38static LIST_HEAD(clk_notifier_list); 38static LIST_HEAD(clk_notifier_list);
39 39
40static struct hlist_head *all_lists[] = {
41 &clk_root_list,
42 &clk_orphan_list,
43 NULL,
44};
45
40/*** private data structures ***/ 46/*** private data structures ***/
41 47
42struct clk_parent_map { 48struct clk_parent_map {
@@ -615,6 +621,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
615{ 621{
616 struct clk *clk_user; 622 struct clk *clk_user;
617 623
624 lockdep_assert_held(&prepare_lock);
625
618 *min_rate = core->min_rate; 626 *min_rate = core->min_rate;
619 *max_rate = core->max_rate; 627 *max_rate = core->max_rate;
620 628
@@ -2460,7 +2468,7 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
2460 if (core->parent == parent) 2468 if (core->parent == parent)
2461 return 0; 2469 return 0;
2462 2470
2463 /* verify ops for for multi-parent clks */ 2471 /* verify ops for multi-parent clks */
2464 if (core->num_parents > 1 && !core->ops->set_parent) 2472 if (core->num_parents > 1 && !core->ops->set_parent)
2465 return -EPERM; 2473 return -EPERM;
2466 2474
@@ -2862,12 +2870,6 @@ static int inited = 0;
2862static DEFINE_MUTEX(clk_debug_lock); 2870static DEFINE_MUTEX(clk_debug_lock);
2863static HLIST_HEAD(clk_debug_list); 2871static HLIST_HEAD(clk_debug_list);
2864 2872
2865static struct hlist_head *all_lists[] = {
2866 &clk_root_list,
2867 &clk_orphan_list,
2868 NULL,
2869};
2870
2871static struct hlist_head *orphan_list[] = { 2873static struct hlist_head *orphan_list[] = {
2872 &clk_orphan_list, 2874 &clk_orphan_list,
2873 NULL, 2875 NULL,
@@ -2876,9 +2878,6 @@ static struct hlist_head *orphan_list[] = {
2876static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, 2878static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2877 int level) 2879 int level)
2878{ 2880{
2879 if (!c)
2880 return;
2881
2882 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n", 2881 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
2883 level * 3 + 1, "", 2882 level * 3 + 1, "",
2884 30 - level * 3, c->name, 2883 30 - level * 3, c->name,
@@ -2893,9 +2892,6 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2893{ 2892{
2894 struct clk_core *child; 2893 struct clk_core *child;
2895 2894
2896 if (!c)
2897 return;
2898
2899 clk_summary_show_one(s, c, level); 2895 clk_summary_show_one(s, c, level);
2900 2896
2901 hlist_for_each_entry(child, &c->children, child_node) 2897 hlist_for_each_entry(child, &c->children, child_node)
@@ -2925,8 +2921,9 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
2925 2921
2926static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) 2922static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2927{ 2923{
2928 if (!c) 2924 unsigned long min_rate, max_rate;
2929 return; 2925
2926 clk_core_get_boundaries(c, &min_rate, &max_rate);
2930 2927
2931 /* This should be JSON format, i.e. elements separated with a comma */ 2928 /* This should be JSON format, i.e. elements separated with a comma */
2932 seq_printf(s, "\"%s\": { ", c->name); 2929 seq_printf(s, "\"%s\": { ", c->name);
@@ -2934,6 +2931,8 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2934 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); 2931 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
2935 seq_printf(s, "\"protect_count\": %d,", c->protect_count); 2932 seq_printf(s, "\"protect_count\": %d,", c->protect_count);
2936 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c)); 2933 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2934 seq_printf(s, "\"min_rate\": %lu,", min_rate);
2935 seq_printf(s, "\"max_rate\": %lu,", max_rate);
2937 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c)); 2936 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
2938 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c)); 2937 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
2939 seq_printf(s, "\"duty_cycle\": %u", 2938 seq_printf(s, "\"duty_cycle\": %u",
@@ -2944,9 +2943,6 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
2944{ 2943{
2945 struct clk_core *child; 2944 struct clk_core *child;
2946 2945
2947 if (!c)
2948 return;
2949
2950 clk_dump_one(s, c, level); 2946 clk_dump_one(s, c, level);
2951 2947
2952 hlist_for_each_entry(child, &c->children, child_node) { 2948 hlist_for_each_entry(child, &c->children, child_node) {
@@ -3042,15 +3038,15 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
3042 */ 3038 */
3043 parent = clk_core_get_parent_by_index(core, i); 3039 parent = clk_core_get_parent_by_index(core, i);
3044 if (parent) 3040 if (parent)
3045 seq_printf(s, "%s", parent->name); 3041 seq_puts(s, parent->name);
3046 else if (core->parents[i].name) 3042 else if (core->parents[i].name)
3047 seq_printf(s, "%s", core->parents[i].name); 3043 seq_puts(s, core->parents[i].name);
3048 else if (core->parents[i].fw_name) 3044 else if (core->parents[i].fw_name)
3049 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name); 3045 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
3050 else if (core->parents[i].index >= 0) 3046 else if (core->parents[i].index >= 0)
3051 seq_printf(s, "%s", 3047 seq_puts(s,
3052 of_clk_get_parent_name(core->of_node, 3048 of_clk_get_parent_name(core->of_node,
3053 core->parents[i].index)); 3049 core->parents[i].index));
3054 else 3050 else
3055 seq_puts(s, "(missing)"); 3051 seq_puts(s, "(missing)");
3056 3052
@@ -3093,6 +3089,34 @@ static int clk_duty_cycle_show(struct seq_file *s, void *data)
3093} 3089}
3094DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle); 3090DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
3095 3091
3092static int clk_min_rate_show(struct seq_file *s, void *data)
3093{
3094 struct clk_core *core = s->private;
3095 unsigned long min_rate, max_rate;
3096
3097 clk_prepare_lock();
3098 clk_core_get_boundaries(core, &min_rate, &max_rate);
3099 clk_prepare_unlock();
3100 seq_printf(s, "%lu\n", min_rate);
3101
3102 return 0;
3103}
3104DEFINE_SHOW_ATTRIBUTE(clk_min_rate);
3105
3106static int clk_max_rate_show(struct seq_file *s, void *data)
3107{
3108 struct clk_core *core = s->private;
3109 unsigned long min_rate, max_rate;
3110
3111 clk_prepare_lock();
3112 clk_core_get_boundaries(core, &min_rate, &max_rate);
3113 clk_prepare_unlock();
3114 seq_printf(s, "%lu\n", max_rate);
3115
3116 return 0;
3117}
3118DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
3119
3096static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 3120static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3097{ 3121{
3098 struct dentry *root; 3122 struct dentry *root;
@@ -3104,6 +3128,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3104 core->dentry = root; 3128 core->dentry = root;
3105 3129
3106 debugfs_create_ulong("clk_rate", 0444, root, &core->rate); 3130 debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
3131 debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
3132 debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
3107 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy); 3133 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
3108 debugfs_create_u32("clk_phase", 0444, root, &core->phase); 3134 debugfs_create_u32("clk_phase", 0444, root, &core->phase);
3109 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops); 3135 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
@@ -3513,9 +3539,9 @@ static int clk_cpy_name(const char **dst_p, const char *src, bool must_exist)
3513 return 0; 3539 return 0;
3514} 3540}
3515 3541
3516static int clk_core_populate_parent_map(struct clk_core *core) 3542static int clk_core_populate_parent_map(struct clk_core *core,
3543 const struct clk_init_data *init)
3517{ 3544{
3518 const struct clk_init_data *init = core->hw->init;
3519 u8 num_parents = init->num_parents; 3545 u8 num_parents = init->num_parents;
3520 const char * const *parent_names = init->parent_names; 3546 const char * const *parent_names = init->parent_names;
3521 const struct clk_hw **parent_hws = init->parent_hws; 3547 const struct clk_hw **parent_hws = init->parent_hws;
@@ -3595,6 +3621,14 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
3595{ 3621{
3596 int ret; 3622 int ret;
3597 struct clk_core *core; 3623 struct clk_core *core;
3624 const struct clk_init_data *init = hw->init;
3625
3626 /*
3627 * The init data is not supposed to be used outside of registration path.
3628 * Set it to NULL so that provider drivers can't use it either and so that
3629 * we catch use of hw->init early on in the core.
3630 */
3631 hw->init = NULL;
3598 3632
3599 core = kzalloc(sizeof(*core), GFP_KERNEL); 3633 core = kzalloc(sizeof(*core), GFP_KERNEL);
3600 if (!core) { 3634 if (!core) {
@@ -3602,17 +3636,17 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
3602 goto fail_out; 3636 goto fail_out;
3603 } 3637 }
3604 3638
3605 core->name = kstrdup_const(hw->init->name, GFP_KERNEL); 3639 core->name = kstrdup_const(init->name, GFP_KERNEL);
3606 if (!core->name) { 3640 if (!core->name) {
3607 ret = -ENOMEM; 3641 ret = -ENOMEM;
3608 goto fail_name; 3642 goto fail_name;
3609 } 3643 }
3610 3644
3611 if (WARN_ON(!hw->init->ops)) { 3645 if (WARN_ON(!init->ops)) {
3612 ret = -EINVAL; 3646 ret = -EINVAL;
3613 goto fail_ops; 3647 goto fail_ops;
3614 } 3648 }
3615 core->ops = hw->init->ops; 3649 core->ops = init->ops;
3616 3650
3617 if (dev && pm_runtime_enabled(dev)) 3651 if (dev && pm_runtime_enabled(dev))
3618 core->rpm_enabled = true; 3652 core->rpm_enabled = true;
@@ -3621,13 +3655,13 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw)
3621 if (dev && dev->driver) 3655 if (dev && dev->driver)
3622 core->owner = dev->driver->owner; 3656 core->owner = dev->driver->owner;
3623 core->hw = hw; 3657 core->hw = hw;
3624 core->flags = hw->init->flags; 3658 core->flags = init->flags;
3625 core->num_parents = hw->init->num_parents; 3659 core->num_parents = init->num_parents;
3626 core->min_rate = 0; 3660 core->min_rate = 0;
3627 core->max_rate = ULONG_MAX; 3661 core->max_rate = ULONG_MAX;
3628 hw->core = core; 3662 hw->core = core;
3629 3663
3630 ret = clk_core_populate_parent_map(core); 3664 ret = clk_core_populate_parent_map(core, init);
3631 if (ret) 3665 if (ret)
3632 goto fail_parents; 3666 goto fail_parents;
3633 3667
@@ -3766,6 +3800,34 @@ static const struct clk_ops clk_nodrv_ops = {
3766 .set_parent = clk_nodrv_set_parent, 3800 .set_parent = clk_nodrv_set_parent,
3767}; 3801};
3768 3802
3803static void clk_core_evict_parent_cache_subtree(struct clk_core *root,
3804 struct clk_core *target)
3805{
3806 int i;
3807 struct clk_core *child;
3808
3809 for (i = 0; i < root->num_parents; i++)
3810 if (root->parents[i].core == target)
3811 root->parents[i].core = NULL;
3812
3813 hlist_for_each_entry(child, &root->children, child_node)
3814 clk_core_evict_parent_cache_subtree(child, target);
3815}
3816
3817/* Remove this clk from all parent caches */
3818static void clk_core_evict_parent_cache(struct clk_core *core)
3819{
3820 struct hlist_head **lists;
3821 struct clk_core *root;
3822
3823 lockdep_assert_held(&prepare_lock);
3824
3825 for (lists = all_lists; *lists; lists++)
3826 hlist_for_each_entry(root, *lists, child_node)
3827 clk_core_evict_parent_cache_subtree(root, core);
3828
3829}
3830
3769/** 3831/**
3770 * clk_unregister - unregister a currently registered clock 3832 * clk_unregister - unregister a currently registered clock
3771 * @clk: clock to unregister 3833 * @clk: clock to unregister
@@ -3804,6 +3866,8 @@ void clk_unregister(struct clk *clk)
3804 clk_core_set_parent_nolock(child, NULL); 3866 clk_core_set_parent_nolock(child, NULL);
3805 } 3867 }
3806 3868
3869 clk_core_evict_parent_cache(clk->core);
3870
3807 hlist_del_init(&clk->core->child_node); 3871 hlist_del_init(&clk->core->child_node);
3808 3872
3809 if (clk->core->prepare_count) 3873 if (clk->core->prepare_count)
@@ -4345,12 +4409,43 @@ void devm_of_clk_del_provider(struct device *dev)
4345} 4409}
4346EXPORT_SYMBOL(devm_of_clk_del_provider); 4410EXPORT_SYMBOL(devm_of_clk_del_provider);
4347 4411
4348/* 4412/**
4349 * Beware the return values when np is valid, but no clock provider is found. 4413 * of_parse_clkspec() - Parse a DT clock specifier for a given device node
4350 * If name == NULL, the function returns -ENOENT. 4414 * @np: device node to parse clock specifier from
4351 * If name != NULL, the function returns -EINVAL. This is because 4415 * @index: index of phandle to parse clock out of. If index < 0, @name is used
4352 * of_parse_phandle_with_args() is called even if of_property_match_string() 4416 * @name: clock name to find and parse. If name is NULL, the index is used
4353 * returns an error. 4417 * @out_args: Result of parsing the clock specifier
4418 *
4419 * Parses a device node's "clocks" and "clock-names" properties to find the
4420 * phandle and cells for the index or name that is desired. The resulting clock
4421 * specifier is placed into @out_args, or an errno is returned when there's a
4422 * parsing error. The @index argument is ignored if @name is non-NULL.
4423 *
4424 * Example:
4425 *
4426 * phandle1: clock-controller@1 {
4427 * #clock-cells = <2>;
4428 * }
4429 *
4430 * phandle2: clock-controller@2 {
4431 * #clock-cells = <1>;
4432 * }
4433 *
4434 * clock-consumer@3 {
4435 * clocks = <&phandle1 1 2 &phandle2 3>;
4436 * clock-names = "name1", "name2";
4437 * }
4438 *
4439 * To get a device_node for `clock-controller@2' node you may call this
4440 * function a few different ways:
4441 *
4442 * of_parse_clkspec(clock-consumer@3, -1, "name2", &args);
4443 * of_parse_clkspec(clock-consumer@3, 1, NULL, &args);
4444 * of_parse_clkspec(clock-consumer@3, 1, "name2", &args);
4445 *
4446 * Return: 0 upon successfully parsing the clock specifier. Otherwise, -ENOENT
4447 * if @name is NULL or -EINVAL if @name is non-NULL and it can't be found in
4448 * the "clock-names" property of @np.
4354 */ 4449 */
4355static int of_parse_clkspec(const struct device_node *np, int index, 4450static int of_parse_clkspec(const struct device_node *np, int index,
4356 const char *name, struct of_phandle_args *out_args) 4451 const char *name, struct of_phandle_args *out_args)
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index 1c99e992d638..1ac11b6a47a3 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -778,12 +778,15 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
778 int i; 778 int i;
779 779
780 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 780 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
781 if (!clk_data) 781 if (!clk_data) {
782 of_node_put(child);
782 return -ENOMEM; 783 return -ENOMEM;
784 }
783 785
784 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL); 786 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
785 if (!clks) { 787 if (!clks) {
786 kfree(clk_data); 788 kfree(clk_data);
789 of_node_put(child);
787 return -ENOMEM; 790 return -ENOMEM;
788 } 791 }
789 792
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
index 42e4667f22fd..2022d9bead91 100644
--- a/drivers/clk/imx/clk-imx7ulp.c
+++ b/drivers/clk/imx/clk-imx7ulp.c
@@ -42,6 +42,19 @@ static const struct clk_div_table ulp_div_table[] = {
42 { .val = 7, .div = 64, }, 42 { .val = 7, .div = 64, },
43}; 43};
44 44
45static const int pcc2_uart_clk_ids[] __initconst = {
46 IMX7ULP_CLK_LPUART4,
47 IMX7ULP_CLK_LPUART5,
48};
49
50static const int pcc3_uart_clk_ids[] __initconst = {
51 IMX7ULP_CLK_LPUART6,
52 IMX7ULP_CLK_LPUART7,
53};
54
55static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
56static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
57
45static void __init imx7ulp_clk_scg1_init(struct device_node *np) 58static void __init imx7ulp_clk_scg1_init(struct device_node *np)
46{ 59{
47 struct clk_hw_onecell_data *clk_data; 60 struct clk_hw_onecell_data *clk_data;
@@ -135,6 +148,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
135 struct clk_hw_onecell_data *clk_data; 148 struct clk_hw_onecell_data *clk_data;
136 struct clk_hw **clks; 149 struct clk_hw **clks;
137 void __iomem *base; 150 void __iomem *base;
151 int i;
138 152
139 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END), 153 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
140 GFP_KERNEL); 154 GFP_KERNEL);
@@ -173,6 +187,14 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
173 imx_check_clk_hws(clks, clk_data->num); 187 imx_check_clk_hws(clks, clk_data->num);
174 188
175 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 189 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
190
191 for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
192 int index = pcc2_uart_clk_ids[i];
193
194 pcc2_uart_clks[i] = &clks[index]->clk;
195 }
196
197 imx_register_uart_clocks(pcc2_uart_clks);
176} 198}
177CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init); 199CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
178 200
@@ -181,6 +203,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
181 struct clk_hw_onecell_data *clk_data; 203 struct clk_hw_onecell_data *clk_data;
182 struct clk_hw **clks; 204 struct clk_hw **clks;
183 void __iomem *base; 205 void __iomem *base;
206 int i;
184 207
185 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END), 208 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
186 GFP_KERNEL); 209 GFP_KERNEL);
@@ -218,6 +241,14 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
218 imx_check_clk_hws(clks, clk_data->num); 241 imx_check_clk_hws(clks, clk_data->num);
219 242
220 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 243 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
244
245 for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
246 int index = pcc3_uart_clk_ids[i];
247
248 pcc3_uart_clks[i] = &clks[index]->clk;
249 }
250
251 imx_register_uart_clocks(pcc3_uart_clks);
221} 252}
222CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init); 253CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
223 254
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 43fa9c361fcb..067ab876911d 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -22,7 +22,7 @@ static u32 share_count_sai3;
22static u32 share_count_sai4; 22static u32 share_count_sai4;
23static u32 share_count_sai5; 23static u32 share_count_sai5;
24static u32 share_count_sai6; 24static u32 share_count_sai6;
25static u32 share_count_dcss; 25static u32 share_count_disp;
26static u32 share_count_pdm; 26static u32 share_count_pdm;
27static u32 share_count_nand; 27static u32 share_count_nand;
28 28
@@ -38,8 +38,8 @@ static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
38}; 38};
39 39
40static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = { 40static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {
41 PLL_1443X_RATE(786432000U, 655, 5, 2, 23593), 41 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
42 PLL_1443X_RATE(722534400U, 301, 5, 1, 3670), 42 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
43}; 43};
44 44
45static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = { 45static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {
@@ -51,43 +51,43 @@ static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
51 PLL_1443X_RATE(650000000U, 325, 3, 2, 0), 51 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
52}; 52};
53 53
54static struct imx_pll14xx_clk imx8mm_audio_pll __initdata = { 54static struct imx_pll14xx_clk imx8mm_audio_pll = {
55 .type = PLL_1443X, 55 .type = PLL_1443X,
56 .rate_table = imx8mm_audiopll_tbl, 56 .rate_table = imx8mm_audiopll_tbl,
57 .rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl), 57 .rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl),
58}; 58};
59 59
60static struct imx_pll14xx_clk imx8mm_video_pll __initdata = { 60static struct imx_pll14xx_clk imx8mm_video_pll = {
61 .type = PLL_1443X, 61 .type = PLL_1443X,
62 .rate_table = imx8mm_videopll_tbl, 62 .rate_table = imx8mm_videopll_tbl,
63 .rate_count = ARRAY_SIZE(imx8mm_videopll_tbl), 63 .rate_count = ARRAY_SIZE(imx8mm_videopll_tbl),
64}; 64};
65 65
66static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = { 66static struct imx_pll14xx_clk imx8mm_dram_pll = {
67 .type = PLL_1443X, 67 .type = PLL_1443X,
68 .rate_table = imx8mm_drampll_tbl, 68 .rate_table = imx8mm_drampll_tbl,
69 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl), 69 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
70}; 70};
71 71
72static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = { 72static struct imx_pll14xx_clk imx8mm_arm_pll = {
73 .type = PLL_1416X, 73 .type = PLL_1416X,
74 .rate_table = imx8mm_pll1416x_tbl, 74 .rate_table = imx8mm_pll1416x_tbl,
75 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), 75 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
76}; 76};
77 77
78static struct imx_pll14xx_clk imx8mm_gpu_pll __initdata = { 78static struct imx_pll14xx_clk imx8mm_gpu_pll = {
79 .type = PLL_1416X, 79 .type = PLL_1416X,
80 .rate_table = imx8mm_pll1416x_tbl, 80 .rate_table = imx8mm_pll1416x_tbl,
81 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), 81 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
82}; 82};
83 83
84static struct imx_pll14xx_clk imx8mm_vpu_pll __initdata = { 84static struct imx_pll14xx_clk imx8mm_vpu_pll = {
85 .type = PLL_1416X, 85 .type = PLL_1416X,
86 .rate_table = imx8mm_pll1416x_tbl, 86 .rate_table = imx8mm_pll1416x_tbl,
87 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), 87 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
88}; 88};
89 89
90static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = { 90static struct imx_pll14xx_clk imx8mm_sys_pll = {
91 .type = PLL_1416X, 91 .type = PLL_1416X,
92 .rate_table = imx8mm_pll1416x_tbl, 92 .rate_table = imx8mm_pll1416x_tbl,
93 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl), 93 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
@@ -175,10 +175,10 @@ static const char *imx8mm_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
175static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", 175static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
176 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", }; 176 "sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
177 177
178static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m", 178static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
179 "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; 179 "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
180 180
181static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "video_pll2_out", "sys_pll1_800m", "sys_pll2_1000m", 181static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
182 "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", }; 182 "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
183 183
184static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", 184static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
@@ -232,7 +232,7 @@ static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll
232static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m", 232static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
233 "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", }; 233 "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
234 234
235static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", 235static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
236 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; 236 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
237 237
238static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m", 238static const char *imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
@@ -287,13 +287,13 @@ static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1
287 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", }; 287 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
288 288
289static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 289static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
290 "sys3_pll2_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; 290 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
291 291
292static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", 292static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
293 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; 293 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
294 294
295static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m", 295static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
296 "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" }; 296 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
297 297
298static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", 298static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
299 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; 299 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
@@ -347,7 +347,7 @@ static const char *imx8mm_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_
347 "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; 347 "sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
348 348
349static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m", 349static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", "sys_pll2_1000m",
350 "audio_pll2_out", "sys_pll2_125m", "sys_pll3_clk", "audio_pll1_out", }; 350 "audio_pll2_out", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
351 351
352static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 352static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
353 353
@@ -357,7 +357,7 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
357static struct clk *clks[IMX8MM_CLK_END]; 357static struct clk *clks[IMX8MM_CLK_END];
358static struct clk_onecell_data clk_data; 358static struct clk_onecell_data clk_data;
359 359
360static struct clk ** const uart_clks[] __initconst = { 360static struct clk ** const uart_clks[] = {
361 &clks[IMX8MM_CLK_UART1_ROOT], 361 &clks[IMX8MM_CLK_UART1_ROOT],
362 &clks[IMX8MM_CLK_UART2_ROOT], 362 &clks[IMX8MM_CLK_UART2_ROOT],
363 &clks[IMX8MM_CLK_UART3_ROOT], 363 &clks[IMX8MM_CLK_UART3_ROOT],
@@ -365,19 +365,20 @@ static struct clk ** const uart_clks[] __initconst = {
365 NULL 365 NULL
366}; 366};
367 367
368static int __init imx8mm_clocks_init(struct device_node *ccm_node) 368static int imx8mm_clocks_probe(struct platform_device *pdev)
369{ 369{
370 struct device_node *np; 370 struct device *dev = &pdev->dev;
371 struct device_node *np = dev->of_node;
371 void __iomem *base; 372 void __iomem *base;
372 int ret; 373 int ret;
373 374
374 clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 375 clks[IMX8MM_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
375 clks[IMX8MM_CLK_24M] = of_clk_get_by_name(ccm_node, "osc_24m"); 376 clks[IMX8MM_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
376 clks[IMX8MM_CLK_32K] = of_clk_get_by_name(ccm_node, "osc_32k"); 377 clks[IMX8MM_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
377 clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(ccm_node, "clk_ext1"); 378 clks[IMX8MM_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
378 clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(ccm_node, "clk_ext2"); 379 clks[IMX8MM_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
379 clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(ccm_node, "clk_ext3"); 380 clks[IMX8MM_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
380 clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(ccm_node, "clk_ext4"); 381 clks[IMX8MM_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
381 382
382 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); 383 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
383 base = of_iomap(np, 0); 384 base = of_iomap(np, 0);
@@ -407,28 +408,16 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
407 clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll); 408 clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll);
408 409
409 /* PLL bypass out */ 410 /* PLL bypass out */
410 clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); 411 clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
411 clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); 412 clks[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
412 clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); 413 clks[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
413 clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); 414 clks[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
414 clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 415 clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
415 clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 416 clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
416 clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); 417 clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
417 clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); 418 clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
418 clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); 419 clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
419 clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); 420 clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
420
421 /* unbypass all the plls */
422 clk_set_parent(clks[IMX8MM_AUDIO_PLL1_BYPASS], clks[IMX8MM_AUDIO_PLL1]);
423 clk_set_parent(clks[IMX8MM_AUDIO_PLL2_BYPASS], clks[IMX8MM_AUDIO_PLL2]);
424 clk_set_parent(clks[IMX8MM_VIDEO_PLL1_BYPASS], clks[IMX8MM_VIDEO_PLL1]);
425 clk_set_parent(clks[IMX8MM_DRAM_PLL_BYPASS], clks[IMX8MM_DRAM_PLL]);
426 clk_set_parent(clks[IMX8MM_GPU_PLL_BYPASS], clks[IMX8MM_GPU_PLL]);
427 clk_set_parent(clks[IMX8MM_VPU_PLL_BYPASS], clks[IMX8MM_VPU_PLL]);
428 clk_set_parent(clks[IMX8MM_ARM_PLL_BYPASS], clks[IMX8MM_ARM_PLL]);
429 clk_set_parent(clks[IMX8MM_SYS_PLL1_BYPASS], clks[IMX8MM_SYS_PLL1]);
430 clk_set_parent(clks[IMX8MM_SYS_PLL2_BYPASS], clks[IMX8MM_SYS_PLL2]);
431 clk_set_parent(clks[IMX8MM_SYS_PLL3_BYPASS], clks[IMX8MM_SYS_PLL3]);
432 421
433 /* PLL out gate */ 422 /* PLL out gate */
434 clks[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); 423 clks[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
@@ -463,10 +452,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
463 clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); 452 clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
464 clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); 453 clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
465 454
466 np = ccm_node; 455 np = dev->of_node;
467 base = of_iomap(np, 0); 456 base = devm_platform_ioremap_resource(pdev, 0);
468 if (WARN_ON(!base)) 457 if (WARN_ON(IS_ERR(base)))
469 return -ENOMEM; 458 return PTR_ERR(base);
470 459
471 /* Core Slice */ 460 /* Core Slice */
472 clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); 461 clks[IMX8MM_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
@@ -614,7 +603,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
614 clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); 603 clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
615 clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); 604 clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
616 clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); 605 clks[IMX8MM_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
617 clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); 606 clks[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
618 clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0); 607 clks[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
619 clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); 608 clks[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
620 clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); 609 clks[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
@@ -627,10 +616,10 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
627 clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0); 616 clks[IMX8MM_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);
628 clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm); 617 clks[IMX8MM_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
629 clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm); 618 clks[IMX8MM_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
630 clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss); 619 clks[IMX8MM_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_disp);
631 clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); 620 clks[IMX8MM_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
632 clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); 621 clks[IMX8MM_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
633 clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); 622 clks[IMX8MM_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_disp);
634 clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); 623 clks[IMX8MM_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
635 clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); 624 clks[IMX8MM_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
636 clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0); 625 clks[IMX8MM_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0);
@@ -658,11 +647,30 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
658 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 647 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
659 if (ret < 0) { 648 if (ret < 0) {
660 pr_err("failed to register clks for i.MX8MM\n"); 649 pr_err("failed to register clks for i.MX8MM\n");
661 return -EINVAL; 650 goto unregister_clks;
662 } 651 }
663 652
664 imx_register_uart_clocks(uart_clks); 653 imx_register_uart_clocks(uart_clks);
665 654
666 return 0; 655 return 0;
656
657unregister_clks:
658 imx_unregister_clocks(clks, ARRAY_SIZE(clks));
659
660 return ret;
667} 661}
668CLK_OF_DECLARE_DRIVER(imx8mm, "fsl,imx8mm-ccm", imx8mm_clocks_init); 662
663static const struct of_device_id imx8mm_clk_of_match[] = {
664 { .compatible = "fsl,imx8mm-ccm" },
665 { /* Sentinel */ },
666};
667MODULE_DEVICE_TABLE(of, imx8mm_clk_of_match);
668
669static struct platform_driver imx8mm_clk_driver = {
670 .probe = imx8mm_clocks_probe,
671 .driver = {
672 .name = "imx8mm-ccm",
673 .of_match_table = of_match_ptr(imx8mm_clk_of_match),
674 },
675};
676module_platform_driver(imx8mm_clk_driver);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 07481a53e336..47a4b44ba3cb 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -42,6 +42,8 @@ enum {
42static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = { 42static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
43 PLL_1416X_RATE(1800000000U, 225, 3, 0), 43 PLL_1416X_RATE(1800000000U, 225, 3, 0),
44 PLL_1416X_RATE(1600000000U, 200, 3, 0), 44 PLL_1416X_RATE(1600000000U, 200, 3, 0),
45 PLL_1416X_RATE(1500000000U, 375, 3, 1),
46 PLL_1416X_RATE(1400000000U, 350, 3, 1),
45 PLL_1416X_RATE(1200000000U, 300, 3, 1), 47 PLL_1416X_RATE(1200000000U, 300, 3, 1),
46 PLL_1416X_RATE(1000000000U, 250, 3, 1), 48 PLL_1416X_RATE(1000000000U, 250, 3, 1),
47 PLL_1416X_RATE(800000000U, 200, 3, 1), 49 PLL_1416X_RATE(800000000U, 200, 3, 1),
@@ -51,8 +53,8 @@ static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
51}; 53};
52 54
53static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = { 55static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
54 PLL_1443X_RATE(786432000U, 655, 5, 2, 23593), 56 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
55 PLL_1443X_RATE(722534400U, 301, 5, 1, 3670), 57 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
56}; 58};
57 59
58static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = { 60static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
@@ -67,36 +69,43 @@ static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
67static struct imx_pll14xx_clk imx8mn_audio_pll = { 69static struct imx_pll14xx_clk imx8mn_audio_pll = {
68 .type = PLL_1443X, 70 .type = PLL_1443X,
69 .rate_table = imx8mn_audiopll_tbl, 71 .rate_table = imx8mn_audiopll_tbl,
72 .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
70}; 73};
71 74
72static struct imx_pll14xx_clk imx8mn_video_pll = { 75static struct imx_pll14xx_clk imx8mn_video_pll = {
73 .type = PLL_1443X, 76 .type = PLL_1443X,
74 .rate_table = imx8mn_videopll_tbl, 77 .rate_table = imx8mn_videopll_tbl,
78 .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
75}; 79};
76 80
77static struct imx_pll14xx_clk imx8mn_dram_pll = { 81static struct imx_pll14xx_clk imx8mn_dram_pll = {
78 .type = PLL_1443X, 82 .type = PLL_1443X,
79 .rate_table = imx8mn_drampll_tbl, 83 .rate_table = imx8mn_drampll_tbl,
84 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
80}; 85};
81 86
82static struct imx_pll14xx_clk imx8mn_arm_pll = { 87static struct imx_pll14xx_clk imx8mn_arm_pll = {
83 .type = PLL_1416X, 88 .type = PLL_1416X,
84 .rate_table = imx8mn_pll1416x_tbl, 89 .rate_table = imx8mn_pll1416x_tbl,
90 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
85}; 91};
86 92
87static struct imx_pll14xx_clk imx8mn_gpu_pll = { 93static struct imx_pll14xx_clk imx8mn_gpu_pll = {
88 .type = PLL_1416X, 94 .type = PLL_1416X,
89 .rate_table = imx8mn_pll1416x_tbl, 95 .rate_table = imx8mn_pll1416x_tbl,
96 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
90}; 97};
91 98
92static struct imx_pll14xx_clk imx8mn_vpu_pll = { 99static struct imx_pll14xx_clk imx8mn_vpu_pll = {
93 .type = PLL_1416X, 100 .type = PLL_1416X,
94 .rate_table = imx8mn_pll1416x_tbl, 101 .rate_table = imx8mn_pll1416x_tbl,
102 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
95}; 103};
96 104
97static struct imx_pll14xx_clk imx8mn_sys_pll = { 105static struct imx_pll14xx_clk imx8mn_sys_pll = {
98 .type = PLL_1416X, 106 .type = PLL_1416X,
99 .rate_table = imx8mn_pll1416x_tbl, 107 .rate_table = imx8mn_pll1416x_tbl,
108 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
100}; 109};
101 110
102static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; 111static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
@@ -140,7 +149,7 @@ static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m",
140 "clk_ext1", "clk_ext4", }; 149 "clk_ext1", "clk_ext4", };
141 150
142static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", 151static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
143 "sys_pll3_out", "sys1_pll_40m", "audio_pll2_out", 152 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
144 "clk_ext1", "clk_ext3", }; 153 "clk_ext1", "clk_ext3", };
145 154
146static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", 155static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
@@ -219,9 +228,9 @@ static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "aud
219 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", 228 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
220 "sys_pll2_250m", "video_pll1_out", }; 229 "sys_pll2_250m", "video_pll1_out", };
221 230
222static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys1_pll_400m", "sys_pll1_800m", 231static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
223 "sys2_pll_500m", "audio_pll2_out", "sys1_pll_266m", 232 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
224 "sys3_pll2_out", "sys1_pll_100m", }; 233 "sys_pll3_out", "sys_pll1_100m", };
225 234
226static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 235static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
227 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 236 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
@@ -271,6 +280,10 @@ static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "
271 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 280 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
272 "clk_ext3", "audio_pll2_out", }; 281 "clk_ext3", "audio_pll2_out", };
273 282
283static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
284 "sys_pll2_100m", "sys_pll1_800m", "clk_ext2",
285 "clk_ext4", "audio_pll2_out" };
286
274static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 287static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
275 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 288 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
276 "sys_pll2_250m", "audio_pll2_out", }; 289 "sys_pll2_250m", "audio_pll2_out", };
@@ -288,7 +301,7 @@ static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys
288 "sys_pll1_80m", "video_pll1_out", }; 301 "sys_pll1_80m", "video_pll1_out", };
289 302
290static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 303static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
291 "sys_pll1_40m", "sys3_pll2_out", "clk_ext2", 304 "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
292 "sys_pll1_80m", "video_pll1_out", }; 305 "sys_pll1_80m", "video_pll1_out", };
293 306
294static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 307static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
@@ -317,7 +330,7 @@ static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "
317 330
318static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 331static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
319 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 332 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
320 "audio_pll2_clk", "sys_pll1_100m", }; 333 "audio_pll2_out", "sys_pll1_100m", };
321 334
322static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 335static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
323 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 336 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
@@ -346,7 +359,7 @@ static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audi
346static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 359static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
347 360
348static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", 361static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
349 "sys_pll1_200m", "audio_pll2_clk", "vpu_pll", 362 "sys_pll1_200m", "audio_pll2_out", "vpu_pll",
350 "sys_pll1_80m", }; 363 "sys_pll1_80m", };
351static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", 364static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
352 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", 365 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
@@ -355,6 +368,14 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
355static struct clk *clks[IMX8MN_CLK_END]; 368static struct clk *clks[IMX8MN_CLK_END];
356static struct clk_onecell_data clk_data; 369static struct clk_onecell_data clk_data;
357 370
371static struct clk ** const uart_clks[] = {
372 &clks[IMX8MN_CLK_UART1_ROOT],
373 &clks[IMX8MN_CLK_UART2_ROOT],
374 &clks[IMX8MN_CLK_UART3_ROOT],
375 &clks[IMX8MN_CLK_UART4_ROOT],
376 NULL
377};
378
358static int imx8mn_clocks_probe(struct platform_device *pdev) 379static int imx8mn_clocks_probe(struct platform_device *pdev)
359{ 380{
360 struct device *dev = &pdev->dev; 381 struct device *dev = &pdev->dev;
@@ -400,40 +421,28 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
400 clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll); 421 clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
401 422
402 /* PLL bypass out */ 423 /* PLL bypass out */
403 clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); 424 clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
404 clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); 425 clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
405 clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); 426 clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
406 clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); 427 clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
407 clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 428 clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
408 clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 429 clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
409 clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); 430 clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
410 clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); 431 clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
411 clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); 432 clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
412 clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); 433 clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
413
414 /* unbypass all the plls */
415 clk_set_parent(clks[IMX8MN_AUDIO_PLL1_BYPASS], clks[IMX8MN_AUDIO_PLL1]);
416 clk_set_parent(clks[IMX8MN_AUDIO_PLL2_BYPASS], clks[IMX8MN_AUDIO_PLL2]);
417 clk_set_parent(clks[IMX8MN_VIDEO_PLL1_BYPASS], clks[IMX8MN_VIDEO_PLL1]);
418 clk_set_parent(clks[IMX8MN_DRAM_PLL_BYPASS], clks[IMX8MN_DRAM_PLL]);
419 clk_set_parent(clks[IMX8MN_GPU_PLL_BYPASS], clks[IMX8MN_GPU_PLL]);
420 clk_set_parent(clks[IMX8MN_VPU_PLL_BYPASS], clks[IMX8MN_VPU_PLL]);
421 clk_set_parent(clks[IMX8MN_ARM_PLL_BYPASS], clks[IMX8MN_ARM_PLL]);
422 clk_set_parent(clks[IMX8MN_SYS_PLL1_BYPASS], clks[IMX8MN_SYS_PLL1]);
423 clk_set_parent(clks[IMX8MN_SYS_PLL2_BYPASS], clks[IMX8MN_SYS_PLL2]);
424 clk_set_parent(clks[IMX8MN_SYS_PLL3_BYPASS], clks[IMX8MN_SYS_PLL3]);
425 434
426 /* PLL out gate */ 435 /* PLL out gate */
427 clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); 436 clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
428 clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); 437 clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
429 clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); 438 clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
430 clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); 439 clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
431 clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13); 440 clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
432 clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13); 441 clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
433 clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13); 442 clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
434 clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13); 443 clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
435 clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13); 444 clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
436 clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13); 445 clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
437 446
438 /* SYS PLL fixed output */ 447 /* SYS PLL fixed output */
439 clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); 448 clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
@@ -516,6 +525,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
516 clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080); 525 clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
517 clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100); 526 clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
518 clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180); 527 clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
528 clks[IMX8MN_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200);
519 clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280); 529 clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
520 clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300); 530 clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
521 clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380); 531 clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
@@ -612,6 +622,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
612 goto unregister_clks; 622 goto unregister_clks;
613 } 623 }
614 624
625 imx_register_uart_clocks(uart_clks);
626
615 return 0; 627 return 0;
616 628
617unregister_clks: 629unregister_clks:
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index d407a07e7e6d..41fc9c63356e 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -41,34 +41,34 @@ static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
41 41
42/* CCM ROOT */ 42/* CCM ROOT */
43static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", 43static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
44 "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll2_out", }; 44 "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
45 45
46static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m", 46static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
47 "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", }; 47 "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
48 48
49static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m", 49static const char * const imx8mq_vpu_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
50 "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", }; 50 "sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "vpu_pll_out", };
51 51
52static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", 52static const char * const imx8mq_gpu_core_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
53 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 53 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
54 54
55static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll2_out", 55static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m", "gpu_pll_out", "sys1_pll_800m", "sys3_pll_out",
56 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 56 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
57 57
58static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m", 58static const char * const imx8mq_main_axi_sels[] = {"osc_25m", "sys2_pll_333m", "sys1_pll_800m", "sys2_pll_250m",
59 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",}; 59 "sys2_pll_1000m", "audio_pll1_out", "video_pll1_out", "sys1_pll_100m",};
60 60
61static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m", 61static const char * const imx8mq_enet_axi_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_250m",
62 "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll2_out", }; 62 "sys2_pll_200m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
63 63
64static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m", 64static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m", "sys1_pll_266m", "sys1_pll_800m", "sys2_pll_200m",
65 "sys1_pll_133m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll1_out", }; 65 "sys1_pll_133m", "sys3_pll_out", "sys2_pll_250m", "audio_pll1_out", };
66 66
67static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", }; 67static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m", "sys1_pll_800m", "vpu_pll_out", "audio_pll2_out", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_200m", "sys1_pll_100m", };
68 68
69static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", }; 69static const char * const imx8mq_disp_axi_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out", "sys1_pll_400m", "audio_pll2_out", "clk_ext1", "clk_ext4", };
70 70
71static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll2_out", 71static const char * const imx8mq_disp_apb_sels[] = {"osc_25m", "sys2_pll_125m", "sys1_pll_800m", "sys3_pll_out",
72 "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", }; 72 "sys1_pll_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
73 73
74static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m", 74static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m", "sys2_pll_200m", "sys1_pll_400m",
@@ -77,53 +77,53 @@ static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m", "sys1_pll_800m",
77static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m", 77static const char * const imx8mq_usb_bus_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_100m",
78 "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", }; 78 "sys2_pll_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
79 79
80static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", 80static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
81 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 81 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
82 82
83static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll2_out", "sys2_pll_1000m", 83static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m", "sys1_pll_800m", "gpu_pll_out", "sys3_pll_out", "sys2_pll_1000m",
84 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 84 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
85 85
86static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_1000m", "sys2_pll_500m", 86static const char * const imx8mq_noc_sels[] = {"osc_25m", "sys1_pll_800m", "sys3_pll_out", "sys2_pll_1000m", "sys2_pll_500m",
87 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 87 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
88 88
89static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll2_out", "sys2_pll_333m", "sys2_pll_200m", 89static const char * const imx8mq_noc_apb_sels[] = {"osc_25m", "sys1_pll_400m", "sys3_pll_out", "sys2_pll_333m", "sys2_pll_200m",
90 "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", }; 90 "sys1_pll_800m", "audio_pll1_out", "video_pll1_out", };
91 91
92static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m", 92static const char * const imx8mq_ahb_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_800m", "sys1_pll_400m",
93 "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; 93 "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
94 94
95static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m", 95static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m", "sys2_pll_500m", "sys1_pll_800m", "sys2_pll_1000m",
96 "sys2_pll_166m", "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", }; 96 "sys2_pll_166m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", };
97 97
98static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", 98static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
99 "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out"}; 99 "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out"};
100 100
101static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m", 101static const char * const imx8mq_dram_alt_sels[] = {"osc_25m", "sys1_pll_800m", "sys1_pll_100m", "sys2_pll_500m",
102 "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", }; 102 "sys2_pll_250m", "sys1_pll_400m", "audio_pll1_out", "sys1_pll_266m", };
103 103
104static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", 104static const char * const imx8mq_dram_apb_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
105 "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; 105 "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
106 106
107static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; 107static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
108 108
109static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll2_out", "audio_pll1_out", }; 109static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_100m", "sys2_pll_125m", "sys3_pll_out", "audio_pll1_out", };
110 110
111static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; 111static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
112 112
113static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll2_out", "audio_pll2_out", }; 113static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
114 114
115static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", 115static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
116 "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll2_out", }; 116 "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
117 117
118static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", 118static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
119 "clk_ext3", "clk_ext4", }; 119 "clk_ext3", "clk_ext4", };
120 120
121static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll2_out", 121static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
122 "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; 122 "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
123 123
124static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; 124static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
125 125
126static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll2_out", "clk_ext4", }; 126static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
127 127
128static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", }; 128static const char * const imx8mq_sai1_sels[] = {"osc_25m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out", "sys1_pll_133m", "osc_27m", "clk_ext1", "clk_ext2", };
129 129
@@ -151,40 +151,40 @@ static const char * const imx8mq_enet_phy_sels[] = {"osc_25m", "sys2_pll_50m", "
151 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", }; 151 "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
152 152
153static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m", 153static const char * const imx8mq_nand_sels[] = {"osc_25m", "sys2_pll_500m", "audio_pll1_out", "sys1_pll_400m",
154 "audio_pll2_out", "sys3_pll2_out", "sys2_pll_250m", "video_pll1_out", }; 154 "audio_pll2_out", "sys3_pll_out", "sys2_pll_250m", "video_pll1_out", };
155 155
156static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", 156static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
157 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; 157 "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
158 158
159static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", 159static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
160 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; 160 "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
161 161
162static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", 162static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m",
163 "audio_pll2_out", "sys1_pll_266m", "sys3_pll2_out", "sys1_pll_100m", }; 163 "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", };
164 164
165static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", 165static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
166 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; 166 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
167 167
168static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", 168static const char * const imx8mq_i2c2_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
169 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; 169 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
170 170
171static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", 171static const char * const imx8mq_i2c3_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
172 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; 172 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
173 173
174static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll2_out", "audio_pll1_out", 174static const char * const imx8mq_i2c4_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out",
175 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; 175 "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", };
176 176
177static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", 177static const char * const imx8mq_uart1_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
178 "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; 178 "sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
179 179
180static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", 180static const char * const imx8mq_uart2_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
181 "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; 181 "sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
182 182
183static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", 183static const char * const imx8mq_uart3_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
184 "sys3_pll2_out", "clk_ext2", "clk_ext4", "audio_pll2_out", }; 184 "sys3_pll_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
185 185
186static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m", 186static const char * const imx8mq_uart4_sels[] = {"osc_25m", "sys1_pll_80m", "sys2_pll_200m", "sys2_pll_100m",
187 "sys3_pll2_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; 187 "sys3_pll_out", "clk_ext2", "clk_ext3", "audio_pll2_out", };
188 188
189static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m", 189static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
190 "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; 190 "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
@@ -196,79 +196,79 @@ static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1
196 "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" }; 196 "sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
197 197
198static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", 198static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
199 "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; 199 "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
200 200
201static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", 201static const char * const imx8mq_ecspi2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
202 "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; 202 "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
203 203
204static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", 204static const char * const imx8mq_pwm1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
205 "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; 205 "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
206 206
207static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", 207static const char * const imx8mq_pwm2_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
208 "sys3_pll2_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", }; 208 "sys3_pll_out", "clk_ext1", "sys1_pll_80m", "video_pll1_out", };
209 209
210static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", 210static const char * const imx8mq_pwm3_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
211 "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; 211 "sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
212 212
213static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m", 213static const char * const imx8mq_pwm4_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_160m", "sys1_pll_40m",
214 "sys3_pll2_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", }; 214 "sys3_pll_out", "clk_ext2", "sys1_pll_80m", "video_pll1_out", };
215 215
216static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m", 216static const char * const imx8mq_gpt1_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_400m", "sys1_pll_40m",
217 "sys1_pll_80m", "audio_pll1_out", "clk_ext1", }; 217 "sys1_pll_80m", "audio_pll1_out", "clk_ext1", };
218 218
219static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out", 219static const char * const imx8mq_wdog_sels[] = {"osc_25m", "sys1_pll_133m", "sys1_pll_160m", "vpu_pll_out",
220 "sys2_pll_125m", "sys3_pll2_out", "sys1_pll_80m", "sys2_pll_166m", }; 220 "sys2_pll_125m", "sys3_pll_out", "sys1_pll_80m", "sys2_pll_166m", };
221 221
222static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll2_out", "sys2_pll_200m", 222static const char * const imx8mq_wrclk_sels[] = {"osc_25m", "sys1_pll_40m", "vpu_pll_out", "sys3_pll_out", "sys2_pll_200m",
223 "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", }; 223 "sys1_pll_266m", "sys2_pll_500m", "sys1_pll_100m", };
224 224
225static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", 225static const char * const imx8mq_dsi_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
226 "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; 226 "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
227 227
228static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", 228static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
229 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; 229 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
230 230
231static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m", 231static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_100m", "sys1_pll_800m",
232 "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; 232 "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
233 233
234static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", 234static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
235 "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; 235 "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
236 236
237static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", 237static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
238 "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; 238 "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
239 239
240static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", 240static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
241 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; 241 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
242 242
243static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", 243static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
244 "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; 244 "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
245 245
246static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m", 246static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
247 "sys2_pll_1000m", "sys3_pll2_out", "audio_pll2_out", "video_pll1_out", }; 247 "sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
248 248
249static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m", 249static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
250 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", }; 250 "sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
251 251
252static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m", 252static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
253 "sys2_pll_1000m", "sys3_pll2_out", "clk_ext3", "audio_pll2_out", }; 253 "sys2_pll_1000m", "sys3_pll_out", "clk_ext3", "audio_pll2_out", };
254 254
255static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", 255static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
256 "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll2_out", }; 256 "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
257 257
258static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", 258static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1",
259 "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", }; 259 "clk_ext2", "clk_ext3", "clk_ext4", "sys1_pll_400m", };
260 260
261static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll2_out", 261static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
262 "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; 262 "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
263 263
264static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m", 264static const char * const imx8mq_ecspi3_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
265 "sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", }; 265 "sys1_pll_800m", "sys3_pll_out", "sys2_pll_250m", "audio_pll2_out", };
266static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 266static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
267 267
268static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m", 268static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "osc_27m", "sys1_pll_200m",
269 "audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", }; 269 "audio_pll2_out", "sys2_pll_500m", "vpu_pll_out", "sys1_pll_80m", };
270static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m", 270static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
271 "sys3_pll2_out", "audio_pll1_out", "video_pll1_out", "ckil", }; 271 "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
272 272
273static struct clk_onecell_data clk_data; 273static struct clk_onecell_data clk_data;
274 274
@@ -406,7 +406,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
406 clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80); 406 clks[IMX8MQ_CLK_NOC_APB] = imx8m_clk_composite_critical("noc_apb", imx8mq_noc_apb_sels, base + 0x8d80);
407 407
408 /* AHB */ 408 /* AHB */
409 clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite("ahb", imx8mq_ahb_sels, base + 0x9000); 409 /* AHB clock is used by the AHB bus therefore marked as critical */
410 clks[IMX8MQ_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels, base + 0x9000);
410 clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100); 411 clks[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mq_audio_ahb_sels, base + 0x9100);
411 412
412 /* IPG */ 413 /* IPG */
@@ -523,8 +524,8 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
523 clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); 524 clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
524 clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); 525 clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
525 clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); 526 clks[IMX8MQ_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
526 clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); 527 clks[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
527 clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_core_ref", base + 0x44e0, 0); 528 clks[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0);
528 clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0); 529 clks[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
529 clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0); 530 clks[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0);
530 clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); 531 clks[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
@@ -539,7 +540,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
539 clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss); 540 clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
540 clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss); 541 clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_dcss);
541 clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss); 542 clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm", base + 0x45d0, 0, &share_count_dcss);
542 clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4_flags("tmu_root_clk", "ipg_root", base + 0x4620, 0, CLK_IS_CRITICAL); 543 clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
543 clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); 544 clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
544 clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0); 545 clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
545 clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0); 546 clks[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_gate4("csi2_root_clk", "csi2_core", base + 0x4660, 0);
@@ -561,10 +562,18 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
561 clk_data.clk_num = ARRAY_SIZE(clks); 562 clk_data.clk_num = ARRAY_SIZE(clks);
562 563
563 err = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 564 err = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
564 WARN_ON(err); 565 if (err < 0) {
566 dev_err(dev, "failed to register clks for i.MX8MQ\n");
567 goto unregister_clks;
568 }
565 569
566 imx_register_uart_clocks(uart_clks); 570 imx_register_uart_clocks(uart_clks);
567 571
572 return 0;
573
574unregister_clks:
575 imx_unregister_clocks(clks, ARRAY_SIZE(clks));
576
568 return err; 577 return err;
569} 578}
570 579
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index b7213023b238..7a815ec76aa5 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
191 tmp &= ~RST_MASK; 191 tmp &= ~RST_MASK;
192 writel_relaxed(tmp, pll->base); 192 writel_relaxed(tmp, pll->base);
193 193
194 /* Enable BYPASS */
195 tmp |= BYPASS_MASK;
196 writel(tmp, pll->base);
197
194 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 198 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
195 (rate->sdiv << SDIV_SHIFT); 199 (rate->sdiv << SDIV_SHIFT);
196 writel_relaxed(div_val, pll->base + 0x4); 200 writel_relaxed(div_val, pll->base + 0x4);
@@ -250,6 +254,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
250 tmp &= ~RST_MASK; 254 tmp &= ~RST_MASK;
251 writel_relaxed(tmp, pll->base); 255 writel_relaxed(tmp, pll->base);
252 256
257 /* Enable BYPASS */
258 tmp |= BYPASS_MASK;
259 writel_relaxed(tmp, pll->base);
260
253 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | 261 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
254 (rate->sdiv << SDIV_SHIFT); 262 (rate->sdiv << SDIV_SHIFT);
255 writel_relaxed(div_val, pll->base + 0x4); 263 writel_relaxed(div_val, pll->base + 0x4);
@@ -283,16 +291,28 @@ static int clk_pll14xx_prepare(struct clk_hw *hw)
283{ 291{
284 struct clk_pll14xx *pll = to_clk_pll14xx(hw); 292 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
285 u32 val; 293 u32 val;
294 int ret;
286 295
287 /* 296 /*
288 * RESETB = 1 from 0, PLL starts its normal 297 * RESETB = 1 from 0, PLL starts its normal
289 * operation after lock time 298 * operation after lock time
290 */ 299 */
291 val = readl_relaxed(pll->base + GNRL_CTL); 300 val = readl_relaxed(pll->base + GNRL_CTL);
301 if (val & RST_MASK)
302 return 0;
303 val |= BYPASS_MASK;
304 writel_relaxed(val, pll->base + GNRL_CTL);
292 val |= RST_MASK; 305 val |= RST_MASK;
293 writel_relaxed(val, pll->base + GNRL_CTL); 306 writel_relaxed(val, pll->base + GNRL_CTL);
294 307
295 return clk_pll14xx_wait_lock(pll); 308 ret = clk_pll14xx_wait_lock(pll);
309 if (ret)
310 return ret;
311
312 val &= ~BYPASS_MASK;
313 writel_relaxed(val, pll->base + GNRL_CTL);
314
315 return 0;
296} 316}
297 317
298static int clk_pll14xx_is_prepared(struct clk_hw *hw) 318static int clk_pll14xx_is_prepared(struct clk_hw *hw)
@@ -348,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
348 struct clk_pll14xx *pll; 368 struct clk_pll14xx *pll;
349 struct clk *clk; 369 struct clk *clk;
350 struct clk_init_data init; 370 struct clk_init_data init;
371 u32 val;
351 372
352 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 373 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
353 if (!pll) 374 if (!pll)
@@ -379,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
379 pll->rate_table = pll_clk->rate_table; 400 pll->rate_table = pll_clk->rate_table;
380 pll->rate_count = pll_clk->rate_count; 401 pll->rate_count = pll_clk->rate_count;
381 402
403 val = readl_relaxed(pll->base + GNRL_CTL);
404 val &= ~BYPASS_MASK;
405 writel_relaxed(val, pll->base + GNRL_CTL);
406
382 clk = clk_register(NULL, &pll->hw); 407 clk = clk_register(NULL, &pll->hw);
383 if (IS_ERR(clk)) { 408 if (IS_ERR(clk)) {
384 pr_err("%s: failed to register pll %s %lu\n", 409 pr_err("%s: failed to register pll %s %lu\n",
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index bb4ec1b33faf..f7a389a50401 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -10,7 +10,6 @@ extern spinlock_t imx_ccm_lock;
10void imx_check_clocks(struct clk *clks[], unsigned int count); 10void imx_check_clocks(struct clk *clks[], unsigned int count);
11void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 11void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
12void imx_register_uart_clocks(struct clk ** const clks[]); 12void imx_register_uart_clocks(struct clk ** const clks[]);
13void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
14void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); 13void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
15void imx_unregister_clocks(struct clk *clks[], unsigned int count); 14void imx_unregister_clocks(struct clk *clks[], unsigned int count);
16 15
@@ -51,12 +50,6 @@ struct imx_pll14xx_clk {
51 int flags; 50 int flags;
52}; 51};
53 52
54#define imx_clk_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift) \
55 imx_clk_hw_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift)->clk
56
57#define imx_clk_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents) \
58 imx_clk_hw_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents)->clk
59
60#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ 53#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
61 imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk 54 imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
62 55
@@ -74,15 +67,6 @@ struct imx_pll14xx_clk {
74#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ 67#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
75 imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk 68 imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
76 69
77#define imx_clk_fixup_divider(name, parent, reg, shift, width, fixup) \
78 imx_clk_hw_fixup_divider(name, parent, reg, shift, width, fixup)->clk
79
80#define imx_clk_fixup_mux(name, reg, shift, width, parents, num_parents, fixup) \
81 imx_clk_hw_fixup_mux(name, reg, shift, width, parents, num_parents, fixup)->clk
82
83#define imx_clk_mux_ldb(name, reg, shift, width, parents, num_parents) \
84 imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents)->clk
85
86#define imx_clk_fixed_factor(name, parent, mult, div) \ 70#define imx_clk_fixed_factor(name, parent, mult, div) \
87 imx_clk_hw_fixed_factor(name, parent, mult, div)->clk 71 imx_clk_hw_fixed_factor(name, parent, mult, div)->clk
88 72
@@ -92,21 +76,12 @@ struct imx_pll14xx_clk {
92#define imx_clk_gate_dis(name, parent, reg, shift) \ 76#define imx_clk_gate_dis(name, parent, reg, shift) \
93 imx_clk_hw_gate_dis(name, parent, reg, shift)->clk 77 imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
94 78
95#define imx_clk_gate_dis_flags(name, parent, reg, shift, flags) \
96 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags)->clk
97
98#define imx_clk_gate_flags(name, parent, reg, shift, flags) \
99 imx_clk_hw_gate_flags(name, parent, reg, shift, flags)->clk
100
101#define imx_clk_gate2(name, parent, reg, shift) \ 79#define imx_clk_gate2(name, parent, reg, shift) \
102 imx_clk_hw_gate2(name, parent, reg, shift)->clk 80 imx_clk_hw_gate2(name, parent, reg, shift)->clk
103 81
104#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ 82#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
105 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk 83 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
106 84
107#define imx_clk_gate2_shared(name, parent, reg, shift, share_count) \
108 imx_clk_hw_gate2_shared(name, parent, reg, shift, share_count)->clk
109
110#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \ 85#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
111 imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk 86 imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
112 87
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 2642d36d1e2c..a3b4635f6278 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -257,4 +257,4 @@ static void __init jz4725b_cgu_init(struct device_node *np)
257 257
258 ingenic_cgu_register_syscore_ops(cgu); 258 ingenic_cgu_register_syscore_ops(cgu);
259} 259}
260CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); 260CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4c0a20949c2c..978f32dd424a 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -53,6 +53,10 @@ static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
54}; 54};
55 55
56static const u8 jz4740_cgu_pll_half_div_table[] = {
57 2, 1,
58};
59
56static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 60static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
57 61
58 /* External clocks */ 62 /* External clocks */
@@ -86,7 +90,10 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
86 [JZ4740_CLK_PLL_HALF] = { 90 [JZ4740_CLK_PLL_HALF] = {
87 "pll half", CGU_CLK_DIV, 91 "pll half", CGU_CLK_DIV,
88 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
89 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, 93 .div = {
94 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
95 jz4740_cgu_pll_half_div_table,
96 },
90 }, 97 },
91 98
92 [JZ4740_CLK_CCLK] = { 99 [JZ4740_CLK_CCLK] = {
@@ -241,4 +248,4 @@ static void __init jz4740_cgu_init(struct device_node *np)
241 248
242 ingenic_cgu_register_syscore_ops(cgu); 249 ingenic_cgu_register_syscore_ops(cgu);
243} 250}
244CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); 251CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index eebc1bea3841..956dd653a43d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -443,4 +443,4 @@ static void __init jz4770_cgu_init(struct device_node *np)
443} 443}
444 444
445/* We only probe via devicetree, no need for a platform driver */ 445/* We only probe via devicetree, no need for a platform driver */
446CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init); 446CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 8c67f89df25e..ea905ff72bf0 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -725,4 +725,4 @@ static void __init jz4780_cgu_init(struct device_node *np)
725 725
726 ingenic_cgu_register_syscore_ops(cgu); 726 ingenic_cgu_register_syscore_ops(cgu);
727} 727}
728CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); 728CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ce3d9b300bab..7efc3617bbd5 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -117,6 +117,62 @@ config COMMON_CLK_MT2712_VENCSYS
117 ---help--- 117 ---help---
118 This driver supports MediaTek MT2712 vencsys clocks. 118 This driver supports MediaTek MT2712 vencsys clocks.
119 119
120config COMMON_CLK_MT6779
121 bool "Clock driver for MediaTek MT6779"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
123 select COMMON_CLK_MEDIATEK
124 default ARCH_MEDIATEK && ARM64
125 help
126 This driver supports MediaTek MT6779 basic clocks.
127
128config COMMON_CLK_MT6779_MMSYS
129 bool "Clock driver for MediaTek MT6779 mmsys"
130 depends on COMMON_CLK_MT6779
131 help
132 This driver supports MediaTek MT6779 mmsys clocks.
133
134config COMMON_CLK_MT6779_IMGSYS
135 bool "Clock driver for MediaTek MT6779 imgsys"
136 depends on COMMON_CLK_MT6779
137 help
138 This driver supports MediaTek MT6779 imgsys clocks.
139
140config COMMON_CLK_MT6779_IPESYS
141 bool "Clock driver for MediaTek MT6779 ipesys"
142 depends on COMMON_CLK_MT6779
143 help
144 This driver supports MediaTek MT6779 ipesys clocks.
145
146config COMMON_CLK_MT6779_CAMSYS
147 bool "Clock driver for MediaTek MT6779 camsys"
148 depends on COMMON_CLK_MT6779
149 help
150 This driver supports MediaTek MT6779 camsys clocks.
151
152config COMMON_CLK_MT6779_VDECSYS
153 bool "Clock driver for MediaTek MT6779 vdecsys"
154 depends on COMMON_CLK_MT6779
155 help
156 This driver supports MediaTek MT6779 vdecsys clocks.
157
158config COMMON_CLK_MT6779_VENCSYS
159 bool "Clock driver for MediaTek MT6779 vencsys"
160 depends on COMMON_CLK_MT6779
161 help
162 This driver supports MediaTek MT6779 vencsys clocks.
163
164config COMMON_CLK_MT6779_MFGCFG
165 bool "Clock driver for MediaTek MT6779 mfgcfg"
166 depends on COMMON_CLK_MT6779
167 help
168 This driver supports MediaTek MT6779 mfgcfg clocks.
169
170config COMMON_CLK_MT6779_AUDSYS
171 bool "Clock driver for Mediatek MT6779 audsys"
172 depends on COMMON_CLK_MT6779
173 help
174 This driver supports Mediatek MT6779 audsys clocks.
175
120config COMMON_CLK_MT6797 176config COMMON_CLK_MT6797
121 bool "Clock driver for MediaTek MT6797" 177 bool "Clock driver for MediaTek MT6797"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST 178 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 672de0099eef..8cdb76a5cd71 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,6 +1,15 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o 2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
3 3
4obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
5obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
6obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
7obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
8obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
9obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
10obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
11obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
12obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
4obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o 13obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
5obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o 14obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
6obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o 15obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 803bf0ae1fd6..a35cf0b22150 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -150,7 +150,8 @@ struct clk *mtk_clk_register_gate(
150 int sta_ofs, 150 int sta_ofs,
151 u8 bit, 151 u8 bit,
152 const struct clk_ops *ops, 152 const struct clk_ops *ops,
153 unsigned long flags) 153 unsigned long flags,
154 struct device *dev)
154{ 155{
155 struct mtk_clk_gate *cg; 156 struct mtk_clk_gate *cg;
156 struct clk *clk; 157 struct clk *clk;
@@ -174,7 +175,7 @@ struct clk *mtk_clk_register_gate(
174 175
175 cg->hw.init = &init; 176 cg->hw.init = &init;
176 177
177 clk = clk_register(NULL, &cg->hw); 178 clk = clk_register(dev, &cg->hw);
178 if (IS_ERR(clk)) 179 if (IS_ERR(clk))
179 kfree(cg); 180 kfree(cg);
180 181
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index e05c73697485..3c3329ec54b7 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -40,7 +40,8 @@ struct clk *mtk_clk_register_gate(
40 int sta_ofs, 40 int sta_ofs,
41 u8 bit, 41 u8 bit,
42 const struct clk_ops *ops, 42 const struct clk_ops *ops,
43 unsigned long flags); 43 unsigned long flags,
44 struct device *dev);
44 45
45#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ 46#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
46 _ops, _flags) { \ 47 _ops, _flags) { \
diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c
new file mode 100644
index 000000000000..11b209f95e25
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-aud.c
@@ -0,0 +1,117 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static const struct mtk_gate_regs audio0_cg_regs = {
19 .set_ofs = 0x0,
20 .clr_ofs = 0x0,
21 .sta_ofs = 0x0,
22};
23
24static const struct mtk_gate_regs audio1_cg_regs = {
25 .set_ofs = 0x4,
26 .clr_ofs = 0x4,
27 .sta_ofs = 0x4,
28};
29
30#define GATE_AUDIO0(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
32 &mtk_clk_gate_ops_no_setclr)
33#define GATE_AUDIO1(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
35 &mtk_clk_gate_ops_no_setclr)
36
37static const struct mtk_gate audio_clks[] = {
38 /* AUDIO0 */
39 GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
40 GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
41 GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
42 GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
43 "aud_eng2_sel", 18),
44 GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
45 "aud_eng1_sel", 19),
46 GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
47 GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
48 GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
49 GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
50 "audio_sel", 26),
51 GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
52 GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
53 /* AUDIO1 */
54 GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
55 "audio_sel", 4),
56 GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
57 "audio_sel", 5),
58 GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
59 "audio_sel", 6),
60 GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
61 "audio_sel", 7),
62 GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
63 "audio_sel", 8),
64 GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
65 "audio_sel", 12),
66 GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
67 "audio_sel", 13),
68 GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
69 "audio_sel", 14),
70 GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
71 "audio_h_sel", 15),
72 GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
73 "audio_h_sel", 16),
74 GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
75 "audio_h_sel", 17),
76 GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
77 "audio_sel", 20),
78 GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
79 "audio_h_sel",
80 21),
81 GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
82 28),
83 GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
84 "audio_sel", 29),
85 GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
86 "audio_sel", 30),
87 GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
88 "audio_h_sel", 31),
89};
90
91static const struct of_device_id of_match_clk_mt6779_aud[] = {
92 { .compatible = "mediatek,mt6779-audio", },
93 {}
94};
95
96static int clk_mt6779_aud_probe(struct platform_device *pdev)
97{
98 struct clk_onecell_data *clk_data;
99 struct device_node *node = pdev->dev.of_node;
100
101 clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
102
103 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
104 clk_data);
105
106 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
107}
108
109static struct platform_driver clk_mt6779_aud_drv = {
110 .probe = clk_mt6779_aud_probe,
111 .driver = {
112 .name = "clk-mt6779-aud",
113 .of_match_table = of_match_clk_mt6779_aud,
114 },
115};
116
117builtin_platform_driver(clk_mt6779_aud_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c
new file mode 100644
index 000000000000..244d4208b7fb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-cam.c
@@ -0,0 +1,66 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs cam_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_CAM(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate cam_clks[] = {
25 GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
26 GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
27 GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
28 GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
29 GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
30 GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
31 GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
32 GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
33 GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
34 GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
35 GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
36 GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
37 GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
38};
39
40static const struct of_device_id of_match_clk_mt6779_cam[] = {
41 { .compatible = "mediatek,mt6779-camsys", },
42 {}
43};
44
45static int clk_mt6779_cam_probe(struct platform_device *pdev)
46{
47 struct clk_onecell_data *clk_data;
48 struct device_node *node = pdev->dev.of_node;
49
50 clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
51
52 mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
53 clk_data);
54
55 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56}
57
58static struct platform_driver clk_mt6779_cam_drv = {
59 .probe = clk_mt6779_cam_probe,
60 .driver = {
61 .name = "clk-mt6779-cam",
62 .of_match_table = of_match_clk_mt6779_cam,
63 },
64};
65
66builtin_platform_driver(clk_mt6779_cam_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c
new file mode 100644
index 000000000000..26292a45c613
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-img.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs img_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IMG(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate img_clks[] = {
25 GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
26 GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
27 GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
28 GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
29 GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
30};
31
32static const struct of_device_id of_match_clk_mt6779_img[] = {
33 { .compatible = "mediatek,mt6779-imgsys", },
34 {}
35};
36
37static int clk_mt6779_img_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
43
44 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_img_drv = {
51 .probe = clk_mt6779_img_probe,
52 .driver = {
53 .name = "clk-mt6779-img",
54 .of_match_table = of_match_clk_mt6779_img,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_img_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c
new file mode 100644
index 000000000000..bb519075639c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-ipe.c
@@ -0,0 +1,60 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs ipe_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IPE(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate ipe_clks[] = {
25 GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
26 GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
27 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
28 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
29 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
30 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
31 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
32};
33
34static const struct of_device_id of_match_clk_mt6779_ipe[] = {
35 { .compatible = "mediatek,mt6779-ipesys", },
36 {}
37};
38
39static int clk_mt6779_ipe_probe(struct platform_device *pdev)
40{
41 struct clk_onecell_data *clk_data;
42 struct device_node *node = pdev->dev.of_node;
43
44 clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
45
46 mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
47 clk_data);
48
49 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50}
51
52static struct platform_driver clk_mt6779_ipe_drv = {
53 .probe = clk_mt6779_ipe_probe,
54 .driver = {
55 .name = "clk-mt6779-ipe",
56 .of_match_table = of_match_clk_mt6779_ipe,
57 },
58};
59
60builtin_platform_driver(clk_mt6779_ipe_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c
new file mode 100644
index 000000000000..c6ee2a89c070
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mfg.c
@@ -0,0 +1,55 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs mfg_cg_regs = {
16 .set_ofs = 0x4,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x0,
19};
20
21#define GATE_MFG(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr)
24
25static const struct mtk_gate mfg_clks[] = {
26 GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
27};
28
29static int clk_mt6779_mfg_probe(struct platform_device *pdev)
30{
31 struct clk_onecell_data *clk_data;
32 struct device_node *node = pdev->dev.of_node;
33
34 clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
35
36 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
37 clk_data);
38
39 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
40}
41
42static const struct of_device_id of_match_clk_mt6779_mfg[] = {
43 { .compatible = "mediatek,mt6779-mfgcfg", },
44 {}
45};
46
47static struct platform_driver clk_mt6779_mfg_drv = {
48 .probe = clk_mt6779_mfg_probe,
49 .driver = {
50 .name = "clk-mt6779-mfg",
51 .of_match_table = of_match_clk_mt6779_mfg,
52 },
53};
54
55builtin_platform_driver(clk_mt6779_mfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c
new file mode 100644
index 000000000000..fb5fbb8e3e41
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mm.c
@@ -0,0 +1,113 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs mm0_cg_regs = {
15 .set_ofs = 0x0104,
16 .clr_ofs = 0x0108,
17 .sta_ofs = 0x0100,
18};
19
20static const struct mtk_gate_regs mm1_cg_regs = {
21 .set_ofs = 0x0114,
22 .clr_ofs = 0x0118,
23 .sta_ofs = 0x0110,
24};
25
26#define GATE_MM0(_id, _name, _parent, _shift) \
27 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
28 &mtk_clk_gate_ops_setclr)
29#define GATE_MM1(_id, _name, _parent, _shift) \
30 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
31 &mtk_clk_gate_ops_setclr)
32
33static const struct mtk_gate mm_clks[] = {
34 /* MM0 */
35 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
36 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
37 GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
38 GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
39 GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
40 GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
41 GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
42 GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
43 GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
44 GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
45 GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
46 GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
47 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
48 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
51 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
52 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
53 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
54 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
55 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
56 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
57 GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
58 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
59 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
60 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
61 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
62 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
63 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
64 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
65 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
66 GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
67 /* MM1 */
68 GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
69 GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
70 GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
71 GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
72 GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
73 GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
74 GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
75 GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
76 GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
77 GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
78 GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
79 GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
80 GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
81 GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
82 GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
83 GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
84 GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
85};
86
87static const struct of_device_id of_match_clk_mt6779_mm[] = {
88 { .compatible = "mediatek,mt6779-mmsys", },
89 {}
90};
91
92static int clk_mt6779_mm_probe(struct platform_device *pdev)
93{
94 struct clk_onecell_data *clk_data;
95 struct device_node *node = pdev->dev.of_node;
96
97 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
98
99 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
100 clk_data);
101
102 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
103}
104
105static struct platform_driver clk_mt6779_mm_drv = {
106 .probe = clk_mt6779_mm_probe,
107 .driver = {
108 .name = "clk-mt6779-mm",
109 .of_match_table = of_match_clk_mt6779_mm,
110 },
111};
112
113builtin_platform_driver(clk_mt6779_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c
new file mode 100644
index 000000000000..1900da2586a1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-vdec.c
@@ -0,0 +1,67 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs vdec0_cg_regs = {
16 .set_ofs = 0x0000,
17 .clr_ofs = 0x0004,
18 .sta_ofs = 0x0000,
19};
20
21static const struct mtk_gate_regs vdec1_cg_regs = {
22 .set_ofs = 0x0008,
23 .clr_ofs = 0x000c,
24 .sta_ofs = 0x0008,
25};
26
27#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
29 &mtk_clk_gate_ops_setclr_inv)
30#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
32 &mtk_clk_gate_ops_setclr_inv)
33
34static const struct mtk_gate vdec_clks[] = {
35 /* VDEC0 */
36 GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
37 /* VDEC1 */
38 GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
39};
40
41static const struct of_device_id of_match_clk_mt6779_vdec[] = {
42 { .compatible = "mediatek,mt6779-vdecsys", },
43 {}
44};
45
46static int clk_mt6779_vdec_probe(struct platform_device *pdev)
47{
48 struct clk_onecell_data *clk_data;
49 struct device_node *node = pdev->dev.of_node;
50
51 clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
52
53 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
54 clk_data);
55
56 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
57}
58
59static struct platform_driver clk_mt6779_vdec_drv = {
60 .probe = clk_mt6779_vdec_probe,
61 .driver = {
62 .name = "clk-mt6779-vdec",
63 .of_match_table = of_match_clk_mt6779_vdec,
64 },
65};
66
67builtin_platform_driver(clk_mt6779_vdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c
new file mode 100644
index 000000000000..b41d1f859edc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-venc.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs venc_cg_regs = {
16 .set_ofs = 0x0004,
17 .clr_ofs = 0x0008,
18 .sta_ofs = 0x0000,
19};
20
21#define GATE_VENC_I(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr_inv)
24
25static const struct mtk_gate venc_clks[] = {
26 GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
27 GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
28 GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
29 GATE_VENC_I(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
30};
31
32static const struct of_device_id of_match_clk_mt6779_venc[] = {
33 { .compatible = "mediatek,mt6779-vencsys", },
34 {}
35};
36
37static int clk_mt6779_venc_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
43
44 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_venc_drv = {
51 .probe = clk_mt6779_venc_probe,
52 .driver = {
53 .name = "clk-mt6779-venc",
54 .of_match_table = of_match_clk_mt6779_venc,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_venc_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
new file mode 100644
index 000000000000..608a9a6621a3
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -0,0 +1,1315 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/of.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include "clk-mtk.h"
13#include "clk-mux.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static DEFINE_SPINLOCK(mt6779_clk_lock);
19
20static const struct mtk_fixed_clk top_fixed_clks[] = {
21 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22};
23
24static const struct mtk_fixed_factor top_divs[] = {
25 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
26 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
27 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
28 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
29 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
30 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
31 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
32 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
33 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
34 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
38 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
39 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
40 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
44 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
45 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
46 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
47 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
48 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
49 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
50 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
52 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
53 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
54 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
55 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
56 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
57 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
58 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
59 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
60 1, 2),
61 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
62 1, 4),
63 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
64 1, 8),
65 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
66 1, 16),
67 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
68 1, 32),
69 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
70 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
71 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
72 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
73 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
74 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
75 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
76 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
77 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
80 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
81 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
82 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
83 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
84 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
85 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
86 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
87 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
88 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
89 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
90 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
91 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
92 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
93 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
94 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
95 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
96 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
97 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
99 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
100 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
101 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
102 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
103 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
104 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
105 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
106 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
107 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
108 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
109 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
110 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
111 "tvdpll", 1, 1),
112 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
113};
114
115static const char * const axi_parents[] = {
116 "clk26m",
117 "mainpll_d2_d4",
118 "mainpll_d7",
119 "osc_d4"
120};
121
122static const char * const mm_parents[] = {
123 "clk26m",
124 "tvdpll_mainpll_d2_ck",
125 "mmpll_d7",
126 "mmpll_d5_d2",
127 "mainpll_d2_d2",
128 "mainpll_d3_d2"
129};
130
131static const char * const scp_parents[] = {
132 "clk26m",
133 "univpll_d2_d8",
134 "mainpll_d2_d4",
135 "mainpll_d3",
136 "univpll_d3",
137 "ad_osc2_ck",
138 "osc2_d2",
139 "osc2_d3"
140};
141
142static const char * const img_parents[] = {
143 "clk26m",
144 "mainpll_d2",
145 "mainpll_d2",
146 "univpll_d3",
147 "mainpll_d3",
148 "mmpll_d5_d2",
149 "tvdpll_mainpll_d2_ck",
150 "mainpll_d5"
151};
152
153static const char * const ipe_parents[] = {
154 "clk26m",
155 "mainpll_d2",
156 "mmpll_d7",
157 "univpll_d3",
158 "mainpll_d3",
159 "mmpll_d5_d2",
160 "mainpll_d2_d2",
161 "mainpll_d5"
162};
163
164static const char * const dpe_parents[] = {
165 "clk26m",
166 "mainpll_d2",
167 "mmpll_d7",
168 "univpll_d3",
169 "mainpll_d3",
170 "mmpll_d5_d2",
171 "mainpll_d2_d2",
172 "mainpll_d5"
173};
174
175static const char * const cam_parents[] = {
176 "clk26m",
177 "mainpll_d2",
178 "mmpll_d6",
179 "mainpll_d3",
180 "mmpll_d7",
181 "univpll_d3",
182 "mmpll_d5_d2",
183 "adsppll_d5",
184 "tvdpll_mainpll_d2_ck",
185 "univpll_d3_d2"
186};
187
188static const char * const ccu_parents[] = {
189 "clk26m",
190 "mainpll_d2",
191 "mmpll_d6",
192 "mainpll_d3",
193 "mmpll_d7",
194 "univpll_d3",
195 "mmpll_d5_d2",
196 "mainpll_d2_d2",
197 "adsppll_d5",
198 "univpll_d3_d2"
199};
200
201static const char * const dsp_parents[] = {
202 "clk26m",
203 "univpll_d3_d8",
204 "univpll_d3_d4",
205 "mainpll_d2_d4",
206 "univpll_d3_d2",
207 "mainpll_d2_d2",
208 "univpll_d2_d2",
209 "mainpll_d3",
210 "univpll_d3",
211 "mmpll_d7",
212 "mmpll_d6",
213 "adsppll_d5",
214 "tvdpll_ck",
215 "tvdpll_mainpll_d2_ck",
216 "univpll_d2",
217 "adsppll_d4"
218};
219
220static const char * const dsp1_parents[] = {
221 "clk26m",
222 "univpll_d3_d8",
223 "univpll_d3_d4",
224 "mainpll_d2_d4",
225 "univpll_d3_d2",
226 "mainpll_d2_d2",
227 "univpll_d2_d2",
228 "mainpll_d3",
229 "univpll_d3",
230 "mmpll_d7",
231 "mmpll_d6",
232 "adsppll_d5",
233 "tvdpll_ck",
234 "tvdpll_mainpll_d2_ck",
235 "univpll_d2",
236 "adsppll_d4"
237};
238
239static const char * const dsp2_parents[] = {
240 "clk26m",
241 "univpll_d3_d8",
242 "univpll_d3_d4",
243 "mainpll_d2_d4",
244 "univpll_d3_d2",
245 "mainpll_d2_d2",
246 "univpll_d2_d2",
247 "mainpll_d3",
248 "univpll_d3",
249 "mmpll_d7",
250 "mmpll_d6",
251 "adsppll_d5",
252 "tvdpll_ck",
253 "tvdpll_mainpll_d2_ck",
254 "univpll_d2",
255 "adsppll_d4"
256};
257
258static const char * const dsp3_parents[] = {
259 "clk26m",
260 "univpll_d3_d8",
261 "mainpll_d2_d4",
262 "univpll_d3_d2",
263 "mainpll_d2_d2",
264 "univpll_d2_d2",
265 "mainpll_d3",
266 "univpll_d3",
267 "mmpll_d7",
268 "mmpll_d6",
269 "mainpll_d2",
270 "tvdpll_ck",
271 "tvdpll_mainpll_d2_ck",
272 "univpll_d2",
273 "adsppll_d4",
274 "mmpll_d4"
275};
276
277static const char * const ipu_if_parents[] = {
278 "clk26m",
279 "univpll_d3_d8",
280 "univpll_d3_d4",
281 "mainpll_d2_d4",
282 "univpll_d3_d2",
283 "mainpll_d2_d2",
284 "univpll_d2_d2",
285 "mainpll_d3",
286 "univpll_d3",
287 "mmpll_d7",
288 "mmpll_d6",
289 "adsppll_d5",
290 "tvdpll_ck",
291 "tvdpll_mainpll_d2_ck",
292 "univpll_d2",
293 "adsppll_d4"
294};
295
296static const char * const mfg_parents[] = {
297 "clk26m",
298 "mfgpll_ck",
299 "univpll_d3",
300 "mainpll_d5"
301};
302
303static const char * const f52m_mfg_parents[] = {
304 "clk26m",
305 "univpll_d3_d2",
306 "univpll_d3_d4",
307 "univpll_d3_d8"
308};
309
310static const char * const camtg_parents[] = {
311 "clk26m",
312 "univpll_192m_d8",
313 "univpll_d3_d8",
314 "univpll_192m_d4",
315 "univpll_d3_d16",
316 "csw_f26m_ck_d2",
317 "univpll_192m_d16",
318 "univpll_192m_d32"
319};
320
321static const char * const camtg2_parents[] = {
322 "clk26m",
323 "univpll_192m_d8",
324 "univpll_d3_d8",
325 "univpll_192m_d4",
326 "univpll_d3_d16",
327 "csw_f26m_ck_d2",
328 "univpll_192m_d16",
329 "univpll_192m_d32"
330};
331
332static const char * const camtg3_parents[] = {
333 "clk26m",
334 "univpll_192m_d8",
335 "univpll_d3_d8",
336 "univpll_192m_d4",
337 "univpll_d3_d16",
338 "csw_f26m_ck_d2",
339 "univpll_192m_d16",
340 "univpll_192m_d32"
341};
342
343static const char * const camtg4_parents[] = {
344 "clk26m",
345 "univpll_192m_d8",
346 "univpll_d3_d8",
347 "univpll_192m_d4",
348 "univpll_d3_d16",
349 "csw_f26m_ck_d2",
350 "univpll_192m_d16",
351 "univpll_192m_d32"
352};
353
354static const char * const uart_parents[] = {
355 "clk26m",
356 "univpll_d3_d8"
357};
358
359static const char * const spi_parents[] = {
360 "clk26m",
361 "mainpll_d5_d2",
362 "mainpll_d3_d4",
363 "msdcpll_d4"
364};
365
366static const char * const msdc50_hclk_parents[] = {
367 "clk26m",
368 "mainpll_d2_d2",
369 "mainpll_d3_d2"
370};
371
372static const char * const msdc50_0_parents[] = {
373 "clk26m",
374 "msdcpll_ck",
375 "msdcpll_d2",
376 "univpll_d2_d4",
377 "mainpll_d3_d2",
378 "univpll_d2_d2"
379};
380
381static const char * const msdc30_1_parents[] = {
382 "clk26m",
383 "univpll_d3_d2",
384 "mainpll_d3_d2",
385 "mainpll_d7",
386 "msdcpll_d2"
387};
388
389static const char * const audio_parents[] = {
390 "clk26m",
391 "mainpll_d5_d4",
392 "mainpll_d7_d4",
393 "mainpll_d2_d16"
394};
395
396static const char * const aud_intbus_parents[] = {
397 "clk26m",
398 "mainpll_d2_d4",
399 "mainpll_d7_d2"
400};
401
402static const char * const fpwrap_ulposc_parents[] = {
403 "osc_d10",
404 "clk26m",
405 "osc_d4",
406 "osc_d8",
407 "osc_d16"
408};
409
410static const char * const atb_parents[] = {
411 "clk26m",
412 "mainpll_d2_d2",
413 "mainpll_d5"
414};
415
416static const char * const sspm_parents[] = {
417 "clk26m",
418 "univpll_d2_d4",
419 "mainpll_d2_d2",
420 "univpll_d2_d2",
421 "mainpll_d3"
422};
423
424static const char * const dpi0_parents[] = {
425 "clk26m",
426 "tvdpll_d2",
427 "tvdpll_d4",
428 "tvdpll_d8",
429 "tvdpll_d16"
430};
431
432static const char * const scam_parents[] = {
433 "clk26m",
434 "mainpll_d5_d2"
435};
436
437static const char * const disppwm_parents[] = {
438 "clk26m",
439 "univpll_d3_d4",
440 "osc_d2",
441 "osc_d4",
442 "osc_d16"
443};
444
445static const char * const usb_top_parents[] = {
446 "clk26m",
447 "univpll_d5_d4",
448 "univpll_d3_d4",
449 "univpll_d5_d2"
450};
451
452static const char * const ssusb_top_xhci_parents[] = {
453 "clk26m",
454 "univpll_d5_d4",
455 "univpll_d3_d4",
456 "univpll_d5_d2"
457};
458
459static const char * const spm_parents[] = {
460 "clk26m",
461 "osc_d8",
462 "mainpll_d2_d8"
463};
464
465static const char * const i2c_parents[] = {
466 "clk26m",
467 "mainpll_d2_d8",
468 "univpll_d5_d2"
469};
470
471static const char * const seninf_parents[] = {
472 "clk26m",
473 "univpll_d7",
474 "univpll_d3_d2",
475 "univpll_d2_d2",
476 "mainpll_d3",
477 "mmpll_d4_d2",
478 "mmpll_d7",
479 "mmpll_d6"
480};
481
482static const char * const seninf1_parents[] = {
483 "clk26m",
484 "univpll_d7",
485 "univpll_d3_d2",
486 "univpll_d2_d2",
487 "mainpll_d3",
488 "mmpll_d4_d2",
489 "mmpll_d7",
490 "mmpll_d6"
491};
492
493static const char * const seninf2_parents[] = {
494 "clk26m",
495 "univpll_d7",
496 "univpll_d3_d2",
497 "univpll_d2_d2",
498 "mainpll_d3",
499 "mmpll_d4_d2",
500 "mmpll_d7",
501 "mmpll_d6"
502};
503
504static const char * const dxcc_parents[] = {
505 "clk26m",
506 "mainpll_d2_d2",
507 "mainpll_d2_d4",
508 "mainpll_d2_d8"
509};
510
511static const char * const aud_engen1_parents[] = {
512 "clk26m",
513 "apll1_d2",
514 "apll1_d4",
515 "apll1_d8"
516};
517
518static const char * const aud_engen2_parents[] = {
519 "clk26m",
520 "apll2_d2",
521 "apll2_d4",
522 "apll2_d8"
523};
524
525static const char * const faes_ufsfde_parents[] = {
526 "clk26m",
527 "mainpll_d2",
528 "mainpll_d2_d2",
529 "mainpll_d3",
530 "mainpll_d2_d4",
531 "univpll_d3"
532};
533
534static const char * const fufs_parents[] = {
535 "clk26m",
536 "mainpll_d2_d4",
537 "mainpll_d2_d8",
538 "mainpll_d2_d16"
539};
540
541static const char * const aud_1_parents[] = {
542 "clk26m",
543 "apll1_ck"
544};
545
546static const char * const aud_2_parents[] = {
547 "clk26m",
548 "apll2_ck"
549};
550
551static const char * const adsp_parents[] = {
552 "clk26m",
553 "mainpll_d3",
554 "univpll_d2_d4",
555 "univpll_d2",
556 "mmpll_d4",
557 "adsppll_d4",
558 "adsppll_d6"
559};
560
561static const char * const dpmaif_parents[] = {
562 "clk26m",
563 "univpll_d2_d4",
564 "mainpll_d3",
565 "mainpll_d2_d2",
566 "univpll_d2_d2",
567 "univpll_d3"
568};
569
570static const char * const venc_parents[] = {
571 "clk26m",
572 "mmpll_d7",
573 "mainpll_d3",
574 "univpll_d2_d2",
575 "mainpll_d2_d2",
576 "univpll_d3",
577 "mmpll_d6",
578 "mainpll_d5",
579 "mainpll_d3_d2",
580 "mmpll_d4_d2",
581 "univpll_d2_d4",
582 "mmpll_d5",
583 "univpll_192m_d2"
584
585};
586
587static const char * const vdec_parents[] = {
588 "clk26m",
589 "univpll_d2_d4",
590 "mainpll_d3",
591 "univpll_d2_d2",
592 "mainpll_d2_d2",
593 "univpll_d3",
594 "univpll_d5",
595 "univpll_d5_d2",
596 "mainpll_d2",
597 "univpll_d2",
598 "univpll_192m_d2"
599};
600
601static const char * const camtm_parents[] = {
602 "clk26m",
603 "univpll_d7",
604 "univpll_d3_d2",
605 "univpll_d2_d2"
606};
607
608static const char * const pwm_parents[] = {
609 "clk26m",
610 "univpll_d2_d8"
611};
612
613static const char * const audio_h_parents[] = {
614 "clk26m",
615 "univpll_d7",
616 "apll1_ck",
617 "apll2_ck"
618};
619
620static const char * const camtg5_parents[] = {
621 "clk26m",
622 "univpll_192m_d8",
623 "univpll_d3_d8",
624 "univpll_192m_d4",
625 "univpll_d3_d16",
626 "csw_f26m_ck_d2",
627 "univpll_192m_d16",
628 "univpll_192m_d32"
629};
630
631/*
632 * CRITICAL CLOCK:
633 * axi_sel is the main bus clock of whole SOC.
634 * spm_sel is the clock of the always-on co-processor.
635 * sspm_sel is the clock of the always-on co-processor.
636 */
637static const struct mtk_mux top_muxes[] = {
638 /* CLK_CFG_0 */
639 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL),
642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
646 /* CLK_CFG_1 */
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
655 /* CLK_CFG_2 */
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
661 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
663 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
664 /* CLK_CFG_3 */
665 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
666 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
667 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
668 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
669 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
670 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
671 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
672 f52m_mfg_parents, 0x50, 0x54, 0x58,
673 24, 2, 31, 0x004, 15),
674 /* CLK_CFG_4 */
675 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
676 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
677 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
678 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
679 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
680 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
681 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
682 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
683 /* CLK_CFG_5 */
684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
685 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
686 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
687 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
688 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
689 msdc50_hclk_parents, 0x70, 0x74, 0x78,
690 16, 2, 23, 0x004, 22),
691 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
692 msdc50_0_parents, 0x70, 0x74, 0x78,
693 24, 3, 31, 0x004, 23),
694 /* CLK_CFG_6 */
695 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
696 msdc30_1_parents, 0x80, 0x84, 0x88,
697 0, 3, 7, 0x004, 24),
698 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
699 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
700 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
701 aud_intbus_parents, 0x80, 0x84, 0x88,
702 16, 2, 23, 0x004, 26),
703 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
704 fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
705 24, 3, 31, 0x004, 27),
706 /* CLK_CFG_7 */
707 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
708 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
709 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
710 0x90, 0x94, 0x98, 8, 3, 15,
711 0x004, 29, CLK_IS_CRITICAL),
712 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
713 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
715 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
716 /* CLK_CFG_8 */
717 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
718 disppwm_parents, 0xa0, 0xa4, 0xa8,
719 0, 3, 7, 0x008, 1),
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
721 usb_top_parents, 0xa0, 0xa4, 0xa8,
722 8, 2, 15, 0x008, 2),
723 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
724 ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
725 16, 2, 23, 0x008, 3),
726 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
727 0xa0, 0xa4, 0xa8, 24, 2, 31,
728 0x008, 4, CLK_IS_CRITICAL),
729 /* CLK_CFG_9 */
730 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
731 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
732 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
733 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
734 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
735 seninf1_parents, 0xb0, 0xb4, 0xb8,
736 16, 2, 23, 0x008, 7),
737 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
738 seninf2_parents, 0xb0, 0xb4, 0xb8,
739 24, 2, 31, 0x008, 8),
740 /* CLK_CFG_10 */
741 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
742 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
743 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
744 aud_engen1_parents, 0xc0, 0xc4, 0xc8,
745 8, 2, 15, 0x008, 10),
746 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
747 aud_engen2_parents, 0xc0, 0xc4, 0xc8,
748 16, 2, 23, 0x008, 11),
749 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
750 faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
751 24, 3, 31,
752 0x008, 12),
753 /* CLK_CFG_11 */
754 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
755 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
757 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
758 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
759 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
761 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
762 /* CLK_CFG_12 */
763 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
764 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
765 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
766 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
767 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
768 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
769 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
770 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
771 /* CLK_CFG_13 */
772 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
773 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
774 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
775 audio_h_parents, 0xf0, 0xf4, 0xf8,
776 8, 2, 15, 0x008, 22),
777 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
778 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
779};
780
781static const char * const i2s0_m_ck_parents[] = {
782 "aud_1_sel",
783 "aud_2_sel"
784};
785
786static const char * const i2s1_m_ck_parents[] = {
787 "aud_1_sel",
788 "aud_2_sel"
789};
790
791static const char * const i2s2_m_ck_parents[] = {
792 "aud_1_sel",
793 "aud_2_sel"
794};
795
796static const char * const i2s3_m_ck_parents[] = {
797 "aud_1_sel",
798 "aud_2_sel"
799};
800
801static const char * const i2s4_m_ck_parents[] = {
802 "aud_1_sel",
803 "aud_2_sel"
804};
805
806static const char * const i2s5_m_ck_parents[] = {
807 "aud_1_sel",
808 "aud_2_sel"
809};
810
811static const struct mtk_composite top_aud_muxes[] = {
812 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
813 0x320, 8, 1),
814 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
815 0x320, 9, 1),
816 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
817 0x320, 10, 1),
818 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
819 0x320, 11, 1),
820 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
821 0x320, 12, 1),
822 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
823 0x328, 20, 1),
824};
825
826static struct mtk_composite top_aud_divs[] = {
827 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
828 0x320, 2, 0x324, 8, 0),
829 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
830 0x320, 3, 0x324, 8, 8),
831 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
832 0x320, 4, 0x324, 8, 16),
833 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
834 0x320, 5, 0x324, 8, 24),
835 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
836 0x320, 6, 0x328, 8, 0),
837 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
838 0x320, 7, 0x328, 8, 8),
839 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
840 0x328, 16, 0x328, 4, 28),
841};
842
843static const struct mtk_gate_regs infra0_cg_regs = {
844 .set_ofs = 0x80,
845 .clr_ofs = 0x84,
846 .sta_ofs = 0x90,
847};
848
849static const struct mtk_gate_regs infra1_cg_regs = {
850 .set_ofs = 0x88,
851 .clr_ofs = 0x8c,
852 .sta_ofs = 0x94,
853};
854
855static const struct mtk_gate_regs infra2_cg_regs = {
856 .set_ofs = 0xa4,
857 .clr_ofs = 0xa8,
858 .sta_ofs = 0xac,
859};
860
861static const struct mtk_gate_regs infra3_cg_regs = {
862 .set_ofs = 0xc0,
863 .clr_ofs = 0xc4,
864 .sta_ofs = 0xc8,
865};
866
867#define GATE_INFRA0(_id, _name, _parent, _shift) \
868 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
869 &mtk_clk_gate_ops_setclr)
870#define GATE_INFRA1(_id, _name, _parent, _shift) \
871 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
872 &mtk_clk_gate_ops_setclr)
873#define GATE_INFRA2(_id, _name, _parent, _shift) \
874 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
875 &mtk_clk_gate_ops_setclr)
876#define GATE_INFRA3(_id, _name, _parent, _shift) \
877 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
878 &mtk_clk_gate_ops_setclr)
879
880static const struct mtk_gate infra_clks[] = {
881 /* INFRA0 */
882 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
883 "axi_sel", 0),
884 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
885 "axi_sel", 1),
886 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
887 "axi_sel", 2),
888 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
889 "axi_sel", 3),
890 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
891 "axi_sel", 4),
892 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
893 "f_f26m_ck", 5),
894 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
895 "axi_sel", 6),
896 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
897 "axi_sel", 8),
898 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
899 "axi_sel", 9),
900 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
901 "axi_sel", 10),
902 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
903 "i2c_sel", 11),
904 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
905 "i2c_sel", 12),
906 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
907 "i2c_sel", 13),
908 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
909 "i2c_sel", 14),
910 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
911 "pwm_sel", 15),
912 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
913 "pwm_sel", 16),
914 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
915 "pwm_sel", 17),
916 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
917 "pwm_sel", 18),
918 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
919 "pwm_sel", 19),
920 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
921 "pwm_sel", 21),
922 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
923 "uart_sel", 23),
924 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
925 "uart_sel", 24),
926 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
927 "uart_sel", 25),
928 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
929 "axi_sel", 27),
930 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
931 "axi_sel", 28),
932 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
933 "axi_sel", 31),
934 /* INFRA1 */
935 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
936 "spi_sel", 1),
937 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
938 "msdc50_hclk_sel", 2),
939 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
940 "axi_sel", 4),
941 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
942 "axi_sel", 5),
943 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
944 "msdc50_0_sel", 6),
945 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
946 "f_f26m_ck", 7),
947 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
948 "axi_sel", 8),
949 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
950 "axi_sel", 9),
951 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
952 "f_f26m_ck", 10),
953 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
954 "axi_sel", 11),
955 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
956 "axi_sel", 12),
957 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
958 "axi_sel", 13),
959 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
960 "f_f26m_ck", 14),
961 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
962 "msdc30_1_sel", 16),
963 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
964 "msdc30_2_sel", 17),
965 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
966 "axi_sel", 18),
967 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
968 "axi_sel", 19),
969 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
970 "axi_sel", 20),
971 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
972 "axi_sel", 23),
973 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
974 "axi_sel", 24),
975 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
976 "axi_sel", 25),
977 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
978 "axi_sel", 26),
979 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
980 "dxcc_sel", 27),
981 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
982 "dxcc_sel", 28),
983 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
984 "axi_sel", 30),
985 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
986 "f_f26m_ck", 31),
987 /* INFRA2 */
988 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
989 "f_f26m_ck", 0),
990 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
991 "usb_top_sel", 1),
992 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
993 "axi_sel", 2),
994 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
995 "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
996 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
997 "spi_sel", 6),
998 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
999 "i2c_sel", 7),
1000 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1001 "f_f26m_ck", 8),
1002 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1003 "spi_sel", 9),
1004 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1005 "spi_sel", 10),
1006 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1007 "fufs_sel", 11),
1008 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1009 "fufs_sel", 12),
1010 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1011 "fufs_sel", 13),
1012 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1013 "axi_sel", 14),
1014 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1015 "axi_sel", 16),
1016 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1017 "axi_sel", 17),
1018 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1019 "i2c_sel", 18),
1020 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1021 "i2c_sel", 19),
1022 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1023 "i2c_sel", 20),
1024 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1025 "i2c_sel", 21),
1026 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1027 "i2c_sel", 22),
1028 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1029 "i2c_sel", 23),
1030 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1031 "i2c_sel", 24),
1032 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1033 "spi_sel", 25),
1034 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1035 "spi_sel", 26),
1036 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1037 "axi_sel", 27),
1038 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1039 "fufs_sel", 28),
1040 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1041 "faes_ufsfde_sel", 29),
1042 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1043 "fufs_sel", 30),
1044 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1045 "ssusb_top_xhci_sel", 31),
1046 /* INFRA3 */
1047 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1048 "msdc50_0_sel", 0),
1049 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1050 "msdc50_0_sel", 1),
1051 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1052 "msdc50_0_sel", 2),
1053 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1054 "f_f26m_ck", 3),
1055 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1056 "f_f26m_ck", 4),
1057 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1058 "axi_sel", 5),
1059 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1060 "i2c_sel", 6),
1061 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1062 "msdc50_hclk_sel", 7),
1063 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1064 "msdc50_hclk_sel", 8),
1065 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1066 "axi_sel", 16),
1067 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1068 "axi_sel", 17),
1069 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1070 "axi_sel", 18),
1071 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1072 "axi_sel", 19),
1073 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1074 "f_f26m_ck", 20),
1075 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1076 "axi_sel", 21),
1077 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1078 "i2c_sel", 22),
1079 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1080 "i2c_sel", 23),
1081 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1082 "msdc50_0_sel", 24),
1083 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1084 "dpmaif_sel", 26),
1085 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1086 "adsp_sel", 27),
1087 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1088 "axi_sel", 28),
1089 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1090 "axi_sel", 29),
1091 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1092 "spi_sel", 30),
1093 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1094 "spi_sel", 31),
1095};
1096
1097static const struct mtk_gate_regs apmixed_cg_regs = {
1098 .set_ofs = 0x20,
1099 .clr_ofs = 0x20,
1100 .sta_ofs = 0x20,
1101};
1102
1103#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1104 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1105 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1106
1107#define GATE_APMIXED(_id, _name, _parent, _shift) \
1108 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1109
1110/*
1111 * CRITICAL CLOCK:
1112 * apmixed_appll26m is the toppest clock gate of all PLLs.
1113 */
1114static const struct mtk_gate apmixed_clks[] = {
1115 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1116 "f_f26m_ck", 4),
1117 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1118 "f_f26m_ck", 5, CLK_IS_CRITICAL),
1119 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1120 "f_f26m_ck", 6),
1121 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1122 "f_f26m_ck", 7),
1123 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1124 "f_f26m_ck", 8),
1125 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1126 "f_f26m_ck", 9),
1127 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1128 "f_f26m_ck", 11),
1129 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1130 "f_f26m_ck", 13),
1131 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1132 "f_f26m_ck", 14),
1133 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1134 "f_f26m_ck", 16),
1135 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1136 "f_f26m_ck", 17),
1137};
1138
1139#define MT6779_PLL_FMAX (3800UL * MHZ)
1140#define MT6779_PLL_FMIN (1500UL * MHZ)
1141
1142#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1143 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1144 _pd_shift, _tuner_reg, _tuner_en_reg, \
1145 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1146 _pcw_chg_reg, _div_table) { \
1147 .id = _id, \
1148 .name = _name, \
1149 .reg = _reg, \
1150 .pwr_reg = _pwr_reg, \
1151 .en_mask = _en_mask, \
1152 .flags = _flags, \
1153 .rst_bar_mask = _rst_bar_mask, \
1154 .fmax = MT6779_PLL_FMAX, \
1155 .fmin = MT6779_PLL_FMIN, \
1156 .pcwbits = _pcwbits, \
1157 .pcwibits = _pcwibits, \
1158 .pd_reg = _pd_reg, \
1159 .pd_shift = _pd_shift, \
1160 .tuner_reg = _tuner_reg, \
1161 .tuner_en_reg = _tuner_en_reg, \
1162 .tuner_en_bit = _tuner_en_bit, \
1163 .pcw_reg = _pcw_reg, \
1164 .pcw_shift = _pcw_shift, \
1165 .pcw_chg_reg = _pcw_chg_reg, \
1166 .div_table = _div_table, \
1167 }
1168
1169#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1170 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1171 _pd_shift, _tuner_reg, _tuner_en_reg, \
1172 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1173 _pcw_chg_reg) \
1174 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1175 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1176 _pd_shift, _tuner_reg, _tuner_en_reg, \
1177 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1178 _pcw_chg_reg, NULL)
1179
1180static const struct mtk_pll_data plls[] = {
1181 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
1182 PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
1183 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
1184 PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
1185 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
1186 PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
1187 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
1188 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
1189 0x0234, 0, 0),
1190 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
1191 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
1192 0, 0, 0, 0x0244, 0, 0),
1193 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
1194 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
1195 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
1196 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
1197 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
1198 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
1199 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
1200 (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
1201 0, 0, 0, 0x02b4, 0, 0),
1202 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
1203 (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
1204 0, 0, 0, 0x0284, 0, 0),
1205 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
1206 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
1207 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
1208 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
1209};
1210
1211static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1212{
1213 struct clk_onecell_data *clk_data;
1214 struct device_node *node = pdev->dev.of_node;
1215
1216 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1217
1218 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1219
1220 mtk_clk_register_gates(node, apmixed_clks,
1221 ARRAY_SIZE(apmixed_clks), clk_data);
1222
1223 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1224}
1225
1226static int clk_mt6779_top_probe(struct platform_device *pdev)
1227{
1228 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 void __iomem *base;
1230 struct clk_onecell_data *clk_data;
1231 struct device_node *node = pdev->dev.of_node;
1232
1233 base = devm_ioremap_resource(&pdev->dev, res);
1234 if (IS_ERR(base))
1235 return PTR_ERR(base);
1236
1237 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1238
1239 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1240 clk_data);
1241
1242 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1243
1244 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1245 node, &mt6779_clk_lock, clk_data);
1246
1247 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1248 base, &mt6779_clk_lock, clk_data);
1249
1250 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1251 base, &mt6779_clk_lock, clk_data);
1252
1253 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1254}
1255
1256static int clk_mt6779_infra_probe(struct platform_device *pdev)
1257{
1258 struct clk_onecell_data *clk_data;
1259 struct device_node *node = pdev->dev.of_node;
1260
1261 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1262
1263 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1264 clk_data);
1265
1266 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1267}
1268
1269static const struct of_device_id of_match_clk_mt6779[] = {
1270 {
1271 .compatible = "mediatek,mt6779-apmixed",
1272 .data = clk_mt6779_apmixed_probe,
1273 }, {
1274 .compatible = "mediatek,mt6779-topckgen",
1275 .data = clk_mt6779_top_probe,
1276 }, {
1277 .compatible = "mediatek,mt6779-infracfg_ao",
1278 .data = clk_mt6779_infra_probe,
1279 }, {
1280 /* sentinel */
1281 }
1282};
1283
1284static int clk_mt6779_probe(struct platform_device *pdev)
1285{
1286 int (*clk_probe)(struct platform_device *pdev);
1287 int r;
1288
1289 clk_probe = of_device_get_match_data(&pdev->dev);
1290 if (!clk_probe)
1291 return -EINVAL;
1292
1293 r = clk_probe(pdev);
1294 if (r)
1295 dev_err(&pdev->dev,
1296 "could not register clock provider: %s: %d\n",
1297 pdev->name, r);
1298
1299 return r;
1300}
1301
1302static struct platform_driver clk_mt6779_drv = {
1303 .probe = clk_mt6779_probe,
1304 .driver = {
1305 .name = "clk-mt6779",
1306 .of_match_table = of_match_clk_mt6779,
1307 },
1308};
1309
1310static int __init clk_mt6779_init(void)
1311{
1312 return platform_driver_register(&clk_mt6779_drv);
1313}
1314
1315arch_initcall(clk_mt6779_init);
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index 99a6b020833e..37b4162c5882 100644
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -5,6 +5,7 @@
5 5
6#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/pm_runtime.h>
8 9
9#include "clk-mtk.h" 10#include "clk-mtk.h"
10#include "clk-gate.h" 11#include "clk-gate.h"
@@ -30,10 +31,12 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
30 struct clk_onecell_data *clk_data; 31 struct clk_onecell_data *clk_data;
31 struct device_node *node = pdev->dev.of_node; 32 struct device_node *node = pdev->dev.of_node;
32 33
34 pm_runtime_enable(&pdev->dev);
35
33 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); 36 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
34 37
35 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), 38 mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
36 clk_data); 39 clk_data, &pdev->dev);
37 40
38 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 41 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
39} 42}
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 73b7e238eee7..51c8d5c9a030 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -17,6 +17,9 @@
17 17
18#include <dt-bindings/clock/mt8183-clk.h> 18#include <dt-bindings/clock/mt8183-clk.h>
19 19
20/* Infra global controller reset set register */
21#define INFRA_RST0_SET_OFFSET 0x120
22
20static DEFINE_SPINLOCK(mt8183_clk_lock); 23static DEFINE_SPINLOCK(mt8183_clk_lock);
21 24
22static const struct mtk_fixed_clk top_fixed_clks[] = { 25static const struct mtk_fixed_clk top_fixed_clks[] = {
@@ -1001,6 +1004,20 @@ static const struct mtk_gate infra_clks[] = {
1001 "msdc50_0_sel", 24), 1004 "msdc50_0_sel", 24),
1002}; 1005};
1003 1006
1007static const struct mtk_gate_regs peri_cg_regs = {
1008 .set_ofs = 0x20c,
1009 .clr_ofs = 0x20c,
1010 .sta_ofs = 0x20c,
1011};
1012
1013#define GATE_PERI(_id, _name, _parent, _shift) \
1014 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
1015 &mtk_clk_gate_ops_no_setclr_inv)
1016
1017static const struct mtk_gate peri_clks[] = {
1018 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
1019};
1020
1004static const struct mtk_gate_regs apmixed_cg_regs = { 1021static const struct mtk_gate_regs apmixed_cg_regs = {
1005 .set_ofs = 0x20, 1022 .set_ofs = 0x20,
1006 .clr_ofs = 0x20, 1023 .clr_ofs = 0x20,
@@ -1207,12 +1224,36 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
1207{ 1224{
1208 struct clk_onecell_data *clk_data; 1225 struct clk_onecell_data *clk_data;
1209 struct device_node *node = pdev->dev.of_node; 1226 struct device_node *node = pdev->dev.of_node;
1227 int r;
1210 1228
1211 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1229 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1212 1230
1213 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1231 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1214 clk_data); 1232 clk_data);
1215 1233
1234 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1235 if (r) {
1236 dev_err(&pdev->dev,
1237 "%s(): could not register clock provider: %d\n",
1238 __func__, r);
1239 return r;
1240 }
1241
1242 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
1243
1244 return r;
1245}
1246
1247static int clk_mt8183_peri_probe(struct platform_device *pdev)
1248{
1249 struct clk_onecell_data *clk_data;
1250 struct device_node *node = pdev->dev.of_node;
1251
1252 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1253
1254 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1255 clk_data);
1256
1216 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1257 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1217} 1258}
1218 1259
@@ -1246,6 +1287,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
1246 .compatible = "mediatek,mt8183-infracfg", 1287 .compatible = "mediatek,mt8183-infracfg",
1247 .data = clk_mt8183_infra_probe, 1288 .data = clk_mt8183_infra_probe,
1248 }, { 1289 }, {
1290 .compatible = "mediatek,mt8183-pericfg",
1291 .data = clk_mt8183_peri_probe,
1292 }, {
1249 .compatible = "mediatek,mt8183-mcucfg", 1293 .compatible = "mediatek,mt8183-mcucfg",
1250 .data = clk_mt8183_mcu_probe, 1294 .data = clk_mt8183_mcu_probe,
1251 }, { 1295 }, {
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index d28790c74919..cec1c8a27211 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -12,6 +12,7 @@
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/mfd/syscon.h> 14#include <linux/mfd/syscon.h>
15#include <linux/device.h>
15 16
16#include "clk-mtk.h" 17#include "clk-mtk.h"
17#include "clk-gate.h" 18#include "clk-gate.h"
@@ -93,9 +94,10 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
93 } 94 }
94} 95}
95 96
96int mtk_clk_register_gates(struct device_node *node, 97int mtk_clk_register_gates_with_dev(struct device_node *node,
97 const struct mtk_gate *clks, 98 const struct mtk_gate *clks,
98 int num, struct clk_onecell_data *clk_data) 99 int num, struct clk_onecell_data *clk_data,
100 struct device *dev)
99{ 101{
100 int i; 102 int i;
101 struct clk *clk; 103 struct clk *clk;
@@ -122,7 +124,7 @@ int mtk_clk_register_gates(struct device_node *node,
122 gate->regs->set_ofs, 124 gate->regs->set_ofs,
123 gate->regs->clr_ofs, 125 gate->regs->clr_ofs,
124 gate->regs->sta_ofs, 126 gate->regs->sta_ofs,
125 gate->shift, gate->ops, gate->flags); 127 gate->shift, gate->ops, gate->flags, dev);
126 128
127 if (IS_ERR(clk)) { 129 if (IS_ERR(clk)) {
128 pr_err("Failed to register clk %s: %ld\n", 130 pr_err("Failed to register clk %s: %ld\n",
@@ -136,6 +138,14 @@ int mtk_clk_register_gates(struct device_node *node,
136 return 0; 138 return 0;
137} 139}
138 140
141int mtk_clk_register_gates(struct device_node *node,
142 const struct mtk_gate *clks,
143 int num, struct clk_onecell_data *clk_data)
144{
145 return mtk_clk_register_gates_with_dev(node,
146 clks, num, clk_data, NULL);
147}
148
139struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 149struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
140 void __iomem *base, spinlock_t *lock) 150 void __iomem *base, spinlock_t *lock)
141{ 151{
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 733a11d1de94..c3d6756b0c7e 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -169,6 +169,11 @@ int mtk_clk_register_gates(struct device_node *node,
169 const struct mtk_gate *clks, int num, 169 const struct mtk_gate *clks, int num,
170 struct clk_onecell_data *clk_data); 170 struct clk_onecell_data *clk_data);
171 171
172int mtk_clk_register_gates_with_dev(struct device_node *node,
173 const struct mtk_gate *clks,
174 int num, struct clk_onecell_data *clk_data,
175 struct device *dev);
176
172struct mtk_clk_divider { 177struct mtk_clk_divider {
173 int id; 178 int id;
174 const char *name; 179 const char *name;
@@ -240,4 +245,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
240void mtk_register_reset_controller(struct device_node *np, 245void mtk_register_reset_controller(struct device_node *np,
241 unsigned int num_regs, int regofs); 246 unsigned int num_regs, int regofs);
242 247
248void mtk_register_reset_controller_set_clr(struct device_node *np,
249 unsigned int num_regs, int regofs);
250
243#endif /* __DRV_CLK_MTK_H */ 251#endif /* __DRV_CLK_MTK_H */
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index d8376b92349e..cb939c071b0c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -19,6 +19,24 @@ struct mtk_reset {
19 struct reset_controller_dev rcdev; 19 struct reset_controller_dev rcdev;
20}; 20};
21 21
22static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
23 unsigned long id)
24{
25 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
26 unsigned int reg = data->regofs + ((id / 32) << 4);
27
28 return regmap_write(data->regmap, reg, 1);
29}
30
31static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
32 unsigned long id)
33{
34 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
35 unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
36
37 return regmap_write(data->regmap, reg, 1);
38}
39
22static int mtk_reset_assert(struct reset_controller_dev *rcdev, 40static int mtk_reset_assert(struct reset_controller_dev *rcdev,
23 unsigned long id) 41 unsigned long id)
24{ 42{
@@ -49,14 +67,32 @@ static int mtk_reset(struct reset_controller_dev *rcdev,
49 return mtk_reset_deassert(rcdev, id); 67 return mtk_reset_deassert(rcdev, id);
50} 68}
51 69
70static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
71 unsigned long id)
72{
73 int ret;
74
75 ret = mtk_reset_assert_set_clr(rcdev, id);
76 if (ret)
77 return ret;
78 return mtk_reset_deassert_set_clr(rcdev, id);
79}
80
52static const struct reset_control_ops mtk_reset_ops = { 81static const struct reset_control_ops mtk_reset_ops = {
53 .assert = mtk_reset_assert, 82 .assert = mtk_reset_assert,
54 .deassert = mtk_reset_deassert, 83 .deassert = mtk_reset_deassert,
55 .reset = mtk_reset, 84 .reset = mtk_reset,
56}; 85};
57 86
58void mtk_register_reset_controller(struct device_node *np, 87static const struct reset_control_ops mtk_reset_ops_set_clr = {
59 unsigned int num_regs, int regofs) 88 .assert = mtk_reset_assert_set_clr,
89 .deassert = mtk_reset_deassert_set_clr,
90 .reset = mtk_reset_set_clr,
91};
92
93static void mtk_register_reset_controller_common(struct device_node *np,
94 unsigned int num_regs, int regofs,
95 const struct reset_control_ops *reset_ops)
60{ 96{
61 struct mtk_reset *data; 97 struct mtk_reset *data;
62 int ret; 98 int ret;
@@ -77,7 +113,7 @@ void mtk_register_reset_controller(struct device_node *np,
77 data->regofs = regofs; 113 data->regofs = regofs;
78 data->rcdev.owner = THIS_MODULE; 114 data->rcdev.owner = THIS_MODULE;
79 data->rcdev.nr_resets = num_regs * 32; 115 data->rcdev.nr_resets = num_regs * 32;
80 data->rcdev.ops = &mtk_reset_ops; 116 data->rcdev.ops = reset_ops;
81 data->rcdev.of_node = np; 117 data->rcdev.of_node = np;
82 118
83 ret = reset_controller_register(&data->rcdev); 119 ret = reset_controller_register(&data->rcdev);
@@ -87,3 +123,17 @@ void mtk_register_reset_controller(struct device_node *np,
87 return; 123 return;
88 } 124 }
89} 125}
126
127void mtk_register_reset_controller(struct device_node *np,
128 unsigned int num_regs, int regofs)
129{
130 mtk_register_reset_controller_common(np, num_regs, regofs,
131 &mtk_reset_ops);
132}
133
134void mtk_register_reset_controller_set_clr(struct device_node *np,
135 unsigned int num_regs, int regofs)
136{
137 mtk_register_reset_controller_common(np, num_regs, regofs,
138 &mtk_reset_ops_set_clr);
139}
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 741df7e955ca..18b23cdf679c 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -12,6 +12,7 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/regmap.h> 13#include <linux/regmap.h>
14#include <linux/reset.h> 14#include <linux/reset.h>
15#include <linux/reset-controller.h>
15#include <linux/slab.h> 16#include <linux/slab.h>
16 17
17#include "axg-audio.h" 18#include "axg-audio.h"
@@ -918,6 +919,84 @@ static int devm_clk_get_enable(struct device *dev, char *id)
918 return 0; 919 return 0;
919} 920}
920 921
922struct axg_audio_reset_data {
923 struct reset_controller_dev rstc;
924 struct regmap *map;
925 unsigned int offset;
926};
927
928static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
929 unsigned long id,
930 unsigned int *reg,
931 unsigned int *bit)
932{
933 unsigned int stride = regmap_get_reg_stride(rst->map);
934
935 *reg = (id / (stride * BITS_PER_BYTE)) * stride;
936 *reg += rst->offset;
937 *bit = id % (stride * BITS_PER_BYTE);
938}
939
940static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
941 unsigned long id, bool assert)
942{
943 struct axg_audio_reset_data *rst =
944 container_of(rcdev, struct axg_audio_reset_data, rstc);
945 unsigned int offset, bit;
946
947 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
948
949 regmap_update_bits(rst->map, offset, BIT(bit),
950 assert ? BIT(bit) : 0);
951
952 return 0;
953}
954
955static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
956 unsigned long id)
957{
958 struct axg_audio_reset_data *rst =
959 container_of(rcdev, struct axg_audio_reset_data, rstc);
960 unsigned int val, offset, bit;
961
962 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
963
964 regmap_read(rst->map, offset, &val);
965
966 return !!(val & BIT(bit));
967}
968
969static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
970 unsigned long id)
971{
972 return axg_audio_reset_update(rcdev, id, true);
973}
974
975static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
976 unsigned long id)
977{
978 return axg_audio_reset_update(rcdev, id, false);
979}
980
981static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
982 unsigned long id)
983{
984 int ret;
985
986 ret = axg_audio_reset_assert(rcdev, id);
987 if (ret)
988 return ret;
989
990 return axg_audio_reset_deassert(rcdev, id);
991}
992
993static const struct reset_control_ops axg_audio_rstc_ops = {
994 .assert = axg_audio_reset_assert,
995 .deassert = axg_audio_reset_deassert,
996 .reset = axg_audio_reset_toggle,
997 .status = axg_audio_reset_status,
998};
999
921static const struct regmap_config axg_audio_regmap_cfg = { 1000static const struct regmap_config axg_audio_regmap_cfg = {
922 .reg_bits = 32, 1001 .reg_bits = 32,
923 .val_bits = 32, 1002 .val_bits = 32,
@@ -927,12 +1006,15 @@ static const struct regmap_config axg_audio_regmap_cfg = {
927 1006
928struct audioclk_data { 1007struct audioclk_data {
929 struct clk_hw_onecell_data *hw_onecell_data; 1008 struct clk_hw_onecell_data *hw_onecell_data;
1009 unsigned int reset_offset;
1010 unsigned int reset_num;
930}; 1011};
931 1012
932static int axg_audio_clkc_probe(struct platform_device *pdev) 1013static int axg_audio_clkc_probe(struct platform_device *pdev)
933{ 1014{
934 struct device *dev = &pdev->dev; 1015 struct device *dev = &pdev->dev;
935 const struct audioclk_data *data; 1016 const struct audioclk_data *data;
1017 struct axg_audio_reset_data *rst;
936 struct regmap *map; 1018 struct regmap *map;
937 struct resource *res; 1019 struct resource *res;
938 void __iomem *regs; 1020 void __iomem *regs;
@@ -971,21 +1053,43 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
971 1053
972 /* Take care to skip the registered input clocks */ 1054 /* Take care to skip the registered input clocks */
973 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) { 1055 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1056 const char *name;
1057
974 hw = data->hw_onecell_data->hws[i]; 1058 hw = data->hw_onecell_data->hws[i];
975 /* array might be sparse */ 1059 /* array might be sparse */
976 if (!hw) 1060 if (!hw)
977 continue; 1061 continue;
978 1062
1063 name = hw->init->name;
1064
979 ret = devm_clk_hw_register(dev, hw); 1065 ret = devm_clk_hw_register(dev, hw);
980 if (ret) { 1066 if (ret) {
981 dev_err(dev, "failed to register clock %s\n", 1067 dev_err(dev, "failed to register clock %s\n", name);
982 hw->init->name);
983 return ret; 1068 return ret;
984 } 1069 }
985 } 1070 }
986 1071
987 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1072 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
988 data->hw_onecell_data); 1073 data->hw_onecell_data);
1074 if (ret)
1075 return ret;
1076
1077 /* Stop here if there is no reset */
1078 if (!data->reset_num)
1079 return 0;
1080
1081 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1082 if (!rst)
1083 return -ENOMEM;
1084
1085 rst->map = map;
1086 rst->offset = data->reset_offset;
1087 rst->rstc.nr_resets = data->reset_num;
1088 rst->rstc.ops = &axg_audio_rstc_ops;
1089 rst->rstc.of_node = dev->of_node;
1090 rst->rstc.owner = THIS_MODULE;
1091
1092 return devm_reset_controller_register(dev, &rst->rstc);
989} 1093}
990 1094
991static const struct audioclk_data axg_audioclk_data = { 1095static const struct audioclk_data axg_audioclk_data = {
@@ -994,6 +1098,8 @@ static const struct audioclk_data axg_audioclk_data = {
994 1098
995static const struct audioclk_data g12a_audioclk_data = { 1099static const struct audioclk_data g12a_audioclk_data = {
996 .hw_onecell_data = &g12a_audio_hw_onecell_data, 1100 .hw_onecell_data = &g12a_audio_hw_onecell_data,
1101 .reset_offset = AUDIO_SW_RESET,
1102 .reset_num = 26,
997}; 1103};
998 1104
999static const struct of_device_id clkc_match_table[] = { 1105static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index 5d972d55d6c7..c00e28b2e1a9 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -22,6 +22,7 @@
22#define AUDIO_MCLK_F_CTRL 0x018 22#define AUDIO_MCLK_F_CTRL 0x018
23#define AUDIO_MST_PAD_CTRL0 0x01c 23#define AUDIO_MST_PAD_CTRL0 0x01c
24#define AUDIO_MST_PAD_CTRL1 0x020 24#define AUDIO_MST_PAD_CTRL1 0x020
25#define AUDIO_SW_RESET 0x024
25#define AUDIO_MST_A_SCLK_CTRL0 0x040 26#define AUDIO_MST_A_SCLK_CTRL0 0x040
26#define AUDIO_MST_A_SCLK_CTRL1 0x044 27#define AUDIO_MST_A_SCLK_CTRL1 0x044
27#define AUDIO_MST_B_SCLK_CTRL0 0x048 28#define AUDIO_MST_B_SCLK_CTRL0 0x048
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index c3f0ffc3280d..ea4c791f106d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -676,6 +676,226 @@ static struct clk_regmap g12b_cpub_clk = {
676 }, 676 },
677}; 677};
678 678
679static struct clk_regmap sm1_gp1_pll;
680
681/* Datasheet names this field as "premux0" */
682static struct clk_regmap sm1_dsu_clk_premux0 = {
683 .data = &(struct clk_regmap_mux_data){
684 .offset = HHI_SYS_CPU_CLK_CNTL5,
685 .mask = 0x3,
686 .shift = 0,
687 },
688 .hw.init = &(struct clk_init_data){
689 .name = "dsu_clk_dyn0_sel",
690 .ops = &clk_regmap_mux_ro_ops,
691 .parent_data = (const struct clk_parent_data []) {
692 { .fw_name = "xtal", },
693 { .hw = &g12a_fclk_div2.hw },
694 { .hw = &g12a_fclk_div3.hw },
695 { .hw = &sm1_gp1_pll.hw },
696 },
697 .num_parents = 4,
698 },
699};
700
701/* Datasheet names this field as "premux1" */
702static struct clk_regmap sm1_dsu_clk_premux1 = {
703 .data = &(struct clk_regmap_mux_data){
704 .offset = HHI_SYS_CPU_CLK_CNTL5,
705 .mask = 0x3,
706 .shift = 16,
707 },
708 .hw.init = &(struct clk_init_data){
709 .name = "dsu_clk_dyn1_sel",
710 .ops = &clk_regmap_mux_ro_ops,
711 .parent_data = (const struct clk_parent_data []) {
712 { .fw_name = "xtal", },
713 { .hw = &g12a_fclk_div2.hw },
714 { .hw = &g12a_fclk_div3.hw },
715 { .hw = &sm1_gp1_pll.hw },
716 },
717 .num_parents = 4,
718 },
719};
720
721/* Datasheet names this field as "Mux0_divn_tcnt" */
722static struct clk_regmap sm1_dsu_clk_mux0_div = {
723 .data = &(struct clk_regmap_div_data){
724 .offset = HHI_SYS_CPU_CLK_CNTL5,
725 .shift = 4,
726 .width = 6,
727 },
728 .hw.init = &(struct clk_init_data){
729 .name = "dsu_clk_dyn0_div",
730 .ops = &clk_regmap_divider_ro_ops,
731 .parent_hws = (const struct clk_hw *[]) {
732 &sm1_dsu_clk_premux0.hw
733 },
734 .num_parents = 1,
735 },
736};
737
738/* Datasheet names this field as "postmux0" */
739static struct clk_regmap sm1_dsu_clk_postmux0 = {
740 .data = &(struct clk_regmap_mux_data){
741 .offset = HHI_SYS_CPU_CLK_CNTL5,
742 .mask = 0x1,
743 .shift = 2,
744 },
745 .hw.init = &(struct clk_init_data){
746 .name = "dsu_clk_dyn0",
747 .ops = &clk_regmap_mux_ro_ops,
748 .parent_hws = (const struct clk_hw *[]) {
749 &sm1_dsu_clk_premux0.hw,
750 &sm1_dsu_clk_mux0_div.hw,
751 },
752 .num_parents = 2,
753 },
754};
755
756/* Datasheet names this field as "Mux1_divn_tcnt" */
757static struct clk_regmap sm1_dsu_clk_mux1_div = {
758 .data = &(struct clk_regmap_div_data){
759 .offset = HHI_SYS_CPU_CLK_CNTL5,
760 .shift = 20,
761 .width = 6,
762 },
763 .hw.init = &(struct clk_init_data){
764 .name = "dsu_clk_dyn1_div",
765 .ops = &clk_regmap_divider_ro_ops,
766 .parent_hws = (const struct clk_hw *[]) {
767 &sm1_dsu_clk_premux1.hw
768 },
769 .num_parents = 1,
770 },
771};
772
773/* Datasheet names this field as "postmux1" */
774static struct clk_regmap sm1_dsu_clk_postmux1 = {
775 .data = &(struct clk_regmap_mux_data){
776 .offset = HHI_SYS_CPU_CLK_CNTL5,
777 .mask = 0x1,
778 .shift = 18,
779 },
780 .hw.init = &(struct clk_init_data){
781 .name = "dsu_clk_dyn1",
782 .ops = &clk_regmap_mux_ro_ops,
783 .parent_hws = (const struct clk_hw *[]) {
784 &sm1_dsu_clk_premux1.hw,
785 &sm1_dsu_clk_mux1_div.hw,
786 },
787 .num_parents = 2,
788 },
789};
790
791/* Datasheet names this field as "Final_dyn_mux_sel" */
792static struct clk_regmap sm1_dsu_clk_dyn = {
793 .data = &(struct clk_regmap_mux_data){
794 .offset = HHI_SYS_CPU_CLK_CNTL5,
795 .mask = 0x1,
796 .shift = 10,
797 },
798 .hw.init = &(struct clk_init_data){
799 .name = "dsu_clk_dyn",
800 .ops = &clk_regmap_mux_ro_ops,
801 .parent_hws = (const struct clk_hw *[]) {
802 &sm1_dsu_clk_postmux0.hw,
803 &sm1_dsu_clk_postmux1.hw,
804 },
805 .num_parents = 2,
806 },
807};
808
809/* Datasheet names this field as "Final_mux_sel" */
810static struct clk_regmap sm1_dsu_final_clk = {
811 .data = &(struct clk_regmap_mux_data){
812 .offset = HHI_SYS_CPU_CLK_CNTL5,
813 .mask = 0x1,
814 .shift = 11,
815 },
816 .hw.init = &(struct clk_init_data){
817 .name = "dsu_clk_final",
818 .ops = &clk_regmap_mux_ro_ops,
819 .parent_hws = (const struct clk_hw *[]) {
820 &sm1_dsu_clk_dyn.hw,
821 &g12a_sys_pll.hw,
822 },
823 .num_parents = 2,
824 },
825};
826
827/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
828static struct clk_regmap sm1_cpu1_clk = {
829 .data = &(struct clk_regmap_mux_data){
830 .offset = HHI_SYS_CPU_CLK_CNTL6,
831 .mask = 0x1,
832 .shift = 24,
833 },
834 .hw.init = &(struct clk_init_data){
835 .name = "cpu1_clk",
836 .ops = &clk_regmap_mux_ro_ops,
837 .parent_hws = (const struct clk_hw *[]) {
838 &g12a_cpu_clk.hw,
839 /* This CPU also have a dedicated clock tree */
840 },
841 .num_parents = 1,
842 },
843};
844
845/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
846static struct clk_regmap sm1_cpu2_clk = {
847 .data = &(struct clk_regmap_mux_data){
848 .offset = HHI_SYS_CPU_CLK_CNTL6,
849 .mask = 0x1,
850 .shift = 25,
851 },
852 .hw.init = &(struct clk_init_data){
853 .name = "cpu2_clk",
854 .ops = &clk_regmap_mux_ro_ops,
855 .parent_hws = (const struct clk_hw *[]) {
856 &g12a_cpu_clk.hw,
857 /* This CPU also have a dedicated clock tree */
858 },
859 .num_parents = 1,
860 },
861};
862
863/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
864static struct clk_regmap sm1_cpu3_clk = {
865 .data = &(struct clk_regmap_mux_data){
866 .offset = HHI_SYS_CPU_CLK_CNTL6,
867 .mask = 0x1,
868 .shift = 26,
869 },
870 .hw.init = &(struct clk_init_data){
871 .name = "cpu3_clk",
872 .ops = &clk_regmap_mux_ro_ops,
873 .parent_hws = (const struct clk_hw *[]) {
874 &g12a_cpu_clk.hw,
875 /* This CPU also have a dedicated clock tree */
876 },
877 .num_parents = 1,
878 },
879};
880
881/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
882static struct clk_regmap sm1_dsu_clk = {
883 .data = &(struct clk_regmap_mux_data){
884 .offset = HHI_SYS_CPU_CLK_CNTL6,
885 .mask = 0x1,
886 .shift = 27,
887 },
888 .hw.init = &(struct clk_init_data){
889 .name = "dsu_clk",
890 .ops = &clk_regmap_mux_ro_ops,
891 .parent_hws = (const struct clk_hw *[]) {
892 &g12a_cpu_clk.hw,
893 &sm1_dsu_final_clk.hw,
894 },
895 .num_parents = 2,
896 },
897};
898
679static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb, 899static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
680 unsigned long event, void *data) 900 unsigned long event, void *data)
681{ 901{
@@ -1443,6 +1663,69 @@ static struct clk_regmap g12a_gp0_pll = {
1443 }, 1663 },
1444}; 1664};
1445 1665
1666static struct clk_regmap sm1_gp1_pll_dco = {
1667 .data = &(struct meson_clk_pll_data){
1668 .en = {
1669 .reg_off = HHI_GP1_PLL_CNTL0,
1670 .shift = 28,
1671 .width = 1,
1672 },
1673 .m = {
1674 .reg_off = HHI_GP1_PLL_CNTL0,
1675 .shift = 0,
1676 .width = 8,
1677 },
1678 .n = {
1679 .reg_off = HHI_GP1_PLL_CNTL0,
1680 .shift = 10,
1681 .width = 5,
1682 },
1683 .frac = {
1684 .reg_off = HHI_GP1_PLL_CNTL1,
1685 .shift = 0,
1686 .width = 17,
1687 },
1688 .l = {
1689 .reg_off = HHI_GP1_PLL_CNTL0,
1690 .shift = 31,
1691 .width = 1,
1692 },
1693 .rst = {
1694 .reg_off = HHI_GP1_PLL_CNTL0,
1695 .shift = 29,
1696 .width = 1,
1697 },
1698 },
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gp1_pll_dco",
1701 .ops = &meson_clk_pll_ro_ops,
1702 .parent_data = &(const struct clk_parent_data) {
1703 .fw_name = "xtal",
1704 },
1705 .num_parents = 1,
1706 /* This clock feeds the DSU, avoid disabling it */
1707 .flags = CLK_IS_CRITICAL,
1708 },
1709};
1710
1711static struct clk_regmap sm1_gp1_pll = {
1712 .data = &(struct clk_regmap_div_data){
1713 .offset = HHI_GP1_PLL_CNTL0,
1714 .shift = 16,
1715 .width = 3,
1716 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1717 CLK_DIVIDER_ROUND_CLOSEST),
1718 },
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gp1_pll",
1721 .ops = &clk_regmap_divider_ro_ops,
1722 .parent_hws = (const struct clk_hw *[]) {
1723 &sm1_gp1_pll_dco.hw
1724 },
1725 .num_parents = 1,
1726 },
1727};
1728
1446/* 1729/*
1447 * Internal hifi pll emulation configuration parameters 1730 * Internal hifi pll emulation configuration parameters
1448 */ 1731 */
@@ -4121,6 +4404,240 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
4121 .num = NR_CLKS, 4404 .num = NR_CLKS,
4122}; 4405};
4123 4406
4407static struct clk_hw_onecell_data sm1_hw_onecell_data = {
4408 .hws = {
4409 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4410 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4411 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4412 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4413 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4414 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4415 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4416 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4417 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4418 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4419 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4420 [CLKID_CLK81] = &g12a_clk81.hw,
4421 [CLKID_MPLL0] = &g12a_mpll0.hw,
4422 [CLKID_MPLL1] = &g12a_mpll1.hw,
4423 [CLKID_MPLL2] = &g12a_mpll2.hw,
4424 [CLKID_MPLL3] = &g12a_mpll3.hw,
4425 [CLKID_DDR] = &g12a_ddr.hw,
4426 [CLKID_DOS] = &g12a_dos.hw,
4427 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4428 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4429 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4430 [CLKID_ISA] = &g12a_isa.hw,
4431 [CLKID_PL301] = &g12a_pl301.hw,
4432 [CLKID_PERIPHS] = &g12a_periphs.hw,
4433 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4434 [CLKID_I2C] = &g12a_i2c.hw,
4435 [CLKID_SANA] = &g12a_sana.hw,
4436 [CLKID_SD] = &g12a_sd.hw,
4437 [CLKID_RNG0] = &g12a_rng0.hw,
4438 [CLKID_UART0] = &g12a_uart0.hw,
4439 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4440 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4441 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4442 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4443 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4444 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4445 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4446 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4447 [CLKID_AUDIO] = &g12a_audio.hw,
4448 [CLKID_ETH] = &g12a_eth_core.hw,
4449 [CLKID_DEMUX] = &g12a_demux.hw,
4450 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4451 [CLKID_ADC] = &g12a_adc.hw,
4452 [CLKID_UART1] = &g12a_uart1.hw,
4453 [CLKID_G2D] = &g12a_g2d.hw,
4454 [CLKID_RESET] = &g12a_reset.hw,
4455 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4456 [CLKID_PARSER] = &g12a_parser.hw,
4457 [CLKID_USB] = &g12a_usb_general.hw,
4458 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4459 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4460 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4461 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4462 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4463 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4464 [CLKID_BT656] = &g12a_bt656.hw,
4465 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4466 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4467 [CLKID_UART2] = &g12a_uart2.hw,
4468 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4469 [CLKID_GIC] = &g12a_gic.hw,
4470 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4471 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4472 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4473 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4474 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4475 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4476 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4477 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4478 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4479 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4480 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4481 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4482 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4483 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4484 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4485 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4486 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4487 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4488 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4489 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4490 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4491 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4492 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4493 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4494 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4495 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4496 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4497 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4498 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4499 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4500 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4501 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4502 [CLKID_ENC480P] = &g12a_enc480p.hw,
4503 [CLKID_RNG1] = &g12a_rng1.hw,
4504 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4505 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4506 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4507 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4508 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4509 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4510 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4511 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4512 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4513 [CLKID_DMA] = &g12a_dma.hw,
4514 [CLKID_EFUSE] = &g12a_efuse.hw,
4515 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4516 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4517 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4518 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4519 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4520 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4521 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4522 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4523 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4524 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4525 [CLKID_VPU] = &g12a_vpu.hw,
4526 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4527 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4528 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4529 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4530 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4531 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4532 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4533 [CLKID_VAPB] = &g12a_vapb.hw,
4534 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4535 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4536 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4537 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4538 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4539 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4540 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4541 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4542 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4543 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4544 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4545 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4546 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4547 [CLKID_VCLK] = &g12a_vclk.hw,
4548 [CLKID_VCLK2] = &g12a_vclk2.hw,
4549 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4550 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4551 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4552 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4553 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4554 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4555 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4556 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4557 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4558 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4559 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4560 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4561 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4562 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4563 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4564 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4565 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4566 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4567 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4568 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4569 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4570 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4571 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4572 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4573 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4574 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4575 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4576 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4577 [CLKID_HDMI] = &g12a_hdmi.hw,
4578 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4579 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4580 [CLKID_MALI_0] = &g12a_mali_0.hw,
4581 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4582 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4583 [CLKID_MALI_1] = &g12a_mali_1.hw,
4584 [CLKID_MALI] = &g12a_mali.hw,
4585 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4586 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4587 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4588 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4589 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4590 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4591 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4592 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4593 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4594 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4595 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4596 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4597 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4598 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4599 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4600 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4601 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4602 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4603 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4604 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4605 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4606 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4607 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4608 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4609 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4610 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4611 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4612 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4613 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4614 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4615 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4616 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4617 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4618 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4619 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4620 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4621 [CLKID_TS] = &g12a_ts.hw,
4622 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4623 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4624 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4625 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4626 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4627 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4628 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4629 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4630 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4631 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4632 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4633 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4634 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4635 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4636 [NR_CLKS] = NULL,
4637 },
4638 .num = NR_CLKS,
4639};
4640
4124/* Convenience table to populate regmap in .probe */ 4641/* Convenience table to populate regmap in .probe */
4125static struct clk_regmap *const g12a_clk_regmaps[] = { 4642static struct clk_regmap *const g12a_clk_regmaps[] = {
4126 &g12a_clk81, 4643 &g12a_clk81,
@@ -4336,6 +4853,20 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
4336 &g12b_cpub_clk_axi, 4853 &g12b_cpub_clk_axi,
4337 &g12b_cpub_clk_trace_sel, 4854 &g12b_cpub_clk_trace_sel,
4338 &g12b_cpub_clk_trace, 4855 &g12b_cpub_clk_trace,
4856 &sm1_gp1_pll_dco,
4857 &sm1_gp1_pll,
4858 &sm1_dsu_clk_premux0,
4859 &sm1_dsu_clk_premux1,
4860 &sm1_dsu_clk_mux0_div,
4861 &sm1_dsu_clk_postmux0,
4862 &sm1_dsu_clk_mux1_div,
4863 &sm1_dsu_clk_postmux1,
4864 &sm1_dsu_clk_dyn,
4865 &sm1_dsu_final_clk,
4866 &sm1_dsu_clk,
4867 &sm1_cpu1_clk,
4868 &sm1_cpu2_clk,
4869 &sm1_cpu3_clk,
4339}; 4870};
4340 4871
4341static const struct reg_sequence g12a_init_regs[] = { 4872static const struct reg_sequence g12a_init_regs[] = {
@@ -4532,6 +5063,15 @@ static const struct meson_g12a_data g12b_clkc_data = {
4532 .dvfs_setup = meson_g12b_dvfs_setup, 5063 .dvfs_setup = meson_g12b_dvfs_setup,
4533}; 5064};
4534 5065
5066static const struct meson_g12a_data sm1_clkc_data = {
5067 .eeclkc_data = {
5068 .regmap_clks = g12a_clk_regmaps,
5069 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5070 .hw_onecell_data = &sm1_hw_onecell_data,
5071 },
5072 .dvfs_setup = meson_g12a_dvfs_setup,
5073};
5074
4535static const struct of_device_id clkc_match_table[] = { 5075static const struct of_device_id clkc_match_table[] = {
4536 { 5076 {
4537 .compatible = "amlogic,g12a-clkc", 5077 .compatible = "amlogic,g12a-clkc",
@@ -4541,6 +5081,10 @@ static const struct of_device_id clkc_match_table[] = {
4541 .compatible = "amlogic,g12b-clkc", 5081 .compatible = "amlogic,g12b-clkc",
4542 .data = &g12b_clkc_data.eeclkc_data 5082 .data = &g12b_clkc_data.eeclkc_data
4543 }, 5083 },
5084 {
5085 .compatible = "amlogic,sm1-clkc",
5086 .data = &sm1_clkc_data.eeclkc_data
5087 },
4544 {} 5088 {}
4545}; 5089};
4546 5090
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 559a34cfdfeb..9df4068aced1 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -29,6 +29,14 @@
29#define HHI_GP0_PLL_CNTL5 0x054 29#define HHI_GP0_PLL_CNTL5 0x054
30#define HHI_GP0_PLL_CNTL6 0x058 30#define HHI_GP0_PLL_CNTL6 0x058
31#define HHI_GP0_PLL_STS 0x05C 31#define HHI_GP0_PLL_STS 0x05C
32#define HHI_GP1_PLL_CNTL0 0x060
33#define HHI_GP1_PLL_CNTL1 0x064
34#define HHI_GP1_PLL_CNTL2 0x068
35#define HHI_GP1_PLL_CNTL3 0x06C
36#define HHI_GP1_PLL_CNTL4 0x070
37#define HHI_GP1_PLL_CNTL5 0x074
38#define HHI_GP1_PLL_CNTL6 0x078
39#define HHI_GP1_PLL_STS 0x07C
32#define HHI_PCIE_PLL_CNTL0 0x098 40#define HHI_PCIE_PLL_CNTL0 0x098
33#define HHI_PCIE_PLL_CNTL1 0x09C 41#define HHI_PCIE_PLL_CNTL1 0x09C
34#define HHI_PCIE_PLL_CNTL2 0x0A0 42#define HHI_PCIE_PLL_CNTL2 0x0A0
@@ -72,6 +80,11 @@
72#define HHI_SYS_CPUB_CLK_CNTL1 0x200 80#define HHI_SYS_CPUB_CLK_CNTL1 0x200
73#define HHI_SYS_CPUB_CLK_CNTL 0x208 81#define HHI_SYS_CPUB_CLK_CNTL 0x208
74#define HHI_VPU_CLKB_CNTL 0x20C 82#define HHI_VPU_CLKB_CNTL 0x20C
83#define HHI_SYS_CPU_CLK_CNTL2 0x210
84#define HHI_SYS_CPU_CLK_CNTL3 0x214
85#define HHI_SYS_CPU_CLK_CNTL4 0x218
86#define HHI_SYS_CPU_CLK_CNTL5 0x21c
87#define HHI_SYS_CPU_CLK_CNTL6 0x220
75#define HHI_GEN_CLK_CNTL 0x228 88#define HHI_GEN_CLK_CNTL 0x228
76#define HHI_VDIN_MEAS_CLK_CNTL 0x250 89#define HHI_VDIN_MEAS_CLK_CNTL 0x250
77#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 90#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
@@ -233,8 +246,17 @@
233#define CLKID_CPUB_CLK_AXI 239 246#define CLKID_CPUB_CLK_AXI 239
234#define CLKID_CPUB_CLK_TRACE_SEL 240 247#define CLKID_CPUB_CLK_TRACE_SEL 240
235#define CLKID_CPUB_CLK_TRACE 241 248#define CLKID_CPUB_CLK_TRACE 241
249#define CLKID_GP1_PLL_DCO 242
250#define CLKID_DSU_CLK_DYN0_SEL 244
251#define CLKID_DSU_CLK_DYN0_DIV 245
252#define CLKID_DSU_CLK_DYN0 246
253#define CLKID_DSU_CLK_DYN1_SEL 247
254#define CLKID_DSU_CLK_DYN1_DIV 248
255#define CLKID_DSU_CLK_DYN1 249
256#define CLKID_DSU_CLK_DYN 250
257#define CLKID_DSU_CLK_FINAL 251
236 258
237#define NR_CLKS 242 259#define NR_CLKS 256
238 260
239/* include the CLKIDs that have been made part of the DT binding */ 261/* include the CLKIDs that have been made part of the DT binding */
240#include <dt-bindings/clock/g12a-clkc.h> 262#include <dt-bindings/clock/g12a-clkc.h>
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index b09f6ded0a30..415e6906a113 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -8,6 +8,9 @@ config MVEBU_CLK_CPU
8config MVEBU_CLK_COREDIV 8config MVEBU_CLK_COREDIV
9 bool 9 bool
10 10
11config ARMADA_AP_CP_HELPER
12 bool
13
11config ARMADA_370_CLK 14config ARMADA_370_CLK
12 bool 15 bool
13 select MVEBU_CLK_COMMON 16 select MVEBU_CLK_COMMON
@@ -35,9 +38,14 @@ config ARMADA_XP_CLK
35 38
36config ARMADA_AP806_SYSCON 39config ARMADA_AP806_SYSCON
37 bool 40 bool
41 select ARMADA_AP_CP_HELPER
42
43config ARMADA_AP_CPU_CLK
44 bool
38 45
39config ARMADA_CP110_SYSCON 46config ARMADA_CP110_SYSCON
40 bool 47 bool
48 select ARMADA_AP_CP_HELPER
41 49
42config DOVE_CLK 50config DOVE_CLK
43 bool 51 bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 93ac3685271f..04464cef0f06 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,6 +2,7 @@
2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o 2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o 3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o 4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
5obj-$(CONFIG_ARMADA_AP_CP_HELPER) += armada_ap_cp_helper.o
5 6
6obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o 7obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
7obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o 8obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o
12obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o 13obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o
13obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o 14obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o
14obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o 15obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
16obj-$(CONFIG_ARMADA_AP_CPU_CLK) += ap-cpu-clk.o
15obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o 17obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
16obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o 18obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
17obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o 19obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
new file mode 100644
index 000000000000..af5e5acad370
--- /dev/null
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -0,0 +1,356 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP CPU Clock Controller
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Omri Itach <omrii@marvell.com>
8 * Gregory Clement <gregory.clement@bootlin.com>
9 */
10
11#define pr_fmt(fmt) "ap-cpu-clk: " fmt
12
13#include <linux/clk-provider.h>
14#include <linux/clk.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include "armada_ap_cp_helper.h"
22
23#define AP806_CPU_CLUSTER0 0
24#define AP806_CPU_CLUSTER1 1
25#define AP806_CPUS_PER_CLUSTER 2
26#define APN806_CPU1_MASK 0x1
27
28#define APN806_CLUSTER_NUM_OFFSET 8
29#define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
30
31#define APN806_MAX_DIVIDER 32
32
33/**
34 * struct cpu_dfs_regs: CPU DFS register mapping
35 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
36 * @force_reg: request to force new ratio regardless of relation to other clocks
37 * @ratio_reg: central request to switch ratios
38 */
39struct cpu_dfs_regs {
40 unsigned int divider_reg;
41 unsigned int force_reg;
42 unsigned int ratio_reg;
43 unsigned int ratio_state_reg;
44 unsigned int divider_mask;
45 unsigned int cluster_offset;
46 unsigned int force_mask;
47 int divider_offset;
48 int divider_ratio;
49 int ratio_offset;
50 int ratio_state_offset;
51 int ratio_state_cluster_offset;
52};
53
54/* AP806 CPU DFS register mapping*/
55#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
56#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
57#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
58#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
59
60#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
61#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
62#define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
63#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
64 (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
65#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
66#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
67 (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
68#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
69#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
70#define AP806_CA72MP2_0_PLL_RATIO_STATE 11
71
72#define STATUS_POLL_PERIOD_US 1
73#define STATUS_POLL_TIMEOUT_US 1000000
74
75#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
76
77static const struct cpu_dfs_regs ap806_dfs_regs = {
78 .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
79 .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
80 .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
81 .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
82 .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
83 .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
84 .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
85 .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
86 .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
87 .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
88 .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
89 .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
90};
91
92/* AP807 CPU DFS register mapping */
93#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
94#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
95#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
96#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
97#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18
98#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
99 (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
100#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
101#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
102 (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
103#define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3
104#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
105#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
106 (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
107#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6
108#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20
109#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3
110
111static const struct cpu_dfs_regs ap807_dfs_regs = {
112 .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
113 .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
114 .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
115 .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
116 .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
117 .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
118 .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
119 .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
120 .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
121 .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
122 .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
123 .ratio_state_cluster_offset =
124 AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
125};
126
127/*
128 * struct ap806_clk: CPU cluster clock controller instance
129 * @cluster: Cluster clock controller index
130 * @clk_name: Cluster clock controller name
131 * @dev : Cluster clock device
132 * @hw: HW specific structure of Cluster clock controller
133 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
134 */
135struct ap_cpu_clk {
136 unsigned int cluster;
137 const char *clk_name;
138 struct device *dev;
139 struct clk_hw hw;
140 struct regmap *pll_cr_base;
141 const struct cpu_dfs_regs *pll_regs;
142};
143
144static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
145 unsigned long parent_rate)
146{
147 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
148 unsigned int cpu_clkdiv_reg;
149 int cpu_clkdiv_ratio;
150
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
152 (clk->cluster * clk->pll_regs->cluster_offset);
153 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
156
157 return parent_rate / cpu_clkdiv_ratio;
158}
159
160static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
161 unsigned long parent_rate)
162{
163 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
164 int ret, reg, divider = parent_rate / rate;
165 unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
166
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
168 (clk->cluster * clk->pll_regs->cluster_offset);
169 cpu_force_reg = clk->pll_regs->force_reg +
170 (clk->cluster * clk->pll_regs->cluster_offset);
171 cpu_ratio_reg = clk->pll_regs->ratio_reg +
172 (clk->cluster * clk->pll_regs->cluster_offset);
173
174 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
175 reg &= ~(clk->pll_regs->divider_mask);
176 reg |= (divider << clk->pll_regs->divider_offset);
177
178 /*
179 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
180 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
181 */
182 if (clk->pll_regs->divider_ratio) {
183 reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
184 reg |= ((divider * clk->pll_regs->divider_ratio) <<
185 AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
186 }
187 regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
188
189
190 regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
191 clk->pll_regs->force_mask,
192 clk->pll_regs->force_mask);
193
194 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
195 BIT(clk->pll_regs->ratio_offset),
196 BIT(clk->pll_regs->ratio_offset));
197
198 stable_bit = BIT(clk->pll_regs->ratio_state_offset +
199 clk->cluster *
200 clk->pll_regs->ratio_state_cluster_offset),
201 ret = regmap_read_poll_timeout(clk->pll_cr_base,
202 clk->pll_regs->ratio_state_reg, reg,
203 reg & stable_bit, STATUS_POLL_PERIOD_US,
204 STATUS_POLL_TIMEOUT_US);
205 if (ret)
206 return ret;
207
208 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
209 BIT(clk->pll_regs->ratio_offset), 0);
210
211 return 0;
212}
213
214static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
215 unsigned long *parent_rate)
216{
217 int divider = *parent_rate / rate;
218
219 divider = min(divider, APN806_MAX_DIVIDER);
220
221 return *parent_rate / divider;
222}
223
224static const struct clk_ops ap_cpu_clk_ops = {
225 .recalc_rate = ap_cpu_clk_recalc_rate,
226 .round_rate = ap_cpu_clk_round_rate,
227 .set_rate = ap_cpu_clk_set_rate,
228};
229
230static int ap_cpu_clock_probe(struct platform_device *pdev)
231{
232 int ret, nclusters = 0, cluster_index = 0;
233 struct device *dev = &pdev->dev;
234 struct device_node *dn, *np = dev->of_node;
235 struct clk_hw_onecell_data *ap_cpu_data;
236 struct ap_cpu_clk *ap_cpu_clk;
237 struct regmap *regmap;
238
239 regmap = syscon_node_to_regmap(np->parent);
240 if (IS_ERR(regmap)) {
241 pr_err("cannot get pll_cr_base regmap\n");
242 return PTR_ERR(regmap);
243 }
244
245 /*
246 * AP806 has 4 cpus and DFS for AP806 is controlled per
247 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
248 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
249 * they are enabled or not. Since cpu0 is the boot cpu, then
250 * cluster0 must exist. If cpu2 or cpu3 is enabled, cluster1
251 * will exist and the cluster number is 2; otherwise the
252 * cluster number is 1.
253 */
254 nclusters = 1;
255 for_each_of_cpu_node(dn) {
256 int cpu, err;
257
258 err = of_property_read_u32(dn, "reg", &cpu);
259 if (WARN_ON(err))
260 return err;
261
262 /* If cpu2 or cpu3 is enabled */
263 if (cpu & APN806_CLUSTER_NUM_MASK) {
264 nclusters = 2;
265 break;
266 }
267 }
268 /*
269 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
270 * so allocate structs per cluster
271 */
272 ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
273 GFP_KERNEL);
274 if (!ap_cpu_clk)
275 return -ENOMEM;
276
277 ap_cpu_data = devm_kzalloc(dev, sizeof(*ap_cpu_data) +
278 sizeof(struct clk_hw *) * nclusters,
279 GFP_KERNEL);
280 if (!ap_cpu_data)
281 return -ENOMEM;
282
283 for_each_of_cpu_node(dn) {
284 char *clk_name = "cpu-cluster-0";
285 struct clk_init_data init;
286 const char *parent_name;
287 struct clk *parent;
288 int cpu, err;
289
290 err = of_property_read_u32(dn, "reg", &cpu);
291 if (WARN_ON(err))
292 return err;
293
294 cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
295 cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
296
297 /* Initialize once for one cluster */
298 if (ap_cpu_data->hws[cluster_index])
299 continue;
300
301 parent = of_clk_get(np, cluster_index);
302 if (IS_ERR(parent)) {
303 dev_err(dev, "Could not get the clock parent\n");
304 return -EINVAL;
305 }
306 parent_name = __clk_get_name(parent);
307 clk_name[12] += cluster_index;
308 ap_cpu_clk[cluster_index].clk_name =
309 ap_cp_unique_name(dev, np->parent, clk_name);
310 ap_cpu_clk[cluster_index].cluster = cluster_index;
311 ap_cpu_clk[cluster_index].pll_cr_base = regmap;
312 ap_cpu_clk[cluster_index].hw.init = &init;
313 ap_cpu_clk[cluster_index].dev = dev;
314 ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
315
316 init.name = ap_cpu_clk[cluster_index].clk_name;
317 init.ops = &ap_cpu_clk_ops;
318 init.num_parents = 1;
319 init.parent_names = &parent_name;
320
321 ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
322 if (ret)
323 return ret;
324 ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
325 }
326
327 ap_cpu_data->num = cluster_index + 1;
328
329 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
330 if (ret)
331 dev_err(dev, "failed to register OF clock provider\n");
332
333 return ret;
334}
335
336static const struct of_device_id ap_cpu_clock_of_match[] = {
337 {
338 .compatible = "marvell,ap806-cpu-clock",
339 .data = &ap806_dfs_regs,
340 },
341 {
342 .compatible = "marvell,ap807-cpu-clock",
343 .data = &ap807_dfs_regs,
344 },
345 { }
346};
347
348static struct platform_driver ap_cpu_clock_driver = {
349 .probe = ap_cpu_clock_probe,
350 .driver = {
351 .name = "marvell-ap-cpu-clock",
352 .of_match_table = ap_cpu_clock_of_match,
353 .suppress_bind_attrs = true,
354 },
355};
356builtin_platform_driver(ap_cpu_clock_driver);
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index ea54a874bbda..948bd1e71aea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -10,18 +10,18 @@
10 10
11#define pr_fmt(fmt) "ap806-system-controller: " fmt 11#define pr_fmt(fmt) "ap806-system-controller: " fmt
12 12
13#include "armada_ap_cp_helper.h"
13#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
14#include <linux/mfd/syscon.h> 15#include <linux/mfd/syscon.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/regmap.h> 19#include <linux/regmap.h>
20 20
21#define AP806_SAR_REG 0x400 21#define AP806_SAR_REG 0x400
22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f 22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
23 23
24#define AP806_CLK_NUM 5 24#define AP806_CLK_NUM 6
25 25
26static struct clk *ap806_clks[AP806_CLK_NUM]; 26static struct clk *ap806_clks[AP806_CLK_NUM];
27 27
@@ -30,86 +30,149 @@ static struct clk_onecell_data ap806_clk_data = {
30 .clk_num = AP806_CLK_NUM, 30 .clk_num = AP806_CLK_NUM,
31}; 31};
32 32
33static char *ap806_unique_name(struct device *dev, struct device_node *np, 33static int ap806_get_sar_clocks(unsigned int freq_mode,
34 char *name) 34 unsigned int *cpuclk_freq,
35 unsigned int *dclk_freq)
35{ 36{
36 const __be32 *reg;
37 u64 addr;
38
39 reg = of_get_property(np, "reg", NULL);
40 addr = of_translate_address(np, reg);
41 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
42 (unsigned long long)addr, name);
43}
44
45static int ap806_syscon_common_probe(struct platform_device *pdev,
46 struct device_node *syscon_node)
47{
48 unsigned int freq_mode, cpuclk_freq;
49 const char *name, *fixedclk_name;
50 struct device *dev = &pdev->dev;
51 struct device_node *np = dev->of_node;
52 struct regmap *regmap;
53 u32 reg;
54 int ret;
55
56 regmap = syscon_node_to_regmap(syscon_node);
57 if (IS_ERR(regmap)) {
58 dev_err(dev, "cannot get regmap\n");
59 return PTR_ERR(regmap);
60 }
61
62 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
63 if (ret) {
64 dev_err(dev, "cannot read from regmap\n");
65 return ret;
66 }
67
68 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
69 switch (freq_mode) { 37 switch (freq_mode) {
70 case 0x0: 38 case 0x0:
39 *cpuclk_freq = 2000;
40 *dclk_freq = 600;
41 break;
71 case 0x1: 42 case 0x1:
72 cpuclk_freq = 2000; 43 *cpuclk_freq = 2000;
44 *dclk_freq = 525;
73 break; 45 break;
74 case 0x6: 46 case 0x6:
47 *cpuclk_freq = 1800;
48 *dclk_freq = 600;
49 break;
75 case 0x7: 50 case 0x7:
76 cpuclk_freq = 1800; 51 *cpuclk_freq = 1800;
52 *dclk_freq = 525;
77 break; 53 break;
78 case 0x4: 54 case 0x4:
55 *cpuclk_freq = 1600;
56 *dclk_freq = 400;
57 break;
79 case 0xB: 58 case 0xB:
59 *cpuclk_freq = 1600;
60 *dclk_freq = 450;
61 break;
80 case 0xD: 62 case 0xD:
81 cpuclk_freq = 1600; 63 *cpuclk_freq = 1600;
64 *dclk_freq = 525;
82 break; 65 break;
83 case 0x1a: 66 case 0x1a:
84 cpuclk_freq = 1400; 67 *cpuclk_freq = 1400;
68 *dclk_freq = 400;
85 break; 69 break;
86 case 0x14: 70 case 0x14:
71 *cpuclk_freq = 1300;
72 *dclk_freq = 400;
73 break;
87 case 0x17: 74 case 0x17:
88 cpuclk_freq = 1300; 75 *cpuclk_freq = 1300;
76 *dclk_freq = 325;
89 break; 77 break;
90 case 0x19: 78 case 0x19:
91 cpuclk_freq = 1200; 79 *cpuclk_freq = 1200;
80 *dclk_freq = 400;
92 break; 81 break;
93 case 0x13: 82 case 0x13:
83 *cpuclk_freq = 1000;
84 *dclk_freq = 325;
85 break;
94 case 0x1d: 86 case 0x1d:
95 cpuclk_freq = 1000; 87 *cpuclk_freq = 1000;
88 *dclk_freq = 400;
96 break; 89 break;
97 case 0x1c: 90 case 0x1c:
98 cpuclk_freq = 800; 91 *cpuclk_freq = 800;
92 *dclk_freq = 400;
99 break; 93 break;
100 case 0x1b: 94 case 0x1b:
101 cpuclk_freq = 600; 95 *cpuclk_freq = 600;
96 *dclk_freq = 400;
102 break; 97 break;
103 default: 98 default:
104 dev_err(dev, "invalid SAR value\n");
105 return -EINVAL; 99 return -EINVAL;
106 } 100 }
107 101
102 return 0;
103}
104
105static int ap807_get_sar_clocks(unsigned int freq_mode,
106 unsigned int *cpuclk_freq,
107 unsigned int *dclk_freq)
108{
109 switch (freq_mode) {
110 case 0x0:
111 *cpuclk_freq = 2000;
112 *dclk_freq = 1200;
113 break;
114 case 0x6:
115 *cpuclk_freq = 2200;
116 *dclk_freq = 1200;
117 break;
118 case 0xD:
119 *cpuclk_freq = 1600;
120 *dclk_freq = 1200;
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 return 0;
127}
128
129static int ap806_syscon_common_probe(struct platform_device *pdev,
130 struct device_node *syscon_node)
131{
132 unsigned int freq_mode, cpuclk_freq, dclk_freq;
133 const char *name, *fixedclk_name;
134 struct device *dev = &pdev->dev;
135 struct device_node *np = dev->of_node;
136 struct regmap *regmap;
137 u32 reg;
138 int ret;
139
140 regmap = syscon_node_to_regmap(syscon_node);
141 if (IS_ERR(regmap)) {
142 dev_err(dev, "cannot get regmap\n");
143 return PTR_ERR(regmap);
144 }
145
146 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
147 if (ret) {
148 dev_err(dev, "cannot read from regmap\n");
149 return ret;
150 }
151
152 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
153
154 if (of_device_is_compatible(pdev->dev.of_node,
155 "marvell,ap806-clock")) {
156 ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
157 } else if (of_device_is_compatible(pdev->dev.of_node,
158 "marvell,ap807-clock")) {
159 ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
160 } else {
161 dev_err(dev, "compatible not supported\n");
162 return -EINVAL;
163 }
164
165 if (ret) {
166 dev_err(dev, "invalid Sample at Reset value\n");
167 return ret;
168 }
169
108 /* Convert to hertz */ 170 /* Convert to hertz */
109 cpuclk_freq *= 1000 * 1000; 171 cpuclk_freq *= 1000 * 1000;
172 dclk_freq *= 1000 * 1000;
110 173
111 /* CPU clocks depend on the Sample At Reset configuration */ 174 /* CPU clocks depend on the Sample At Reset configuration */
112 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0"); 175 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
113 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL, 176 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
114 0, cpuclk_freq); 177 0, cpuclk_freq);
115 if (IS_ERR(ap806_clks[0])) { 178 if (IS_ERR(ap806_clks[0])) {
@@ -117,7 +180,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
117 goto fail0; 180 goto fail0;
118 } 181 }
119 182
120 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1"); 183 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
121 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0, 184 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
122 cpuclk_freq); 185 cpuclk_freq);
123 if (IS_ERR(ap806_clks[1])) { 186 if (IS_ERR(ap806_clks[1])) {
@@ -126,7 +189,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
126 } 189 }
127 190
128 /* Fixed clock is always 1200 Mhz */ 191 /* Fixed clock is always 1200 Mhz */
129 fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed"); 192 fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
130 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL, 193 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
131 0, 1200 * 1000 * 1000); 194 0, 1200 * 1000 * 1000);
132 if (IS_ERR(ap806_clks[2])) { 195 if (IS_ERR(ap806_clks[2])) {
@@ -135,7 +198,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
135 } 198 }
136 199
137 /* MSS Clock is fixed clock divided by 6 */ 200 /* MSS Clock is fixed clock divided by 6 */
138 name = ap806_unique_name(dev, syscon_node, "mss"); 201 name = ap_cp_unique_name(dev, syscon_node, "mss");
139 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name, 202 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
140 0, 1, 6); 203 0, 1, 6);
141 if (IS_ERR(ap806_clks[3])) { 204 if (IS_ERR(ap806_clks[3])) {
@@ -144,7 +207,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
144 } 207 }
145 208
146 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */ 209 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
147 name = ap806_unique_name(dev, syscon_node, "sdio"); 210 name = ap_cp_unique_name(dev, syscon_node, "sdio");
148 ap806_clks[4] = clk_register_fixed_factor(NULL, name, 211 ap806_clks[4] = clk_register_fixed_factor(NULL, name,
149 fixedclk_name, 212 fixedclk_name,
150 0, 1, 3); 213 0, 1, 3);
@@ -153,6 +216,14 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
153 goto fail4; 216 goto fail4;
154 } 217 }
155 218
219 /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
220 name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
221 ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
222 if (IS_ERR(ap806_clks[5])) {
223 ret = PTR_ERR(ap806_clks[5]);
224 goto fail5;
225 }
226
156 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 227 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
157 if (ret) 228 if (ret)
158 goto fail_clk_add; 229 goto fail_clk_add;
@@ -160,6 +231,8 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
160 return 0; 231 return 0;
161 232
162fail_clk_add: 233fail_clk_add:
234 clk_unregister_fixed_factor(ap806_clks[5]);
235fail5:
163 clk_unregister_fixed_factor(ap806_clks[4]); 236 clk_unregister_fixed_factor(ap806_clks[4]);
164fail4: 237fail4:
165 clk_unregister_fixed_factor(ap806_clks[3]); 238 clk_unregister_fixed_factor(ap806_clks[3]);
@@ -206,6 +279,7 @@ builtin_platform_driver(ap806_syscon_legacy_driver);
206 279
207static const struct of_device_id ap806_clock_of_match[] = { 280static const struct of_device_id ap806_clock_of_match[] = {
208 { .compatible = "marvell,ap806-clock", }, 281 { .compatible = "marvell,ap806-clock", },
282 { .compatible = "marvell,ap807-clock", },
209 { } 283 { }
210}; 284};
211 285
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.c b/drivers/clk/mvebu/armada_ap_cp_helper.c
new file mode 100644
index 000000000000..6a930f697ee5
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.c
@@ -0,0 +1,30 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP and CP110 helper
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Gregory Clement <gregory.clement@bootlin.com>
8 *
9 */
10
11#include "armada_ap_cp_helper.h"
12#include <linux/device.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15
16char *ap_cp_unique_name(struct device *dev, struct device_node *np,
17 const char *name)
18{
19 const __be32 *reg;
20 u64 addr;
21
22 /* Do not create a name if there is no clock */
23 if (!name)
24 return NULL;
25
26 reg = of_get_property(np, "reg", NULL);
27 addr = of_translate_address(np, reg);
28 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
29 (unsigned long long)addr, name);
30}
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.h b/drivers/clk/mvebu/armada_ap_cp_helper.h
new file mode 100644
index 000000000000..810af1e5dfa4
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.h
@@ -0,0 +1,11 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __ARMADA_AP_CP_HELPER_H
4#define __ARMADA_AP_CP_HELPER_H
5
6struct device;
7struct device_node;
8
9char *ap_cp_unique_name(struct device *dev, struct device_node *np,
10 const char *name);
11#endif
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index b6de283f45e3..808463276145 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -26,11 +26,11 @@
26 26
27#define pr_fmt(fmt) "cp110-system-controller: " fmt 27#define pr_fmt(fmt) "cp110-system-controller: " fmt
28 28
29#include "armada_ap_cp_helper.h"
29#include <linux/clk-provider.h> 30#include <linux/clk-provider.h>
30#include <linux/mfd/syscon.h> 31#include <linux/mfd/syscon.h>
31#include <linux/init.h> 32#include <linux/init.h>
32#include <linux/of.h> 33#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <linux/regmap.h> 35#include <linux/regmap.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
@@ -212,22 +212,6 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
212 return ERR_PTR(-EINVAL); 212 return ERR_PTR(-EINVAL);
213} 213}
214 214
215static char *cp110_unique_name(struct device *dev, struct device_node *np,
216 const char *name)
217{
218 const __be32 *reg;
219 u64 addr;
220
221 /* Do not create a name if there is no clock */
222 if (!name)
223 return NULL;
224
225 reg = of_get_property(np, "reg", NULL);
226 addr = of_translate_address(np, reg);
227 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
228 (unsigned long long)addr, name);
229}
230
231static int cp110_syscon_common_probe(struct platform_device *pdev, 215static int cp110_syscon_common_probe(struct platform_device *pdev,
232 struct device_node *syscon_node) 216 struct device_node *syscon_node)
233{ 217{
@@ -261,7 +245,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
261 cp110_clk_data->num = CP110_CLK_NUM; 245 cp110_clk_data->num = CP110_CLK_NUM;
262 246
263 /* Register the PLL0 which is the root of the hw tree */ 247 /* Register the PLL0 which is the root of the hw tree */
264 pll0_name = cp110_unique_name(dev, syscon_node, "pll0"); 248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
265 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0, 249 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
266 1000 * 1000 * 1000); 250 1000 * 1000 * 1000);
267 if (IS_ERR(hw)) { 251 if (IS_ERR(hw)) {
@@ -272,7 +256,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
272 cp110_clks[CP110_CORE_PLL0] = hw; 256 cp110_clks[CP110_CORE_PLL0] = hw;
273 257
274 /* PPv2 is PLL0/3 */ 258 /* PPv2 is PLL0/3 */
275 ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core"); 259 ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
276 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3); 260 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
277 if (IS_ERR(hw)) { 261 if (IS_ERR(hw)) {
278 ret = PTR_ERR(hw); 262 ret = PTR_ERR(hw);
@@ -282,7 +266,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
282 cp110_clks[CP110_CORE_PPV2] = hw; 266 cp110_clks[CP110_CORE_PPV2] = hw;
283 267
284 /* X2CORE clock is PLL0/2 */ 268 /* X2CORE clock is PLL0/2 */
285 x2core_name = cp110_unique_name(dev, syscon_node, "x2core"); 269 x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
286 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name, 270 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
287 0, 1, 2); 271 0, 1, 2);
288 if (IS_ERR(hw)) { 272 if (IS_ERR(hw)) {
@@ -293,7 +277,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
293 cp110_clks[CP110_CORE_X2CORE] = hw; 277 cp110_clks[CP110_CORE_X2CORE] = hw;
294 278
295 /* Core clock is X2CORE/2 */ 279 /* Core clock is X2CORE/2 */
296 core_name = cp110_unique_name(dev, syscon_node, "core"); 280 core_name = ap_cp_unique_name(dev, syscon_node, "core");
297 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name, 281 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
298 0, 1, 2); 282 0, 1, 2);
299 if (IS_ERR(hw)) { 283 if (IS_ERR(hw)) {
@@ -303,7 +287,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
303 287
304 cp110_clks[CP110_CORE_CORE] = hw; 288 cp110_clks[CP110_CORE_CORE] = hw;
305 /* NAND can be either PLL0/2.5 or core clock */ 289 /* NAND can be either PLL0/2.5 or core clock */
306 nand_name = cp110_unique_name(dev, syscon_node, "nand-core"); 290 nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
307 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK) 291 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
308 hw = clk_hw_register_fixed_factor(NULL, nand_name, 292 hw = clk_hw_register_fixed_factor(NULL, nand_name,
309 pll0_name, 0, 2, 5); 293 pll0_name, 0, 2, 5);
@@ -318,7 +302,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
318 cp110_clks[CP110_CORE_NAND] = hw; 302 cp110_clks[CP110_CORE_NAND] = hw;
319 303
320 /* SDIO clock is PLL0/2.5 */ 304 /* SDIO clock is PLL0/2.5 */
321 sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core"); 305 sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
322 hw = clk_hw_register_fixed_factor(NULL, sdio_name, 306 hw = clk_hw_register_fixed_factor(NULL, sdio_name,
323 pll0_name, 0, 2, 5); 307 pll0_name, 0, 2, 5);
324 if (IS_ERR(hw)) { 308 if (IS_ERR(hw)) {
@@ -330,7 +314,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
330 314
331 /* create the unique name for all the gate clocks */ 315 /* create the unique name for all the gate clocks */
332 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) 316 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
333 gate_name[i] = cp110_unique_name(dev, syscon_node, 317 gate_name[i] = ap_cp_unique_name(dev, syscon_node,
334 gate_base_names[i]); 318 gate_base_names[i]);
335 319
336 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) { 320 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83cc361e..32dbb4f09492 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -21,7 +21,6 @@ if COMMON_CLK_QCOM
21 21
22config QCOM_A53PLL 22config QCOM_A53PLL
23 tristate "MSM8916 A53 PLL" 23 tristate "MSM8916 A53 PLL"
24 default ARCH_QCOM
25 help 24 help
26 Support for the A53 PLL on MSM8916 devices. It provides 25 Support for the A53 PLL on MSM8916 devices. It provides
27 the CPU with frequencies above 1GHz. 26 the CPU with frequencies above 1GHz.
@@ -31,7 +30,6 @@ config QCOM_A53PLL
31config QCOM_CLK_APCS_MSM8916 30config QCOM_CLK_APCS_MSM8916
32 tristate "MSM8916 APCS Clock Controller" 31 tristate "MSM8916 APCS Clock Controller"
33 depends on QCOM_APCS_IPC || COMPILE_TEST 32 depends on QCOM_APCS_IPC || COMPILE_TEST
34 default ARCH_QCOM
35 help 33 help
36 Support for the APCS Clock Controller on msm8916 devices. The 34 Support for the APCS Clock Controller on msm8916 devices. The
37 APCS is managing the mux and divider which feeds the CPUs. 35 APCS is managing the mux and divider which feeds the CPUs.
@@ -292,6 +290,13 @@ config SDM_LPASSCC_845
292 Say Y if you want to use the LPASS branch clocks of the LPASS clock 290 Say Y if you want to use the LPASS branch clocks of the LPASS clock
293 controller to reset the LPASS subsystem. 291 controller to reset the LPASS subsystem.
294 292
293config SM_GCC_8150
294 tristate "SM8150 Global Clock Controller"
295 help
296 Support for the global clock controller on SM8150 devices.
297 Say Y if you want to use peripheral devices such as UART,
298 SPI, I2C, USB, SD/UFS, PCIe etc.
299
295config SPMI_PMIC_CLKDIV 300config SPMI_PMIC_CLKDIV
296 tristate "SPMI PMIC clkdiv Support" 301 tristate "SPMI PMIC clkdiv Support"
297 depends on SPMI || COMPILE_TEST 302 depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb1f037..4a813b4055d0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o 50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o 51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o 52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
53obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
53obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o 54obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
54obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o 55obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
55obj-$(CONFIG_QCOM_HFPLL) += hfpll.o 56obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0ced4a5a9a17..055318f97991 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -32,6 +32,7 @@
32# define PLL_LOCK_DET BIT(31) 32# define PLL_LOCK_DET BIT(31)
33 33
34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
35#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 36#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
36#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 37#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
37 38
@@ -44,14 +45,17 @@
44# define PLL_VCO_MASK 0x3 45# define PLL_VCO_MASK 0x3
45 46
46#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 47#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
48#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
47 49
48#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 50#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
49#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 51#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
52#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
50#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 53#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
51#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 54#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
52#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 55#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
53#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 56#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
54#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 57#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
58#define PLL_CAL_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
55 59
56const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 60const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 61 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
@@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
96 [PLL_OFF_OPMODE] = 0x2c, 100 [PLL_OFF_OPMODE] = 0x2c,
97 [PLL_OFF_FRAC] = 0x38, 101 [PLL_OFF_FRAC] = 0x38,
98 }, 102 },
103 [CLK_ALPHA_PLL_TYPE_TRION] = {
104 [PLL_OFF_L_VAL] = 0x04,
105 [PLL_OFF_CAL_L_VAL] = 0x08,
106 [PLL_OFF_USER_CTL] = 0x0c,
107 [PLL_OFF_USER_CTL_U] = 0x10,
108 [PLL_OFF_USER_CTL_U1] = 0x14,
109 [PLL_OFF_CONFIG_CTL] = 0x18,
110 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
111 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
112 [PLL_OFF_TEST_CTL] = 0x24,
113 [PLL_OFF_TEST_CTL_U] = 0x28,
114 [PLL_OFF_STATUS] = 0x30,
115 [PLL_OFF_OPMODE] = 0x38,
116 [PLL_OFF_ALPHA_VAL] = 0x40,
117 [PLL_OFF_CAL_VAL] = 0x44,
118 },
99}; 119};
100EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 120EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
101 121
@@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
120#define FABIA_PLL_OUT_MASK 0x7 140#define FABIA_PLL_OUT_MASK 0x7
121#define FABIA_PLL_RATE_MARGIN 500 141#define FABIA_PLL_RATE_MARGIN 500
122 142
143#define TRION_PLL_STANDBY 0x0
144#define TRION_PLL_RUN 0x1
145#define TRION_PLL_OUT_MASK 0x7
146
123#define pll_alpha_width(p) \ 147#define pll_alpha_width(p) \
124 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 148 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
125 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 149 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
730 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 754 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
731} 755}
732 756
757static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
758 struct regmap *regmap)
759{
760 u32 mode_regval, opmode_regval;
761 int ret;
762
763 ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
764 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
765 if (ret)
766 return 0;
767
768 return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
769}
770
771static int clk_trion_pll_is_enabled(struct clk_hw *hw)
772{
773 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
774
775 return trion_pll_is_enabled(pll, pll->clkr.regmap);
776}
777
778static int clk_trion_pll_enable(struct clk_hw *hw)
779{
780 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
781 struct regmap *regmap = pll->clkr.regmap;
782 u32 val;
783 int ret;
784
785 ret = regmap_read(regmap, PLL_MODE(pll), &val);
786 if (ret)
787 return ret;
788
789 /* If in FSM mode, just vote for it */
790 if (val & PLL_VOTE_FSM_ENA) {
791 ret = clk_enable_regmap(hw);
792 if (ret)
793 return ret;
794 return wait_for_pll_enable_active(pll);
795 }
796
797 /* Set operation mode to RUN */
798 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
799
800 ret = wait_for_pll_enable_lock(pll);
801 if (ret)
802 return ret;
803
804 /* Enable the PLL outputs */
805 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
806 TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
807 if (ret)
808 return ret;
809
810 /* Enable the global PLL outputs */
811 return regmap_update_bits(regmap, PLL_MODE(pll),
812 PLL_OUTCTRL, PLL_OUTCTRL);
813}
814
815static void clk_trion_pll_disable(struct clk_hw *hw)
816{
817 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
818 struct regmap *regmap = pll->clkr.regmap;
819 u32 val;
820 int ret;
821
822 ret = regmap_read(regmap, PLL_MODE(pll), &val);
823 if (ret)
824 return;
825
826 /* If in FSM mode, just unvote it */
827 if (val & PLL_VOTE_FSM_ENA) {
828 clk_disable_regmap(hw);
829 return;
830 }
831
832 /* Disable the global PLL output */
833 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
834 if (ret)
835 return;
836
837 /* Disable the PLL outputs */
838 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
839 TRION_PLL_OUT_MASK, 0);
840 if (ret)
841 return;
842
843 /* Place the PLL mode in STANDBY */
844 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
845 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
846}
847
848static unsigned long
849clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
850{
851 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
852 struct regmap *regmap = pll->clkr.regmap;
853 u32 l, frac;
854 u64 prate = parent_rate;
855
856 regmap_read(regmap, PLL_L_VAL(pll), &l);
857 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
858
859 return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
860}
861
862static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
863 unsigned long *prate)
864{
865 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
866 unsigned long min_freq, max_freq;
867 u32 l;
868 u64 a;
869
870 rate = alpha_pll_round_rate(rate, *prate,
871 &l, &a, ALPHA_REG_16BIT_WIDTH);
872 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
873 return rate;
874
875 min_freq = pll->vco_table[0].min_freq;
876 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
877
878 return clamp(rate, min_freq, max_freq);
879}
880
733const struct clk_ops clk_alpha_pll_ops = { 881const struct clk_ops clk_alpha_pll_ops = {
734 .enable = clk_alpha_pll_enable, 882 .enable = clk_alpha_pll_enable,
735 .disable = clk_alpha_pll_disable, 883 .disable = clk_alpha_pll_disable,
@@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
760}; 908};
761EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 909EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
762 910
911const struct clk_ops clk_trion_fixed_pll_ops = {
912 .enable = clk_trion_pll_enable,
913 .disable = clk_trion_pll_disable,
914 .is_enabled = clk_trion_pll_is_enabled,
915 .recalc_rate = clk_trion_pll_recalc_rate,
916 .round_rate = clk_trion_pll_round_rate,
917};
918EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
919
763static unsigned long 920static unsigned long
764clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 921clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
765{ 922{
@@ -832,7 +989,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
832 int div; 989 int div;
833 990
834 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 991 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
835 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; 992 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
836 993
837 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 994 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
838 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 995 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
@@ -1036,11 +1193,6 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1036 u32 i, div = 1, val; 1193 u32 i, div = 1, val;
1037 int ret; 1194 int ret;
1038 1195
1039 if (!pll->post_div_table) {
1040 pr_err("Missing the post_div_table for the PLL\n");
1041 return -EINVAL;
1042 }
1043
1044 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1196 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1045 if (ret) 1197 if (ret)
1046 return ret; 1198 return ret;
@@ -1058,16 +1210,71 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1058 return (parent_rate / div); 1210 return (parent_rate / div);
1059} 1211}
1060 1212
1061static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1213static unsigned long
1062 unsigned long rate, unsigned long *prate) 1214clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1063{ 1215{
1064 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1216 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1217 struct regmap *regmap = pll->clkr.regmap;
1218 u32 i, div = 1, val;
1065 1219
1066 if (!pll->post_div_table) { 1220 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1067 pr_err("Missing the post_div_table for the PLL\n"); 1221
1068 return -EINVAL; 1222 val >>= pll->post_div_shift;
1223 val &= PLL_POST_DIV_MASK(pll);
1224
1225 for (i = 0; i < pll->num_post_div; i++) {
1226 if (pll->post_div_table[i].val == val) {
1227 div = pll->post_div_table[i].div;
1228 break;
1229 }
1230 }
1231
1232 return (parent_rate / div);
1233}
1234
1235static long
1236clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1237 unsigned long *prate)
1238{
1239 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1240
1241 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1242 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1243};
1244
1245static int
1246clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1247 unsigned long parent_rate)
1248{
1249 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1250 struct regmap *regmap = pll->clkr.regmap;
1251 int i, val = 0, div;
1252
1253 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1254 for (i = 0; i < pll->num_post_div; i++) {
1255 if (pll->post_div_table[i].div == div) {
1256 val = pll->post_div_table[i].val;
1257 break;
1258 }
1069 } 1259 }
1070 1260
1261 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1262 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1263 val << PLL_POST_DIV_SHIFT);
1264}
1265
1266const struct clk_ops clk_trion_pll_postdiv_ops = {
1267 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1268 .round_rate = clk_trion_pll_postdiv_round_rate,
1269 .set_rate = clk_trion_pll_postdiv_set_rate,
1270};
1271EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
1272
1273static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1274 unsigned long rate, unsigned long *prate)
1275{
1276 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1277
1071 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1278 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1072 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1279 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1073} 1280}
@@ -1089,12 +1296,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1089 if (val & PLL_VOTE_FSM_ENA) 1296 if (val & PLL_VOTE_FSM_ENA)
1090 return 0; 1297 return 0;
1091 1298
1092 if (!pll->post_div_table) { 1299 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1093 pr_err("Missing the post_div_table for the PLL\n");
1094 return -EINVAL;
1095 }
1096
1097 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1098 for (i = 0; i < pll->num_post_div; i++) { 1300 for (i = 0; i < pll->num_post_div; i++) {
1099 if (pll->post_div_table[i].div == div) { 1301 if (pll->post_div_table[i].div == div) {
1100 val = pll->post_div_table[i].val; 1302 val = pll->post_div_table[i].val;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 66755f0f84fc..15f27f4b06df 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -13,22 +13,27 @@ enum {
13 CLK_ALPHA_PLL_TYPE_HUAYRA, 13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO, 14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA, 15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
16 CLK_ALPHA_PLL_TYPE_MAX, 17 CLK_ALPHA_PLL_TYPE_MAX,
17}; 18};
18 19
19enum { 20enum {
20 PLL_OFF_L_VAL, 21 PLL_OFF_L_VAL,
22 PLL_OFF_CAL_L_VAL,
21 PLL_OFF_ALPHA_VAL, 23 PLL_OFF_ALPHA_VAL,
22 PLL_OFF_ALPHA_VAL_U, 24 PLL_OFF_ALPHA_VAL_U,
23 PLL_OFF_USER_CTL, 25 PLL_OFF_USER_CTL,
24 PLL_OFF_USER_CTL_U, 26 PLL_OFF_USER_CTL_U,
27 PLL_OFF_USER_CTL_U1,
25 PLL_OFF_CONFIG_CTL, 28 PLL_OFF_CONFIG_CTL,
26 PLL_OFF_CONFIG_CTL_U, 29 PLL_OFF_CONFIG_CTL_U,
30 PLL_OFF_CONFIG_CTL_U1,
27 PLL_OFF_TEST_CTL, 31 PLL_OFF_TEST_CTL,
28 PLL_OFF_TEST_CTL_U, 32 PLL_OFF_TEST_CTL_U,
29 PLL_OFF_STATUS, 33 PLL_OFF_STATUS,
30 PLL_OFF_OPMODE, 34 PLL_OFF_OPMODE,
31 PLL_OFF_FRAC, 35 PLL_OFF_FRAC,
36 PLL_OFF_CAL_VAL,
32 PLL_OFF_MAX_REGS 37 PLL_OFF_MAX_REGS
33}; 38};
34 39
@@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
117 const struct alpha_pll_config *config); 122 const struct alpha_pll_config *config);
118void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 123void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
119 const struct alpha_pll_config *config); 124 const struct alpha_pll_config *config);
125extern const struct clk_ops clk_trion_fixed_pll_ops;
126extern const struct clk_ops clk_trion_pll_postdiv_ops;
120 127
121#endif 128#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 8c02bffe50df..b98b81ef43a1 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -119,7 +119,7 @@ static int update_config(struct clk_rcg2 *rcg)
119 } 119 }
120 120
121 WARN(1, "%s: rcg didn't update its configuration.", name); 121 WARN(1, "%s: rcg didn't update its configuration.", name);
122 return 0; 122 return -EBUSY;
123} 123}
124 124
125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
@@ -1105,8 +1105,6 @@ static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
1105 1105
1106 rcg->freq_tbl = NULL; 1106 rcg->freq_tbl = NULL;
1107 1107
1108 pr_debug("DFS registered for clk %s\n", init->name);
1109
1110 return 0; 1108 return 0;
1111} 1109}
1112 1110
@@ -1117,12 +1115,8 @@ int qcom_cc_register_rcg_dfs(struct regmap *regmap,
1117 1115
1118 for (i = 0; i < len; i++) { 1116 for (i = 0; i < len; i++) {
1119 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap); 1117 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
1120 if (ret) { 1118 if (ret)
1121 const char *name = rcgs[i].init->name;
1122
1123 pr_err("DFS register failed for clk %s\n", name);
1124 return ret; 1119 return ret;
1125 }
1126 } 1120 }
1127 1121
1128 return 0; 1122 return 0;
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index a32bfaeb7e61..96a36f6ff667 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -85,7 +85,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
85 .hw.init = &(struct clk_init_data){ \ 85 .hw.init = &(struct clk_init_data){ \
86 .ops = &clk_rpmh_ops, \ 86 .ops = &clk_rpmh_ops, \
87 .name = #_name, \ 87 .name = #_name, \
88 .parent_names = (const char *[]){ "xo_board" }, \ 88 .parent_data = &(const struct clk_parent_data){ \
89 .fw_name = "xo", \
90 .name = "xo_board", \
91 }, \
89 .num_parents = 1, \ 92 .num_parents = 1, \
90 }, \ 93 }, \
91 }; \ 94 }; \
@@ -100,7 +103,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
100 .hw.init = &(struct clk_init_data){ \ 103 .hw.init = &(struct clk_init_data){ \
101 .ops = &clk_rpmh_ops, \ 104 .ops = &clk_rpmh_ops, \
102 .name = #_name_active, \ 105 .name = #_name_active, \
103 .parent_names = (const char *[]){ "xo_board" }, \ 106 .parent_data = &(const struct clk_parent_data){ \
107 .fw_name = "xo", \
108 .name = "xo_board", \
109 }, \
104 .num_parents = 1, \ 110 .num_parents = 1, \
105 }, \ 111 }, \
106 } 112 }
@@ -358,6 +364,33 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
358 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 364 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
359}; 365};
360 366
367DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
368DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
369DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
370DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
371DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
372DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
373
374static struct clk_hw *sm8150_rpmh_clocks[] = {
375 [RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
376 [RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
377 [RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
378 [RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
379 [RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
380 [RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
381 [RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
382 [RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
383 [RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
384 [RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
385 [RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
386 [RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
387};
388
389static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
390 .clks = sm8150_rpmh_clocks,
391 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
392};
393
361static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 394static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
362 void *data) 395 void *data)
363{ 396{
@@ -386,6 +419,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
386 hw_clks = desc->clks; 419 hw_clks = desc->clks;
387 420
388 for (i = 0; i < desc->num_clks; i++) { 421 for (i = 0; i < desc->num_clks; i++) {
422 const char *name = hw_clks[i]->init->name;
389 u32 res_addr; 423 u32 res_addr;
390 size_t aux_data_len; 424 size_t aux_data_len;
391 const struct bcm_db *data; 425 const struct bcm_db *data;
@@ -416,8 +450,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
416 450
417 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 451 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
418 if (ret) { 452 if (ret) {
419 dev_err(&pdev->dev, "failed to register %s\n", 453 dev_err(&pdev->dev, "failed to register %s\n", name);
420 hw_clks[i]->init->name);
421 return ret; 454 return ret;
422 } 455 }
423 } 456 }
@@ -437,6 +470,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
437 470
438static const struct of_device_id clk_rpmh_match_table[] = { 471static const struct of_device_id clk_rpmh_match_table[] = {
439 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 472 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
473 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
440 { } 474 { }
441}; 475};
442MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 476MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index a6b2f86112d8..28ddc747d703 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -306,4 +306,24 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
306} 306}
307EXPORT_SYMBOL_GPL(qcom_cc_probe); 307EXPORT_SYMBOL_GPL(qcom_cc_probe);
308 308
309int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
310 const struct qcom_cc_desc *desc)
311{
312 struct regmap *regmap;
313 struct resource *res;
314 void __iomem *base;
315
316 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
317 base = devm_ioremap_resource(&pdev->dev, res);
318 if (IS_ERR(base))
319 return -ENOMEM;
320
321 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
322 if (IS_ERR(regmap))
323 return PTR_ERR(regmap);
324
325 return qcom_cc_really_probe(pdev, desc, regmap);
326}
327EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
328
309MODULE_LICENSE("GPL v2"); 329MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 1e2a8bdac55a..bb39a7e106d8 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -61,5 +61,7 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
61 struct regmap *regmap); 61 struct regmap *regmap);
62extern int qcom_cc_probe(struct platform_device *pdev, 62extern int qcom_cc_probe(struct platform_device *pdev,
63 const struct qcom_cc_desc *desc); 63 const struct qcom_cc_desc *desc);
64extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
65 const struct qcom_cc_desc *desc);
64 66
65#endif 67#endif
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 39ade58b4ada..e01f5f591d1e 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1108,7 +1108,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1108 .name = "sdcc2_apps_clk_src", 1108 .name = "sdcc2_apps_clk_src",
1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1110 .num_parents = 4, 1110 .num_parents = 4,
1111 .ops = &clk_rcg2_ops, 1111 .ops = &clk_rcg2_floor_ops,
1112 }, 1112 },
1113}; 1113};
1114 1114
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 033688264c7b..091acd59c1d6 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1042,7 +1042,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1042 .name = "sdcc2_apps_clk_src", 1042 .name = "sdcc2_apps_clk_src",
1043 .parent_names = gcc_parent_names_4, 1043 .parent_names = gcc_parent_names_4,
1044 .num_parents = 4, 1044 .num_parents = 4,
1045 .ops = &clk_rcg2_ops, 1045 .ops = &clk_rcg2_floor_ops,
1046 }, 1046 },
1047}; 1047};
1048 1048
@@ -1066,7 +1066,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
1066 .name = "sdcc4_apps_clk_src", 1066 .name = "sdcc4_apps_clk_src",
1067 .parent_names = gcc_parent_names_1, 1067 .parent_names = gcc_parent_names_1,
1068 .num_parents = 3, 1068 .num_parents = 3,
1069 .ops = &clk_rcg2_ops, 1069 .ops = &clk_rcg2_floor_ops,
1070 }, 1070 },
1071}; 1071};
1072 1072
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 29cf464dd2c8..bd32212f37e6 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -1057,7 +1057,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
1057 .name = "sdcc1_apps_clk_src", 1057 .name = "sdcc1_apps_clk_src",
1058 .parent_names = gcc_parent_names_13, 1058 .parent_names = gcc_parent_names_13,
1059 .num_parents = 5, 1059 .num_parents = 5,
1060 .ops = &clk_rcg2_ops, 1060 .ops = &clk_rcg2_floor_ops,
1061 }, 1061 },
1062}; 1062};
1063 1063
@@ -1103,7 +1103,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1103 .name = "sdcc2_apps_clk_src", 1103 .name = "sdcc2_apps_clk_src",
1104 .parent_names = gcc_parent_names_14, 1104 .parent_names = gcc_parent_names_14,
1105 .num_parents = 4, 1105 .num_parents = 4,
1106 .ops = &clk_rcg2_ops, 1106 .ops = &clk_rcg2_floor_ops,
1107 }, 1107 },
1108}; 1108};
1109 1109
@@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
2604 }, 2604 },
2605}; 2605};
2606 2606
2607static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2608 .halt_reg = 0x1e004,
2609 .halt_check = BRANCH_HALT,
2610 .clkr = {
2611 .enable_reg = 0x1e004,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_wdsp_q6ss_ahbs_clk",
2615 .ops = &clk_branch2_ops,
2616 },
2617 },
2618};
2619
2620static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2621 .halt_reg = 0x1e008,
2622 .halt_check = BRANCH_HALT,
2623 .clkr = {
2624 .enable_reg = 0x1e008,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_wdsp_q6ss_axim_clk",
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631};
2632
2607static struct clk_hw *gcc_qcs404_hws[] = { 2633static struct clk_hw *gcc_qcs404_hws[] = {
2608 &cxo.hw, 2634 &cxo.hw,
2609}; 2635};
@@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
2749 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2775 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2750 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, 2776 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2751 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, 2777 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2778 [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2779 [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2780
2752}; 2781};
2753 2782
2754static const struct qcom_reset_map gcc_qcs404_resets[] = { 2783static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
2774 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, 2803 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2775 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, 2804 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2776 [GCC_EMAC_BCR] = { 0x4e000 }, 2805 [GCC_EMAC_BCR] = { 0x4e000 },
2806 [GCC_WDSP_RESTART] = {0x19000},
2777}; 2807};
2778 2808
2779static const struct regmap_config gcc_qcs404_regmap_config = { 2809static const struct regmap_config gcc_qcs404_regmap_config = {
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 8827db23066f..bf5730832ef3 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -787,7 +787,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
787 .name = "sdcc2_apps_clk_src", 787 .name = "sdcc2_apps_clk_src",
788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, 788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
789 .num_parents = 4, 789 .num_parents = 4,
790 .ops = &clk_rcg2_ops, 790 .ops = &clk_rcg2_floor_ops,
791 }, 791 },
792}; 792};
793 793
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 7131dcf9b060..95be125c3bdd 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
685 .name = "gcc_sdcc2_apps_clk_src", 685 .name = "gcc_sdcc2_apps_clk_src",
686 .parent_names = gcc_parent_names_10, 686 .parent_names = gcc_parent_names_10,
687 .num_parents = 5, 687 .num_parents = 5,
688 .ops = &clk_rcg2_ops, 688 .ops = &clk_rcg2_floor_ops,
689 }, 689 },
690}; 690};
691 691
@@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
709 .name = "gcc_sdcc4_apps_clk_src", 709 .name = "gcc_sdcc4_apps_clk_src",
710 .parent_names = gcc_parent_names_0, 710 .parent_names = gcc_parent_names_0,
711 .num_parents = 4, 711 .num_parents = 4,
712 .ops = &clk_rcg2_ops, 712 .ops = &clk_rcg2_floor_ops,
713 }, 713 },
714}; 714};
715 715
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
new file mode 100644
index 000000000000..20877214acff
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -0,0 +1,3588 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
3
4#include <linux/kernel.h>
5#include <linux/bitops.h>
6#include <linux/err.h>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13#include <linux/reset-controller.h>
14
15#include <dt-bindings/clock/qcom,gcc-sm8150.h>
16
17#include "common.h"
18#include "clk-alpha-pll.h"
19#include "clk-branch.h"
20#include "clk-pll.h"
21#include "clk-rcg.h"
22#include "clk-regmap.h"
23#include "reset.h"
24
25enum {
26 P_BI_TCXO,
27 P_AUD_REF_CLK,
28 P_CORE_BI_PLL_TEST_SE,
29 P_GPLL0_OUT_EVEN,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL7_OUT_MAIN,
32 P_GPLL9_OUT_MAIN,
33 P_SLEEP_CLK,
34};
35
36static const struct pll_vco trion_vco[] = {
37 { 249600000, 2000000000, 0 },
38};
39
40static struct clk_alpha_pll gpll0 = {
41 .offset = 0x0,
42 .vco_table = trion_vco,
43 .num_vco = ARRAY_SIZE(trion_vco),
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
45 .clkr = {
46 .enable_reg = 0x52000,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
49 .name = "gpll0",
50 .parent_data = &(const struct clk_parent_data){
51 .fw_name = "bi_tcxo",
52 .name = "bi_tcxo",
53 },
54 .num_parents = 1,
55 .ops = &clk_trion_fixed_pll_ops,
56 },
57 },
58};
59
60static const struct clk_div_table post_div_table_trion_even[] = {
61 { 0x0, 1 },
62 { 0x1, 2 },
63 { 0x3, 4 },
64 { 0x7, 8 },
65 { }
66};
67
68static struct clk_alpha_pll_postdiv gpll0_out_even = {
69 .offset = 0x0,
70 .post_div_shift = 8,
71 .post_div_table = post_div_table_trion_even,
72 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
74 .width = 4,
75 .clkr.hw.init = &(struct clk_init_data){
76 .name = "gpll0_out_even",
77 .parent_data = &(const struct clk_parent_data){
78 .fw_name = "bi_tcxo",
79 .name = "bi_tcxo",
80 },
81 .num_parents = 1,
82 .ops = &clk_trion_pll_postdiv_ops,
83 },
84};
85
86static struct clk_alpha_pll gpll7 = {
87 .offset = 0x1a000,
88 .vco_table = trion_vco,
89 .num_vco = ARRAY_SIZE(trion_vco),
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
91 .clkr = {
92 .enable_reg = 0x52000,
93 .enable_mask = BIT(7),
94 .hw.init = &(struct clk_init_data){
95 .name = "gpll7",
96 .parent_data = &(const struct clk_parent_data){
97 .fw_name = "bi_tcxo",
98 .name = "bi_tcxo",
99 },
100 .num_parents = 1,
101 .ops = &clk_trion_fixed_pll_ops,
102 },
103 },
104};
105
106static struct clk_alpha_pll gpll9 = {
107 .offset = 0x1c000,
108 .vco_table = trion_vco,
109 .num_vco = ARRAY_SIZE(trion_vco),
110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
111 .clkr = {
112 .enable_reg = 0x52000,
113 .enable_mask = BIT(9),
114 .hw.init = &(struct clk_init_data){
115 .name = "gpll9",
116 .parent_data = &(const struct clk_parent_data){
117 .fw_name = "bi_tcxo",
118 .name = "bi_tcxo",
119 },
120 .num_parents = 1,
121 .ops = &clk_trion_fixed_pll_ops,
122 },
123 },
124};
125
126static const struct parent_map gcc_parent_map_0[] = {
127 { P_BI_TCXO, 0 },
128 { P_GPLL0_OUT_MAIN, 1 },
129 { P_GPLL0_OUT_EVEN, 6 },
130 { P_CORE_BI_PLL_TEST_SE, 7 },
131};
132
133static const struct clk_parent_data gcc_parents_0[] = {
134 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135 { .hw = &gpll0.clkr.hw },
136 { .hw = &gpll0_out_even.clkr.hw },
137 { .fw_name = "core_bi_pll_test_se" },
138};
139
140static const struct parent_map gcc_parent_map_1[] = {
141 { P_BI_TCXO, 0 },
142 { P_GPLL0_OUT_MAIN, 1 },
143 { P_SLEEP_CLK, 5 },
144 { P_GPLL0_OUT_EVEN, 6 },
145 { P_CORE_BI_PLL_TEST_SE, 7 },
146};
147
148static const struct clk_parent_data gcc_parents_1[] = {
149 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
150 { .hw = &gpll0.clkr.hw },
151 { .fw_name = "sleep_clk", .name = "sleep_clk" },
152 { .hw = &gpll0_out_even.clkr.hw },
153 { .fw_name = "core_bi_pll_test_se" },
154};
155
156static const struct parent_map gcc_parent_map_2[] = {
157 { P_BI_TCXO, 0 },
158 { P_SLEEP_CLK, 5 },
159 { P_CORE_BI_PLL_TEST_SE, 7 },
160};
161
162static const struct clk_parent_data gcc_parents_2[] = {
163 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
164 { .fw_name = "sleep_clk", .name = "sleep_clk" },
165 { .fw_name = "core_bi_pll_test_se" },
166};
167
168static const struct parent_map gcc_parent_map_3[] = {
169 { P_BI_TCXO, 0 },
170 { P_GPLL0_OUT_MAIN, 1 },
171 { P_CORE_BI_PLL_TEST_SE, 7 },
172};
173
174static const struct clk_parent_data gcc_parents_3[] = {
175 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
176 { .hw = &gpll0.clkr.hw },
177 { .fw_name = "core_bi_pll_test_se"},
178};
179
180static const struct parent_map gcc_parent_map_4[] = {
181 { P_BI_TCXO, 0 },
182 { P_CORE_BI_PLL_TEST_SE, 7 },
183};
184
185static const struct clk_parent_data gcc_parents_4[] = {
186 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
187 { .fw_name = "core_bi_pll_test_se" },
188};
189
190static const struct parent_map gcc_parent_map_5[] = {
191 { P_BI_TCXO, 0 },
192 { P_GPLL0_OUT_MAIN, 1 },
193 { P_GPLL7_OUT_MAIN, 3 },
194 { P_GPLL0_OUT_EVEN, 6 },
195 { P_CORE_BI_PLL_TEST_SE, 7 },
196};
197
198static const struct clk_parent_data gcc_parents_5[] = {
199 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
200 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll7.clkr.hw },
202 { .hw = &gpll0_out_even.clkr.hw },
203 { .fw_name = "core_bi_pll_test_se" },
204};
205
206static const struct parent_map gcc_parent_map_6[] = {
207 { P_BI_TCXO, 0 },
208 { P_GPLL0_OUT_MAIN, 1 },
209 { P_GPLL9_OUT_MAIN, 2 },
210 { P_GPLL0_OUT_EVEN, 6 },
211 { P_CORE_BI_PLL_TEST_SE, 7 },
212};
213
214static const struct clk_parent_data gcc_parents_6[] = {
215 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
216 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll9.clkr.hw },
218 { .hw = &gpll0_out_even.clkr.hw },
219 { .fw_name = "core_bi_pll_test_se" },
220};
221
222static const struct parent_map gcc_parent_map_7[] = {
223 { P_BI_TCXO, 0 },
224 { P_GPLL0_OUT_MAIN, 1 },
225 { P_AUD_REF_CLK, 2 },
226 { P_GPLL0_OUT_EVEN, 6 },
227 { P_CORE_BI_PLL_TEST_SE, 7 },
228};
229
230static const struct clk_parent_data gcc_parents_7[] = {
231 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
232 { .hw = &gpll0.clkr.hw },
233 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
234 { .hw = &gpll0_out_even.clkr.hw },
235 { .fw_name = "core_bi_pll_test_se" },
236};
237
238static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
239 F(19200000, P_BI_TCXO, 1, 0, 0),
240 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
241 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
242 { }
243};
244
245static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
246 .cmd_rcgr = 0x48014,
247 .mnd_width = 0,
248 .hid_width = 5,
249 .parent_map = gcc_parent_map_0,
250 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "gcc_cpuss_ahb_clk_src",
253 .parent_data = gcc_parents_0,
254 .num_parents = 4,
255 .flags = CLK_SET_RATE_PARENT,
256 .ops = &clk_rcg2_ops,
257 },
258};
259
260static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
261 F(19200000, P_BI_TCXO, 1, 0, 0),
262 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
263 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
264 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
265 { }
266};
267
268static struct clk_rcg2 gcc_emac_ptp_clk_src = {
269 .cmd_rcgr = 0x6038,
270 .mnd_width = 0,
271 .hid_width = 5,
272 .parent_map = gcc_parent_map_5,
273 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
274 .clkr.hw.init = &(struct clk_init_data){
275 .name = "gcc_emac_ptp_clk_src",
276 .parent_data = gcc_parents_5,
277 .num_parents = 5,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_rcg2_ops,
280 },
281};
282
283static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
284 F(2500000, P_BI_TCXO, 1, 25, 192),
285 F(5000000, P_BI_TCXO, 1, 25, 96),
286 F(19200000, P_BI_TCXO, 1, 0, 0),
287 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
288 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
289 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
290 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
291 { }
292};
293
294static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
295 .cmd_rcgr = 0x601c,
296 .mnd_width = 8,
297 .hid_width = 5,
298 .parent_map = gcc_parent_map_5,
299 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gcc_emac_rgmii_clk_src",
302 .parent_data = gcc_parents_5,
303 .num_parents = 5,
304 .flags = CLK_SET_RATE_PARENT,
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
310 F(19200000, P_BI_TCXO, 1, 0, 0),
311 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
312 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
313 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
314 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
315 { }
316};
317
318static struct clk_rcg2 gcc_gp1_clk_src = {
319 .cmd_rcgr = 0x64004,
320 .mnd_width = 8,
321 .hid_width = 5,
322 .parent_map = gcc_parent_map_1,
323 .freq_tbl = ftbl_gcc_gp1_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "gcc_gp1_clk_src",
326 .parent_data = gcc_parents_1,
327 .num_parents = 5,
328 .flags = CLK_SET_RATE_PARENT,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct clk_rcg2 gcc_gp2_clk_src = {
334 .cmd_rcgr = 0x65004,
335 .mnd_width = 8,
336 .hid_width = 5,
337 .parent_map = gcc_parent_map_1,
338 .freq_tbl = ftbl_gcc_gp1_clk_src,
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "gcc_gp2_clk_src",
341 .parent_data = gcc_parents_1,
342 .num_parents = 5,
343 .flags = CLK_SET_RATE_PARENT,
344 .ops = &clk_rcg2_ops,
345 },
346};
347
348static struct clk_rcg2 gcc_gp3_clk_src = {
349 .cmd_rcgr = 0x66004,
350 .mnd_width = 8,
351 .hid_width = 5,
352 .parent_map = gcc_parent_map_1,
353 .freq_tbl = ftbl_gcc_gp1_clk_src,
354 .clkr.hw.init = &(struct clk_init_data){
355 .name = "gcc_gp3_clk_src",
356 .parent_data = gcc_parents_1,
357 .num_parents = 5,
358 .flags = CLK_SET_RATE_PARENT,
359 .ops = &clk_rcg2_ops,
360 },
361};
362
363static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
364 F(9600000, P_BI_TCXO, 2, 0, 0),
365 F(19200000, P_BI_TCXO, 1, 0, 0),
366 { }
367};
368
369static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
370 .cmd_rcgr = 0x6b02c,
371 .mnd_width = 16,
372 .hid_width = 5,
373 .parent_map = gcc_parent_map_2,
374 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gcc_pcie_0_aux_clk_src",
377 .parent_data = gcc_parents_2,
378 .num_parents = 3,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
381 },
382};
383
384static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
385 .cmd_rcgr = 0x8d02c,
386 .mnd_width = 16,
387 .hid_width = 5,
388 .parent_map = gcc_parent_map_2,
389 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
390 .clkr.hw.init = &(struct clk_init_data){
391 .name = "gcc_pcie_1_aux_clk_src",
392 .parent_data = gcc_parents_2,
393 .num_parents = 3,
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_rcg2_ops,
396 },
397};
398
399static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
400 F(19200000, P_BI_TCXO, 1, 0, 0),
401 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
402 { }
403};
404
405static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
406 .cmd_rcgr = 0x6f014,
407 .mnd_width = 0,
408 .hid_width = 5,
409 .parent_map = gcc_parent_map_0,
410 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gcc_pcie_phy_refgen_clk_src",
413 .parent_data = gcc_parents_0,
414 .num_parents = 4,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_rcg2_ops,
417 },
418};
419
420static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
421 F(9600000, P_BI_TCXO, 2, 0, 0),
422 F(19200000, P_BI_TCXO, 1, 0, 0),
423 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
424 { }
425};
426
427static struct clk_rcg2 gcc_pdm2_clk_src = {
428 .cmd_rcgr = 0x33010,
429 .mnd_width = 0,
430 .hid_width = 5,
431 .parent_map = gcc_parent_map_0,
432 .freq_tbl = ftbl_gcc_pdm2_clk_src,
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "gcc_pdm2_clk_src",
435 .parent_data = gcc_parents_0,
436 .num_parents = 4,
437 .flags = CLK_SET_RATE_PARENT,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
443 F(19200000, P_BI_TCXO, 1, 0, 0),
444 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
445 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
446 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
447 { }
448};
449
450static struct clk_rcg2 gcc_qspi_core_clk_src = {
451 .cmd_rcgr = 0x4b008,
452 .mnd_width = 0,
453 .hid_width = 5,
454 .parent_map = gcc_parent_map_0,
455 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "gcc_qspi_core_clk_src",
458 .parent_data = gcc_parents_0,
459 .num_parents = 4,
460 .flags = CLK_SET_RATE_PARENT,
461 .ops = &clk_rcg2_ops,
462 },
463};
464
465static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
466 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
467 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
468 F(19200000, P_BI_TCXO, 1, 0, 0),
469 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
470 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
471 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
472 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
473 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
474 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
475 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
476 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
477 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
478 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
479 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
480 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
481 { }
482};
483
484static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
485 .cmd_rcgr = 0x17148,
486 .mnd_width = 16,
487 .hid_width = 5,
488 .parent_map = gcc_parent_map_0,
489 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
490 .clkr.hw.init = &(struct clk_init_data){
491 .name = "gcc_qupv3_wrap0_s0_clk_src",
492 .parent_data = gcc_parents_0,
493 .num_parents = 4,
494 .flags = CLK_SET_RATE_PARENT,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
500 .cmd_rcgr = 0x17278,
501 .mnd_width = 16,
502 .hid_width = 5,
503 .parent_map = gcc_parent_map_0,
504 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "gcc_qupv3_wrap0_s1_clk_src",
507 .parent_data = gcc_parents_0,
508 .num_parents = 4,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
515 .cmd_rcgr = 0x173a8,
516 .mnd_width = 16,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_0,
519 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "gcc_qupv3_wrap0_s2_clk_src",
522 .parent_data = gcc_parents_0,
523 .num_parents = 4,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_rcg2_ops,
526 },
527};
528
529static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
530 .cmd_rcgr = 0x174d8,
531 .mnd_width = 16,
532 .hid_width = 5,
533 .parent_map = gcc_parent_map_0,
534 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
535 .clkr.hw.init = &(struct clk_init_data){
536 .name = "gcc_qupv3_wrap0_s3_clk_src",
537 .parent_data = gcc_parents_0,
538 .num_parents = 4,
539 .flags = CLK_SET_RATE_PARENT,
540 .ops = &clk_rcg2_ops,
541 },
542};
543
544static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
545 .cmd_rcgr = 0x17608,
546 .mnd_width = 16,
547 .hid_width = 5,
548 .parent_map = gcc_parent_map_0,
549 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "gcc_qupv3_wrap0_s4_clk_src",
552 .parent_data = gcc_parents_0,
553 .num_parents = 4,
554 .flags = CLK_SET_RATE_PARENT,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
560 .cmd_rcgr = 0x17738,
561 .mnd_width = 16,
562 .hid_width = 5,
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "gcc_qupv3_wrap0_s5_clk_src",
567 .parent_data = gcc_parents_0,
568 .num_parents = 4,
569 .flags = CLK_SET_RATE_PARENT,
570 .ops = &clk_rcg2_ops,
571 },
572};
573
574static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
575 .cmd_rcgr = 0x17868,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_0,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "gcc_qupv3_wrap0_s6_clk_src",
582 .parent_data = gcc_parents_0,
583 .num_parents = 4,
584 .flags = CLK_SET_RATE_PARENT,
585 .ops = &clk_rcg2_ops,
586 },
587};
588
589static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
590 .cmd_rcgr = 0x17998,
591 .mnd_width = 16,
592 .hid_width = 5,
593 .parent_map = gcc_parent_map_0,
594 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
595 .clkr.hw.init = &(struct clk_init_data){
596 .name = "gcc_qupv3_wrap0_s7_clk_src",
597 .parent_data = gcc_parents_0,
598 .num_parents = 4,
599 .flags = CLK_SET_RATE_PARENT,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
605 .cmd_rcgr = 0x18148,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "gcc_qupv3_wrap1_s0_clk_src",
612 .parent_data = gcc_parents_0,
613 .num_parents = 4,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
620 .cmd_rcgr = 0x18278,
621 .mnd_width = 16,
622 .hid_width = 5,
623 .parent_map = gcc_parent_map_0,
624 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "gcc_qupv3_wrap1_s1_clk_src",
627 .parent_data = gcc_parents_0,
628 .num_parents = 4,
629 .flags = CLK_SET_RATE_PARENT,
630 .ops = &clk_rcg2_ops,
631 },
632};
633
634static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
635 .cmd_rcgr = 0x183a8,
636 .mnd_width = 16,
637 .hid_width = 5,
638 .parent_map = gcc_parent_map_0,
639 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "gcc_qupv3_wrap1_s2_clk_src",
642 .parent_data = gcc_parents_0,
643 .num_parents = 4,
644 .flags = CLK_SET_RATE_PARENT,
645 .ops = &clk_rcg2_ops,
646 },
647};
648
649static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
650 .cmd_rcgr = 0x184d8,
651 .mnd_width = 16,
652 .hid_width = 5,
653 .parent_map = gcc_parent_map_0,
654 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "gcc_qupv3_wrap1_s3_clk_src",
657 .parent_data = gcc_parents_0,
658 .num_parents = 4,
659 .flags = CLK_SET_RATE_PARENT,
660 .ops = &clk_rcg2_ops,
661 },
662};
663
664static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
665 .cmd_rcgr = 0x18608,
666 .mnd_width = 16,
667 .hid_width = 5,
668 .parent_map = gcc_parent_map_0,
669 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "gcc_qupv3_wrap1_s4_clk_src",
672 .parent_data = gcc_parents_0,
673 .num_parents = 4,
674 .flags = CLK_SET_RATE_PARENT,
675 .ops = &clk_rcg2_ops,
676 },
677};
678
679static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
680 .cmd_rcgr = 0x18738,
681 .mnd_width = 16,
682 .hid_width = 5,
683 .parent_map = gcc_parent_map_0,
684 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "gcc_qupv3_wrap1_s5_clk_src",
687 .parent_data = gcc_parents_0,
688 .num_parents = 4,
689 .flags = CLK_SET_RATE_PARENT,
690 .ops = &clk_rcg2_ops,
691 },
692};
693
694static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
695 .cmd_rcgr = 0x1e148,
696 .mnd_width = 16,
697 .hid_width = 5,
698 .parent_map = gcc_parent_map_0,
699 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "gcc_qupv3_wrap2_s0_clk_src",
702 .parent_data = gcc_parents_0,
703 .num_parents = 4,
704 .flags = CLK_SET_RATE_PARENT,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
710 .cmd_rcgr = 0x1e278,
711 .mnd_width = 16,
712 .hid_width = 5,
713 .parent_map = gcc_parent_map_0,
714 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "gcc_qupv3_wrap2_s1_clk_src",
717 .parent_data = gcc_parents_0,
718 .num_parents = 4,
719 .flags = CLK_SET_RATE_PARENT,
720 .ops = &clk_rcg2_ops,
721 },
722};
723
724static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
725 .cmd_rcgr = 0x1e3a8,
726 .mnd_width = 16,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_0,
729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "gcc_qupv3_wrap2_s2_clk_src",
732 .parent_data = gcc_parents_0,
733 .num_parents = 4,
734 .flags = CLK_SET_RATE_PARENT,
735 .ops = &clk_rcg2_ops,
736 },
737};
738
739static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
740 .cmd_rcgr = 0x1e4d8,
741 .mnd_width = 16,
742 .hid_width = 5,
743 .parent_map = gcc_parent_map_0,
744 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "gcc_qupv3_wrap2_s3_clk_src",
747 .parent_data = gcc_parents_0,
748 .num_parents = 4,
749 .flags = CLK_SET_RATE_PARENT,
750 .ops = &clk_rcg2_ops,
751 },
752};
753
754static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
755 .cmd_rcgr = 0x1e608,
756 .mnd_width = 16,
757 .hid_width = 5,
758 .parent_map = gcc_parent_map_0,
759 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "gcc_qupv3_wrap2_s4_clk_src",
762 .parent_data = gcc_parents_0,
763 .num_parents = 4,
764 .flags = CLK_SET_RATE_PARENT,
765 .ops = &clk_rcg2_ops,
766 },
767};
768
769static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
770 .cmd_rcgr = 0x1e738,
771 .mnd_width = 16,
772 .hid_width = 5,
773 .parent_map = gcc_parent_map_0,
774 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "gcc_qupv3_wrap2_s5_clk_src",
777 .parent_data = gcc_parents_0,
778 .num_parents = 4,
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_rcg2_ops,
781 },
782};
783
784static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
785 F(400000, P_BI_TCXO, 12, 1, 4),
786 F(9600000, P_BI_TCXO, 2, 0, 0),
787 F(19200000, P_BI_TCXO, 1, 0, 0),
788 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
789 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
790 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
791 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
796 .cmd_rcgr = 0x1400c,
797 .mnd_width = 8,
798 .hid_width = 5,
799 .parent_map = gcc_parent_map_6,
800 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "gcc_sdcc2_apps_clk_src",
803 .parent_data = gcc_parents_6,
804 .num_parents = 5,
805 .flags = CLK_SET_RATE_PARENT,
806 .ops = &clk_rcg2_floor_ops,
807 },
808};
809
810static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
811 F(400000, P_BI_TCXO, 12, 1, 4),
812 F(9600000, P_BI_TCXO, 2, 0, 0),
813 F(19200000, P_BI_TCXO, 1, 0, 0),
814 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
815 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
816 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
817 { }
818};
819
820static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
821 .cmd_rcgr = 0x1600c,
822 .mnd_width = 8,
823 .hid_width = 5,
824 .parent_map = gcc_parent_map_3,
825 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "gcc_sdcc4_apps_clk_src",
828 .parent_data = gcc_parents_3,
829 .num_parents = 3,
830 .flags = CLK_SET_RATE_PARENT,
831 .ops = &clk_rcg2_floor_ops,
832 },
833};
834
835static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
836 F(105495, P_BI_TCXO, 2, 1, 91),
837 { }
838};
839
840static struct clk_rcg2 gcc_tsif_ref_clk_src = {
841 .cmd_rcgr = 0x36010,
842 .mnd_width = 8,
843 .hid_width = 5,
844 .parent_map = gcc_parent_map_7,
845 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
846 .clkr.hw.init = &(struct clk_init_data){
847 .name = "gcc_tsif_ref_clk_src",
848 .parent_data = gcc_parents_7,
849 .num_parents = 5,
850 .flags = CLK_SET_RATE_PARENT,
851 .ops = &clk_rcg2_ops,
852 },
853};
854
855static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
856 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
857 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
858 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
859 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
860 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
861 { }
862};
863
864static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
865 .cmd_rcgr = 0x75020,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_0,
869 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "gcc_ufs_card_axi_clk_src",
872 .parent_data = gcc_parents_0,
873 .num_parents = 4,
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
880 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
881 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
882 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
883 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
884 { }
885};
886
887static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
888 .cmd_rcgr = 0x75060,
889 .mnd_width = 0,
890 .hid_width = 5,
891 .parent_map = gcc_parent_map_0,
892 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "gcc_ufs_card_ice_core_clk_src",
895 .parent_data = gcc_parents_0,
896 .num_parents = 4,
897 .flags = CLK_SET_RATE_PARENT,
898 .ops = &clk_rcg2_ops,
899 },
900};
901
902static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
903 F(19200000, P_BI_TCXO, 1, 0, 0),
904 { }
905};
906
907static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
908 .cmd_rcgr = 0x75094,
909 .mnd_width = 0,
910 .hid_width = 5,
911 .parent_map = gcc_parent_map_4,
912 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
913 .clkr.hw.init = &(struct clk_init_data){
914 .name = "gcc_ufs_card_phy_aux_clk_src",
915 .parent_data = gcc_parents_4,
916 .num_parents = 2,
917 .flags = CLK_SET_RATE_PARENT,
918 .ops = &clk_rcg2_ops,
919 },
920};
921
922static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
923 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
924 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
925 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
926 { }
927};
928
929static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
930 .cmd_rcgr = 0x75078,
931 .mnd_width = 0,
932 .hid_width = 5,
933 .parent_map = gcc_parent_map_0,
934 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "gcc_ufs_card_unipro_core_clk_src",
937 .parent_data = gcc_parents_0,
938 .num_parents = 4,
939 .flags = CLK_SET_RATE_PARENT,
940 .ops = &clk_rcg2_ops,
941 },
942};
943
944static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
945 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
946 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
947 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
948 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
949 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
950 { }
951};
952
953static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
954 .cmd_rcgr = 0x77020,
955 .mnd_width = 8,
956 .hid_width = 5,
957 .parent_map = gcc_parent_map_0,
958 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "gcc_ufs_phy_axi_clk_src",
961 .parent_data = gcc_parents_0,
962 .num_parents = 4,
963 .flags = CLK_SET_RATE_PARENT,
964 .ops = &clk_rcg2_ops,
965 },
966};
967
968static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
969 .cmd_rcgr = 0x77060,
970 .mnd_width = 0,
971 .hid_width = 5,
972 .parent_map = gcc_parent_map_0,
973 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_ufs_phy_ice_core_clk_src",
976 .parent_data = gcc_parents_0,
977 .num_parents = 4,
978 .flags = CLK_SET_RATE_PARENT,
979 .ops = &clk_rcg2_ops,
980 },
981};
982
983static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
984 .cmd_rcgr = 0x77094,
985 .mnd_width = 0,
986 .hid_width = 5,
987 .parent_map = gcc_parent_map_4,
988 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
989 .clkr.hw.init = &(struct clk_init_data){
990 .name = "gcc_ufs_phy_phy_aux_clk_src",
991 .parent_data = gcc_parents_4,
992 .num_parents = 2,
993 .flags = CLK_SET_RATE_PARENT,
994 .ops = &clk_rcg2_ops,
995 },
996};
997
998static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
999 .cmd_rcgr = 0x77078,
1000 .mnd_width = 0,
1001 .hid_width = 5,
1002 .parent_map = gcc_parent_map_0,
1003 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "gcc_ufs_phy_unipro_core_clk_src",
1006 .parent_data = gcc_parents_0,
1007 .num_parents = 4,
1008 .flags = CLK_SET_RATE_PARENT,
1009 .ops = &clk_rcg2_ops,
1010 },
1011};
1012
1013static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1014 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1015 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1016 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1017 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1018 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1019 { }
1020};
1021
1022static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1023 .cmd_rcgr = 0xf01c,
1024 .mnd_width = 8,
1025 .hid_width = 5,
1026 .parent_map = gcc_parent_map_0,
1027 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "gcc_usb30_prim_master_clk_src",
1030 .parent_data = gcc_parents_0,
1031 .num_parents = 4,
1032 .flags = CLK_SET_RATE_PARENT,
1033 .ops = &clk_rcg2_ops,
1034 },
1035};
1036
1037static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1038 F(19200000, P_BI_TCXO, 1, 0, 0),
1039 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1040 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1045 .cmd_rcgr = 0xf034,
1046 .mnd_width = 0,
1047 .hid_width = 5,
1048 .parent_map = gcc_parent_map_0,
1049 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1050 .clkr.hw.init = &(struct clk_init_data){
1051 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1052 .parent_data = gcc_parents_0,
1053 .num_parents = 4,
1054 .flags = CLK_SET_RATE_PARENT,
1055 .ops = &clk_rcg2_ops,
1056 },
1057};
1058
1059static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1060 .cmd_rcgr = 0x1001c,
1061 .mnd_width = 8,
1062 .hid_width = 5,
1063 .parent_map = gcc_parent_map_0,
1064 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "gcc_usb30_sec_master_clk_src",
1067 .parent_data = gcc_parents_0,
1068 .num_parents = 4,
1069 .flags = CLK_SET_RATE_PARENT,
1070 .ops = &clk_rcg2_ops,
1071 },
1072};
1073
1074static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1075 .cmd_rcgr = 0x10034,
1076 .mnd_width = 0,
1077 .hid_width = 5,
1078 .parent_map = gcc_parent_map_0,
1079 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1080 .clkr.hw.init = &(struct clk_init_data){
1081 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1082 .parent_data = gcc_parents_0,
1083 .num_parents = 4,
1084 .flags = CLK_SET_RATE_PARENT,
1085 .ops = &clk_rcg2_ops,
1086 },
1087};
1088
1089static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1090 .cmd_rcgr = 0xf060,
1091 .mnd_width = 0,
1092 .hid_width = 5,
1093 .parent_map = gcc_parent_map_2,
1094 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1095 .clkr.hw.init = &(struct clk_init_data){
1096 .name = "gcc_usb3_prim_phy_aux_clk_src",
1097 .parent_data = gcc_parents_2,
1098 .num_parents = 3,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_rcg2_ops,
1101 },
1102};
1103
1104static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1105 .cmd_rcgr = 0x10060,
1106 .mnd_width = 0,
1107 .hid_width = 5,
1108 .parent_map = gcc_parent_map_2,
1109 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_usb3_sec_phy_aux_clk_src",
1112 .parent_data = gcc_parents_2,
1113 .num_parents = 3,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1120 .halt_reg = 0x90018,
1121 .halt_check = BRANCH_HALT,
1122 .clkr = {
1123 .enable_reg = 0x90018,
1124 .enable_mask = BIT(0),
1125 .hw.init = &(struct clk_init_data){
1126 .name = "gcc_aggre_noc_pcie_tbu_clk",
1127 .ops = &clk_branch2_ops,
1128 },
1129 },
1130};
1131
1132static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1133 .halt_reg = 0x750c0,
1134 .halt_check = BRANCH_HALT,
1135 .hwcg_reg = 0x750c0,
1136 .hwcg_bit = 1,
1137 .clkr = {
1138 .enable_reg = 0x750c0,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(struct clk_init_data){
1141 .name = "gcc_aggre_ufs_card_axi_clk",
1142 .parent_hws = (const struct clk_hw *[]){
1143 &gcc_ufs_card_axi_clk_src.clkr.hw },
1144 .num_parents = 1,
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1147 },
1148 },
1149};
1150
1151static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1152 .halt_reg = 0x750c0,
1153 .halt_check = BRANCH_HALT,
1154 .hwcg_reg = 0x750c0,
1155 .hwcg_bit = 1,
1156 .clkr = {
1157 .enable_reg = 0x750c0,
1158 .enable_mask = BIT(1),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1161 .parent_hws = (const struct clk_hw *[]){
1162 &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch_simple_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1171 .halt_reg = 0x770c0,
1172 .halt_check = BRANCH_HALT,
1173 .hwcg_reg = 0x770c0,
1174 .hwcg_bit = 1,
1175 .clkr = {
1176 .enable_reg = 0x770c0,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_aggre_ufs_phy_axi_clk",
1180 .parent_hws = (const struct clk_hw *[]){
1181 &gcc_ufs_phy_axi_clk_src.clkr.hw },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1190 .halt_reg = 0x770c0,
1191 .halt_check = BRANCH_HALT,
1192 .hwcg_reg = 0x770c0,
1193 .hwcg_bit = 1,
1194 .clkr = {
1195 .enable_reg = 0x770c0,
1196 .enable_mask = BIT(1),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1199 .parent_hws = (const struct clk_hw *[]){
1200 &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1201 .num_parents = 1,
1202 .flags = CLK_SET_RATE_PARENT,
1203 .ops = &clk_branch_simple_ops,
1204 },
1205 },
1206};
1207
1208static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1209 .halt_reg = 0xf07c,
1210 .halt_check = BRANCH_HALT,
1211 .clkr = {
1212 .enable_reg = 0xf07c,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "gcc_aggre_usb3_prim_axi_clk",
1216 .parent_hws = (const struct clk_hw *[]){
1217 &gcc_usb30_prim_master_clk_src.clkr.hw },
1218 .num_parents = 1,
1219 .flags = CLK_SET_RATE_PARENT,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223};
1224
1225static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1226 .halt_reg = 0x1007c,
1227 .halt_check = BRANCH_HALT,
1228 .clkr = {
1229 .enable_reg = 0x1007c,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "gcc_aggre_usb3_sec_axi_clk",
1233 .parent_hws = (const struct clk_hw *[]){
1234 &gcc_usb30_sec_master_clk_src.clkr.hw },
1235 .num_parents = 1,
1236 .flags = CLK_SET_RATE_PARENT,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch gcc_boot_rom_ahb_clk = {
1243 .halt_reg = 0x38004,
1244 .halt_check = BRANCH_HALT_VOTED,
1245 .hwcg_reg = 0x38004,
1246 .hwcg_bit = 1,
1247 .clkr = {
1248 .enable_reg = 0x52004,
1249 .enable_mask = BIT(10),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_boot_rom_ahb_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257/*
1258 * Clock ON depends on external parent 'config noc', so cant poll
1259 * delay and also mark as crtitical for camss boot
1260 */
1261static struct clk_branch gcc_camera_ahb_clk = {
1262 .halt_reg = 0xb008,
1263 .halt_check = BRANCH_HALT_DELAY,
1264 .hwcg_reg = 0xb008,
1265 .hwcg_bit = 1,
1266 .clkr = {
1267 .enable_reg = 0xb008,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "gcc_camera_ahb_clk",
1271 .flags = CLK_IS_CRITICAL,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275};
1276
1277static struct clk_branch gcc_camera_hf_axi_clk = {
1278 .halt_reg = 0xb030,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0xb030,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_camera_hf_axi_clk",
1285 .ops = &clk_branch2_ops,
1286 },
1287 },
1288};
1289
1290static struct clk_branch gcc_camera_sf_axi_clk = {
1291 .halt_reg = 0xb034,
1292 .halt_check = BRANCH_HALT,
1293 .clkr = {
1294 .enable_reg = 0xb034,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_camera_sf_axi_clk",
1298 .ops = &clk_branch2_ops,
1299 },
1300 },
1301};
1302
1303/* XO critical input to camss, so no need to poll */
1304static struct clk_branch gcc_camera_xo_clk = {
1305 .halt_reg = 0xb044,
1306 .halt_check = BRANCH_HALT_DELAY,
1307 .clkr = {
1308 .enable_reg = 0xb044,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_camera_xo_clk",
1312 .flags = CLK_IS_CRITICAL,
1313 .ops = &clk_branch2_ops,
1314 },
1315 },
1316};
1317
1318static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1319 .halt_reg = 0xf078,
1320 .halt_check = BRANCH_HALT,
1321 .clkr = {
1322 .enable_reg = 0xf078,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1326 .parent_hws = (const struct clk_hw *[]){
1327 &gcc_usb30_prim_master_clk_src.clkr.hw },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1336 .halt_reg = 0x10078,
1337 .halt_check = BRANCH_HALT,
1338 .clkr = {
1339 .enable_reg = 0x10078,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1343 .parent_hws = (const struct clk_hw *[]){
1344 &gcc_usb30_sec_master_clk_src.clkr.hw },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350};
1351
1352static struct clk_branch gcc_cpuss_ahb_clk = {
1353 .halt_reg = 0x48000,
1354 .halt_check = BRANCH_HALT_VOTED,
1355 .clkr = {
1356 .enable_reg = 0x52004,
1357 .enable_mask = BIT(21),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "gcc_cpuss_ahb_clk",
1360 .parent_hws = (const struct clk_hw *[]){
1361 &gcc_cpuss_ahb_clk_src.clkr.hw },
1362 .num_parents = 1,
1363 /* required for cpuss */
1364 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1366 },
1367 },
1368};
1369
1370static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1371 .halt_reg = 0x48190,
1372 .halt_check = BRANCH_HALT,
1373 .clkr = {
1374 .enable_reg = 0x48190,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "gcc_cpuss_dvm_bus_clk",
1378 /* required for cpuss */
1379 .flags = CLK_IS_CRITICAL,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383};
1384
1385static struct clk_branch gcc_cpuss_gnoc_clk = {
1386 .halt_reg = 0x48004,
1387 .halt_check = BRANCH_HALT_VOTED,
1388 .hwcg_reg = 0x48004,
1389 .hwcg_bit = 1,
1390 .clkr = {
1391 .enable_reg = 0x52004,
1392 .enable_mask = BIT(22),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gcc_cpuss_gnoc_clk",
1395 /* required for cpuss */
1396 .flags = CLK_IS_CRITICAL,
1397 .ops = &clk_branch2_ops,
1398 },
1399 },
1400};
1401
1402static struct clk_branch gcc_cpuss_rbcpr_clk = {
1403 .halt_reg = 0x48008,
1404 .halt_check = BRANCH_HALT,
1405 .clkr = {
1406 .enable_reg = 0x48008,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_cpuss_rbcpr_clk",
1410 .ops = &clk_branch2_ops,
1411 },
1412 },
1413};
1414
1415static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1416 .halt_reg = 0x71154,
1417 .halt_check = BRANCH_VOTED,
1418 .clkr = {
1419 .enable_reg = 0x71154,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_ddrss_gpu_axi_clk",
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428/*
1429 * Clock ON depends on external parent 'config noc', so cant poll
1430 * delay and also mark as crtitical for disp boot
1431 */
1432static struct clk_branch gcc_disp_ahb_clk = {
1433 .halt_reg = 0xb00c,
1434 .halt_check = BRANCH_HALT_DELAY,
1435 .hwcg_reg = 0xb00c,
1436 .hwcg_bit = 1,
1437 .clkr = {
1438 .enable_reg = 0xb00c,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_disp_ahb_clk",
1442 .flags = CLK_IS_CRITICAL,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446};
1447
1448static struct clk_branch gcc_disp_hf_axi_clk = {
1449 .halt_reg = 0xb038,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0xb038,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_disp_hf_axi_clk",
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_disp_sf_axi_clk = {
1462 .halt_reg = 0xb03c,
1463 .halt_check = BRANCH_HALT,
1464 .clkr = {
1465 .enable_reg = 0xb03c,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_disp_sf_axi_clk",
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474/* XO critical input to disp, so no need to poll */
1475static struct clk_branch gcc_disp_xo_clk = {
1476 .halt_reg = 0xb048,
1477 .halt_check = BRANCH_HALT_DELAY,
1478 .clkr = {
1479 .enable_reg = 0xb048,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_disp_xo_clk",
1483 .flags = CLK_IS_CRITICAL,
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_emac_axi_clk = {
1490 .halt_reg = 0x6010,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6010,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_emac_axi_clk",
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500};
1501
1502static struct clk_branch gcc_emac_ptp_clk = {
1503 .halt_reg = 0x6034,
1504 .halt_check = BRANCH_HALT,
1505 .clkr = {
1506 .enable_reg = 0x6034,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "gcc_emac_ptp_clk",
1510 .parent_hws = (const struct clk_hw *[]){
1511 &gcc_emac_ptp_clk_src.clkr.hw },
1512 .num_parents = 1,
1513 .flags = CLK_SET_RATE_PARENT,
1514 .ops = &clk_branch2_ops,
1515 },
1516 },
1517};
1518
1519static struct clk_branch gcc_emac_rgmii_clk = {
1520 .halt_reg = 0x6018,
1521 .halt_check = BRANCH_HALT,
1522 .clkr = {
1523 .enable_reg = 0x6018,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "gcc_emac_rgmii_clk",
1527 .parent_hws = (const struct clk_hw *[]){
1528 &gcc_emac_rgmii_clk_src.clkr.hw },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch gcc_emac_slv_ahb_clk = {
1537 .halt_reg = 0x6014,
1538 .halt_check = BRANCH_HALT,
1539 .hwcg_reg = 0x6014,
1540 .hwcg_bit = 1,
1541 .clkr = {
1542 .enable_reg = 0x6014,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_emac_slv_ahb_clk",
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549};
1550
1551static struct clk_branch gcc_gp1_clk = {
1552 .halt_reg = 0x64000,
1553 .halt_check = BRANCH_HALT,
1554 .clkr = {
1555 .enable_reg = 0x64000,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_gp1_clk",
1559 .parent_hws = (const struct clk_hw *[]){
1560 &gcc_gp1_clk_src.clkr.hw },
1561 .num_parents = 1,
1562 .flags = CLK_SET_RATE_PARENT,
1563 .ops = &clk_branch2_ops,
1564 },
1565 },
1566};
1567
1568static struct clk_branch gcc_gp2_clk = {
1569 .halt_reg = 0x65000,
1570 .halt_check = BRANCH_HALT,
1571 .clkr = {
1572 .enable_reg = 0x65000,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_gp2_clk",
1576 .parent_hws = (const struct clk_hw *[]){
1577 &gcc_gp2_clk_src.clkr.hw },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583};
1584
1585static struct clk_branch gcc_gp3_clk = {
1586 .halt_reg = 0x66000,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x66000,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_gp3_clk",
1593 .parent_hws = (const struct clk_hw *[]){
1594 &gcc_gp3_clk_src.clkr.hw },
1595 .num_parents = 1,
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1598 },
1599 },
1600};
1601
1602static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1603 .halt_reg = 0x71004,
1604 .halt_check = BRANCH_HALT,
1605 .hwcg_reg = 0x71004,
1606 .hwcg_bit = 1,
1607 .clkr = {
1608 .enable_reg = 0x71004,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_gpu_cfg_ahb_clk",
1612 /* required for gpu */
1613 .flags = CLK_IS_CRITICAL,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch gcc_gpu_iref_clk = {
1620 .halt_reg = 0x8c010,
1621 .halt_check = BRANCH_HALT,
1622 .clkr = {
1623 .enable_reg = 0x8c010,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_gpu_iref_clk",
1627 .ops = &clk_branch2_ops,
1628 },
1629 },
1630};
1631
1632static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1633 .halt_reg = 0x7100c,
1634 .halt_check = BRANCH_VOTED,
1635 .clkr = {
1636 .enable_reg = 0x7100c,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "gcc_gpu_memnoc_gfx_clk",
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1646 .halt_reg = 0x71018,
1647 .halt_check = BRANCH_HALT,
1648 .clkr = {
1649 .enable_reg = 0x71018,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656};
1657
1658static struct clk_branch gcc_npu_at_clk = {
1659 .halt_reg = 0x4d010,
1660 .halt_check = BRANCH_VOTED,
1661 .clkr = {
1662 .enable_reg = 0x4d010,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_npu_at_clk",
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch gcc_npu_axi_clk = {
1672 .halt_reg = 0x4d008,
1673 .halt_check = BRANCH_VOTED,
1674 .clkr = {
1675 .enable_reg = 0x4d008,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "gcc_npu_axi_clk",
1679 .ops = &clk_branch2_ops,
1680 },
1681 },
1682};
1683
1684static struct clk_branch gcc_npu_cfg_ahb_clk = {
1685 .halt_reg = 0x4d004,
1686 .halt_check = BRANCH_HALT,
1687 .hwcg_reg = 0x4d004,
1688 .hwcg_bit = 1,
1689 .clkr = {
1690 .enable_reg = 0x4d004,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "gcc_npu_cfg_ahb_clk",
1694 /* required for npu */
1695 .flags = CLK_IS_CRITICAL,
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699};
1700
1701static struct clk_branch gcc_npu_trig_clk = {
1702 .halt_reg = 0x4d00c,
1703 .halt_check = BRANCH_VOTED,
1704 .clkr = {
1705 .enable_reg = 0x4d00c,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "gcc_npu_trig_clk",
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712};
1713
1714static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1715 .halt_reg = 0x6f02c,
1716 .halt_check = BRANCH_HALT,
1717 .clkr = {
1718 .enable_reg = 0x6f02c,
1719 .enable_mask = BIT(0),
1720 .hw.init = &(struct clk_init_data){
1721 .name = "gcc_pcie0_phy_refgen_clk",
1722 .parent_hws = (const struct clk_hw *[]){
1723 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1724 .num_parents = 1,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1732 .halt_reg = 0x6f030,
1733 .halt_check = BRANCH_HALT,
1734 .clkr = {
1735 .enable_reg = 0x6f030,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_pcie1_phy_refgen_clk",
1739 .parent_hws = (const struct clk_hw *[]){
1740 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1741 .num_parents = 1,
1742 .flags = CLK_SET_RATE_PARENT,
1743 .ops = &clk_branch2_ops,
1744 },
1745 },
1746};
1747
1748static struct clk_branch gcc_pcie_0_aux_clk = {
1749 .halt_reg = 0x6b020,
1750 .halt_check = BRANCH_HALT_VOTED,
1751 .clkr = {
1752 .enable_reg = 0x5200c,
1753 .enable_mask = BIT(3),
1754 .hw.init = &(struct clk_init_data){
1755 .name = "gcc_pcie_0_aux_clk",
1756 .parent_hws = (const struct clk_hw *[]){
1757 &gcc_pcie_0_aux_clk_src.clkr.hw },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1766 .halt_reg = 0x6b01c,
1767 .halt_check = BRANCH_HALT_VOTED,
1768 .hwcg_reg = 0x6b01c,
1769 .hwcg_bit = 1,
1770 .clkr = {
1771 .enable_reg = 0x5200c,
1772 .enable_mask = BIT(2),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_pcie_0_cfg_ahb_clk",
1775 .ops = &clk_branch2_ops,
1776 },
1777 },
1778};
1779
1780static struct clk_branch gcc_pcie_0_clkref_clk = {
1781 .halt_reg = 0x8c00c,
1782 .halt_check = BRANCH_HALT,
1783 .clkr = {
1784 .enable_reg = 0x8c00c,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_pcie_0_clkref_clk",
1788 .ops = &clk_branch2_ops,
1789 },
1790 },
1791};
1792
1793static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1794 .halt_reg = 0x6b018,
1795 .halt_check = BRANCH_HALT_VOTED,
1796 .clkr = {
1797 .enable_reg = 0x5200c,
1798 .enable_mask = BIT(1),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "gcc_pcie_0_mstr_axi_clk",
1801 .ops = &clk_branch2_ops,
1802 },
1803 },
1804};
1805
1806/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1807static struct clk_branch gcc_pcie_0_pipe_clk = {
1808 .halt_reg = 0x6b024,
1809 .halt_check = BRANCH_HALT_DELAY,
1810 .clkr = {
1811 .enable_reg = 0x5200c,
1812 .enable_mask = BIT(4),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_pcie_0_pipe_clk",
1815 .ops = &clk_branch2_ops,
1816 },
1817 },
1818};
1819
1820static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1821 .halt_reg = 0x6b014,
1822 .halt_check = BRANCH_HALT_VOTED,
1823 .hwcg_reg = 0x6b014,
1824 .hwcg_bit = 1,
1825 .clkr = {
1826 .enable_reg = 0x5200c,
1827 .enable_mask = BIT(0),
1828 .hw.init = &(struct clk_init_data){
1829 .name = "gcc_pcie_0_slv_axi_clk",
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833};
1834
1835static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1836 .halt_reg = 0x6b010,
1837 .halt_check = BRANCH_HALT_VOTED,
1838 .clkr = {
1839 .enable_reg = 0x5200c,
1840 .enable_mask = BIT(5),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1843 .ops = &clk_branch2_ops,
1844 },
1845 },
1846};
1847
1848static struct clk_branch gcc_pcie_1_aux_clk = {
1849 .halt_reg = 0x8d020,
1850 .halt_check = BRANCH_HALT_VOTED,
1851 .clkr = {
1852 .enable_reg = 0x52004,
1853 .enable_mask = BIT(29),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_pcie_1_aux_clk",
1856 .parent_hws = (const struct clk_hw *[]){
1857 &gcc_pcie_1_aux_clk_src.clkr.hw },
1858 .num_parents = 1,
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863};
1864
1865static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1866 .halt_reg = 0x8d01c,
1867 .halt_check = BRANCH_HALT_VOTED,
1868 .hwcg_reg = 0x8d01c,
1869 .hwcg_bit = 1,
1870 .clkr = {
1871 .enable_reg = 0x52004,
1872 .enable_mask = BIT(28),
1873 .hw.init = &(struct clk_init_data){
1874 .name = "gcc_pcie_1_cfg_ahb_clk",
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878};
1879
1880static struct clk_branch gcc_pcie_1_clkref_clk = {
1881 .halt_reg = 0x8c02c,
1882 .halt_check = BRANCH_HALT,
1883 .clkr = {
1884 .enable_reg = 0x8c02c,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "gcc_pcie_1_clkref_clk",
1888 .ops = &clk_branch2_ops,
1889 },
1890 },
1891};
1892
1893static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1894 .halt_reg = 0x8d018,
1895 .halt_check = BRANCH_HALT_VOTED,
1896 .clkr = {
1897 .enable_reg = 0x52004,
1898 .enable_mask = BIT(27),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "gcc_pcie_1_mstr_axi_clk",
1901 .ops = &clk_branch2_ops,
1902 },
1903 },
1904};
1905
1906/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1907static struct clk_branch gcc_pcie_1_pipe_clk = {
1908 .halt_reg = 0x8d024,
1909 .halt_check = BRANCH_HALT_DELAY,
1910 .clkr = {
1911 .enable_reg = 0x52004,
1912 .enable_mask = BIT(30),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "gcc_pcie_1_pipe_clk",
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1921 .halt_reg = 0x8d014,
1922 .halt_check = BRANCH_HALT_VOTED,
1923 .hwcg_reg = 0x8d014,
1924 .hwcg_bit = 1,
1925 .clkr = {
1926 .enable_reg = 0x52004,
1927 .enable_mask = BIT(26),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_pcie_1_slv_axi_clk",
1930 .ops = &clk_branch2_ops,
1931 },
1932 },
1933};
1934
1935static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1936 .halt_reg = 0x8d010,
1937 .halt_check = BRANCH_HALT_VOTED,
1938 .clkr = {
1939 .enable_reg = 0x52004,
1940 .enable_mask = BIT(25),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_pcie_phy_aux_clk = {
1949 .halt_reg = 0x6f004,
1950 .halt_check = BRANCH_HALT,
1951 .clkr = {
1952 .enable_reg = 0x6f004,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_pcie_phy_aux_clk",
1956 .parent_hws = (const struct clk_hw *[]){
1957 &gcc_pcie_0_aux_clk_src.clkr.hw },
1958 .num_parents = 1,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1961 },
1962 },
1963};
1964
1965static struct clk_branch gcc_pdm2_clk = {
1966 .halt_reg = 0x3300c,
1967 .halt_check = BRANCH_HALT,
1968 .clkr = {
1969 .enable_reg = 0x3300c,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_pdm2_clk",
1973 .parent_hws = (const struct clk_hw *[]){
1974 &gcc_pdm2_clk_src.clkr.hw },
1975 .num_parents = 1,
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1978 },
1979 },
1980};
1981
1982static struct clk_branch gcc_pdm_ahb_clk = {
1983 .halt_reg = 0x33004,
1984 .halt_check = BRANCH_HALT,
1985 .hwcg_reg = 0x33004,
1986 .hwcg_bit = 1,
1987 .clkr = {
1988 .enable_reg = 0x33004,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_pdm_ahb_clk",
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch gcc_pdm_xo4_clk = {
1998 .halt_reg = 0x33008,
1999 .halt_check = BRANCH_HALT,
2000 .clkr = {
2001 .enable_reg = 0x33008,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_pdm_xo4_clk",
2005 .ops = &clk_branch2_ops,
2006 },
2007 },
2008};
2009
2010static struct clk_branch gcc_prng_ahb_clk = {
2011 .halt_reg = 0x34004,
2012 .halt_check = BRANCH_HALT_VOTED,
2013 .clkr = {
2014 .enable_reg = 0x52004,
2015 .enable_mask = BIT(13),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "gcc_prng_ahb_clk",
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2024 .halt_reg = 0xb018,
2025 .halt_check = BRANCH_HALT,
2026 .hwcg_reg = 0xb018,
2027 .hwcg_bit = 1,
2028 .clkr = {
2029 .enable_reg = 0xb018,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_qmip_camera_nrt_ahb_clk",
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2039 .halt_reg = 0xb01c,
2040 .halt_check = BRANCH_HALT,
2041 .hwcg_reg = 0xb01c,
2042 .hwcg_bit = 1,
2043 .clkr = {
2044 .enable_reg = 0xb01c,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_qmip_camera_rt_ahb_clk",
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_qmip_disp_ahb_clk = {
2054 .halt_reg = 0xb020,
2055 .halt_check = BRANCH_HALT,
2056 .hwcg_reg = 0xb020,
2057 .hwcg_bit = 1,
2058 .clkr = {
2059 .enable_reg = 0xb020,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "gcc_qmip_disp_ahb_clk",
2063 .ops = &clk_branch2_ops,
2064 },
2065 },
2066};
2067
2068static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2069 .halt_reg = 0xb010,
2070 .halt_check = BRANCH_HALT,
2071 .hwcg_reg = 0xb010,
2072 .hwcg_bit = 1,
2073 .clkr = {
2074 .enable_reg = 0xb010,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_qmip_video_cvp_ahb_clk",
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2084 .halt_reg = 0xb014,
2085 .halt_check = BRANCH_HALT,
2086 .hwcg_reg = 0xb014,
2087 .hwcg_bit = 1,
2088 .clkr = {
2089 .enable_reg = 0xb014,
2090 .enable_mask = BIT(0),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "gcc_qmip_video_vcodec_ahb_clk",
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2099 .halt_reg = 0x4b000,
2100 .halt_check = BRANCH_HALT,
2101 .clkr = {
2102 .enable_reg = 0x4b000,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2106 .ops = &clk_branch2_ops,
2107 },
2108 },
2109};
2110
2111static struct clk_branch gcc_qspi_core_clk = {
2112 .halt_reg = 0x4b004,
2113 .halt_check = BRANCH_HALT,
2114 .clkr = {
2115 .enable_reg = 0x4b004,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_qspi_core_clk",
2119 .parent_hws = (const struct clk_hw *[]){
2120 &gcc_qspi_core_clk_src.clkr.hw },
2121 .num_parents = 1,
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2129 .halt_reg = 0x17144,
2130 .halt_check = BRANCH_HALT_VOTED,
2131 .clkr = {
2132 .enable_reg = 0x5200c,
2133 .enable_mask = BIT(10),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_qupv3_wrap0_s0_clk",
2136 .parent_hws = (const struct clk_hw *[]){
2137 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2138 .num_parents = 1,
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2141 },
2142 },
2143};
2144
2145static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2146 .halt_reg = 0x17274,
2147 .halt_check = BRANCH_HALT_VOTED,
2148 .clkr = {
2149 .enable_reg = 0x5200c,
2150 .enable_mask = BIT(11),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_qupv3_wrap0_s1_clk",
2153 .parent_hws = (const struct clk_hw *[]){
2154 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2155 .num_parents = 1,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2163 .halt_reg = 0x173a4,
2164 .halt_check = BRANCH_HALT_VOTED,
2165 .clkr = {
2166 .enable_reg = 0x5200c,
2167 .enable_mask = BIT(12),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_qupv3_wrap0_s2_clk",
2170 .parent_hws = (const struct clk_hw *[]){
2171 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2172 .num_parents = 1,
2173 .flags = CLK_SET_RATE_PARENT,
2174 .ops = &clk_branch2_ops,
2175 },
2176 },
2177};
2178
2179static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2180 .halt_reg = 0x174d4,
2181 .halt_check = BRANCH_HALT_VOTED,
2182 .clkr = {
2183 .enable_reg = 0x5200c,
2184 .enable_mask = BIT(13),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_qupv3_wrap0_s3_clk",
2187 .parent_hws = (const struct clk_hw *[]){
2188 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194};
2195
2196static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2197 .halt_reg = 0x17604,
2198 .halt_check = BRANCH_HALT_VOTED,
2199 .clkr = {
2200 .enable_reg = 0x5200c,
2201 .enable_mask = BIT(14),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_qupv3_wrap0_s4_clk",
2204 .parent_hws = (const struct clk_hw *[]){
2205 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2206 .num_parents = 1,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211};
2212
2213static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2214 .halt_reg = 0x17734,
2215 .halt_check = BRANCH_HALT_VOTED,
2216 .clkr = {
2217 .enable_reg = 0x5200c,
2218 .enable_mask = BIT(15),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "gcc_qupv3_wrap0_s5_clk",
2221 .parent_hws = (const struct clk_hw *[]){
2222 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2223 .num_parents = 1,
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2226 },
2227 },
2228};
2229
2230static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2231 .halt_reg = 0x17864,
2232 .halt_check = BRANCH_HALT_VOTED,
2233 .clkr = {
2234 .enable_reg = 0x5200c,
2235 .enable_mask = BIT(16),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap0_s6_clk",
2238 .parent_hws = (const struct clk_hw *[]){
2239 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2240 .num_parents = 1,
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2243 },
2244 },
2245};
2246
2247static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2248 .halt_reg = 0x17994,
2249 .halt_check = BRANCH_HALT_VOTED,
2250 .clkr = {
2251 .enable_reg = 0x5200c,
2252 .enable_mask = BIT(17),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "gcc_qupv3_wrap0_s7_clk",
2255 .parent_hws = (const struct clk_hw *[]){
2256 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2265 .halt_reg = 0x18144,
2266 .halt_check = BRANCH_HALT_VOTED,
2267 .clkr = {
2268 .enable_reg = 0x5200c,
2269 .enable_mask = BIT(22),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap1_s0_clk",
2272 .parent_hws = (const struct clk_hw *[]){
2273 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2274 .num_parents = 1,
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2277 },
2278 },
2279};
2280
2281static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2282 .halt_reg = 0x18274,
2283 .halt_check = BRANCH_HALT_VOTED,
2284 .clkr = {
2285 .enable_reg = 0x5200c,
2286 .enable_mask = BIT(23),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_qupv3_wrap1_s1_clk",
2289 .parent_hws = (const struct clk_hw *[]){
2290 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2291 .num_parents = 1,
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2294 },
2295 },
2296};
2297
2298static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2299 .halt_reg = 0x183a4,
2300 .halt_check = BRANCH_HALT_VOTED,
2301 .clkr = {
2302 .enable_reg = 0x5200c,
2303 .enable_mask = BIT(24),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_qupv3_wrap1_s2_clk",
2306 .parent_hws = (const struct clk_hw *[]){
2307 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2308 .num_parents = 1,
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2311 },
2312 },
2313};
2314
2315static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2316 .halt_reg = 0x184d4,
2317 .halt_check = BRANCH_HALT_VOTED,
2318 .clkr = {
2319 .enable_reg = 0x5200c,
2320 .enable_mask = BIT(25),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_qupv3_wrap1_s3_clk",
2323 .parent_hws = (const struct clk_hw *[]){
2324 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2325 .num_parents = 1,
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330};
2331
2332static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2333 .halt_reg = 0x18604,
2334 .halt_check = BRANCH_HALT_VOTED,
2335 .clkr = {
2336 .enable_reg = 0x5200c,
2337 .enable_mask = BIT(26),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_qupv3_wrap1_s4_clk",
2340 .parent_hws = (const struct clk_hw *[]){
2341 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2342 .num_parents = 1,
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2345 },
2346 },
2347};
2348
2349static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2350 .halt_reg = 0x18734,
2351 .halt_check = BRANCH_HALT_VOTED,
2352 .clkr = {
2353 .enable_reg = 0x5200c,
2354 .enable_mask = BIT(27),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_qupv3_wrap1_s5_clk",
2357 .parent_hws = (const struct clk_hw *[]){
2358 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2359 .num_parents = 1,
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2362 },
2363 },
2364};
2365
2366static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2367 .halt_reg = 0x1e144,
2368 .halt_check = BRANCH_HALT_VOTED,
2369 .clkr = {
2370 .enable_reg = 0x52014,
2371 .enable_mask = BIT(4),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_qupv3_wrap2_s0_clk",
2374 .parent_hws = (const struct clk_hw *[]){
2375 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2384 .halt_reg = 0x1e274,
2385 .halt_check = BRANCH_HALT_VOTED,
2386 .clkr = {
2387 .enable_reg = 0x52014,
2388 .enable_mask = BIT(5),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_qupv3_wrap2_s1_clk",
2391 .parent_hws = (const struct clk_hw *[]){
2392 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2393 .num_parents = 1,
2394 .flags = CLK_SET_RATE_PARENT,
2395 .ops = &clk_branch2_ops,
2396 },
2397 },
2398};
2399
2400static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2401 .halt_reg = 0x1e3a4,
2402 .halt_check = BRANCH_HALT_VOTED,
2403 .clkr = {
2404 .enable_reg = 0x52014,
2405 .enable_mask = BIT(6),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_qupv3_wrap2_s2_clk",
2408 .parent_hws = (const struct clk_hw *[]){
2409 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415};
2416
2417static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2418 .halt_reg = 0x1e4d4,
2419 .halt_check = BRANCH_HALT_VOTED,
2420 .clkr = {
2421 .enable_reg = 0x52014,
2422 .enable_mask = BIT(7),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_qupv3_wrap2_s3_clk",
2425 .parent_hws = (const struct clk_hw *[]){
2426 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2427 .num_parents = 1,
2428 .flags = CLK_SET_RATE_PARENT,
2429 .ops = &clk_branch2_ops,
2430 },
2431 },
2432};
2433
2434static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2435 .halt_reg = 0x1e604,
2436 .halt_check = BRANCH_HALT_VOTED,
2437 .clkr = {
2438 .enable_reg = 0x52014,
2439 .enable_mask = BIT(8),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "gcc_qupv3_wrap2_s4_clk",
2442 .parent_hws = (const struct clk_hw *[]){
2443 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2444 .num_parents = 1,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2447 },
2448 },
2449};
2450
2451static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2452 .halt_reg = 0x1e734,
2453 .halt_check = BRANCH_HALT_VOTED,
2454 .clkr = {
2455 .enable_reg = 0x52014,
2456 .enable_mask = BIT(9),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_qupv3_wrap2_s5_clk",
2459 .parent_hws = (const struct clk_hw *[]){
2460 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2461 .num_parents = 1,
2462 .flags = CLK_SET_RATE_PARENT,
2463 .ops = &clk_branch2_ops,
2464 },
2465 },
2466};
2467
2468static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2469 .halt_reg = 0x17004,
2470 .halt_check = BRANCH_HALT_VOTED,
2471 .clkr = {
2472 .enable_reg = 0x5200c,
2473 .enable_mask = BIT(6),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2476 .ops = &clk_branch2_ops,
2477 },
2478 },
2479};
2480
2481static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2482 .halt_reg = 0x17008,
2483 .halt_check = BRANCH_HALT_VOTED,
2484 .hwcg_reg = 0x17008,
2485 .hwcg_bit = 1,
2486 .clkr = {
2487 .enable_reg = 0x5200c,
2488 .enable_mask = BIT(7),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494};
2495
2496static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2497 .halt_reg = 0x18004,
2498 .halt_check = BRANCH_HALT_VOTED,
2499 .clkr = {
2500 .enable_reg = 0x5200c,
2501 .enable_mask = BIT(20),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2504 .ops = &clk_branch2_ops,
2505 },
2506 },
2507};
2508
2509static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2510 .halt_reg = 0x18008,
2511 .halt_check = BRANCH_HALT_VOTED,
2512 .hwcg_reg = 0x18008,
2513 .hwcg_bit = 1,
2514 .clkr = {
2515 .enable_reg = 0x5200c,
2516 .enable_mask = BIT(21),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2519 .ops = &clk_branch2_ops,
2520 },
2521 },
2522};
2523
2524static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2525 .halt_reg = 0x1e004,
2526 .halt_check = BRANCH_HALT_VOTED,
2527 .clkr = {
2528 .enable_reg = 0x52014,
2529 .enable_mask = BIT(2),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2532 .ops = &clk_branch2_ops,
2533 },
2534 },
2535};
2536
2537static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2538 .halt_reg = 0x1e008,
2539 .halt_check = BRANCH_HALT_VOTED,
2540 .hwcg_reg = 0x1e008,
2541 .hwcg_bit = 1,
2542 .clkr = {
2543 .enable_reg = 0x52014,
2544 .enable_mask = BIT(1),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2547 .ops = &clk_branch2_ops,
2548 },
2549 },
2550};
2551
2552static struct clk_branch gcc_sdcc2_ahb_clk = {
2553 .halt_reg = 0x14008,
2554 .halt_check = BRANCH_HALT,
2555 .clkr = {
2556 .enable_reg = 0x14008,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sdcc2_ahb_clk",
2560 .ops = &clk_branch2_ops,
2561 },
2562 },
2563};
2564
2565static struct clk_branch gcc_sdcc2_apps_clk = {
2566 .halt_reg = 0x14004,
2567 .halt_check = BRANCH_HALT,
2568 .clkr = {
2569 .enable_reg = 0x14004,
2570 .enable_mask = BIT(0),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gcc_sdcc2_apps_clk",
2573 .parent_hws = (const struct clk_hw *[]){
2574 &gcc_sdcc2_apps_clk_src.clkr.hw },
2575 .num_parents = 1,
2576 .flags = CLK_SET_RATE_PARENT,
2577 .ops = &clk_branch2_ops,
2578 },
2579 },
2580};
2581
2582static struct clk_branch gcc_sdcc4_ahb_clk = {
2583 .halt_reg = 0x16008,
2584 .halt_check = BRANCH_HALT,
2585 .clkr = {
2586 .enable_reg = 0x16008,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_sdcc4_ahb_clk",
2590 .ops = &clk_branch2_ops,
2591 },
2592 },
2593};
2594
2595static struct clk_branch gcc_sdcc4_apps_clk = {
2596 .halt_reg = 0x16004,
2597 .halt_check = BRANCH_HALT,
2598 .clkr = {
2599 .enable_reg = 0x16004,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_sdcc4_apps_clk",
2603 .parent_hws = (const struct clk_hw *[]){
2604 &gcc_sdcc4_apps_clk_src.clkr.hw },
2605 .num_parents = 1,
2606 .flags = CLK_SET_RATE_PARENT,
2607 .ops = &clk_branch2_ops,
2608 },
2609 },
2610};
2611
2612static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2613 .halt_reg = 0x4819c,
2614 .halt_check = BRANCH_HALT_VOTED,
2615 .clkr = {
2616 .enable_reg = 0x52004,
2617 .enable_mask = BIT(0),
2618 .hw.init = &(struct clk_init_data){
2619 .name = "gcc_sys_noc_cpuss_ahb_clk",
2620 .parent_hws = (const struct clk_hw *[]){
2621 &gcc_cpuss_ahb_clk_src.clkr.hw },
2622 .num_parents = 1,
2623 /* required for cpuss */
2624 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2625 .ops = &clk_branch2_ops,
2626 },
2627 },
2628};
2629
2630static struct clk_branch gcc_tsif_ahb_clk = {
2631 .halt_reg = 0x36004,
2632 .halt_check = BRANCH_HALT,
2633 .clkr = {
2634 .enable_reg = 0x36004,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "gcc_tsif_ahb_clk",
2638 .ops = &clk_branch2_ops,
2639 },
2640 },
2641};
2642
2643static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2644 .halt_reg = 0x3600c,
2645 .halt_check = BRANCH_HALT,
2646 .clkr = {
2647 .enable_reg = 0x3600c,
2648 .enable_mask = BIT(0),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "gcc_tsif_inactivity_timers_clk",
2651 .ops = &clk_branch2_ops,
2652 },
2653 },
2654};
2655
2656static struct clk_branch gcc_tsif_ref_clk = {
2657 .halt_reg = 0x36008,
2658 .halt_check = BRANCH_HALT,
2659 .clkr = {
2660 .enable_reg = 0x36008,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "gcc_tsif_ref_clk",
2664 .parent_hws = (const struct clk_hw *[]){
2665 &gcc_tsif_ref_clk_src.clkr.hw },
2666 .num_parents = 1,
2667 .flags = CLK_SET_RATE_PARENT,
2668 .ops = &clk_branch2_ops,
2669 },
2670 },
2671};
2672
2673static struct clk_branch gcc_ufs_card_ahb_clk = {
2674 .halt_reg = 0x75014,
2675 .halt_check = BRANCH_HALT,
2676 .hwcg_reg = 0x75014,
2677 .hwcg_bit = 1,
2678 .clkr = {
2679 .enable_reg = 0x75014,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "gcc_ufs_card_ahb_clk",
2683 .ops = &clk_branch2_ops,
2684 },
2685 },
2686};
2687
2688static struct clk_branch gcc_ufs_card_axi_clk = {
2689 .halt_reg = 0x75010,
2690 .halt_check = BRANCH_HALT,
2691 .hwcg_reg = 0x75010,
2692 .hwcg_bit = 1,
2693 .clkr = {
2694 .enable_reg = 0x75010,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "gcc_ufs_card_axi_clk",
2698 .parent_hws = (const struct clk_hw *[]){
2699 &gcc_ufs_card_axi_clk_src.clkr.hw },
2700 .num_parents = 1,
2701 .flags = CLK_SET_RATE_PARENT,
2702 .ops = &clk_branch2_ops,
2703 },
2704 },
2705};
2706
2707static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2708 .halt_reg = 0x75010,
2709 .halt_check = BRANCH_HALT,
2710 .hwcg_reg = 0x75010,
2711 .hwcg_bit = 1,
2712 .clkr = {
2713 .enable_reg = 0x75010,
2714 .enable_mask = BIT(1),
2715 .hw.init = &(struct clk_init_data){
2716 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2717 .parent_hws = (const struct clk_hw *[]){
2718 &gcc_ufs_card_axi_clk.clkr.hw },
2719 .num_parents = 1,
2720 .flags = CLK_SET_RATE_PARENT,
2721 .ops = &clk_branch_simple_ops,
2722 },
2723 },
2724};
2725
2726static struct clk_branch gcc_ufs_card_clkref_clk = {
2727 .halt_reg = 0x8c004,
2728 .halt_check = BRANCH_HALT,
2729 .clkr = {
2730 .enable_reg = 0x8c004,
2731 .enable_mask = BIT(0),
2732 .hw.init = &(struct clk_init_data){
2733 .name = "gcc_ufs_card_clkref_clk",
2734 .ops = &clk_branch2_ops,
2735 },
2736 },
2737};
2738
2739static struct clk_branch gcc_ufs_card_ice_core_clk = {
2740 .halt_reg = 0x7505c,
2741 .halt_check = BRANCH_HALT,
2742 .hwcg_reg = 0x7505c,
2743 .hwcg_bit = 1,
2744 .clkr = {
2745 .enable_reg = 0x7505c,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(struct clk_init_data){
2748 .name = "gcc_ufs_card_ice_core_clk",
2749 .parent_hws = (const struct clk_hw *[]){
2750 &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2751 .num_parents = 1,
2752 .flags = CLK_SET_RATE_PARENT,
2753 .ops = &clk_branch2_ops,
2754 },
2755 },
2756};
2757
2758static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2759 .halt_reg = 0x7505c,
2760 .halt_check = BRANCH_HALT,
2761 .hwcg_reg = 0x7505c,
2762 .hwcg_bit = 1,
2763 .clkr = {
2764 .enable_reg = 0x7505c,
2765 .enable_mask = BIT(1),
2766 .hw.init = &(struct clk_init_data){
2767 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2768 .parent_hws = (const struct clk_hw *[]){
2769 &gcc_ufs_card_ice_core_clk.clkr.hw },
2770 .num_parents = 1,
2771 .flags = CLK_SET_RATE_PARENT,
2772 .ops = &clk_branch_simple_ops,
2773 },
2774 },
2775};
2776
2777static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2778 .halt_reg = 0x75090,
2779 .halt_check = BRANCH_HALT,
2780 .hwcg_reg = 0x75090,
2781 .hwcg_bit = 1,
2782 .clkr = {
2783 .enable_reg = 0x75090,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_ufs_card_phy_aux_clk",
2787 .parent_hws = (const struct clk_hw *[]){
2788 &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2797 .halt_reg = 0x75090,
2798 .halt_check = BRANCH_HALT,
2799 .hwcg_reg = 0x75090,
2800 .hwcg_bit = 1,
2801 .clkr = {
2802 .enable_reg = 0x75090,
2803 .enable_mask = BIT(1),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2806 .parent_hws = (const struct clk_hw *[]){
2807 &gcc_ufs_card_phy_aux_clk.clkr.hw },
2808 .num_parents = 1,
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch_simple_ops,
2811 },
2812 },
2813};
2814
2815static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2816 .halt_reg = 0x75058,
2817 .halt_check = BRANCH_HALT,
2818 .hwcg_reg = 0x75058,
2819 .hwcg_bit = 1,
2820 .clkr = {
2821 .enable_reg = 0x75058,
2822 .enable_mask = BIT(0),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "gcc_ufs_card_unipro_core_clk",
2825 .parent_hws = (const struct clk_hw *[]){
2826 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2827 .num_parents = 1,
2828 .flags = CLK_SET_RATE_PARENT,
2829 .ops = &clk_branch2_ops,
2830 },
2831 },
2832};
2833
2834static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2835 .halt_reg = 0x75058,
2836 .halt_check = BRANCH_HALT,
2837 .hwcg_reg = 0x75058,
2838 .hwcg_bit = 1,
2839 .clkr = {
2840 .enable_reg = 0x75058,
2841 .enable_mask = BIT(1),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2844 .parent_hws = (const struct clk_hw *[]){
2845 &gcc_ufs_card_unipro_core_clk.clkr.hw },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_branch_simple_ops,
2849 },
2850 },
2851};
2852
2853static struct clk_branch gcc_ufs_mem_clkref_clk = {
2854 .halt_reg = 0x8c000,
2855 .halt_check = BRANCH_HALT,
2856 .clkr = {
2857 .enable_reg = 0x8c000,
2858 .enable_mask = BIT(0),
2859 .hw.init = &(struct clk_init_data){
2860 .name = "gcc_ufs_mem_clkref_clk",
2861 .ops = &clk_branch2_ops,
2862 },
2863 },
2864};
2865
2866static struct clk_branch gcc_ufs_phy_ahb_clk = {
2867 .halt_reg = 0x77014,
2868 .halt_check = BRANCH_HALT,
2869 .hwcg_reg = 0x77014,
2870 .hwcg_bit = 1,
2871 .clkr = {
2872 .enable_reg = 0x77014,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(struct clk_init_data){
2875 .name = "gcc_ufs_phy_ahb_clk",
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch gcc_ufs_phy_axi_clk = {
2882 .halt_reg = 0x77010,
2883 .halt_check = BRANCH_HALT,
2884 .hwcg_reg = 0x77010,
2885 .hwcg_bit = 1,
2886 .clkr = {
2887 .enable_reg = 0x77010,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_ufs_phy_axi_clk",
2891 .parent_hws = (const struct clk_hw *[]){
2892 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2893 .num_parents = 1,
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2896 },
2897 },
2898};
2899
2900static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2901 .halt_reg = 0x77010,
2902 .halt_check = BRANCH_HALT,
2903 .hwcg_reg = 0x77010,
2904 .hwcg_bit = 1,
2905 .clkr = {
2906 .enable_reg = 0x77010,
2907 .enable_mask = BIT(1),
2908 .hw.init = &(struct clk_init_data){
2909 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2910 .parent_hws = (const struct clk_hw *[]){
2911 &gcc_ufs_phy_axi_clk.clkr.hw },
2912 .num_parents = 1,
2913 .flags = CLK_SET_RATE_PARENT,
2914 .ops = &clk_branch_simple_ops,
2915 },
2916 },
2917};
2918
2919static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2920 .halt_reg = 0x7705c,
2921 .halt_check = BRANCH_HALT,
2922 .hwcg_reg = 0x7705c,
2923 .hwcg_bit = 1,
2924 .clkr = {
2925 .enable_reg = 0x7705c,
2926 .enable_mask = BIT(0),
2927 .hw.init = &(struct clk_init_data){
2928 .name = "gcc_ufs_phy_ice_core_clk",
2929 .parent_hws = (const struct clk_hw *[]){
2930 &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
2931 .num_parents = 1,
2932 .flags = CLK_SET_RATE_PARENT,
2933 .ops = &clk_branch2_ops,
2934 },
2935 },
2936};
2937
2938static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2939 .halt_reg = 0x7705c,
2940 .halt_check = BRANCH_HALT,
2941 .hwcg_reg = 0x7705c,
2942 .hwcg_bit = 1,
2943 .clkr = {
2944 .enable_reg = 0x7705c,
2945 .enable_mask = BIT(1),
2946 .hw.init = &(struct clk_init_data){
2947 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2948 .parent_hws = (const struct clk_hw *[]){
2949 &gcc_ufs_phy_ice_core_clk.clkr.hw },
2950 .num_parents = 1,
2951 .flags = CLK_SET_RATE_PARENT,
2952 .ops = &clk_branch_simple_ops,
2953 },
2954 },
2955};
2956
2957static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2958 .halt_reg = 0x77090,
2959 .halt_check = BRANCH_HALT,
2960 .hwcg_reg = 0x77090,
2961 .hwcg_bit = 1,
2962 .clkr = {
2963 .enable_reg = 0x77090,
2964 .enable_mask = BIT(0),
2965 .hw.init = &(struct clk_init_data){
2966 .name = "gcc_ufs_phy_phy_aux_clk",
2967 .parent_hws = (const struct clk_hw *[]){
2968 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
2969 .num_parents = 1,
2970 .flags = CLK_SET_RATE_PARENT,
2971 .ops = &clk_branch2_ops,
2972 },
2973 },
2974};
2975
2976static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2977 .halt_reg = 0x77090,
2978 .halt_check = BRANCH_HALT,
2979 .hwcg_reg = 0x77090,
2980 .hwcg_bit = 1,
2981 .clkr = {
2982 .enable_reg = 0x77090,
2983 .enable_mask = BIT(1),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2986 .parent_hws = (const struct clk_hw *[]){
2987 &gcc_ufs_phy_phy_aux_clk.clkr.hw },
2988 .num_parents = 1,
2989 .flags = CLK_SET_RATE_PARENT,
2990 .ops = &clk_branch_simple_ops,
2991 },
2992 },
2993};
2994
2995static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2996 .halt_reg = 0x77058,
2997 .halt_check = BRANCH_HALT,
2998 .hwcg_reg = 0x77058,
2999 .hwcg_bit = 1,
3000 .clkr = {
3001 .enable_reg = 0x77058,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_ufs_phy_unipro_core_clk",
3005 .parent_hws = (const struct clk_hw *[]){
3006 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3007 .num_parents = 1,
3008 .flags = CLK_SET_RATE_PARENT,
3009 .ops = &clk_branch2_ops,
3010 },
3011 },
3012};
3013
3014static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3015 .halt_reg = 0x77058,
3016 .halt_check = BRANCH_HALT,
3017 .hwcg_reg = 0x77058,
3018 .hwcg_bit = 1,
3019 .clkr = {
3020 .enable_reg = 0x77058,
3021 .enable_mask = BIT(1),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3024 .parent_hws = (const struct clk_hw *[]){
3025 &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3026 .num_parents = 1,
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_branch_simple_ops,
3029 },
3030 },
3031};
3032
3033static struct clk_branch gcc_usb30_prim_master_clk = {
3034 .halt_reg = 0xf010,
3035 .halt_check = BRANCH_HALT,
3036 .clkr = {
3037 .enable_reg = 0xf010,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "gcc_usb30_prim_master_clk",
3041 .parent_hws = (const struct clk_hw *[]){
3042 &gcc_usb30_prim_master_clk_src.clkr.hw },
3043 .num_parents = 1,
3044 .flags = CLK_SET_RATE_PARENT,
3045 .ops = &clk_branch2_ops,
3046 },
3047 },
3048};
3049
3050static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3051 .halt_reg = 0xf018,
3052 .halt_check = BRANCH_HALT,
3053 .clkr = {
3054 .enable_reg = 0xf018,
3055 .enable_mask = BIT(0),
3056 .hw.init = &(struct clk_init_data){
3057 .name = "gcc_usb30_prim_mock_utmi_clk",
3058 .parent_hws = (const struct clk_hw *[]){
3059 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3060 .num_parents = 1,
3061 .flags = CLK_SET_RATE_PARENT,
3062 .ops = &clk_branch2_ops,
3063 },
3064 },
3065};
3066
3067static struct clk_branch gcc_usb30_prim_sleep_clk = {
3068 .halt_reg = 0xf014,
3069 .halt_check = BRANCH_HALT,
3070 .clkr = {
3071 .enable_reg = 0xf014,
3072 .enable_mask = BIT(0),
3073 .hw.init = &(struct clk_init_data){
3074 .name = "gcc_usb30_prim_sleep_clk",
3075 .ops = &clk_branch2_ops,
3076 },
3077 },
3078};
3079
3080static struct clk_branch gcc_usb30_sec_master_clk = {
3081 .halt_reg = 0x10010,
3082 .halt_check = BRANCH_HALT,
3083 .clkr = {
3084 .enable_reg = 0x10010,
3085 .enable_mask = BIT(0),
3086 .hw.init = &(struct clk_init_data){
3087 .name = "gcc_usb30_sec_master_clk",
3088 .parent_hws = (const struct clk_hw *[]){
3089 &gcc_usb30_sec_master_clk_src.clkr.hw },
3090 .num_parents = 1,
3091 .flags = CLK_SET_RATE_PARENT,
3092 .ops = &clk_branch2_ops,
3093 },
3094 },
3095};
3096
3097static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3098 .halt_reg = 0x10018,
3099 .halt_check = BRANCH_HALT,
3100 .clkr = {
3101 .enable_reg = 0x10018,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_usb30_sec_mock_utmi_clk",
3105 .parent_hws = (const struct clk_hw *[]){
3106 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3107 .num_parents = 1,
3108 .flags = CLK_SET_RATE_PARENT,
3109 .ops = &clk_branch2_ops,
3110 },
3111 },
3112};
3113
3114static struct clk_branch gcc_usb30_sec_sleep_clk = {
3115 .halt_reg = 0x10014,
3116 .halt_check = BRANCH_HALT,
3117 .clkr = {
3118 .enable_reg = 0x10014,
3119 .enable_mask = BIT(0),
3120 .hw.init = &(struct clk_init_data){
3121 .name = "gcc_usb30_sec_sleep_clk",
3122 .ops = &clk_branch2_ops,
3123 },
3124 },
3125};
3126
3127static struct clk_branch gcc_usb3_prim_clkref_clk = {
3128 .halt_reg = 0x8c008,
3129 .halt_check = BRANCH_HALT,
3130 .clkr = {
3131 .enable_reg = 0x8c008,
3132 .enable_mask = BIT(0),
3133 .hw.init = &(struct clk_init_data){
3134 .name = "gcc_usb3_prim_clkref_clk",
3135 .ops = &clk_branch2_ops,
3136 },
3137 },
3138};
3139
3140static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3141 .halt_reg = 0xf050,
3142 .halt_check = BRANCH_HALT,
3143 .clkr = {
3144 .enable_reg = 0xf050,
3145 .enable_mask = BIT(0),
3146 .hw.init = &(struct clk_init_data){
3147 .name = "gcc_usb3_prim_phy_aux_clk",
3148 .parent_hws = (const struct clk_hw *[]){
3149 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3150 .num_parents = 1,
3151 .flags = CLK_SET_RATE_PARENT,
3152 .ops = &clk_branch2_ops,
3153 },
3154 },
3155};
3156
3157static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3158 .halt_reg = 0xf054,
3159 .halt_check = BRANCH_HALT,
3160 .clkr = {
3161 .enable_reg = 0xf054,
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_usb3_prim_phy_com_aux_clk",
3165 .parent_hws = (const struct clk_hw *[]){
3166 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3167 .num_parents = 1,
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3170 },
3171 },
3172};
3173
3174static struct clk_branch gcc_usb3_sec_clkref_clk = {
3175 .halt_reg = 0x8c028,
3176 .halt_check = BRANCH_HALT,
3177 .clkr = {
3178 .enable_reg = 0x8c028,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb3_sec_clkref_clk",
3182 .ops = &clk_branch2_ops,
3183 },
3184 },
3185};
3186
3187static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3188 .halt_reg = 0x10050,
3189 .halt_check = BRANCH_HALT,
3190 .clkr = {
3191 .enable_reg = 0x10050,
3192 .enable_mask = BIT(0),
3193 .hw.init = &(struct clk_init_data){
3194 .name = "gcc_usb3_sec_phy_aux_clk",
3195 .parent_hws = (const struct clk_hw *[]){
3196 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3197 .num_parents = 1,
3198 .flags = CLK_SET_RATE_PARENT,
3199 .ops = &clk_branch2_ops,
3200 },
3201 },
3202};
3203
3204static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3205 .halt_reg = 0x10054,
3206 .halt_check = BRANCH_HALT,
3207 .clkr = {
3208 .enable_reg = 0x10054,
3209 .enable_mask = BIT(0),
3210 .hw.init = &(struct clk_init_data){
3211 .name = "gcc_usb3_sec_phy_com_aux_clk",
3212 .parent_hws = (const struct clk_hw *[]){
3213 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3214 .num_parents = 1,
3215 .flags = CLK_SET_RATE_PARENT,
3216 .ops = &clk_branch2_ops,
3217 },
3218 },
3219};
3220
3221/*
3222 * Clock ON depends on external parent 'config noc', so cant poll
3223 * delay and also mark as crtitical for video boot
3224 */
3225static struct clk_branch gcc_video_ahb_clk = {
3226 .halt_reg = 0xb004,
3227 .halt_check = BRANCH_HALT_DELAY,
3228 .hwcg_reg = 0xb004,
3229 .hwcg_bit = 1,
3230 .clkr = {
3231 .enable_reg = 0xb004,
3232 .enable_mask = BIT(0),
3233 .hw.init = &(struct clk_init_data){
3234 .name = "gcc_video_ahb_clk",
3235 .flags = CLK_IS_CRITICAL,
3236 .ops = &clk_branch2_ops,
3237 },
3238 },
3239};
3240
3241static struct clk_branch gcc_video_axi0_clk = {
3242 .halt_reg = 0xb024,
3243 .halt_check = BRANCH_HALT,
3244 .clkr = {
3245 .enable_reg = 0xb024,
3246 .enable_mask = BIT(0),
3247 .hw.init = &(struct clk_init_data){
3248 .name = "gcc_video_axi0_clk",
3249 .ops = &clk_branch2_ops,
3250 },
3251 },
3252};
3253
3254static struct clk_branch gcc_video_axi1_clk = {
3255 .halt_reg = 0xb028,
3256 .halt_check = BRANCH_HALT,
3257 .clkr = {
3258 .enable_reg = 0xb028,
3259 .enable_mask = BIT(0),
3260 .hw.init = &(struct clk_init_data){
3261 .name = "gcc_video_axi1_clk",
3262 .ops = &clk_branch2_ops,
3263 },
3264 },
3265};
3266
3267static struct clk_branch gcc_video_axic_clk = {
3268 .halt_reg = 0xb02c,
3269 .halt_check = BRANCH_HALT,
3270 .clkr = {
3271 .enable_reg = 0xb02c,
3272 .enable_mask = BIT(0),
3273 .hw.init = &(struct clk_init_data){
3274 .name = "gcc_video_axic_clk",
3275 .ops = &clk_branch2_ops,
3276 },
3277 },
3278};
3279
3280/* XO critical input to video, so no need to poll */
3281static struct clk_branch gcc_video_xo_clk = {
3282 .halt_reg = 0xb040,
3283 .halt_check = BRANCH_HALT_DELAY,
3284 .clkr = {
3285 .enable_reg = 0xb040,
3286 .enable_mask = BIT(0),
3287 .hw.init = &(struct clk_init_data){
3288 .name = "gcc_video_xo_clk",
3289 .flags = CLK_IS_CRITICAL,
3290 .ops = &clk_branch2_ops,
3291 },
3292 },
3293};
3294
3295static struct clk_regmap *gcc_sm8150_clocks[] = {
3296 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3297 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3298 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3299 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3300 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3301 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3302 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3303 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3304 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3305 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3306 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3307 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3308 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3309 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3310 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3311 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3312 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3313 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3314 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3315 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3316 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3317 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3318 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3319 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3320 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3321 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3322 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3323 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3324 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3325 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3326 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3327 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3328 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3329 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3330 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3331 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3332 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3333 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3334 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3335 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3336 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3337 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3338 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3339 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3340 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3341 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3342 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3343 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3344 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3345 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3346 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3347 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3348 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3349 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3350 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3351 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3352 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3353 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3354 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3355 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3356 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3357 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3358 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3359 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3360 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3361 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3367 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3368 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3369 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3370 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3371 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3372 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3373 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3374 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3375 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3376 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3377 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3378 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3379 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3380 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3381 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3382 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3383 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3384 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3385 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3386 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3387 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3388 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3389 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3390 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3391 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3392 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3393 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3394 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3395 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3396 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3397 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3398 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3399 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3400 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3401 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3402 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3403 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3404 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3405 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3406 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3407 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3408 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3409 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3410 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3411 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3412 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3413 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3414 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3415 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3416 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3417 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3418 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3419 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3420 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3421 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3422 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3423 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3424 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3425 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3426 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3427 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3428 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3429 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3430 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3431 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3432 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3433 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3434 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3435 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3436 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3437 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3438 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3439 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3440 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3441 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3442 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3443 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3444 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3445 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3446 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3447 &gcc_ufs_card_unipro_core_clk_src.clkr,
3448 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3449 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3450 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3451 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3452 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3453 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3454 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3455 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3456 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3457 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3458 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3459 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3460 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3461 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3462 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3463 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3464 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3465 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3466 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3467 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3468 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3469 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3470 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3471 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3472 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3473 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3474 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3475 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3476 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3477 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3478 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3479 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3480 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3481 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3482 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3483 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3484 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3485 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3486 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3487 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3488 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3489 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3490 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3491 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3492 [GPLL0] = &gpll0.clkr,
3493 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3494 [GPLL7] = &gpll7.clkr,
3495 [GPLL9] = &gpll9.clkr,
3496};
3497
3498static const struct qcom_reset_map gcc_sm8150_resets[] = {
3499 [GCC_EMAC_BCR] = { 0x6000 },
3500 [GCC_GPU_BCR] = { 0x71000 },
3501 [GCC_MMSS_BCR] = { 0xb000 },
3502 [GCC_NPU_BCR] = { 0x4d000 },
3503 [GCC_PCIE_0_BCR] = { 0x6b000 },
3504 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3505 [GCC_PCIE_1_BCR] = { 0x8d000 },
3506 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3507 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3508 [GCC_PDM_BCR] = { 0x33000 },
3509 [GCC_PRNG_BCR] = { 0x34000 },
3510 [GCC_QSPI_BCR] = { 0x24008 },
3511 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3512 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3513 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3514 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3515 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3516 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3517 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3518 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3519 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3520 [GCC_SDCC2_BCR] = { 0x14000 },
3521 [GCC_SDCC4_BCR] = { 0x16000 },
3522 [GCC_TSIF_BCR] = { 0x36000 },
3523 [GCC_UFS_CARD_BCR] = { 0x75000 },
3524 [GCC_UFS_PHY_BCR] = { 0x77000 },
3525 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3526 [GCC_USB30_SEC_BCR] = { 0x10000 },
3527 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3528};
3529
3530static const struct regmap_config gcc_sm8150_regmap_config = {
3531 .reg_bits = 32,
3532 .reg_stride = 4,
3533 .val_bits = 32,
3534 .max_register = 0x9c040,
3535 .fast_io = true,
3536};
3537
3538static const struct qcom_cc_desc gcc_sm8150_desc = {
3539 .config = &gcc_sm8150_regmap_config,
3540 .clks = gcc_sm8150_clocks,
3541 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3542 .resets = gcc_sm8150_resets,
3543 .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3544};
3545
3546static const struct of_device_id gcc_sm8150_match_table[] = {
3547 { .compatible = "qcom,gcc-sm8150" },
3548 { }
3549};
3550MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3551
3552static int gcc_sm8150_probe(struct platform_device *pdev)
3553{
3554 struct regmap *regmap;
3555
3556 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3557 if (IS_ERR(regmap))
3558 return PTR_ERR(regmap);
3559
3560 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3561 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3562 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3563
3564 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3565}
3566
3567static struct platform_driver gcc_sm8150_driver = {
3568 .probe = gcc_sm8150_probe,
3569 .driver = {
3570 .name = "gcc-sm8150",
3571 .of_match_table = gcc_sm8150_match_table,
3572 },
3573};
3574
3575static int __init gcc_sm8150_init(void)
3576{
3577 return platform_driver_register(&gcc_sm8150_driver);
3578}
3579subsys_initcall(gcc_sm8150_init);
3580
3581static void __exit gcc_sm8150_exit(void)
3582{
3583 platform_driver_unregister(&gcc_sm8150_driver);
3584}
3585module_exit(gcc_sm8150_exit);
3586
3587MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3588MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
index e246b99dfbc6..56d3e9928892 100644
--- a/drivers/clk/qcom/lpasscc-sdm845.c
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -112,25 +112,6 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), 112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
113}; 113};
114 114
115static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
116 const struct qcom_cc_desc *desc)
117{
118 struct regmap *regmap;
119 struct resource *res;
120 void __iomem *base;
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
123 base = devm_ioremap_resource(&pdev->dev, res);
124 if (IS_ERR(base))
125 return PTR_ERR(base);
126
127 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
128 if (IS_ERR(regmap))
129 return PTR_ERR(regmap);
130
131 return qcom_cc_really_probe(pdev, desc, regmap);
132}
133
134static int lpass_cc_sdm845_probe(struct platform_device *pdev) 115static int lpass_cc_sdm845_probe(struct platform_device *pdev)
135{ 116{
136 const struct qcom_cc_desc *desc; 117 const struct qcom_cc_desc *desc;
@@ -139,14 +120,14 @@ static int lpass_cc_sdm845_probe(struct platform_device *pdev)
139 lpass_regmap_config.name = "cc"; 120 lpass_regmap_config.name = "cc";
140 desc = &lpass_cc_sdm845_desc; 121 desc = &lpass_cc_sdm845_desc;
141 122
142 ret = lpass_clocks_sdm845_probe(pdev, 0, desc); 123 ret = qcom_cc_probe_by_index(pdev, 0, desc);
143 if (ret) 124 if (ret)
144 return ret; 125 return ret;
145 126
146 lpass_regmap_config.name = "qdsp6ss"; 127 lpass_regmap_config.name = "qdsp6ss";
147 desc = &lpass_qdsp6ss_sdm845_desc; 128 desc = &lpass_qdsp6ss_sdm845_desc;
148 129
149 return lpass_clocks_sdm845_probe(pdev, 1, desc); 130 return qcom_cc_probe_by_index(pdev, 1, desc);
150} 131}
151 132
152static const struct of_device_id lpass_cc_sdm845_match_table[] = { 133static const struct of_device_id lpass_cc_sdm845_match_table[] = {
diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c
index aa859e6ec9bd..4cfbbf5bf4d9 100644
--- a/drivers/clk/qcom/turingcc-qcs404.c
+++ b/drivers/clk/qcom/turingcc-qcs404.c
@@ -96,7 +96,7 @@ static const struct regmap_config turingcc_regmap_config = {
96 .reg_bits = 32, 96 .reg_bits = 32,
97 .reg_stride = 4, 97 .reg_stride = 4,
98 .val_bits = 32, 98 .val_bits = 32,
99 .max_register = 0x30000, 99 .max_register = 0x23004,
100 .fast_io = true, 100 .fast_io = true,
101}; 101};
102 102
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 2db9093546c6..e326e6dc09fc 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -334,7 +334,8 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)
334 return; 334 return;
335 335
336 pd->name = np->name; 336 pd->name = np->name;
337 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 337 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
338 GENPD_FLAG_ACTIVE_WAKEUP;
338 pd->attach_dev = cpg_mstp_attach_dev; 339 pd->attach_dev = cpg_mstp_attach_dev;
339 pd->detach_dev = cpg_mstp_detach_dev; 340 pd->detach_dev = cpg_mstp_detach_dev;
340 pm_genpd_init(pd, &pm_domain_always_on_gov, false); 341 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index b33e1383efe3..1907ee195a08 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -421,7 +421,8 @@ static int r9a06g032_add_clk_domain(struct device *dev)
421 return -ENOMEM; 421 return -ENOMEM;
422 422
423 pd->name = np->name; 423 pd->name = np->name;
424 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 424 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
425 GENPD_FLAG_ACTIVE_WAKEUP;
425 pd->attach_dev = r9a06g032_attach_dev; 426 pd->attach_dev = r9a06g032_attach_dev;
426 pd->detach_dev = r9a06g032_detach_dev; 427 pd->detach_dev = r9a06g032_detach_dev;
427 pm_genpd_init(pd, &pm_domain_always_on_gov, false); 428 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c
index cc90b11a9c25..b97f5f9326cf 100644
--- a/drivers/clk/renesas/rcar-usb2-clock-sel.c
+++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c
@@ -117,7 +117,6 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
117 struct device *dev = &pdev->dev; 117 struct device *dev = &pdev->dev;
118 struct device_node *np = dev->of_node; 118 struct device_node *np = dev->of_node;
119 struct usb2_clock_sel_priv *priv; 119 struct usb2_clock_sel_priv *priv;
120 struct resource *res;
121 struct clk *clk; 120 struct clk *clk;
122 struct clk_init_data init; 121 struct clk_init_data init;
123 122
@@ -125,8 +124,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
125 if (!priv) 124 if (!priv)
126 return -ENOMEM; 125 return -ENOMEM;
127 126
128 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 127 priv->base = devm_platform_ioremap_resource(pdev, 0);
129 priv->base = devm_ioremap_resource(dev, res);
130 if (IS_ERR(priv->base)) 128 if (IS_ERR(priv->base))
131 return PTR_ERR(priv->base); 129 return PTR_ERR(priv->base);
132 130
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index d4075b130674..132cc96895e3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -551,7 +551,8 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
551 551
552 genpd = &pd->genpd; 552 genpd = &pd->genpd;
553 genpd->name = np->name; 553 genpd->name = np->name;
554 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 554 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
555 GENPD_FLAG_ACTIVE_WAKEUP;
555 genpd->attach_dev = cpg_mssr_attach_dev; 556 genpd->attach_dev = cpg_mssr_attach_dev;
556 genpd->detach_dev = cpg_mssr_detach_dev; 557 genpd->detach_dev = cpg_mssr_detach_dev;
557 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 558 pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index ff35ab463a6f..7c5b5813a87c 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -20,6 +20,7 @@ obj-y += clk-rk3128.o
20obj-y += clk-rk3188.o 20obj-y += clk-rk3188.o
21obj-y += clk-rk3228.o 21obj-y += clk-rk3228.o
22obj-y += clk-rk3288.o 22obj-y += clk-rk3288.o
23obj-y += clk-rk3308.o
23obj-y += clk-rk3328.o 24obj-y += clk-rk3328.o
24obj-y += clk-rk3368.o 25obj-y += clk-rk3368.o
25obj-y += clk-rk3399.o 26obj-y += clk-rk3399.o
diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c
new file mode 100644
index 000000000000..b0baf87a283e
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3308.c
@@ -0,0 +1,955 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/of_address.h>
11#include <linux/syscore_ops.h>
12#include <dt-bindings/clock/rk3308-cru.h>
13#include "clk.h"
14
15#define RK3308_GRF_SOC_STATUS0 0x380
16
17enum rk3308_plls {
18 apll, dpll, vpll0, vpll1,
19};
20
21static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
22 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
23 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
24 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
25 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
26 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
27 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
28 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
29 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
30 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
31 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
44 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
45 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
46 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
47 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
48 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
49 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
50 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
51 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
52 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
53 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
54 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
55 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
56 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
57 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
58 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
59 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
60 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
61 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
62 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
63 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
64 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
65 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
66 { /* sentinel */ },
67};
68
69#define RK3308_DIV_ACLKM_MASK 0x7
70#define RK3308_DIV_ACLKM_SHIFT 12
71#define RK3308_DIV_PCLK_DBG_MASK 0xf
72#define RK3308_DIV_PCLK_DBG_SHIFT 8
73
74#define RK3308_CLKSEL0(_aclk_core, _pclk_dbg) \
75{ \
76 .reg = RK3308_CLKSEL_CON(0), \
77 .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
78 RK3308_DIV_ACLKM_SHIFT) | \
79 HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
80 RK3308_DIV_PCLK_DBG_SHIFT), \
81}
82
83#define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
84{ \
85 .prate = _prate, \
86 .divs = { \
87 RK3308_CLKSEL0(_aclk_core, _pclk_dbg), \
88 }, \
89}
90
91static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
92 RK3308_CPUCLK_RATE(1608000000, 1, 7),
93 RK3308_CPUCLK_RATE(1512000000, 1, 7),
94 RK3308_CPUCLK_RATE(1488000000, 1, 5),
95 RK3308_CPUCLK_RATE(1416000000, 1, 5),
96 RK3308_CPUCLK_RATE(1392000000, 1, 5),
97 RK3308_CPUCLK_RATE(1296000000, 1, 5),
98 RK3308_CPUCLK_RATE(1200000000, 1, 5),
99 RK3308_CPUCLK_RATE(1104000000, 1, 5),
100 RK3308_CPUCLK_RATE(1008000000, 1, 5),
101 RK3308_CPUCLK_RATE(912000000, 1, 5),
102 RK3308_CPUCLK_RATE(816000000, 1, 3),
103 RK3308_CPUCLK_RATE(696000000, 1, 3),
104 RK3308_CPUCLK_RATE(600000000, 1, 3),
105 RK3308_CPUCLK_RATE(408000000, 1, 1),
106 RK3308_CPUCLK_RATE(312000000, 1, 1),
107 RK3308_CPUCLK_RATE(216000000, 1, 1),
108 RK3308_CPUCLK_RATE(96000000, 1, 1),
109};
110
111static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
112 .core_reg = RK3308_CLKSEL_CON(0),
113 .div_core_shift = 0,
114 .div_core_mask = 0xf,
115 .mux_core_alt = 1,
116 .mux_core_main = 0,
117 .mux_core_shift = 6,
118 .mux_core_mask = 0x3,
119};
120
121PNAME(mux_pll_p) = { "xin24m" };
122PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
123PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
124PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
125PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
126PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
127PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
128PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
129PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
130PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
131PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
132PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
133PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
134PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
135PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
136PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
137PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
138PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
139PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
140PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
141PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
142PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" };
143PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
144PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
145PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
146PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
147PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" };
148PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" };
149PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
150PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
151PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
152PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" };
153PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
154PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
155PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
156PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
157PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" };
158PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
159PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
160PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
161PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
162PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" };
163PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
164PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
165PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
166PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
167PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" };
168PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
169PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
170PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
171PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" };
172PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
173PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
174PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
175PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
176PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
177PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
178
179static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
180 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
181 0, RK3308_PLL_CON(0),
182 RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
183 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
184 0, RK3308_PLL_CON(8),
185 RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
186 [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
187 0, RK3308_PLL_CON(16),
188 RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),
189 [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
190 0, RK3308_PLL_CON(24),
191 RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates),
192};
193
194#define MFLAGS CLK_MUX_HIWORD_MASK
195#define DFLAGS CLK_DIVIDER_HIWORD_MASK
196#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
197
198static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata =
199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
200 RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
201
202static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata =
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
204 RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
205
206static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata =
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
208 RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
209
210static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata =
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
212 RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
213
214static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata =
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
216 RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
217
218static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata =
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
220 RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
221
222static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata =
223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
224 RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
225
226static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata =
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
228 RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
229
230static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata =
231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
232 RK3308_CLKSEL_CON(52), 10, 2, MFLAGS);
233
234static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata =
235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
236 RK3308_CLKSEL_CON(54), 10, 2, MFLAGS);
237
238static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata =
239 MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
240 RK3308_CLKSEL_CON(56), 10, 2, MFLAGS);
241
242static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata =
243 MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
244 RK3308_CLKSEL_CON(58), 10, 2, MFLAGS);
245
246static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata =
247 MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT,
248 RK3308_CLKSEL_CON(60), 10, 2, MFLAGS);
249
250static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata =
251 MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT,
252 RK3308_CLKSEL_CON(62), 10, 2, MFLAGS);
253
254static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata =
255 MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT,
256 RK3308_CLKSEL_CON(64), 10, 2, MFLAGS);
257
258static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata =
259 MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT,
260 RK3308_CLKSEL_CON(66), 10, 2, MFLAGS);
261
262static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata =
263 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
264 RK3308_CLKSEL_CON(68), 10, 2, MFLAGS);
265
266static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata =
267 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
268 RK3308_CLKSEL_CON(70), 10, 2, MFLAGS);
269
270static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata =
271 MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT,
272 RK3308_CLKSEL_CON(48), 14, 2, MFLAGS);
273
274static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata =
275 MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT,
276 RK3308_CLKSEL_CON(50), 15, 1, MFLAGS);
277
278
279static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
280 /*
281 * Clock-Architecture Diagram 1
282 */
283
284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
285 RK3308_MODE_CON, 8, 2, MFLAGS),
286 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
287
288 /*
289 * Clock-Architecture Diagram 2
290 */
291
292 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
293 RK3308_CLKGATE_CON(0), 0, GFLAGS),
294 GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
295 RK3308_CLKGATE_CON(0), 0, GFLAGS),
296 GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
297 RK3308_CLKGATE_CON(0), 0, GFLAGS),
298 COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
299 RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
300 RK3308_CLKGATE_CON(0), 2, GFLAGS),
301 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
302 RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
303 RK3308_CLKGATE_CON(0), 1, GFLAGS),
304
305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
306 RK3308_CLKGATE_CON(0), 3, GFLAGS),
307
308 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
309 RK3308_CLKGATE_CON(0), 4, GFLAGS),
310
311 /*
312 * Clock-Architecture Diagram 3
313 */
314
315 COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
316 RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
317 RK3308_CLKGATE_CON(1), 0, GFLAGS),
318 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
319 RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
320 RK3308_CLKGATE_CON(1), 3, GFLAGS),
321 GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
322 RK3308_CLKGATE_CON(4), 15, GFLAGS),
323 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
324 RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
325 RK3308_CLKGATE_CON(1), 2, GFLAGS),
326 COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
327 RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
328 RK3308_CLKGATE_CON(1), 1, GFLAGS),
329
330 COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
331 RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
332 RK3308_CLKGATE_CON(1), 9, GFLAGS),
333 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
334 RK3308_CLKSEL_CON(12), 0,
335 RK3308_CLKGATE_CON(1), 11, GFLAGS,
336 &rk3308_uart0_fracmux),
337 GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
338 RK3308_CLKGATE_CON(1), 12, GFLAGS),
339
340 COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
341 RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
342 RK3308_CLKGATE_CON(1), 13, GFLAGS),
343 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
344 RK3308_CLKSEL_CON(15), 0,
345 RK3308_CLKGATE_CON(1), 15, GFLAGS,
346 &rk3308_uart1_fracmux),
347 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
348 RK3308_CLKGATE_CON(2), 0, GFLAGS),
349
350 COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
351 RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
352 RK3308_CLKGATE_CON(2), 1, GFLAGS),
353 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
354 RK3308_CLKSEL_CON(18), 0,
355 RK3308_CLKGATE_CON(2), 3, GFLAGS,
356 &rk3308_uart2_fracmux),
357 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
358 RK3308_CLKGATE_CON(2), 4, GFLAGS),
359
360 COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
361 RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
362 RK3308_CLKGATE_CON(2), 5, GFLAGS),
363 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
364 RK3308_CLKSEL_CON(21), 0,
365 RK3308_CLKGATE_CON(2), 7, GFLAGS,
366 &rk3308_uart3_fracmux),
367 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
368 RK3308_CLKGATE_CON(2), 8, GFLAGS),
369
370 COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
371 RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
372 RK3308_CLKGATE_CON(2), 9, GFLAGS),
373 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
374 RK3308_CLKSEL_CON(24), 0,
375 RK3308_CLKGATE_CON(2), 11, GFLAGS,
376 &rk3308_uart4_fracmux),
377 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
378 RK3308_CLKGATE_CON(2), 12, GFLAGS),
379
380 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
381 RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS,
382 RK3308_CLKGATE_CON(2), 13, GFLAGS),
383 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
384 RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS,
385 RK3308_CLKGATE_CON(2), 14, GFLAGS),
386 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
387 RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS,
388 RK3308_CLKGATE_CON(2), 15, GFLAGS),
389 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
390 RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
391 RK3308_CLKGATE_CON(3), 0, GFLAGS),
392
393 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
394 RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
395 RK3308_CLKGATE_CON(3), 1, GFLAGS),
396 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
397 RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
398 RK3308_CLKGATE_CON(15), 0, GFLAGS),
399 COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
400 RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
401 RK3308_CLKGATE_CON(15), 1, GFLAGS),
402
403 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
404 RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
405 RK3308_CLKGATE_CON(3), 2, GFLAGS),
406 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
407 RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
408 RK3308_CLKGATE_CON(3), 3, GFLAGS),
409 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
410 RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
411 RK3308_CLKGATE_CON(3), 4, GFLAGS),
412
413 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
414 RK3308_CLKGATE_CON(3), 10, GFLAGS),
415 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
416 RK3308_CLKGATE_CON(3), 11, GFLAGS),
417 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
418 RK3308_CLKGATE_CON(3), 12, GFLAGS),
419 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
420 RK3308_CLKGATE_CON(3), 13, GFLAGS),
421 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
422 RK3308_CLKGATE_CON(3), 14, GFLAGS),
423 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
424 RK3308_CLKGATE_CON(3), 15, GFLAGS),
425
426 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
427 RK3308_CLKSEL_CON(33), 0, 11, DFLAGS,
428 RK3308_CLKGATE_CON(3), 5, GFLAGS),
429 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
430 RK3308_CLKSEL_CON(34), 0, 11, DFLAGS,
431 RK3308_CLKGATE_CON(3), 6, GFLAGS),
432
433 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
434 RK3308_CLKSEL_CON(35), 0, 4, DFLAGS,
435 RK3308_CLKGATE_CON(3), 7, GFLAGS),
436 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
437 RK3308_CLKSEL_CON(35), 4, 2, DFLAGS,
438 RK3308_CLKGATE_CON(3), 8, GFLAGS),
439
440 GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
441 RK3308_CLKGATE_CON(3), 9, GFLAGS),
442
443 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
444 RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
445 RK3308_CLKGATE_CON(1), 4, GFLAGS),
446 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
447 RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS,
448 RK3308_CLKGATE_CON(1), 5, GFLAGS),
449
450 COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
451 RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
452 RK3308_CLKGATE_CON(1), 6, GFLAGS),
453 COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
454 RK3308_CLKSEL_CON(9), 0,
455 RK3308_CLKGATE_CON(1), 7, GFLAGS,
456 &rk3308_dclk_vop_fracmux),
457 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
458 RK3308_CLKGATE_CON(1), 8, GFLAGS),
459
460 /*
461 * Clock-Architecture Diagram 4
462 */
463
464 COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
465 RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
466 RK3308_CLKGATE_CON(8), 0, GFLAGS),
467 COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
468 RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
469 RK3308_CLKGATE_CON(8), 1, GFLAGS),
470 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
471 RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
472 RK3308_CLKGATE_CON(8), 2, GFLAGS),
473 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
474 RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
475 RK3308_CLKGATE_CON(8), 3, GFLAGS),
476
477 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
478 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
479 RK3308_CLKGATE_CON(8), 4, GFLAGS),
480 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
481 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
482 RK3308_CLKGATE_CON(8), 4, GFLAGS),
483 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
484 RK3308_CLKSEL_CON(38), 15, 1, MFLAGS,
485 RK3308_CLKGATE_CON(8), 5, GFLAGS),
486
487 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
488 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
489 RK3308_CLKGATE_CON(8), 6, GFLAGS),
490 COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
491 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
492 RK3308_CLKGATE_CON(8), 6, GFLAGS),
493 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
494 RK3308_CLKSEL_CON(39), 15, 1, MFLAGS,
495 RK3308_CLKGATE_CON(8), 7, GFLAGS),
496 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1),
497 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
498
499 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
500 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
501 RK3308_CLKGATE_CON(8), 8, GFLAGS),
502 COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
503 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
504 RK3308_CLKGATE_CON(8), 8, GFLAGS),
505 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
506 RK3308_CLKSEL_CON(40), 15, 1, MFLAGS,
507 RK3308_CLKGATE_CON(8), 9, GFLAGS),
508 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1),
509 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1),
510
511 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
512 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
513 RK3308_CLKGATE_CON(8), 10, GFLAGS),
514 COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
515 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
516 RK3308_CLKGATE_CON(8), 10, GFLAGS),
517 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
518 RK3308_CLKSEL_CON(41), 15, 1, MFLAGS,
519 RK3308_CLKGATE_CON(8), 11, GFLAGS),
520 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1),
521 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1),
522
523 COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
524 RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS,
525 RK3308_CLKGATE_CON(8), 12, GFLAGS),
526
527 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0,
528 RK3308_CLKGATE_CON(8), 13, GFLAGS),
529
530 COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
531 RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
532 RK3308_CLKGATE_CON(8), 14, GFLAGS),
533 MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT,
534 RK3308_CLKSEL_CON(43), 14, 1, MFLAGS),
535 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0,
536 RK3308_CLKGATE_CON(9), 1, GFLAGS),
537 GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0,
538 RK3308_CLKGATE_CON(9), 0, GFLAGS),
539 FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2),
540 FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20),
541 MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
542 RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
543
544 COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
545 RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
546 RK3308_CLKGATE_CON(8), 15, GFLAGS),
547
548 /*
549 * Clock-Architecture Diagram 5
550 */
551
552 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
553 RK3308_CLKGATE_CON(0), 12, GFLAGS),
554
555 GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
556 RK3308_CLKGATE_CON(4), 10, GFLAGS),
557 GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
558 RK3308_CLKGATE_CON(4), 11, GFLAGS),
559 GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
560 RK3308_CLKGATE_CON(4), 12, GFLAGS),
561 GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
562 RK3308_CLKGATE_CON(4), 13, GFLAGS),
563
564 COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
565 RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
566 RK3308_CLKGATE_CON(0), 10, GFLAGS),
567 GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
568 RK3308_CLKGATE_CON(0), 11, GFLAGS),
569 FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
570 RK3308_CLKGATE_CON(0), 13, GFLAGS),
571 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
572 RK3308_CLKSEL_CON(1), 8, 1, MFLAGS,
573 RK3308_CLKGATE_CON(4), 14, GFLAGS),
574
575 /*
576 * Clock-Architecture Diagram 6
577 */
578
579 GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
580 RK3308_CLKGATE_CON(4), 5, GFLAGS),
581 GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
582 RK3308_CLKGATE_CON(4), 6, GFLAGS),
583
584 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
585 RK3308_CLKSEL_CON(3), 0,
586 RK3308_CLKGATE_CON(4), 3, GFLAGS,
587 &rk3308_rtc32k_fracmux),
588 MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
589 RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
590 COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
591 RK3308_CLKSEL_CON(4), 0, 16, DFLAGS,
592 RK3308_CLKGATE_CON(4), 2, GFLAGS),
593
594 COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
595 RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS,
596 RK3308_CLKGATE_CON(4), 7, GFLAGS),
597 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
598 RK3308_CLKSEL_CON(72), 7, 1, MFLAGS,
599 RK3308_CLKGATE_CON(4), 8, GFLAGS),
600
601 GATE(0, "clk_wifi_dpll", "dpll", 0,
602 RK3308_CLKGATE_CON(15), 2, GFLAGS),
603 GATE(0, "clk_wifi_vpll0", "vpll0", 0,
604 RK3308_CLKGATE_CON(15), 3, GFLAGS),
605 GATE(0, "clk_wifi_osc", "xin24m", 0,
606 RK3308_CLKGATE_CON(15), 4, GFLAGS),
607 COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
608 RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS,
609 RK3308_CLKGATE_CON(4), 0, GFLAGS),
610 COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
611 RK3308_CLKSEL_CON(44), 7, 1, MFLAGS,
612 RK3308_CLKGATE_CON(4), 1, GFLAGS),
613
614 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
615 RK3308_CLKGATE_CON(4), 4, GFLAGS),
616
617 /*
618 * Clock-Architecture Diagram 7
619 */
620
621 COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
622 RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
623 RK3308_CLKGATE_CON(10), 0, GFLAGS),
624 COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
625 RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
626 RK3308_CLKGATE_CON(10), 1, GFLAGS),
627 COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
628 RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
629 RK3308_CLKGATE_CON(10), 2, GFLAGS),
630
631 COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0,
632 RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS,
633 RK3308_CLKGATE_CON(10), 3, GFLAGS),
634 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
635 RK3308_CLKSEL_CON(47), 0,
636 RK3308_CLKGATE_CON(10), 4, GFLAGS,
637 &rk3308_pdm_fracmux),
638 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
639 RK3308_CLKGATE_CON(10), 5, GFLAGS),
640
641 COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
642 RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
643 RK3308_CLKGATE_CON(10), 12, GFLAGS),
644 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
645 RK3308_CLKSEL_CON(53), 0,
646 RK3308_CLKGATE_CON(10), 13, GFLAGS,
647 &rk3308_i2s0_8ch_tx_fracmux),
648 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
649 RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
650 RK3308_CLKGATE_CON(10), 14, GFLAGS),
651 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
652 RK3308_CLKSEL_CON(52), 15, 1, MFLAGS,
653 RK3308_CLKGATE_CON(10), 15, GFLAGS),
654
655 COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
656 RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
657 RK3308_CLKGATE_CON(11), 0, GFLAGS),
658 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
659 RK3308_CLKSEL_CON(55), 0,
660 RK3308_CLKGATE_CON(11), 1, GFLAGS,
661 &rk3308_i2s0_8ch_rx_fracmux),
662 COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
663 RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
664 RK3308_CLKGATE_CON(11), 2, GFLAGS),
665 GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0,
666 RK3308_CLKGATE_CON(11), 3, GFLAGS),
667
668 COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
669 RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
670 RK3308_CLKGATE_CON(11), 4, GFLAGS),
671 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
672 RK3308_CLKSEL_CON(57), 0,
673 RK3308_CLKGATE_CON(11), 5, GFLAGS,
674 &rk3308_i2s1_8ch_tx_fracmux),
675 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
676 RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
677 RK3308_CLKGATE_CON(11), 6, GFLAGS),
678 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT,
679 RK3308_CLKSEL_CON(56), 15, 1, MFLAGS,
680 RK3308_CLKGATE_CON(11), 7, GFLAGS),
681
682 COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
683 RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
684 RK3308_CLKGATE_CON(11), 8, GFLAGS),
685 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
686 RK3308_CLKSEL_CON(59), 0,
687 RK3308_CLKGATE_CON(11), 9, GFLAGS,
688 &rk3308_i2s1_8ch_rx_fracmux),
689 COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
690 RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
691 RK3308_CLKGATE_CON(11), 10, GFLAGS),
692 GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0,
693 RK3308_CLKGATE_CON(11), 11, GFLAGS),
694
695 COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
696 RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
697 RK3308_CLKGATE_CON(11), 12, GFLAGS),
698 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
699 RK3308_CLKSEL_CON(61), 0,
700 RK3308_CLKGATE_CON(11), 13, GFLAGS,
701 &rk3308_i2s2_8ch_tx_fracmux),
702 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
703 RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
704 RK3308_CLKGATE_CON(11), 14, GFLAGS),
705 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT,
706 RK3308_CLKSEL_CON(60), 15, 1, MFLAGS,
707 RK3308_CLKGATE_CON(11), 15, GFLAGS),
708
709 COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
710 RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
711 RK3308_CLKGATE_CON(12), 0, GFLAGS),
712 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
713 RK3308_CLKSEL_CON(63), 0,
714 RK3308_CLKGATE_CON(12), 1, GFLAGS,
715 &rk3308_i2s2_8ch_rx_fracmux),
716 COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
717 RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
718 RK3308_CLKGATE_CON(12), 2, GFLAGS),
719 GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0,
720 RK3308_CLKGATE_CON(12), 3, GFLAGS),
721
722 COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
723 RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
724 RK3308_CLKGATE_CON(12), 4, GFLAGS),
725 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
726 RK3308_CLKSEL_CON(65), 0,
727 RK3308_CLKGATE_CON(12), 5, GFLAGS,
728 &rk3308_i2s3_8ch_tx_fracmux),
729 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
730 RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
731 RK3308_CLKGATE_CON(12), 6, GFLAGS),
732 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT,
733 RK3308_CLKSEL_CON(64), 15, 1, MFLAGS,
734 RK3308_CLKGATE_CON(12), 7, GFLAGS),
735
736 COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
737 RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
738 RK3308_CLKGATE_CON(12), 8, GFLAGS),
739 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
740 RK3308_CLKSEL_CON(67), 0,
741 RK3308_CLKGATE_CON(12), 9, GFLAGS,
742 &rk3308_i2s3_8ch_rx_fracmux),
743 COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
744 RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
745 RK3308_CLKGATE_CON(12), 10, GFLAGS),
746 GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0,
747 RK3308_CLKGATE_CON(12), 11, GFLAGS),
748
749 COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
750 RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
751 RK3308_CLKGATE_CON(12), 12, GFLAGS),
752 COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
753 RK3308_CLKSEL_CON(69), 0,
754 RK3308_CLKGATE_CON(12), 13, GFLAGS,
755 &rk3308_i2s0_2ch_fracmux),
756 GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
757 RK3308_CLKGATE_CON(12), 14, GFLAGS),
758 COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
759 RK3308_CLKSEL_CON(68), 15, 1, MFLAGS,
760 RK3308_CLKGATE_CON(12), 15, GFLAGS),
761
762 COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
763 RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS,
764 RK3308_CLKGATE_CON(13), 0, GFLAGS),
765 COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
766 RK3308_CLKSEL_CON(71), 0,
767 RK3308_CLKGATE_CON(13), 1, GFLAGS,
768 &rk3308_i2s1_2ch_fracmux),
769 GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
770 RK3308_CLKGATE_CON(13), 2, GFLAGS),
771 COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
772 RK3308_CLKSEL_CON(70), 15, 1, MFLAGS,
773 RK3308_CLKGATE_CON(13), 3, GFLAGS),
774
775 COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
776 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
777 RK3308_CLKGATE_CON(10), 6, GFLAGS),
778 COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
779 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
780 RK3308_CLKGATE_CON(10), 6, GFLAGS),
781 MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
782 RK3308_CLKSEL_CON(48), 12, 1, MFLAGS),
783 COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
784 RK3308_CLKSEL_CON(49), 0,
785 RK3308_CLKGATE_CON(10), 7, GFLAGS,
786 &rk3308_spdif_tx_fracmux),
787 GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
788 RK3308_CLKGATE_CON(10), 8, GFLAGS),
789
790 COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
791 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
792 RK3308_CLKGATE_CON(10), 9, GFLAGS),
793 COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
794 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
795 RK3308_CLKGATE_CON(10), 9, GFLAGS),
796 MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
797 RK3308_CLKSEL_CON(50), 14, 1, MFLAGS),
798 COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
799 RK3308_CLKSEL_CON(51), 0,
800 RK3308_CLKGATE_CON(10), 10, GFLAGS,
801 &rk3308_spdif_rx_fracmux),
802 GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
803 RK3308_CLKGATE_CON(10), 11, GFLAGS),
804
805 /*
806 * Clock-Architecture Diagram 8
807 */
808
809 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS),
810 GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS),
811 GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS),
812 GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS),
813 GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS),
814
815 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS),
816 GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS),
817 GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS),
818
819 GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS),
820 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
821 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS),
822 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS),
823 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS),
824 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS),
825 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS),
826 GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS),
827 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS),
828
829 GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS),
830 GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS),
831
832 GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS),
833 GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS),
834 GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS),
835 GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS),
836 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
837 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS),
838 GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS),
839 GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS),
840 GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS),
841 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS),
842 GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS),
843
844 GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS),
845 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS),
846
847 GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS),
848 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS),
849 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
850 GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
851 GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
852 /* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
853 SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
854 /* aclk_dmac1 is controlled by sgrf_clkgat_con. */
855 SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
856 /* watchdog pclk is controlled by sgrf_clkgat_con. */
857 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
858
859 GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
860 GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
861 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS),
862 GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS),
863
864 GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS),
865 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
866 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
867 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
868 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
869 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS),
870 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
871 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
872 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
873 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
874 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
875 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
876 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
877 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
878 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS),
879 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS),
880 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS),
881 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS),
882 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
883 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
884 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS),
885 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS),
886 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS),
887 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS),
888 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS),
889 GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS),
890 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS),
891 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS),
892 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS),
893 GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS),
894 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS),
895 GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
896 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
897 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
898 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
899 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
900 GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
901 GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
902};
903
904static const char *const rk3308_critical_clocks[] __initconst = {
905 "aclk_bus",
906 "hclk_bus",
907 "pclk_bus",
908 "aclk_peri",
909 "hclk_peri",
910 "pclk_peri",
911 "hclk_audio",
912 "pclk_audio",
913 "sclk_ddrc",
914};
915
916static void __init rk3308_clk_init(struct device_node *np)
917{
918 struct rockchip_clk_provider *ctx;
919 void __iomem *reg_base;
920
921 reg_base = of_iomap(np, 0);
922 if (!reg_base) {
923 pr_err("%s: could not map cru region\n", __func__);
924 return;
925 }
926
927 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
928 if (IS_ERR(ctx)) {
929 pr_err("%s: rockchip clk init failed\n", __func__);
930 iounmap(reg_base);
931 return;
932 }
933
934 rockchip_clk_register_plls(ctx, rk3308_pll_clks,
935 ARRAY_SIZE(rk3308_pll_clks),
936 RK3308_GRF_SOC_STATUS0);
937 rockchip_clk_register_branches(ctx, rk3308_clk_branches,
938 ARRAY_SIZE(rk3308_clk_branches));
939 rockchip_clk_protect_critical(rk3308_critical_clocks,
940 ARRAY_SIZE(rk3308_critical_clocks));
941
942 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
943 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
944 &rk3308_cpuclk_data, rk3308_cpuclk_rates,
945 ARRAY_SIZE(rk3308_cpuclk_rates));
946
947 rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0),
948 ROCKCHIP_SOFTRST_HIWORD_MASK);
949
950 rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL);
951
952 rockchip_clk_of_add_provider(np, ctx);
953}
954
955CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 96cc6af5632c..5947d3192866 100644
--- a/drivers/clk/rockchip/clk-rv1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -122,7 +122,6 @@ PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
122PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 122PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
123PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 123PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
124PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" }; 124PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
125PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" };
126PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 125PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
127PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 126PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
128PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" }; 127PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index b811597a3d38..2271a84124b0 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -121,6 +121,19 @@ struct clk;
121#define RK3288_EMMC_CON0 0x218 121#define RK3288_EMMC_CON0 0x218
122#define RK3288_EMMC_CON1 0x21c 122#define RK3288_EMMC_CON1 0x21c
123 123
124#define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
125#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
126#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
127#define RK3308_GLB_SRST_FST 0xb8
128#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
129#define RK3308_MODE_CON 0xa0
130#define RK3308_SDMMC_CON0 0x480
131#define RK3308_SDMMC_CON1 0x484
132#define RK3308_SDIO_CON0 0x488
133#define RK3308_SDIO_CON1 0x48c
134#define RK3308_EMMC_CON0 0x490
135#define RK3308_EMMC_CON1 0x494
136
124#define RK3328_PLL_CON(x) RK2928_PLL_CON(x) 137#define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
125#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 138#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
126#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 139#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c
index ad7951b6b285..dcf4e25a0216 100644
--- a/drivers/clk/sirf/clk-common.c
+++ b/drivers/clk/sirf/clk-common.c
@@ -297,9 +297,10 @@ static u8 dmn_clk_get_parent(struct clk_hw *hw)
297{ 297{
298 struct clk_dmn *clk = to_dmnclk(hw); 298 struct clk_dmn *clk = to_dmnclk(hw);
299 u32 cfg = clkc_readl(clk->regofs); 299 u32 cfg = clkc_readl(clk->regofs);
300 const char *name = clk_hw_get_name(hw);
300 301
301 /* parent of io domain can only be pll3 */ 302 /* parent of io domain can only be pll3 */
302 if (strcmp(hw->init->name, "io") == 0) 303 if (strcmp(name, "io") == 0)
303 return 4; 304 return 4;
304 305
305 WARN_ON((cfg & (BIT(3) - 1)) > 4); 306 WARN_ON((cfg & (BIT(3) - 1)) > 4);
@@ -311,9 +312,10 @@ static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
311{ 312{
312 struct clk_dmn *clk = to_dmnclk(hw); 313 struct clk_dmn *clk = to_dmnclk(hw);
313 u32 cfg = clkc_readl(clk->regofs); 314 u32 cfg = clkc_readl(clk->regofs);
315 const char *name = clk_hw_get_name(hw);
314 316
315 /* parent of io domain can only be pll3 */ 317 /* parent of io domain can only be pll3 */
316 if (strcmp(hw->init->name, "io") == 0) 318 if (strcmp(name, "io") == 0)
317 return -EINVAL; 319 return -EINVAL;
318 320
319 cfg &= ~(BIT(3) - 1); 321 cfg &= ~(BIT(3) - 1);
@@ -353,7 +355,8 @@ static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
353{ 355{
354 unsigned long fin; 356 unsigned long fin;
355 unsigned ratio, wait, hold; 357 unsigned ratio, wait, hold;
356 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; 358 const char *name = clk_hw_get_name(hw);
359 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
357 360
358 fin = *parent_rate; 361 fin = *parent_rate;
359 ratio = fin / rate; 362 ratio = fin / rate;
@@ -375,7 +378,8 @@ static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
375 struct clk_dmn *clk = to_dmnclk(hw); 378 struct clk_dmn *clk = to_dmnclk(hw);
376 unsigned long fin; 379 unsigned long fin;
377 unsigned ratio, wait, hold, reg; 380 unsigned ratio, wait, hold, reg;
378 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4; 381 const char *name = clk_hw_get_name(hw);
382 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
379 383
380 fin = parent_rate; 384 fin = parent_rate;
381 ratio = fin / rate; 385 ratio = fin / rate;
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 3966cd43b552..43ecd507bf83 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -30,22 +30,23 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
30{ 30{
31 u32 l4_src; 31 u32 l4_src;
32 u32 perpll_src; 32 u32 perpll_src;
33 const char *name = clk_hw_get_name(hwclk);
33 34
34 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 35 if (streq(name, SOCFPGA_L4_MP_CLK)) {
35 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 36 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
36 return l4_src &= 0x1; 37 return l4_src &= 0x1;
37 } 38 }
38 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 39 if (streq(name, SOCFPGA_L4_SP_CLK)) {
39 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 40 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
40 return !!(l4_src & 2); 41 return !!(l4_src & 2);
41 } 42 }
42 43
43 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 44 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
44 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) 45 if (streq(name, SOCFPGA_MMC_CLK))
45 return perpll_src &= 0x3; 46 return perpll_src &= 0x3;
46 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 47 if (streq(name, SOCFPGA_NAND_CLK) ||
47 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) 48 streq(name, SOCFPGA_NAND_X_CLK))
48 return (perpll_src >> 2) & 3; 49 return (perpll_src >> 2) & 3;
49 50
50 /* QSPI clock */ 51 /* QSPI clock */
51 return (perpll_src >> 4) & 3; 52 return (perpll_src >> 4) & 3;
@@ -55,24 +56,25 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
55static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) 56static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
56{ 57{
57 u32 src_reg; 58 u32 src_reg;
59 const char *name = clk_hw_get_name(hwclk);
58 60
59 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 61 if (streq(name, SOCFPGA_L4_MP_CLK)) {
60 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 62 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
61 src_reg &= ~0x1; 63 src_reg &= ~0x1;
62 src_reg |= parent; 64 src_reg |= parent;
63 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 65 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
64 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 66 } else if (streq(name, SOCFPGA_L4_SP_CLK)) {
65 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 67 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
66 src_reg &= ~0x2; 68 src_reg &= ~0x2;
67 src_reg |= (parent << 1); 69 src_reg |= (parent << 1);
68 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 70 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
69 } else { 71 } else {
70 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 72 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
71 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { 73 if (streq(name, SOCFPGA_MMC_CLK)) {
72 src_reg &= ~0x3; 74 src_reg &= ~0x3;
73 src_reg |= parent; 75 src_reg |= parent;
74 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 76 } else if (streq(name, SOCFPGA_NAND_CLK) ||
75 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) { 77 streq(name, SOCFPGA_NAND_X_CLK)) {
76 src_reg &= ~0xC; 78 src_reg &= ~0xC;
77 src_reg |= (parent << 2); 79 src_reg |= (parent << 2);
78 } else {/* QSPI clock */ 80 } else {/* QSPI clock */
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index a8ff7229611d..3e0c55727b89 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -40,11 +40,12 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
40{ 40{
41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); 41 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
42 u32 clk_src; 42 u32 clk_src;
43 const char *name = clk_hw_get_name(hwclk);
43 44
44 clk_src = readl(socfpgaclk->hw.reg); 45 clk_src = readl(socfpgaclk->hw.reg);
45 if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) || 46 if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
46 streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) || 47 streq(name, SOCFPGA_NOC_FREE_CLK) ||
47 streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK)) 48 streq(name, SOCFPGA_SDMMC_FREE_CLK))
48 return (clk_src >> CLK_MGR_FREE_SHIFT) & 49 return (clk_src >> CLK_MGR_FREE_SHIFT) &
49 CLK_MGR_FREE_MASK; 50 CLK_MGR_FREE_MASK;
50 else 51 else
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index e5bc8c828cf0..9163bbb46411 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -335,7 +335,7 @@ static const struct aux_clk_masks i2s_prs1_masks = {
335}; 335};
336 336
337/* i2s sclk (bit clock) syynthesizers masks */ 337/* i2s sclk (bit clock) syynthesizers masks */
338static struct aux_clk_masks i2s_sclk_masks = { 338static const struct aux_clk_masks i2s_sclk_masks = {
339 .eq_sel_mask = AUX_EQ_SEL_MASK, 339 .eq_sel_mask = AUX_EQ_SEL_MASK,
340 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT, 340 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
341 .eq1_mask = AUX_EQ1_SEL, 341 .eq1_mask = AUX_EQ1_SEL,
diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c
index a5bdca1de5d0..9d56eac43832 100644
--- a/drivers/clk/sprd/common.c
+++ b/drivers/clk/sprd/common.c
@@ -76,16 +76,17 @@ int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)
76 struct clk_hw *hw; 76 struct clk_hw *hw;
77 77
78 for (i = 0; i < clkhw->num; i++) { 78 for (i = 0; i < clkhw->num; i++) {
79 const char *name;
79 80
80 hw = clkhw->hws[i]; 81 hw = clkhw->hws[i];
81
82 if (!hw) 82 if (!hw)
83 continue; 83 continue;
84 84
85 name = hw->init->name;
85 ret = devm_clk_hw_register(dev, hw); 86 ret = devm_clk_hw_register(dev, hw);
86 if (ret) { 87 if (ret) {
87 dev_err(dev, "Couldn't register clock %d - %s\n", 88 dev_err(dev, "Couldn't register clock %d - %s\n",
88 i, hw->init->name); 89 i, name);
89 return ret; 90 return ret;
90 } 91 }
91 } 92 }
diff --git a/drivers/clk/sprd/pll.c b/drivers/clk/sprd/pll.c
index 36b4402bf09e..640270f51aa5 100644
--- a/drivers/clk/sprd/pll.c
+++ b/drivers/clk/sprd/pll.c
@@ -136,6 +136,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
136 k2 + refin * nint * CLK_PLL_1M; 136 k2 + refin * nint * CLK_PLL_1M;
137 } 137 }
138 138
139 kfree(cfg);
139 return rate; 140 return rate;
140} 141}
141 142
@@ -222,6 +223,7 @@ static int _sprd_pll_set_rate(const struct sprd_pll *pll,
222 if (!ret) 223 if (!ret)
223 udelay(pll->udelay); 224 udelay(pll->udelay);
224 225
226 kfree(cfg);
225 return ret; 227 return ret;
226} 228}
227 229
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index d18e49b4976f..4413b6e04a8e 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -326,6 +326,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
326 return; 326 return;
327 327
328 reg = of_iomap(pnode, 0); 328 reg = of_iomap(pnode, 0);
329 of_node_put(pnode);
329 if (!reg) 330 if (!reg)
330 return; 331 return;
331 332
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index ca1ccdb8a3b1..a156bd0c6af7 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,7 +67,6 @@ struct clkgen_quadfs_data {
67}; 67};
68 68
69static const struct clk_ops st_quadfs_pll_c32_ops; 69static const struct clk_ops st_quadfs_pll_c32_ops;
70static const struct clk_ops st_quadfs_fs660c32_ops;
71 70
72static int clk_fs660c32_dig_get_params(unsigned long input, 71static int clk_fs660c32_dig_get_params(unsigned long input,
73 unsigned long output, struct stm_fs *fs); 72 unsigned long output, struct stm_fs *fs);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8a688bd45ec..c3952f2c42ba 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -61,19 +61,6 @@ static const struct clk_ops stm_pll3200c32_ops;
61static const struct clk_ops stm_pll3200c32_a9_ops; 61static const struct clk_ops stm_pll3200c32_a9_ops;
62static const struct clk_ops stm_pll4600c28_ops; 62static const struct clk_ops stm_pll4600c28_ops;
63 63
64static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
65 /* 407 A0 */
66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
67 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
68 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
69 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
70 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
71 .num_odfs = 1,
72 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
73 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
74 .ops = &stm_pll3200c32_ops,
75};
76
77static const struct clkgen_pll_data st_pll3200c32_cx_0 = { 64static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
78 /* 407 C0 PLL0 */ 65 /* 407 C0 PLL0 */
79 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index aebef4af9861..d89353a3cdec 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -505,7 +505,7 @@ static struct ccu_div i2s3_clk = {
505 .hw.init = CLK_HW_INIT_PARENTS("i2s3", 505 .hw.init = CLK_HW_INIT_PARENTS("i2s3",
506 audio_parents, 506 audio_parents,
507 &ccu_div_ops, 507 &ccu_div_ops,
508 0), 508 CLK_SET_RATE_PARENT),
509 }, 509 },
510}; 510};
511 511
@@ -518,7 +518,7 @@ static struct ccu_div i2s0_clk = {
518 .hw.init = CLK_HW_INIT_PARENTS("i2s0", 518 .hw.init = CLK_HW_INIT_PARENTS("i2s0",
519 audio_parents, 519 audio_parents,
520 &ccu_div_ops, 520 &ccu_div_ops,
521 0), 521 CLK_SET_RATE_PARENT),
522 }, 522 },
523}; 523};
524 524
@@ -531,7 +531,7 @@ static struct ccu_div i2s1_clk = {
531 .hw.init = CLK_HW_INIT_PARENTS("i2s1", 531 .hw.init = CLK_HW_INIT_PARENTS("i2s1",
532 audio_parents, 532 audio_parents,
533 &ccu_div_ops, 533 &ccu_div_ops,
534 0), 534 CLK_SET_RATE_PARENT),
535 }, 535 },
536}; 536};
537 537
@@ -544,7 +544,7 @@ static struct ccu_div i2s2_clk = {
544 .hw.init = CLK_HW_INIT_PARENTS("i2s2", 544 .hw.init = CLK_HW_INIT_PARENTS("i2s2",
545 audio_parents, 545 audio_parents,
546 &ccu_div_ops, 546 &ccu_div_ops,
547 0), 547 CLK_SET_RATE_PARENT),
548 }, 548 },
549}; 549};
550 550
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 9b3939fc7faa..5c779eec454b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -77,7 +77,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
77 BIT(28), /* lock */ 77 BIT(28), /* lock */
78 0); 78 0);
79 79
80static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 80static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
81 "osc24M", 0x020, 81 "osc24M", 0x020,
82 8, 5, /* N */ 82 8, 5, /* N */
83 4, 2, /* K */ 83 4, 2, /* K */
@@ -116,6 +116,14 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
116 2, /* post-div */ 116 2, /* post-div */
117 0); 117 0);
118 118
119static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
120 "osc24M", 0x04c,
121 8, 7, /* N */
122 0, 2, /* M */
123 BIT(31), /* gate */
124 BIT(28), /* lock */
125 0);
126
119static const char * const cpu_parents[] = { "osc32k", "osc24M", 127static const char * const cpu_parents[] = { "osc32k", "osc24M",
120 "pll-cpu", "pll-cpu" }; 128 "pll-cpu", "pll-cpu" };
121static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents, 129static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
@@ -227,6 +235,8 @@ static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
227 0x068, BIT(0), 0); 235 0x068, BIT(0), 0);
228static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 236static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
229 0x068, BIT(5), 0); 237 0x068, BIT(5), 0);
238static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
239 0x068, BIT(12), 0);
230 240
231static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 241static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
232 0x06c, BIT(0), 0); 242 0x06c, BIT(0), 0);
@@ -298,12 +308,18 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
298 BIT(31), /* gate */ 308 BIT(31), /* gate */
299 0); 309 0);
300 310
311static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
312 "pll-audio-2x", "pll-audio" };
313static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
314 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
315
301static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 316static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
302 0x0cc, BIT(8), 0); 317 0x0cc, BIT(8), 0);
303static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 318static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
304 0x0cc, BIT(16), 0); 319 0x0cc, BIT(16), 0);
305 320
306static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" }; 321static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
322 "pll-periph0-2x" };
307static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 323static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
308 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 324 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
309 325
@@ -363,10 +379,11 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = {
363 &pll_audio_base_clk.common, 379 &pll_audio_base_clk.common,
364 &pll_video_clk.common, 380 &pll_video_clk.common,
365 &pll_ve_clk.common, 381 &pll_ve_clk.common,
366 &pll_ddr_clk.common, 382 &pll_ddr0_clk.common,
367 &pll_periph0_clk.common, 383 &pll_periph0_clk.common,
368 &pll_isp_clk.common, 384 &pll_isp_clk.common,
369 &pll_periph1_clk.common, 385 &pll_periph1_clk.common,
386 &pll_ddr1_clk.common,
370 &cpu_clk.common, 387 &cpu_clk.common,
371 &axi_clk.common, 388 &axi_clk.common,
372 &ahb1_clk.common, 389 &ahb1_clk.common,
@@ -433,6 +450,80 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
433 &pll_audio_base_clk.common.hw 450 &pll_audio_base_clk.common.hw
434}; 451};
435 452
453static struct ccu_common *sun8i_v3_ccu_clks[] = {
454 &pll_cpu_clk.common,
455 &pll_audio_base_clk.common,
456 &pll_video_clk.common,
457 &pll_ve_clk.common,
458 &pll_ddr0_clk.common,
459 &pll_periph0_clk.common,
460 &pll_isp_clk.common,
461 &pll_periph1_clk.common,
462 &pll_ddr1_clk.common,
463 &cpu_clk.common,
464 &axi_clk.common,
465 &ahb1_clk.common,
466 &apb1_clk.common,
467 &apb2_clk.common,
468 &ahb2_clk.common,
469 &bus_ce_clk.common,
470 &bus_dma_clk.common,
471 &bus_mmc0_clk.common,
472 &bus_mmc1_clk.common,
473 &bus_mmc2_clk.common,
474 &bus_dram_clk.common,
475 &bus_emac_clk.common,
476 &bus_hstimer_clk.common,
477 &bus_spi0_clk.common,
478 &bus_otg_clk.common,
479 &bus_ehci0_clk.common,
480 &bus_ohci0_clk.common,
481 &bus_ve_clk.common,
482 &bus_tcon0_clk.common,
483 &bus_csi_clk.common,
484 &bus_de_clk.common,
485 &bus_codec_clk.common,
486 &bus_pio_clk.common,
487 &bus_i2s0_clk.common,
488 &bus_i2c0_clk.common,
489 &bus_i2c1_clk.common,
490 &bus_uart0_clk.common,
491 &bus_uart1_clk.common,
492 &bus_uart2_clk.common,
493 &bus_ephy_clk.common,
494 &bus_dbg_clk.common,
495 &mmc0_clk.common,
496 &mmc0_sample_clk.common,
497 &mmc0_output_clk.common,
498 &mmc1_clk.common,
499 &mmc1_sample_clk.common,
500 &mmc1_output_clk.common,
501 &mmc2_clk.common,
502 &mmc2_sample_clk.common,
503 &mmc2_output_clk.common,
504 &ce_clk.common,
505 &spi0_clk.common,
506 &i2s0_clk.common,
507 &usb_phy0_clk.common,
508 &usb_ohci0_clk.common,
509 &dram_clk.common,
510 &dram_ve_clk.common,
511 &dram_csi_clk.common,
512 &dram_ohci_clk.common,
513 &dram_ehci_clk.common,
514 &de_clk.common,
515 &tcon_clk.common,
516 &csi_misc_clk.common,
517 &csi0_mclk_clk.common,
518 &csi1_sclk_clk.common,
519 &csi1_mclk_clk.common,
520 &ve_clk.common,
521 &ac_dig_clk.common,
522 &avs_clk.common,
523 &mbus_clk.common,
524 &mipi_csi_clk.common,
525};
526
436/* We hardcode the divider to 4 for now */ 527/* We hardcode the divider to 4 for now */
437static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", 528static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
438 clk_parent_pll_audio, 529 clk_parent_pll_audio,
@@ -460,11 +551,12 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
460 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 551 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
461 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 552 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
462 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 553 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
463 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 554 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
464 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 555 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
465 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 556 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
466 [CLK_PLL_ISP] = &pll_isp_clk.common.hw, 557 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
467 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 558 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
559 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
468 [CLK_CPU] = &cpu_clk.common.hw, 560 [CLK_CPU] = &cpu_clk.common.hw,
469 [CLK_AXI] = &axi_clk.common.hw, 561 [CLK_AXI] = &axi_clk.common.hw,
470 [CLK_AHB1] = &ahb1_clk.common.hw, 562 [CLK_AHB1] = &ahb1_clk.common.hw,
@@ -502,6 +594,9 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
502 [CLK_MMC1] = &mmc1_clk.common.hw, 594 [CLK_MMC1] = &mmc1_clk.common.hw,
503 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 595 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
504 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 596 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
597 [CLK_MMC2] = &mmc2_clk.common.hw,
598 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
599 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
505 [CLK_CE] = &ce_clk.common.hw, 600 [CLK_CE] = &ce_clk.common.hw,
506 [CLK_SPI0] = &spi0_clk.common.hw, 601 [CLK_SPI0] = &spi0_clk.common.hw,
507 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 602 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
@@ -526,6 +621,88 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
526 .num = CLK_NUMBER, 621 .num = CLK_NUMBER,
527}; 622};
528 623
624static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
625 .hws = {
626 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
627 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
628 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
629 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
630 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
631 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
632 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
633 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
634 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
635 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
636 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
637 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
638 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
639 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
640 [CLK_CPU] = &cpu_clk.common.hw,
641 [CLK_AXI] = &axi_clk.common.hw,
642 [CLK_AHB1] = &ahb1_clk.common.hw,
643 [CLK_APB1] = &apb1_clk.common.hw,
644 [CLK_APB2] = &apb2_clk.common.hw,
645 [CLK_AHB2] = &ahb2_clk.common.hw,
646 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
647 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
648 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
649 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
650 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
651 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
652 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
653 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
654 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
655 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
656 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
657 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
658 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
659 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
660 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
661 [CLK_BUS_DE] = &bus_de_clk.common.hw,
662 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
663 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
664 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
665 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
666 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
667 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
668 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
669 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
670 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
671 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
672 [CLK_MMC0] = &mmc0_clk.common.hw,
673 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
674 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
675 [CLK_MMC1] = &mmc1_clk.common.hw,
676 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
677 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
678 [CLK_MMC2] = &mmc2_clk.common.hw,
679 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
680 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
681 [CLK_CE] = &ce_clk.common.hw,
682 [CLK_SPI0] = &spi0_clk.common.hw,
683 [CLK_I2S0] = &i2s0_clk.common.hw,
684 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
685 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
686 [CLK_DRAM] = &dram_clk.common.hw,
687 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
688 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
689 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
690 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
691 [CLK_DE] = &de_clk.common.hw,
692 [CLK_TCON0] = &tcon_clk.common.hw,
693 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
694 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
695 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
696 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
697 [CLK_VE] = &ve_clk.common.hw,
698 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
699 [CLK_AVS] = &avs_clk.common.hw,
700 [CLK_MBUS] = &mbus_clk.common.hw,
701 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
702 },
703 .num = CLK_NUMBER,
704};
705
529static struct ccu_reset_map sun8i_v3s_ccu_resets[] = { 706static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
530 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 707 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
531 708
@@ -561,6 +738,42 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
561 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 738 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
562}; 739};
563 740
741static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
742 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
743
744 [RST_MBUS] = { 0x0fc, BIT(31) },
745
746 [RST_BUS_CE] = { 0x2c0, BIT(5) },
747 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
748 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
749 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
750 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
751 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
752 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
753 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
754 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
755 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
756 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
757 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
758
759 [RST_BUS_VE] = { 0x2c4, BIT(0) },
760 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
761 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
762 [RST_BUS_DE] = { 0x2c4, BIT(12) },
763 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
764
765 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
766
767 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
768 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
769
770 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
771 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
772 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
773 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
774 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
775};
776
564static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = { 777static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
565 .ccu_clks = sun8i_v3s_ccu_clks, 778 .ccu_clks = sun8i_v3s_ccu_clks,
566 .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks), 779 .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
@@ -571,7 +784,18 @@ static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
571 .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets), 784 .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
572}; 785};
573 786
574static void __init sun8i_v3s_ccu_setup(struct device_node *node) 787static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
788 .ccu_clks = sun8i_v3_ccu_clks,
789 .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks),
790
791 .hw_clks = &sun8i_v3_hw_clks,
792
793 .resets = sun8i_v3_ccu_resets,
794 .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
795};
796
797static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
798 const struct sunxi_ccu_desc *ccu_desc)
575{ 799{
576 void __iomem *reg; 800 void __iomem *reg;
577 u32 val; 801 u32 val;
@@ -587,7 +811,21 @@ static void __init sun8i_v3s_ccu_setup(struct device_node *node)
587 val &= ~GENMASK(19, 16); 811 val &= ~GENMASK(19, 16);
588 writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); 812 writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
589 813
590 sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc); 814 sunxi_ccu_probe(node, reg, ccu_desc);
815}
816
817static void __init sun8i_v3s_ccu_setup(struct device_node *node)
818{
819 sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
820}
821
822static void __init sun8i_v3_ccu_setup(struct device_node *node)
823{
824 sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
591} 825}
826
592CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu", 827CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
593 sun8i_v3s_ccu_setup); 828 sun8i_v3s_ccu_setup);
829
830CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
831 sun8i_v3_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
index fbc1da8b4520..b0160d305a67 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
@@ -20,7 +20,7 @@
20#define CLK_PLL_AUDIO_8X 5 20#define CLK_PLL_AUDIO_8X 5
21#define CLK_PLL_VIDEO 6 21#define CLK_PLL_VIDEO 6
22#define CLK_PLL_VE 7 22#define CLK_PLL_VE 7
23#define CLK_PLL_DDR 8 23#define CLK_PLL_DDR0 8
24#define CLK_PLL_PERIPH0 9 24#define CLK_PLL_PERIPH0 9
25#define CLK_PLL_PERIPH0_2X 10 25#define CLK_PLL_PERIPH0_2X 10
26#define CLK_PLL_ISP 11 26#define CLK_PLL_ISP 11
@@ -49,6 +49,8 @@
49 49
50/* And the GPU module clock is exported */ 50/* And the GPU module clock is exported */
51 51
52#define CLK_NUMBER (CLK_MIPI_CSI + 1) 52#define CLK_PLL_DDR1 74
53
54#define CLK_NUMBER (CLK_I2S0 + 1)
53 55
54#endif /* _CCU_SUN8I_H3_H_ */ 56#endif /* _CCU_SUN8I_H3_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 7fe3ac980e5f..2e20e650b6c0 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -97,14 +97,15 @@ int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
97 97
98 for (i = 0; i < desc->hw_clks->num ; i++) { 98 for (i = 0; i < desc->hw_clks->num ; i++) {
99 struct clk_hw *hw = desc->hw_clks->hws[i]; 99 struct clk_hw *hw = desc->hw_clks->hws[i];
100 const char *name;
100 101
101 if (!hw) 102 if (!hw)
102 continue; 103 continue;
103 104
105 name = hw->init->name;
104 ret = of_clk_hw_register(node, hw); 106 ret = of_clk_hw_register(node, hw);
105 if (ret) { 107 if (ret) {
106 pr_err("Couldn't register clock %d - %s\n", 108 pr_err("Couldn't register clock %d - %s\n", i, name);
107 i, clk_hw_get_name(hw));
108 goto err_clk_unreg; 109 goto err_clk_unreg;
109 } 110 }
110 } 111 }
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 015a657d3382..ac5bc8857a51 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -140,6 +140,7 @@ static void __init omap_clk_register_apll(void *user,
140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
141 struct dpll_data *ad = clk_hw->dpll_data; 141 struct dpll_data *ad = clk_hw->dpll_data;
142 struct clk *clk; 142 struct clk *clk;
143 const struct clk_init_data *init = clk_hw->hw.init;
143 144
144 clk = of_clk_get(node, 0); 145 clk = of_clk_get(node, 0);
145 if (IS_ERR(clk)) { 146 if (IS_ERR(clk)) {
@@ -168,15 +169,15 @@ static void __init omap_clk_register_apll(void *user,
168 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 169 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name);
169 if (!IS_ERR(clk)) { 170 if (!IS_ERR(clk)) {
170 of_clk_add_provider(node, of_clk_src_simple_get, clk); 171 of_clk_add_provider(node, of_clk_src_simple_get, clk);
171 kfree(clk_hw->hw.init->parent_names); 172 kfree(init->parent_names);
172 kfree(clk_hw->hw.init); 173 kfree(init);
173 return; 174 return;
174 } 175 }
175 176
176cleanup: 177cleanup:
177 kfree(clk_hw->dpll_data); 178 kfree(clk_hw->dpll_data);
178 kfree(clk_hw->hw.init->parent_names); 179 kfree(init->parent_names);
179 kfree(clk_hw->hw.init); 180 kfree(init);
180 kfree(clk_hw); 181 kfree(clk_hw);
181} 182}
182 183
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index e8cee6f3b4a0..087cfa75ac24 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -66,6 +66,7 @@ static int __init dm814x_adpll_early_init(void)
66 } 66 }
67 67
68 of_platform_populate(np, NULL, NULL, NULL); 68 of_platform_populate(np, NULL, NULL, NULL);
69 of_node_put(np);
69 70
70 return 0; 71 return 0;
71} 72}
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 659dadb23279..247510e306e2 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -165,6 +165,7 @@ static void __init _register_dpll(void *user,
165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
166 struct dpll_data *dd = clk_hw->dpll_data; 166 struct dpll_data *dd = clk_hw->dpll_data;
167 struct clk *clk; 167 struct clk *clk;
168 const struct clk_init_data *init = hw->init;
168 169
169 clk = of_clk_get(node, 0); 170 clk = of_clk_get(node, 0);
170 if (IS_ERR(clk)) { 171 if (IS_ERR(clk)) {
@@ -196,15 +197,15 @@ static void __init _register_dpll(void *user,
196 197
197 if (!IS_ERR(clk)) { 198 if (!IS_ERR(clk)) {
198 of_clk_add_provider(node, of_clk_src_simple_get, clk); 199 of_clk_add_provider(node, of_clk_src_simple_get, clk);
199 kfree(clk_hw->hw.init->parent_names); 200 kfree(init->parent_names);
200 kfree(clk_hw->hw.init); 201 kfree(init);
201 return; 202 return;
202 } 203 }
203 204
204cleanup: 205cleanup:
205 kfree(clk_hw->dpll_data); 206 kfree(clk_hw->dpll_data);
206 kfree(clk_hw->hw.init->parent_names); 207 kfree(init->parent_names);
207 kfree(clk_hw->hw.init); 208 kfree(init);
208 kfree(clk_hw); 209 kfree(clk_hw);
209} 210}
210 211
@@ -291,14 +292,12 @@ static void __init of_ti_dpll_setup(struct device_node *node,
291 struct dpll_data *dd = NULL; 292 struct dpll_data *dd = NULL;
292 u8 dpll_mode = 0; 293 u8 dpll_mode = 0;
293 294
294 dd = kzalloc(sizeof(*dd), GFP_KERNEL); 295 dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
295 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 296 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
296 init = kzalloc(sizeof(*init), GFP_KERNEL); 297 init = kzalloc(sizeof(*init), GFP_KERNEL);
297 if (!dd || !clk_hw || !init) 298 if (!dd || !clk_hw || !init)
298 goto cleanup; 299 goto cleanup;
299 300
300 memcpy(dd, ddt, sizeof(*dd));
301
302 clk_hw->dpll_data = dd; 301 clk_hw->dpll_data = dd;
303 clk_hw->ops = &clkhwops_omap3_dpll; 302 clk_hw->ops = &clkhwops_omap3_dpll;
304 clk_hw->hw.init = init; 303 clk_hw->hw.init = init;
diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c
index 90bb0b041b7a..fd54d5c0251c 100644
--- a/drivers/clk/versatile/clk-versatile.c
+++ b/drivers/clk/versatile/clk-versatile.c
@@ -70,6 +70,7 @@ static void __init cm_osc_setup(struct device_node *np,
70 return; 70 return;
71 } 71 }
72 cm_base = of_iomap(parent, 0); 72 cm_base = of_iomap(parent, 0);
73 of_node_put(parent);
73 if (!cm_base) { 74 if (!cm_base) {
74 pr_err("could not remap core module base\n"); 75 pr_err("could not remap core module base\n");
75 return; 76 return;
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index fd6c347bec6a..dd7045bc48c1 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -564,6 +564,7 @@ static int __init top_clocks_init(struct device_node *np)
564{ 564{
565 void __iomem *reg_base; 565 void __iomem *reg_base;
566 int i, ret; 566 int i, ret;
567 const char *name;
567 568
568 reg_base = of_iomap(np, 0); 569 reg_base = of_iomap(np, 0);
569 if (!reg_base) { 570 if (!reg_base) {
@@ -573,11 +574,10 @@ static int __init top_clocks_init(struct device_node *np)
573 574
574 for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) { 575 for (i = 0; i < ARRAY_SIZE(zx296718_pll_clk); i++) {
575 zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base; 576 zx296718_pll_clk[i].reg_base += (uintptr_t)reg_base;
577 name = zx296718_pll_clk[i].hw.init->name;
576 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw); 578 ret = clk_hw_register(NULL, &zx296718_pll_clk[i].hw);
577 if (ret) { 579 if (ret)
578 pr_warn("top clk %s init error!\n", 580 pr_warn("top clk %s init error!\n", name);
579 zx296718_pll_clk[i].hw.init->name);
580 }
581 } 581 }
582 582
583 for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) { 583 for (i = 0; i < ARRAY_SIZE(top_ffactor_clk); i++) {
@@ -585,11 +585,10 @@ static int __init top_clocks_init(struct device_node *np)
585 top_hw_onecell_data.hws[top_ffactor_clk[i].id] = 585 top_hw_onecell_data.hws[top_ffactor_clk[i].id] =
586 &top_ffactor_clk[i].factor.hw; 586 &top_ffactor_clk[i].factor.hw;
587 587
588 name = top_ffactor_clk[i].factor.hw.init->name;
588 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw); 589 ret = clk_hw_register(NULL, &top_ffactor_clk[i].factor.hw);
589 if (ret) { 590 if (ret)
590 pr_warn("top clk %s init error!\n", 591 pr_warn("top clk %s init error!\n", name);
591 top_ffactor_clk[i].factor.hw.init->name);
592 }
593 } 592 }
594 593
595 for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) { 594 for (i = 0; i < ARRAY_SIZE(top_mux_clk); i++) {
@@ -598,11 +597,10 @@ static int __init top_clocks_init(struct device_node *np)
598 &top_mux_clk[i].mux.hw; 597 &top_mux_clk[i].mux.hw;
599 598
600 top_mux_clk[i].mux.reg += (uintptr_t)reg_base; 599 top_mux_clk[i].mux.reg += (uintptr_t)reg_base;
600 name = top_mux_clk[i].mux.hw.init->name;
601 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw); 601 ret = clk_hw_register(NULL, &top_mux_clk[i].mux.hw);
602 if (ret) { 602 if (ret)
603 pr_warn("top clk %s init error!\n", 603 pr_warn("top clk %s init error!\n", name);
604 top_mux_clk[i].mux.hw.init->name);
605 }
606 } 604 }
607 605
608 for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) { 606 for (i = 0; i < ARRAY_SIZE(top_gate_clk); i++) {
@@ -611,11 +609,10 @@ static int __init top_clocks_init(struct device_node *np)
611 &top_gate_clk[i].gate.hw; 609 &top_gate_clk[i].gate.hw;
612 610
613 top_gate_clk[i].gate.reg += (uintptr_t)reg_base; 611 top_gate_clk[i].gate.reg += (uintptr_t)reg_base;
612 name = top_gate_clk[i].gate.hw.init->name;
614 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw); 613 ret = clk_hw_register(NULL, &top_gate_clk[i].gate.hw);
615 if (ret) { 614 if (ret)
616 pr_warn("top clk %s init error!\n", 615 pr_warn("top clk %s init error!\n", name);
617 top_gate_clk[i].gate.hw.init->name);
618 }
619 } 616 }
620 617
621 for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) { 618 for (i = 0; i < ARRAY_SIZE(top_div_clk); i++) {
@@ -624,11 +621,10 @@ static int __init top_clocks_init(struct device_node *np)
624 &top_div_clk[i].div.hw; 621 &top_div_clk[i].div.hw;
625 622
626 top_div_clk[i].div.reg += (uintptr_t)reg_base; 623 top_div_clk[i].div.reg += (uintptr_t)reg_base;
624 name = top_div_clk[i].div.hw.init->name;
627 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw); 625 ret = clk_hw_register(NULL, &top_div_clk[i].div.hw);
628 if (ret) { 626 if (ret)
629 pr_warn("top clk %s init error!\n", 627 pr_warn("top clk %s init error!\n", name);
630 top_div_clk[i].div.hw.init->name);
631 }
632 } 628 }
633 629
634 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 630 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
@@ -754,6 +750,7 @@ static int __init lsp0_clocks_init(struct device_node *np)
754{ 750{
755 void __iomem *reg_base; 751 void __iomem *reg_base;
756 int i, ret; 752 int i, ret;
753 const char *name;
757 754
758 reg_base = of_iomap(np, 0); 755 reg_base = of_iomap(np, 0);
759 if (!reg_base) { 756 if (!reg_base) {
@@ -767,11 +764,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
767 &lsp0_mux_clk[i].mux.hw; 764 &lsp0_mux_clk[i].mux.hw;
768 765
769 lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base; 766 lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base;
767 name = lsp0_mux_clk[i].mux.hw.init->name;
770 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw); 768 ret = clk_hw_register(NULL, &lsp0_mux_clk[i].mux.hw);
771 if (ret) { 769 if (ret)
772 pr_warn("lsp0 clk %s init error!\n", 770 pr_warn("lsp0 clk %s init error!\n", name);
773 lsp0_mux_clk[i].mux.hw.init->name);
774 }
775 } 771 }
776 772
777 for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) { 773 for (i = 0; i < ARRAY_SIZE(lsp0_gate_clk); i++) {
@@ -780,11 +776,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
780 &lsp0_gate_clk[i].gate.hw; 776 &lsp0_gate_clk[i].gate.hw;
781 777
782 lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base; 778 lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base;
779 name = lsp0_gate_clk[i].gate.hw.init->name;
783 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw); 780 ret = clk_hw_register(NULL, &lsp0_gate_clk[i].gate.hw);
784 if (ret) { 781 if (ret)
785 pr_warn("lsp0 clk %s init error!\n", 782 pr_warn("lsp0 clk %s init error!\n", name);
786 lsp0_gate_clk[i].gate.hw.init->name);
787 }
788 } 783 }
789 784
790 for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) { 785 for (i = 0; i < ARRAY_SIZE(lsp0_div_clk); i++) {
@@ -793,11 +788,10 @@ static int __init lsp0_clocks_init(struct device_node *np)
793 &lsp0_div_clk[i].div.hw; 788 &lsp0_div_clk[i].div.hw;
794 789
795 lsp0_div_clk[i].div.reg += (uintptr_t)reg_base; 790 lsp0_div_clk[i].div.reg += (uintptr_t)reg_base;
791 name = lsp0_div_clk[i].div.hw.init->name;
796 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw); 792 ret = clk_hw_register(NULL, &lsp0_div_clk[i].div.hw);
797 if (ret) { 793 if (ret)
798 pr_warn("lsp0 clk %s init error!\n", 794 pr_warn("lsp0 clk %s init error!\n", name);
799 lsp0_div_clk[i].div.hw.init->name);
800 }
801 } 795 }
802 796
803 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 797 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
@@ -862,6 +856,7 @@ static int __init lsp1_clocks_init(struct device_node *np)
862{ 856{
863 void __iomem *reg_base; 857 void __iomem *reg_base;
864 int i, ret; 858 int i, ret;
859 const char *name;
865 860
866 reg_base = of_iomap(np, 0); 861 reg_base = of_iomap(np, 0);
867 if (!reg_base) { 862 if (!reg_base) {
@@ -875,11 +870,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
875 &lsp0_mux_clk[i].mux.hw; 870 &lsp0_mux_clk[i].mux.hw;
876 871
877 lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base; 872 lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base;
873 name = lsp1_mux_clk[i].mux.hw.init->name;
878 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw); 874 ret = clk_hw_register(NULL, &lsp1_mux_clk[i].mux.hw);
879 if (ret) { 875 if (ret)
880 pr_warn("lsp1 clk %s init error!\n", 876 pr_warn("lsp1 clk %s init error!\n", name);
881 lsp1_mux_clk[i].mux.hw.init->name);
882 }
883 } 877 }
884 878
885 for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) { 879 for (i = 0; i < ARRAY_SIZE(lsp1_gate_clk); i++) {
@@ -888,11 +882,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
888 &lsp1_gate_clk[i].gate.hw; 882 &lsp1_gate_clk[i].gate.hw;
889 883
890 lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base; 884 lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base;
885 name = lsp1_gate_clk[i].gate.hw.init->name;
891 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw); 886 ret = clk_hw_register(NULL, &lsp1_gate_clk[i].gate.hw);
892 if (ret) { 887 if (ret)
893 pr_warn("lsp1 clk %s init error!\n", 888 pr_warn("lsp1 clk %s init error!\n", name);
894 lsp1_gate_clk[i].gate.hw.init->name);
895 }
896 } 889 }
897 890
898 for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) { 891 for (i = 0; i < ARRAY_SIZE(lsp1_div_clk); i++) {
@@ -901,11 +894,10 @@ static int __init lsp1_clocks_init(struct device_node *np)
901 &lsp1_div_clk[i].div.hw; 894 &lsp1_div_clk[i].div.hw;
902 895
903 lsp1_div_clk[i].div.reg += (uintptr_t)reg_base; 896 lsp1_div_clk[i].div.reg += (uintptr_t)reg_base;
897 name = lsp1_div_clk[i].div.hw.init->name;
904 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw); 898 ret = clk_hw_register(NULL, &lsp1_div_clk[i].div.hw);
905 if (ret) { 899 if (ret)
906 pr_warn("lsp1 clk %s init error!\n", 900 pr_warn("lsp1 clk %s init error!\n", name);
907 lsp1_div_clk[i].div.hw.init->name);
908 }
909 } 901 }
910 902
911 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 903 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
@@ -979,6 +971,7 @@ static int __init audio_clocks_init(struct device_node *np)
979{ 971{
980 void __iomem *reg_base; 972 void __iomem *reg_base;
981 int i, ret; 973 int i, ret;
974 const char *name;
982 975
983 reg_base = of_iomap(np, 0); 976 reg_base = of_iomap(np, 0);
984 if (!reg_base) { 977 if (!reg_base) {
@@ -992,11 +985,10 @@ static int __init audio_clocks_init(struct device_node *np)
992 &audio_mux_clk[i].mux.hw; 985 &audio_mux_clk[i].mux.hw;
993 986
994 audio_mux_clk[i].mux.reg += (uintptr_t)reg_base; 987 audio_mux_clk[i].mux.reg += (uintptr_t)reg_base;
988 name = audio_mux_clk[i].mux.hw.init->name;
995 ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw); 989 ret = clk_hw_register(NULL, &audio_mux_clk[i].mux.hw);
996 if (ret) { 990 if (ret)
997 pr_warn("audio clk %s init error!\n", 991 pr_warn("audio clk %s init error!\n", name);
998 audio_mux_clk[i].mux.hw.init->name);
999 }
1000 } 992 }
1001 993
1002 for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) { 994 for (i = 0; i < ARRAY_SIZE(audio_adiv_clk); i++) {
@@ -1005,11 +997,10 @@ static int __init audio_clocks_init(struct device_node *np)
1005 &audio_adiv_clk[i].hw; 997 &audio_adiv_clk[i].hw;
1006 998
1007 audio_adiv_clk[i].reg_base += (uintptr_t)reg_base; 999 audio_adiv_clk[i].reg_base += (uintptr_t)reg_base;
1000 name = audio_adiv_clk[i].hw.init->name;
1008 ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw); 1001 ret = clk_hw_register(NULL, &audio_adiv_clk[i].hw);
1009 if (ret) { 1002 if (ret)
1010 pr_warn("audio clk %s init error!\n", 1003 pr_warn("audio clk %s init error!\n", name);
1011 audio_adiv_clk[i].hw.init->name);
1012 }
1013 } 1004 }
1014 1005
1015 for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) { 1006 for (i = 0; i < ARRAY_SIZE(audio_div_clk); i++) {
@@ -1018,11 +1009,10 @@ static int __init audio_clocks_init(struct device_node *np)
1018 &audio_div_clk[i].div.hw; 1009 &audio_div_clk[i].div.hw;
1019 1010
1020 audio_div_clk[i].div.reg += (uintptr_t)reg_base; 1011 audio_div_clk[i].div.reg += (uintptr_t)reg_base;
1012 name = audio_div_clk[i].div.hw.init->name;
1021 ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw); 1013 ret = clk_hw_register(NULL, &audio_div_clk[i].div.hw);
1022 if (ret) { 1014 if (ret)
1023 pr_warn("audio clk %s init error!\n", 1015 pr_warn("audio clk %s init error!\n", name);
1024 audio_div_clk[i].div.hw.init->name);
1025 }
1026 } 1016 }
1027 1017
1028 for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) { 1018 for (i = 0; i < ARRAY_SIZE(audio_gate_clk); i++) {
@@ -1031,11 +1021,10 @@ static int __init audio_clocks_init(struct device_node *np)
1031 &audio_gate_clk[i].gate.hw; 1021 &audio_gate_clk[i].gate.hw;
1032 1022
1033 audio_gate_clk[i].gate.reg += (uintptr_t)reg_base; 1023 audio_gate_clk[i].gate.reg += (uintptr_t)reg_base;
1024 name = audio_gate_clk[i].gate.hw.init->name;
1034 ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw); 1025 ret = clk_hw_register(NULL, &audio_gate_clk[i].gate.hw);
1035 if (ret) { 1026 if (ret)
1036 pr_warn("audio clk %s init error!\n", 1027 pr_warn("audio clk %s init error!\n", name);
1037 audio_gate_clk[i].gate.hw.init->name);
1038 }
1039 } 1028 }
1040 1029
1041 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 1030 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
diff --git a/drivers/phy/ti/phy-am654-serdes.c b/drivers/phy/ti/phy-am654-serdes.c
index f14f1f053a75..88a047b9fa6f 100644
--- a/drivers/phy/ti/phy-am654-serdes.c
+++ b/drivers/phy/ti/phy-am654-serdes.c
@@ -335,6 +335,7 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
335{ 335{
336 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw); 336 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
337 struct regmap *regmap = mux->regmap; 337 struct regmap *regmap = mux->regmap;
338 const char *name = clk_hw_get_name(hw);
338 unsigned int reg = mux->reg; 339 unsigned int reg = mux->reg;
339 int clk_id = mux->clk_id; 340 int clk_id = mux->clk_id;
340 int parents[SERDES_NUM_CLOCKS]; 341 int parents[SERDES_NUM_CLOCKS];
@@ -374,8 +375,7 @@ static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
374 * This can never happen, unless we missed 375 * This can never happen, unless we missed
375 * a valid combination in serdes_am654_mux_table. 376 * a valid combination in serdes_am654_mux_table.
376 */ 377 */
377 WARN(1, "Failed to find the parent of %s clock\n", 378 WARN(1, "Failed to find the parent of %s clock\n", name);
378 hw->init->name);
379 return -EINVAL; 379 return -EINVAL;
380 } 380 }
381 381
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index c0e75c373605..d50ee023b559 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -279,7 +279,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
279 279
280 of_property_read_string_index(node, "clock-output-names", 1, 280 of_property_read_string_index(node, "clock-output-names", 1,
281 &clkout_name); 281 &clkout_name);
282 rtc->ext_losc = clk_register_gate(NULL, clkout_name, rtc->hw.init->name, 282 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
283 0, rtc->base + SUN6I_LOSC_OUT_GATING, 283 0, rtc->base + SUN6I_LOSC_OUT_GATING,
284 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 284 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
285 &rtc->lock); 285 &rtc->lock);
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..38074a5f7296
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,113 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
2#ifndef DT_BINDINGS_AST2600_CLOCK_H
3#define DT_BINDINGS_AST2600_CLOCK_H
4
5#define ASPEED_CLK_GATE_ECLK 0
6#define ASPEED_CLK_GATE_GCLK 1
7
8#define ASPEED_CLK_GATE_MCLK 2
9
10#define ASPEED_CLK_GATE_VCLK 3
11#define ASPEED_CLK_GATE_BCLK 4
12#define ASPEED_CLK_GATE_DCLK 5
13
14#define ASPEED_CLK_GATE_LCLK 6
15#define ASPEED_CLK_GATE_LHCCLK 7
16
17#define ASPEED_CLK_GATE_D1CLK 8
18#define ASPEED_CLK_GATE_YCLK 9
19
20#define ASPEED_CLK_GATE_REF0CLK 10
21#define ASPEED_CLK_GATE_REF1CLK 11
22
23#define ASPEED_CLK_GATE_ESPICLK 12
24
25#define ASPEED_CLK_GATE_USBUHCICLK 13
26#define ASPEED_CLK_GATE_USBPORT1CLK 14
27#define ASPEED_CLK_GATE_USBPORT2CLK 15
28
29#define ASPEED_CLK_GATE_RSACLK 16
30#define ASPEED_CLK_GATE_RVASCLK 17
31
32#define ASPEED_CLK_GATE_MAC1CLK 18
33#define ASPEED_CLK_GATE_MAC2CLK 19
34#define ASPEED_CLK_GATE_MAC3CLK 20
35#define ASPEED_CLK_GATE_MAC4CLK 21
36
37#define ASPEED_CLK_GATE_UART1CLK 22
38#define ASPEED_CLK_GATE_UART2CLK 23
39#define ASPEED_CLK_GATE_UART3CLK 24
40#define ASPEED_CLK_GATE_UART4CLK 25
41#define ASPEED_CLK_GATE_UART5CLK 26
42#define ASPEED_CLK_GATE_UART6CLK 27
43#define ASPEED_CLK_GATE_UART7CLK 28
44#define ASPEED_CLK_GATE_UART8CLK 29
45#define ASPEED_CLK_GATE_UART9CLK 30
46#define ASPEED_CLK_GATE_UART10CLK 31
47#define ASPEED_CLK_GATE_UART11CLK 32
48#define ASPEED_CLK_GATE_UART12CLK 33
49#define ASPEED_CLK_GATE_UART13CLK 34
50
51#define ASPEED_CLK_GATE_SDCLK 35
52#define ASPEED_CLK_GATE_EMMCCLK 36
53
54#define ASPEED_CLK_GATE_I3C0CLK 37
55#define ASPEED_CLK_GATE_I3C1CLK 38
56#define ASPEED_CLK_GATE_I3C2CLK 39
57#define ASPEED_CLK_GATE_I3C3CLK 40
58#define ASPEED_CLK_GATE_I3C4CLK 41
59#define ASPEED_CLK_GATE_I3C5CLK 42
60#define ASPEED_CLK_GATE_I3C6CLK 43
61#define ASPEED_CLK_GATE_I3C7CLK 44
62
63#define ASPEED_CLK_GATE_FSICLK 45
64
65#define ASPEED_CLK_HPLL 46
66#define ASPEED_CLK_MPLL 47
67#define ASPEED_CLK_DPLL 48
68#define ASPEED_CLK_EPLL 49
69#define ASPEED_CLK_APLL 50
70#define ASPEED_CLK_AHB 51
71#define ASPEED_CLK_APB1 52
72#define ASPEED_CLK_APB2 53
73#define ASPEED_CLK_BCLK 54
74#define ASPEED_CLK_D1CLK 55
75#define ASPEED_CLK_VCLK 56
76#define ASPEED_CLK_LHCLK 57
77#define ASPEED_CLK_UART 58
78#define ASPEED_CLK_UARTX 59
79#define ASPEED_CLK_SDIO 60
80#define ASPEED_CLK_EMMC 61
81#define ASPEED_CLK_ECLK 62
82#define ASPEED_CLK_ECLK_MUX 63
83#define ASPEED_CLK_MAC12 64
84#define ASPEED_CLK_MAC34 65
85#define ASPEED_CLK_USBPHY_40M 66
86
87/* Only list resets here that are not part of a gate */
88#define ASPEED_RESET_ADC 55
89#define ASPEED_RESET_JTAG_MASTER2 54
90#define ASPEED_RESET_I3C_DMA 39
91#define ASPEED_RESET_PWM 37
92#define ASPEED_RESET_PECI 36
93#define ASPEED_RESET_MII 35
94#define ASPEED_RESET_I2C 34
95#define ASPEED_RESET_H2X 31
96#define ASPEED_RESET_GP_MCU 30
97#define ASPEED_RESET_DP_MCU 29
98#define ASPEED_RESET_DP 28
99#define ASPEED_RESET_RC_XDMA 27
100#define ASPEED_RESET_GRAPHICS 26
101#define ASPEED_RESET_DEV_XDMA 25
102#define ASPEED_RESET_DEV_MCTP 24
103#define ASPEED_RESET_RC_MCTP 23
104#define ASPEED_RESET_JTAG_MASTER 22
105#define ASPEED_RESET_PCIE_DEV_O 21
106#define ASPEED_RESET_PCIE_DEV_OEN 20
107#define ASPEED_RESET_PCIE_RC_O 19
108#define ASPEED_RESET_PCIE_RC_OEN 18
109#define ASPEED_RESET_PCI_DP 5
110#define ASPEED_RESET_AHB 1
111#define ASPEED_RESET_SDRAM 0
112
113#endif
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 2cec01f96897..b60c03430cf1 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -58,3 +58,5 @@
58#define BCM2835_CLOCK_DSI1E 48 58#define BCM2835_CLOCK_DSI1E 48
59#define BCM2835_CLOCK_DSI0P 49 59#define BCM2835_CLOCK_DSI0P 49
60#define BCM2835_CLOCK_DSI1P 50 60#define BCM2835_CLOCK_DSI1P 50
61
62#define BCM2711_CLOCK_EMMC2 51
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 5255b1c2420e..d7b201652f4c 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -209,7 +209,8 @@
209#define IMX8MN_CLK_ARM 191 209#define IMX8MN_CLK_ARM 191
210#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192 210#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
211#define IMX8MN_CLK_GPU_CORE_ROOT 193 211#define IMX8MN_CLK_GPU_CORE_ROOT 193
212#define IMX8MN_CLK_GIC 194
212 213
213#define IMX8MN_CLK_END 194 214#define IMX8MN_CLK_END 195
214 215
215#endif 216#endif
diff --git a/include/dt-bindings/clock/mt6779-clk.h b/include/dt-bindings/clock/mt6779-clk.h
new file mode 100644
index 000000000000..b083139afbd2
--- /dev/null
+++ b/include/dt-bindings/clock/mt6779-clk.h
@@ -0,0 +1,436 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_MT6779_H
8#define _DT_BINDINGS_CLK_MT6779_H
9
10/* TOPCKGEN */
11#define CLK_TOP_AXI 1
12#define CLK_TOP_MM 2
13#define CLK_TOP_CAM 3
14#define CLK_TOP_MFG 4
15#define CLK_TOP_CAMTG 5
16#define CLK_TOP_UART 6
17#define CLK_TOP_SPI 7
18#define CLK_TOP_MSDC50_0_HCLK 8
19#define CLK_TOP_MSDC50_0 9
20#define CLK_TOP_MSDC30_1 10
21#define CLK_TOP_MSDC30_2 11
22#define CLK_TOP_AUD 12
23#define CLK_TOP_AUD_INTBUS 13
24#define CLK_TOP_FPWRAP_ULPOSC 14
25#define CLK_TOP_SCP 15
26#define CLK_TOP_ATB 16
27#define CLK_TOP_SSPM 17
28#define CLK_TOP_DPI0 18
29#define CLK_TOP_SCAM 19
30#define CLK_TOP_AUD_1 20
31#define CLK_TOP_AUD_2 21
32#define CLK_TOP_DISP_PWM 22
33#define CLK_TOP_SSUSB_TOP_XHCI 23
34#define CLK_TOP_USB_TOP 24
35#define CLK_TOP_SPM 25
36#define CLK_TOP_I2C 26
37#define CLK_TOP_F52M_MFG 27
38#define CLK_TOP_SENINF 28
39#define CLK_TOP_DXCC 29
40#define CLK_TOP_CAMTG2 30
41#define CLK_TOP_AUD_ENG1 31
42#define CLK_TOP_AUD_ENG2 32
43#define CLK_TOP_FAES_UFSFDE 33
44#define CLK_TOP_FUFS 34
45#define CLK_TOP_IMG 35
46#define CLK_TOP_DSP 36
47#define CLK_TOP_DSP1 37
48#define CLK_TOP_DSP2 38
49#define CLK_TOP_IPU_IF 39
50#define CLK_TOP_CAMTG3 40
51#define CLK_TOP_CAMTG4 41
52#define CLK_TOP_PMICSPI 42
53#define CLK_TOP_MAINPLL_CK 43
54#define CLK_TOP_MAINPLL_D2 44
55#define CLK_TOP_MAINPLL_D3 45
56#define CLK_TOP_MAINPLL_D5 46
57#define CLK_TOP_MAINPLL_D7 47
58#define CLK_TOP_MAINPLL_D2_D2 48
59#define CLK_TOP_MAINPLL_D2_D4 49
60#define CLK_TOP_MAINPLL_D2_D8 50
61#define CLK_TOP_MAINPLL_D2_D16 51
62#define CLK_TOP_MAINPLL_D3_D2 52
63#define CLK_TOP_MAINPLL_D3_D4 53
64#define CLK_TOP_MAINPLL_D3_D8 54
65#define CLK_TOP_MAINPLL_D5_D2 55
66#define CLK_TOP_MAINPLL_D5_D4 56
67#define CLK_TOP_MAINPLL_D7_D2 57
68#define CLK_TOP_MAINPLL_D7_D4 58
69#define CLK_TOP_UNIVPLL_CK 59
70#define CLK_TOP_UNIVPLL_D2 60
71#define CLK_TOP_UNIVPLL_D3 61
72#define CLK_TOP_UNIVPLL_D5 62
73#define CLK_TOP_UNIVPLL_D7 63
74#define CLK_TOP_UNIVPLL_D2_D2 64
75#define CLK_TOP_UNIVPLL_D2_D4 65
76#define CLK_TOP_UNIVPLL_D2_D8 66
77#define CLK_TOP_UNIVPLL_D3_D2 67
78#define CLK_TOP_UNIVPLL_D3_D4 68
79#define CLK_TOP_UNIVPLL_D3_D8 69
80#define CLK_TOP_UNIVPLL_D5_D2 70
81#define CLK_TOP_UNIVPLL_D5_D4 71
82#define CLK_TOP_UNIVPLL_D5_D8 72
83#define CLK_TOP_APLL1_CK 73
84#define CLK_TOP_APLL1_D2 74
85#define CLK_TOP_APLL1_D4 75
86#define CLK_TOP_APLL1_D8 76
87#define CLK_TOP_APLL2_CK 77
88#define CLK_TOP_APLL2_D2 78
89#define CLK_TOP_APLL2_D4 79
90#define CLK_TOP_APLL2_D8 80
91#define CLK_TOP_TVDPLL_CK 81
92#define CLK_TOP_TVDPLL_D2 82
93#define CLK_TOP_TVDPLL_D4 83
94#define CLK_TOP_TVDPLL_D8 84
95#define CLK_TOP_TVDPLL_D16 85
96#define CLK_TOP_MSDCPLL_CK 86
97#define CLK_TOP_MSDCPLL_D2 87
98#define CLK_TOP_MSDCPLL_D4 88
99#define CLK_TOP_MSDCPLL_D8 89
100#define CLK_TOP_MSDCPLL_D16 90
101#define CLK_TOP_AD_OSC_CK 91
102#define CLK_TOP_OSC_D2 92
103#define CLK_TOP_OSC_D4 93
104#define CLK_TOP_OSC_D8 94
105#define CLK_TOP_OSC_D16 95
106#define CLK_TOP_F26M_CK_D2 96
107#define CLK_TOP_MFGPLL_CK 97
108#define CLK_TOP_UNIVP_192M_CK 98
109#define CLK_TOP_UNIVP_192M_D2 99
110#define CLK_TOP_UNIVP_192M_D4 100
111#define CLK_TOP_UNIVP_192M_D8 101
112#define CLK_TOP_UNIVP_192M_D16 102
113#define CLK_TOP_UNIVP_192M_D32 103
114#define CLK_TOP_MMPLL_CK 104
115#define CLK_TOP_MMPLL_D4 105
116#define CLK_TOP_MMPLL_D4_D2 106
117#define CLK_TOP_MMPLL_D4_D4 107
118#define CLK_TOP_MMPLL_D5 108
119#define CLK_TOP_MMPLL_D5_D2 109
120#define CLK_TOP_MMPLL_D5_D4 110
121#define CLK_TOP_MMPLL_D6 111
122#define CLK_TOP_MMPLL_D7 112
123#define CLK_TOP_CLK26M 113
124#define CLK_TOP_CLK13M 114
125#define CLK_TOP_ADSP 115
126#define CLK_TOP_DPMAIF 116
127#define CLK_TOP_VENC 117
128#define CLK_TOP_VDEC 118
129#define CLK_TOP_CAMTM 119
130#define CLK_TOP_PWM 120
131#define CLK_TOP_ADSPPLL_CK 121
132#define CLK_TOP_I2S0_M_SEL 122
133#define CLK_TOP_I2S1_M_SEL 123
134#define CLK_TOP_I2S2_M_SEL 124
135#define CLK_TOP_I2S3_M_SEL 125
136#define CLK_TOP_I2S4_M_SEL 126
137#define CLK_TOP_I2S5_M_SEL 127
138#define CLK_TOP_APLL12_DIV0 128
139#define CLK_TOP_APLL12_DIV1 129
140#define CLK_TOP_APLL12_DIV2 130
141#define CLK_TOP_APLL12_DIV3 131
142#define CLK_TOP_APLL12_DIV4 132
143#define CLK_TOP_APLL12_DIVB 133
144#define CLK_TOP_APLL12_DIV5 134
145#define CLK_TOP_IPE 135
146#define CLK_TOP_DPE 136
147#define CLK_TOP_CCU 137
148#define CLK_TOP_DSP3 138
149#define CLK_TOP_SENINF1 139
150#define CLK_TOP_SENINF2 140
151#define CLK_TOP_AUD_H 141
152#define CLK_TOP_CAMTG5 142
153#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143
154#define CLK_TOP_AD_OSC2_CK 144
155#define CLK_TOP_OSC2_D2 145
156#define CLK_TOP_OSC2_D3 146
157#define CLK_TOP_FMEM_466M_CK 147
158#define CLK_TOP_ADSPPLL_D4 148
159#define CLK_TOP_ADSPPLL_D5 149
160#define CLK_TOP_ADSPPLL_D6 150
161#define CLK_TOP_OSC_D10 151
162#define CLK_TOP_UNIVPLL_D3_D16 152
163#define CLK_TOP_NR_CLK 153
164
165/* APMIXED */
166#define CLK_APMIXED_ARMPLL_LL 1
167#define CLK_APMIXED_ARMPLL_BL 2
168#define CLK_APMIXED_ARMPLL_BB 3
169#define CLK_APMIXED_CCIPLL 4
170#define CLK_APMIXED_MAINPLL 5
171#define CLK_APMIXED_UNIV2PLL 6
172#define CLK_APMIXED_MSDCPLL 7
173#define CLK_APMIXED_ADSPPLL 8
174#define CLK_APMIXED_MMPLL 9
175#define CLK_APMIXED_MFGPLL 10
176#define CLK_APMIXED_TVDPLL 11
177#define CLK_APMIXED_APLL1 12
178#define CLK_APMIXED_APLL2 13
179#define CLK_APMIXED_SSUSB26M 14
180#define CLK_APMIXED_APPLL26M 15
181#define CLK_APMIXED_MIPIC0_26M 16
182#define CLK_APMIXED_MDPLLGP26M 17
183#define CLK_APMIXED_MM_F26M 18
184#define CLK_APMIXED_UFS26M 19
185#define CLK_APMIXED_MIPIC1_26M 20
186#define CLK_APMIXED_MEMPLL26M 21
187#define CLK_APMIXED_CLKSQ_LVPLL_26M 22
188#define CLK_APMIXED_MIPID0_26M 23
189#define CLK_APMIXED_MIPID1_26M 24
190#define CLK_APMIXED_NR_CLK 25
191
192/* CAMSYS */
193#define CLK_CAM_LARB10 1
194#define CLK_CAM_DFP_VAD 2
195#define CLK_CAM_LARB11 3
196#define CLK_CAM_LARB9 4
197#define CLK_CAM_CAM 5
198#define CLK_CAM_CAMTG 6
199#define CLK_CAM_SENINF 7
200#define CLK_CAM_CAMSV0 8
201#define CLK_CAM_CAMSV1 9
202#define CLK_CAM_CAMSV2 10
203#define CLK_CAM_CAMSV3 11
204#define CLK_CAM_CCU 12
205#define CLK_CAM_FAKE_ENG 13
206#define CLK_CAM_NR_CLK 14
207
208/* INFRA */
209#define CLK_INFRA_PMIC_TMR 1
210#define CLK_INFRA_PMIC_AP 2
211#define CLK_INFRA_PMIC_MD 3
212#define CLK_INFRA_PMIC_CONN 4
213#define CLK_INFRA_SCPSYS 5
214#define CLK_INFRA_SEJ 6
215#define CLK_INFRA_APXGPT 7
216#define CLK_INFRA_ICUSB 8
217#define CLK_INFRA_GCE 9
218#define CLK_INFRA_THERM 10
219#define CLK_INFRA_I2C0 11
220#define CLK_INFRA_I2C1 12
221#define CLK_INFRA_I2C2 13
222#define CLK_INFRA_I2C3 14
223#define CLK_INFRA_PWM_HCLK 15
224#define CLK_INFRA_PWM1 16
225#define CLK_INFRA_PWM2 17
226#define CLK_INFRA_PWM3 18
227#define CLK_INFRA_PWM4 19
228#define CLK_INFRA_PWM 20
229#define CLK_INFRA_UART0 21
230#define CLK_INFRA_UART1 22
231#define CLK_INFRA_UART2 23
232#define CLK_INFRA_UART3 24
233#define CLK_INFRA_GCE_26M 25
234#define CLK_INFRA_CQ_DMA_FPC 26
235#define CLK_INFRA_BTIF 27
236#define CLK_INFRA_SPI0 28
237#define CLK_INFRA_MSDC0 29
238#define CLK_INFRA_MSDC1 30
239#define CLK_INFRA_MSDC2 31
240#define CLK_INFRA_MSDC0_SCK 32
241#define CLK_INFRA_DVFSRC 33
242#define CLK_INFRA_GCPU 34
243#define CLK_INFRA_TRNG 35
244#define CLK_INFRA_AUXADC 36
245#define CLK_INFRA_CPUM 37
246#define CLK_INFRA_CCIF1_AP 38
247#define CLK_INFRA_CCIF1_MD 39
248#define CLK_INFRA_AUXADC_MD 40
249#define CLK_INFRA_MSDC1_SCK 41
250#define CLK_INFRA_MSDC2_SCK 42
251#define CLK_INFRA_AP_DMA 43
252#define CLK_INFRA_XIU 44
253#define CLK_INFRA_DEVICE_APC 45
254#define CLK_INFRA_CCIF_AP 46
255#define CLK_INFRA_DEBUGSYS 47
256#define CLK_INFRA_AUD 48
257#define CLK_INFRA_CCIF_MD 49
258#define CLK_INFRA_DXCC_SEC_CORE 50
259#define CLK_INFRA_DXCC_AO 51
260#define CLK_INFRA_DRAMC_F26M 52
261#define CLK_INFRA_IRTX 53
262#define CLK_INFRA_DISP_PWM 54
263#define CLK_INFRA_DPMAIF_CK 55
264#define CLK_INFRA_AUD_26M_BCLK 56
265#define CLK_INFRA_SPI1 57
266#define CLK_INFRA_I2C4 58
267#define CLK_INFRA_MODEM_TEMP_SHARE 59
268#define CLK_INFRA_SPI2 60
269#define CLK_INFRA_SPI3 61
270#define CLK_INFRA_UNIPRO_SCK 62
271#define CLK_INFRA_UNIPRO_TICK 63
272#define CLK_INFRA_UFS_MP_SAP_BCLK 64
273#define CLK_INFRA_MD32_BCLK 65
274#define CLK_INFRA_SSPM 66
275#define CLK_INFRA_UNIPRO_MBIST 67
276#define CLK_INFRA_SSPM_BUS_HCLK 68
277#define CLK_INFRA_I2C5 69
278#define CLK_INFRA_I2C5_ARBITER 70
279#define CLK_INFRA_I2C5_IMM 71
280#define CLK_INFRA_I2C1_ARBITER 72
281#define CLK_INFRA_I2C1_IMM 73
282#define CLK_INFRA_I2C2_ARBITER 74
283#define CLK_INFRA_I2C2_IMM 75
284#define CLK_INFRA_SPI4 76
285#define CLK_INFRA_SPI5 77
286#define CLK_INFRA_CQ_DMA 78
287#define CLK_INFRA_UFS 79
288#define CLK_INFRA_AES_UFSFDE 80
289#define CLK_INFRA_UFS_TICK 81
290#define CLK_INFRA_MSDC0_SELF 82
291#define CLK_INFRA_MSDC1_SELF 83
292#define CLK_INFRA_MSDC2_SELF 84
293#define CLK_INFRA_SSPM_26M_SELF 85
294#define CLK_INFRA_SSPM_32K_SELF 86
295#define CLK_INFRA_UFS_AXI 87
296#define CLK_INFRA_I2C6 88
297#define CLK_INFRA_AP_MSDC0 89
298#define CLK_INFRA_MD_MSDC0 90
299#define CLK_INFRA_USB 91
300#define CLK_INFRA_DEVMPU_BCLK 92
301#define CLK_INFRA_CCIF2_AP 93
302#define CLK_INFRA_CCIF2_MD 94
303#define CLK_INFRA_CCIF3_AP 95
304#define CLK_INFRA_CCIF3_MD 96
305#define CLK_INFRA_SEJ_F13M 97
306#define CLK_INFRA_AES_BCLK 98
307#define CLK_INFRA_I2C7 99
308#define CLK_INFRA_I2C8 100
309#define CLK_INFRA_FBIST2FPC 101
310#define CLK_INFRA_CCIF4_AP 102
311#define CLK_INFRA_CCIF4_MD 103
312#define CLK_INFRA_FADSP 104
313#define CLK_INFRA_SSUSB_XHCI 105
314#define CLK_INFRA_SPI6 106
315#define CLK_INFRA_SPI7 107
316#define CLK_INFRA_NR_CLK 108
317
318/* MFGCFG */
319#define CLK_MFGCFG_BG3D 1
320#define CLK_MFGCFG_NR_CLK 2
321
322/* IMG */
323#define CLK_IMG_WPE_A 1
324#define CLK_IMG_MFB 2
325#define CLK_IMG_DIP 3
326#define CLK_IMG_LARB6 4
327#define CLK_IMG_LARB5 5
328#define CLK_IMG_NR_CLK 6
329
330/* IPE */
331#define CLK_IPE_LARB7 1
332#define CLK_IPE_LARB8 2
333#define CLK_IPE_SMI_SUBCOM 3
334#define CLK_IPE_FD 4
335#define CLK_IPE_FE 5
336#define CLK_IPE_RSC 6
337#define CLK_IPE_DPE 7
338#define CLK_IPE_NR_CLK 8
339
340/* MM_CONFIG */
341#define CLK_MM_SMI_COMMON 1
342#define CLK_MM_SMI_LARB0 2
343#define CLK_MM_SMI_LARB1 3
344#define CLK_MM_GALS_COMM0 4
345#define CLK_MM_GALS_COMM1 5
346#define CLK_MM_GALS_CCU2MM 6
347#define CLK_MM_GALS_IPU12MM 7
348#define CLK_MM_GALS_IMG2MM 8
349#define CLK_MM_GALS_CAM2MM 9
350#define CLK_MM_GALS_IPU2MM 10
351#define CLK_MM_MDP_DL_TXCK 11
352#define CLK_MM_IPU_DL_TXCK 12
353#define CLK_MM_MDP_RDMA0 13
354#define CLK_MM_MDP_RDMA1 14
355#define CLK_MM_MDP_RSZ0 15
356#define CLK_MM_MDP_RSZ1 16
357#define CLK_MM_MDP_TDSHP 17
358#define CLK_MM_MDP_WROT0 18
359#define CLK_MM_FAKE_ENG 19
360#define CLK_MM_DISP_OVL0 20
361#define CLK_MM_DISP_OVL0_2L 21
362#define CLK_MM_DISP_OVL1_2L 22
363#define CLK_MM_DISP_RDMA0 23
364#define CLK_MM_DISP_RDMA1 24
365#define CLK_MM_DISP_WDMA0 25
366#define CLK_MM_DISP_COLOR0 26
367#define CLK_MM_DISP_CCORR0 27
368#define CLK_MM_DISP_AAL0 28
369#define CLK_MM_DISP_GAMMA0 29
370#define CLK_MM_DISP_DITHER0 30
371#define CLK_MM_DISP_SPLIT 31
372#define CLK_MM_DSI0_MM_CK 32
373#define CLK_MM_DSI0_IF_CK 33
374#define CLK_MM_DPI_MM_CK 34
375#define CLK_MM_DPI_IF_CK 35
376#define CLK_MM_FAKE_ENG2 36
377#define CLK_MM_MDP_DL_RX_CK 37
378#define CLK_MM_IPU_DL_RX_CK 38
379#define CLK_MM_26M 39
380#define CLK_MM_MM_R2Y 40
381#define CLK_MM_DISP_RSZ 41
382#define CLK_MM_MDP_WDMA0 42
383#define CLK_MM_MDP_AAL 43
384#define CLK_MM_MDP_HDR 44
385#define CLK_MM_DBI_MM_CK 45
386#define CLK_MM_DBI_IF_CK 46
387#define CLK_MM_MDP_WROT1 47
388#define CLK_MM_DISP_POSTMASK0 48
389#define CLK_MM_DISP_HRT_BW 49
390#define CLK_MM_DISP_OVL_FBDC 50
391#define CLK_MM_NR_CLK 51
392
393/* VDEC_GCON */
394#define CLK_VDEC_VDEC 1
395#define CLK_VDEC_LARB1 2
396#define CLK_VDEC_GCON_NR_CLK 3
397
398/* VENC_GCON */
399#define CLK_VENC_GCON_LARB 1
400#define CLK_VENC_GCON_VENC 2
401#define CLK_VENC_GCON_JPGENC 3
402#define CLK_VENC_GCON_GALS 4
403#define CLK_VENC_GCON_NR_CLK 5
404
405/* AUD */
406#define CLK_AUD_AFE 1
407#define CLK_AUD_22M 2
408#define CLK_AUD_24M 3
409#define CLK_AUD_APLL2_TUNER 4
410#define CLK_AUD_APLL_TUNER 5
411#define CLK_AUD_TDM 6
412#define CLK_AUD_ADC 7
413#define CLK_AUD_DAC 8
414#define CLK_AUD_DAC_PREDIS 9
415#define CLK_AUD_TML 10
416#define CLK_AUD_NLE 11
417#define CLK_AUD_I2S1_BCLK_SW 12
418#define CLK_AUD_I2S2_BCLK_SW 13
419#define CLK_AUD_I2S3_BCLK_SW 14
420#define CLK_AUD_I2S4_BCLK_SW 15
421#define CLK_AUD_I2S5_BCLK_SW 16
422#define CLK_AUD_CONN_I2S_ASRC 17
423#define CLK_AUD_GENERAL1_ASRC 18
424#define CLK_AUD_GENERAL2_ASRC 19
425#define CLK_AUD_DAC_HIRES 20
426#define CLK_AUD_PDN_ADDA6_ADC 21
427#define CLK_AUD_ADC_HIRES 22
428#define CLK_AUD_ADC_HIRES_TML 23
429#define CLK_AUD_ADDA6_ADC_HIRES 24
430#define CLK_AUD_3RD_DAC 25
431#define CLK_AUD_3RD_DAC_PREDIS 26
432#define CLK_AUD_3RD_DAC_TML 27
433#define CLK_AUD_3RD_DAC_HIRES 28
434#define CLK_AUD_NR_CLK 29
435
436#endif /* _DT_BINDINGS_CLK_MT6779_H */
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
index 0046506eb24c..a7b470b0ec8a 100644
--- a/include/dt-bindings/clock/mt8183-clk.h
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -284,6 +284,10 @@
284#define CLK_INFRA_FBIST2FPC 100 284#define CLK_INFRA_FBIST2FPC 100
285#define CLK_INFRA_NR_CLK 101 285#define CLK_INFRA_NR_CLK 101
286 286
287/* PERICFG */
288#define CLK_PERI_AXI 0
289#define CLK_PERI_NR_CLK 1
290
287/* MFGCFG */ 291/* MFGCFG */
288#define CLK_MFG_BG3D 0 292#define CLK_MFG_BG3D 0
289#define CLK_MFG_NR_CLK 1 293#define CLK_MFG_NR_CLK 1
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 2cd62c98561f..bc3051543347 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -146,6 +146,8 @@
146#define GCC_MDP_TBU_CLK 138 146#define GCC_MDP_TBU_CLK 138
147#define GCC_QDSS_DAP_CLK 139 147#define GCC_QDSS_DAP_CLK 139
148#define GCC_DCC_XO_CLK 140 148#define GCC_DCC_XO_CLK 140
149#define GCC_WCSS_Q6_AHB_CLK 141
150#define GCC_WCSS_Q6_AXIM_CLK 142
149#define GCC_CDSP_CFG_AHB_CLK 143 151#define GCC_CDSP_CFG_AHB_CLK 143
150#define GCC_BIMC_CDSP_CLK 144 152#define GCC_BIMC_CDSP_CLK 144
151#define GCC_CDSP_TBU_CLK 145 153#define GCC_CDSP_TBU_CLK 145
@@ -173,5 +175,6 @@
173#define GCC_PCIE_0_CORE_STICKY_ARES 19 175#define GCC_PCIE_0_CORE_STICKY_ARES 19
174#define GCC_PCIE_0_SLEEP_ARES 20 176#define GCC_PCIE_0_SLEEP_ARES 20
175#define GCC_PCIE_0_PIPE_ARES 21 177#define GCC_PCIE_0_PIPE_ARES 21
178#define GCC_WDSP_RESTART 22
176 179
177#endif 180#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
new file mode 100644
index 000000000000..90d60ef94c64
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -0,0 +1,243 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
7#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
8
9/* GCC clocks */
10#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
11#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
12#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
13#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
14#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
15#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
16#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
17#define GCC_BOOT_ROM_AHB_CLK 7
18#define GCC_CAMERA_AHB_CLK 8
19#define GCC_CAMERA_HF_AXI_CLK 9
20#define GCC_CAMERA_SF_AXI_CLK 10
21#define GCC_CAMERA_XO_CLK 11
22#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
23#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
24#define GCC_CPUSS_AHB_CLK 14
25#define GCC_CPUSS_AHB_CLK_SRC 15
26#define GCC_CPUSS_DVM_BUS_CLK 16
27#define GCC_CPUSS_GNOC_CLK 17
28#define GCC_CPUSS_RBCPR_CLK 18
29#define GCC_DDRSS_GPU_AXI_CLK 19
30#define GCC_DISP_AHB_CLK 20
31#define GCC_DISP_HF_AXI_CLK 21
32#define GCC_DISP_SF_AXI_CLK 22
33#define GCC_DISP_XO_CLK 23
34#define GCC_EMAC_AXI_CLK 24
35#define GCC_EMAC_PTP_CLK 25
36#define GCC_EMAC_PTP_CLK_SRC 26
37#define GCC_EMAC_RGMII_CLK 27
38#define GCC_EMAC_RGMII_CLK_SRC 28
39#define GCC_EMAC_SLV_AHB_CLK 29
40#define GCC_GP1_CLK 30
41#define GCC_GP1_CLK_SRC 31
42#define GCC_GP2_CLK 32
43#define GCC_GP2_CLK_SRC 33
44#define GCC_GP3_CLK 34
45#define GCC_GP3_CLK_SRC 35
46#define GCC_GPU_CFG_AHB_CLK 36
47#define GCC_GPU_GPLL0_CLK_SRC 37
48#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
49#define GCC_GPU_IREF_CLK 39
50#define GCC_GPU_MEMNOC_GFX_CLK 40
51#define GCC_GPU_SNOC_DVM_GFX_CLK 41
52#define GCC_NPU_AT_CLK 42
53#define GCC_NPU_AXI_CLK 43
54#define GCC_NPU_CFG_AHB_CLK 44
55#define GCC_NPU_GPLL0_CLK_SRC 45
56#define GCC_NPU_GPLL0_DIV_CLK_SRC 46
57#define GCC_NPU_TRIG_CLK 47
58#define GCC_PCIE0_PHY_REFGEN_CLK 48
59#define GCC_PCIE1_PHY_REFGEN_CLK 49
60#define GCC_PCIE_0_AUX_CLK 50
61#define GCC_PCIE_0_AUX_CLK_SRC 51
62#define GCC_PCIE_0_CFG_AHB_CLK 52
63#define GCC_PCIE_0_CLKREF_CLK 53
64#define GCC_PCIE_0_MSTR_AXI_CLK 54
65#define GCC_PCIE_0_PIPE_CLK 55
66#define GCC_PCIE_0_SLV_AXI_CLK 56
67#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
68#define GCC_PCIE_1_AUX_CLK 58
69#define GCC_PCIE_1_AUX_CLK_SRC 59
70#define GCC_PCIE_1_CFG_AHB_CLK 60
71#define GCC_PCIE_1_CLKREF_CLK 61
72#define GCC_PCIE_1_MSTR_AXI_CLK 62
73#define GCC_PCIE_1_PIPE_CLK 63
74#define GCC_PCIE_1_SLV_AXI_CLK 64
75#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
76#define GCC_PCIE_PHY_AUX_CLK 66
77#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
78#define GCC_PDM2_CLK 68
79#define GCC_PDM2_CLK_SRC 69
80#define GCC_PDM_AHB_CLK 70
81#define GCC_PDM_XO4_CLK 71
82#define GCC_PRNG_AHB_CLK 72
83#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73
84#define GCC_QMIP_CAMERA_RT_AHB_CLK 74
85#define GCC_QMIP_DISP_AHB_CLK 75
86#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76
87#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77
88#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78
89#define GCC_QSPI_CORE_CLK 79
90#define GCC_QSPI_CORE_CLK_SRC 80
91#define GCC_QUPV3_WRAP0_S0_CLK 81
92#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82
93#define GCC_QUPV3_WRAP0_S1_CLK 83
94#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84
95#define GCC_QUPV3_WRAP0_S2_CLK 85
96#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86
97#define GCC_QUPV3_WRAP0_S3_CLK 87
98#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88
99#define GCC_QUPV3_WRAP0_S4_CLK 89
100#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90
101#define GCC_QUPV3_WRAP0_S5_CLK 91
102#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92
103#define GCC_QUPV3_WRAP0_S6_CLK 93
104#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94
105#define GCC_QUPV3_WRAP0_S7_CLK 95
106#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96
107#define GCC_QUPV3_WRAP1_S0_CLK 97
108#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
109#define GCC_QUPV3_WRAP1_S1_CLK 99
110#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
111#define GCC_QUPV3_WRAP1_S2_CLK 101
112#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
113#define GCC_QUPV3_WRAP1_S3_CLK 103
114#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
115#define GCC_QUPV3_WRAP1_S4_CLK 105
116#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
117#define GCC_QUPV3_WRAP1_S5_CLK 107
118#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
119#define GCC_QUPV3_WRAP2_S0_CLK 109
120#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
121#define GCC_QUPV3_WRAP2_S1_CLK 111
122#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
123#define GCC_QUPV3_WRAP2_S2_CLK 113
124#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
125#define GCC_QUPV3_WRAP2_S3_CLK 115
126#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
127#define GCC_QUPV3_WRAP2_S4_CLK 117
128#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
129#define GCC_QUPV3_WRAP2_S5_CLK 119
130#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
131#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
132#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
133#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
134#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
135#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
136#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
137#define GCC_SDCC2_AHB_CLK 127
138#define GCC_SDCC2_APPS_CLK 128
139#define GCC_SDCC2_APPS_CLK_SRC 129
140#define GCC_SDCC4_AHB_CLK 130
141#define GCC_SDCC4_APPS_CLK 131
142#define GCC_SDCC4_APPS_CLK_SRC 132
143#define GCC_SYS_NOC_CPUSS_AHB_CLK 133
144#define GCC_TSIF_AHB_CLK 134
145#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135
146#define GCC_TSIF_REF_CLK 136
147#define GCC_TSIF_REF_CLK_SRC 137
148#define GCC_UFS_CARD_AHB_CLK 138
149#define GCC_UFS_CARD_AXI_CLK 139
150#define GCC_UFS_CARD_AXI_CLK_SRC 140
151#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141
152#define GCC_UFS_CARD_CLKREF_CLK 142
153#define GCC_UFS_CARD_ICE_CORE_CLK 143
154#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144
155#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145
156#define GCC_UFS_CARD_PHY_AUX_CLK 146
157#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147
158#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148
159#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149
160#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150
161#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151
162#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152
163#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153
164#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154
165#define GCC_UFS_MEM_CLKREF_CLK 155
166#define GCC_UFS_PHY_AHB_CLK 156
167#define GCC_UFS_PHY_AXI_CLK 157
168#define GCC_UFS_PHY_AXI_CLK_SRC 158
169#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
170#define GCC_UFS_PHY_ICE_CORE_CLK 160
171#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
172#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162
173#define GCC_UFS_PHY_PHY_AUX_CLK 163
174#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
175#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
176#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166
177#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
178#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
179#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169
180#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170
181#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171
182#define GCC_USB30_PRIM_MASTER_CLK 172
183#define GCC_USB30_PRIM_MASTER_CLK_SRC 173
184#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174
185#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175
186#define GCC_USB30_PRIM_SLEEP_CLK 176
187#define GCC_USB30_SEC_MASTER_CLK 177
188#define GCC_USB30_SEC_MASTER_CLK_SRC 178
189#define GCC_USB30_SEC_MOCK_UTMI_CLK 179
190#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180
191#define GCC_USB30_SEC_SLEEP_CLK 181
192#define GCC_USB3_PRIM_CLKREF_CLK 182
193#define GCC_USB3_PRIM_PHY_AUX_CLK 183
194#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184
195#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185
196#define GCC_USB3_PRIM_PHY_PIPE_CLK 186
197#define GCC_USB3_SEC_CLKREF_CLK 187
198#define GCC_USB3_SEC_PHY_AUX_CLK 188
199#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189
200#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190
201#define GCC_USB3_SEC_PHY_PIPE_CLK 191
202#define GCC_VIDEO_AHB_CLK 192
203#define GCC_VIDEO_AXI0_CLK 193
204#define GCC_VIDEO_AXI1_CLK 194
205#define GCC_VIDEO_AXIC_CLK 195
206#define GCC_VIDEO_XO_CLK 196
207#define GPLL0 197
208#define GPLL0_OUT_EVEN 198
209#define GPLL7 199
210#define GPLL9 200
211
212/* Reset clocks */
213#define GCC_EMAC_BCR 0
214#define GCC_GPU_BCR 1
215#define GCC_MMSS_BCR 2
216#define GCC_NPU_BCR 3
217#define GCC_PCIE_0_BCR 4
218#define GCC_PCIE_0_PHY_BCR 5
219#define GCC_PCIE_1_BCR 6
220#define GCC_PCIE_1_PHY_BCR 7
221#define GCC_PCIE_PHY_BCR 8
222#define GCC_PDM_BCR 9
223#define GCC_PRNG_BCR 10
224#define GCC_QSPI_BCR 11
225#define GCC_QUPV3_WRAPPER_0_BCR 12
226#define GCC_QUPV3_WRAPPER_1_BCR 13
227#define GCC_QUPV3_WRAPPER_2_BCR 14
228#define GCC_QUSB2PHY_PRIM_BCR 15
229#define GCC_QUSB2PHY_SEC_BCR 16
230#define GCC_USB3_PHY_PRIM_BCR 17
231#define GCC_USB3_DP_PHY_PRIM_BCR 18
232#define GCC_USB3_PHY_SEC_BCR 19
233#define GCC_USB3PHY_PHY_SEC_BCR 20
234#define GCC_SDCC2_BCR 21
235#define GCC_SDCC4_BCR 22
236#define GCC_TSIF_BCR 23
237#define GCC_UFS_CARD_BCR 24
238#define GCC_UFS_PHY_BCR 25
239#define GCC_USB30_PRIM_BCR 26
240#define GCC_USB30_SEC_BCR 27
241#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
242
243#endif
diff --git a/include/dt-bindings/clock/rk3308-cru.h b/include/dt-bindings/clock/rk3308-cru.h
new file mode 100644
index 000000000000..d97840f9ee2e
--- /dev/null
+++ b/include/dt-bindings/clock/rk3308-cru.h
@@ -0,0 +1,387 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
9
10/* core clocks */
11#define PLL_APLL 1
12#define PLL_DPLL 2
13#define PLL_VPLL0 3
14#define PLL_VPLL1 4
15#define ARMCLK 5
16
17/* sclk (special clocks) */
18#define USB480M 14
19#define SCLK_RTC32K 15
20#define SCLK_PVTM_CORE 16
21#define SCLK_UART0 17
22#define SCLK_UART1 18
23#define SCLK_UART2 19
24#define SCLK_UART3 20
25#define SCLK_UART4 21
26#define SCLK_I2C0 22
27#define SCLK_I2C1 23
28#define SCLK_I2C2 24
29#define SCLK_I2C3 25
30#define SCLK_PWM0 26
31#define SCLK_SPI0 27
32#define SCLK_SPI1 28
33#define SCLK_SPI2 29
34#define SCLK_TIMER0 30
35#define SCLK_TIMER1 31
36#define SCLK_TIMER2 32
37#define SCLK_TIMER3 33
38#define SCLK_TIMER4 34
39#define SCLK_TIMER5 35
40#define SCLK_TSADC 36
41#define SCLK_SARADC 37
42#define SCLK_OTP 38
43#define SCLK_OTP_USR 39
44#define SCLK_CPU_BOOST 40
45#define SCLK_CRYPTO 41
46#define SCLK_CRYPTO_APK 42
47#define SCLK_NANDC_DIV 43
48#define SCLK_NANDC_DIV50 44
49#define SCLK_NANDC 45
50#define SCLK_SDMMC_DIV 46
51#define SCLK_SDMMC_DIV50 47
52#define SCLK_SDMMC 48
53#define SCLK_SDMMC_DRV 49
54#define SCLK_SDMMC_SAMPLE 50
55#define SCLK_SDIO_DIV 51
56#define SCLK_SDIO_DIV50 52
57#define SCLK_SDIO 53
58#define SCLK_SDIO_DRV 54
59#define SCLK_SDIO_SAMPLE 55
60#define SCLK_EMMC_DIV 56
61#define SCLK_EMMC_DIV50 57
62#define SCLK_EMMC 58
63#define SCLK_EMMC_DRV 59
64#define SCLK_EMMC_SAMPLE 60
65#define SCLK_SFC 61
66#define SCLK_OTG_ADP 62
67#define SCLK_MAC_SRC 63
68#define SCLK_MAC 64
69#define SCLK_MAC_REF 65
70#define SCLK_MAC_RX_TX 66
71#define SCLK_MAC_RMII 67
72#define SCLK_DDR_MON_TIMER 68
73#define SCLK_DDR_MON 69
74#define SCLK_DDRCLK 70
75#define SCLK_PMU 71
76#define SCLK_USBPHY_REF 72
77#define SCLK_WIFI 73
78#define SCLK_PVTM_PMU 74
79#define SCLK_PDM 75
80#define SCLK_I2S0_8CH_TX 76
81#define SCLK_I2S0_8CH_TX_OUT 77
82#define SCLK_I2S0_8CH_RX 78
83#define SCLK_I2S0_8CH_RX_OUT 79
84#define SCLK_I2S1_8CH_TX 80
85#define SCLK_I2S1_8CH_TX_OUT 81
86#define SCLK_I2S1_8CH_RX 82
87#define SCLK_I2S1_8CH_RX_OUT 83
88#define SCLK_I2S2_8CH_TX 84
89#define SCLK_I2S2_8CH_TX_OUT 85
90#define SCLK_I2S2_8CH_RX 86
91#define SCLK_I2S2_8CH_RX_OUT 87
92#define SCLK_I2S3_8CH_TX 88
93#define SCLK_I2S3_8CH_TX_OUT 89
94#define SCLK_I2S3_8CH_RX 90
95#define SCLK_I2S3_8CH_RX_OUT 91
96#define SCLK_I2S0_2CH 92
97#define SCLK_I2S0_2CH_OUT 93
98#define SCLK_I2S1_2CH 94
99#define SCLK_I2S1_2CH_OUT 95
100#define SCLK_SPDIF_TX_DIV 96
101#define SCLK_SPDIF_TX_DIV50 97
102#define SCLK_SPDIF_TX 98
103#define SCLK_SPDIF_RX_DIV 99
104#define SCLK_SPDIF_RX_DIV50 100
105#define SCLK_SPDIF_RX 101
106#define SCLK_I2S0_8CH_TX_MUX 102
107#define SCLK_I2S0_8CH_RX_MUX 103
108#define SCLK_I2S1_8CH_TX_MUX 104
109#define SCLK_I2S1_8CH_RX_MUX 105
110#define SCLK_I2S2_8CH_TX_MUX 106
111#define SCLK_I2S2_8CH_RX_MUX 107
112#define SCLK_I2S3_8CH_TX_MUX 108
113#define SCLK_I2S3_8CH_RX_MUX 109
114#define SCLK_I2S0_8CH_TX_SRC 110
115#define SCLK_I2S0_8CH_RX_SRC 111
116#define SCLK_I2S1_8CH_TX_SRC 112
117#define SCLK_I2S1_8CH_RX_SRC 113
118#define SCLK_I2S2_8CH_TX_SRC 114
119#define SCLK_I2S2_8CH_RX_SRC 115
120#define SCLK_I2S3_8CH_TX_SRC 116
121#define SCLK_I2S3_8CH_RX_SRC 117
122#define SCLK_I2S0_2CH_SRC 118
123#define SCLK_I2S1_2CH_SRC 119
124#define SCLK_PWM1 120
125#define SCLK_PWM2 121
126#define SCLK_OWIRE 122
127
128/* dclk */
129#define DCLK_VOP 125
130
131/* aclk */
132#define ACLK_BUS_SRC 130
133#define ACLK_BUS 131
134#define ACLK_PERI_SRC 132
135#define ACLK_PERI 133
136#define ACLK_MAC 134
137#define ACLK_CRYPTO 135
138#define ACLK_VOP 136
139#define ACLK_GIC 137
140#define ACLK_DMAC0 138
141#define ACLK_DMAC1 139
142
143/* hclk */
144#define HCLK_BUS 150
145#define HCLK_PERI 151
146#define HCLK_AUDIO 152
147#define HCLK_NANDC 153
148#define HCLK_SDMMC 154
149#define HCLK_SDIO 155
150#define HCLK_EMMC 156
151#define HCLK_SFC 157
152#define HCLK_OTG 158
153#define HCLK_HOST 159
154#define HCLK_HOST_ARB 160
155#define HCLK_PDM 161
156#define HCLK_SPDIFTX 162
157#define HCLK_SPDIFRX 163
158#define HCLK_I2S0_8CH 164
159#define HCLK_I2S1_8CH 165
160#define HCLK_I2S2_8CH 166
161#define HCLK_I2S3_8CH 167
162#define HCLK_I2S0_2CH 168
163#define HCLK_I2S1_2CH 169
164#define HCLK_VAD 170
165#define HCLK_CRYPTO 171
166#define HCLK_VOP 172
167
168/* pclk */
169#define PCLK_BUS 190
170#define PCLK_DDR 191
171#define PCLK_PERI 192
172#define PCLK_PMU 193
173#define PCLK_AUDIO 194
174#define PCLK_MAC 195
175#define PCLK_ACODEC 196
176#define PCLK_UART0 197
177#define PCLK_UART1 198
178#define PCLK_UART2 199
179#define PCLK_UART3 200
180#define PCLK_UART4 201
181#define PCLK_I2C0 202
182#define PCLK_I2C1 203
183#define PCLK_I2C2 204
184#define PCLK_I2C3 205
185#define PCLK_PWM0 206
186#define PCLK_SPI0 207
187#define PCLK_SPI1 208
188#define PCLK_SPI2 209
189#define PCLK_SARADC 210
190#define PCLK_TSADC 211
191#define PCLK_TIMER 212
192#define PCLK_OTP_NS 213
193#define PCLK_WDT 214
194#define PCLK_GPIO0 215
195#define PCLK_GPIO1 216
196#define PCLK_GPIO2 217
197#define PCLK_GPIO3 218
198#define PCLK_GPIO4 219
199#define PCLK_SGRF 220
200#define PCLK_GRF 221
201#define PCLK_USBSD_DET 222
202#define PCLK_DDR_UPCTL 223
203#define PCLK_DDR_MON 224
204#define PCLK_DDRPHY 225
205#define PCLK_DDR_STDBY 226
206#define PCLK_USB_GRF 227
207#define PCLK_CRU 228
208#define PCLK_OTP_PHY 229
209#define PCLK_CPU_BOOST 230
210#define PCLK_PWM1 231
211#define PCLK_PWM2 232
212#define PCLK_CAN 233
213#define PCLK_OWIRE 234
214
215#define CLK_NR_CLKS (PCLK_OWIRE + 1)
216
217/* soft-reset indices */
218
219/* cru_softrst_con0 */
220#define SRST_CORE0_PO 0
221#define SRST_CORE1_PO 1
222#define SRST_CORE2_PO 2
223#define SRST_CORE3_PO 3
224#define SRST_CORE0 4
225#define SRST_CORE1 5
226#define SRST_CORE2 6
227#define SRST_CORE3 7
228#define SRST_CORE0_DBG 8
229#define SRST_CORE1_DBG 9
230#define SRST_CORE2_DBG 10
231#define SRST_CORE3_DBG 11
232#define SRST_TOPDBG 12
233#define SRST_CORE_NOC 13
234#define SRST_STRC_A 14
235#define SRST_L2C 15
236
237/* cru_softrst_con1 */
238#define SRST_DAP 16
239#define SRST_CORE_PVTM 17
240#define SRST_CORE_PRF 18
241#define SRST_CORE_GRF 19
242#define SRST_DDRUPCTL 20
243#define SRST_DDRUPCTL_P 22
244#define SRST_MSCH 23
245#define SRST_DDRMON_P 25
246#define SRST_DDRSTDBY_P 26
247#define SRST_DDRSTDBY 27
248#define SRST_DDRPHY 28
249#define SRST_DDRPHY_DIV 29
250#define SRST_DDRPHY_P 30
251
252/* cru_softrst_con2 */
253#define SRST_BUS_NIU_H 32
254#define SRST_USB_NIU_P 33
255#define SRST_CRYPTO_A 34
256#define SRST_CRYPTO_H 35
257#define SRST_CRYPTO 36
258#define SRST_CRYPTO_APK 37
259#define SRST_VOP_A 38
260#define SRST_VOP_H 39
261#define SRST_VOP_D 40
262#define SRST_INTMEM_A 41
263#define SRST_ROM_H 42
264#define SRST_GIC_A 43
265#define SRST_UART0_P 44
266#define SRST_UART0 45
267#define SRST_UART1_P 46
268#define SRST_UART1 47
269
270/* cru_softrst_con3 */
271#define SRST_UART2_P 48
272#define SRST_UART2 49
273#define SRST_UART3_P 50
274#define SRST_UART3 51
275#define SRST_UART4_P 52
276#define SRST_UART4 53
277#define SRST_I2C0_P 54
278#define SRST_I2C0 55
279#define SRST_I2C1_P 56
280#define SRST_I2C1 57
281#define SRST_I2C2_P 58
282#define SRST_I2C2 59
283#define SRST_I2C3_P 60
284#define SRST_I2C3 61
285#define SRST_PWM0_P 62
286#define SRST_PWM0 63
287
288/* cru_softrst_con4 */
289#define SRST_SPI0_P 64
290#define SRST_SPI0 65
291#define SRST_SPI1_P 66
292#define SRST_SPI1 67
293#define SRST_SPI2_P 68
294#define SRST_SPI2 69
295#define SRST_SARADC_P 70
296#define SRST_TSADC_P 71
297#define SRST_TSADC 72
298#define SRST_TIMER0_P 73
299#define SRST_TIMER0 74
300#define SRST_TIMER1 75
301#define SRST_TIMER2 76
302#define SRST_TIMER3 77
303#define SRST_TIMER4 78
304#define SRST_TIMER5 79
305
306/* cru_softrst_con5 */
307#define SRST_OTP_NS_P 80
308#define SRST_OTP_NS_SBPI 81
309#define SRST_OTP_NS_USR 82
310#define SRST_OTP_PHY_P 83
311#define SRST_OTP_PHY 84
312#define SRST_GPIO0_P 86
313#define SRST_GPIO1_P 87
314#define SRST_GPIO2_P 88
315#define SRST_GPIO3_P 89
316#define SRST_GPIO4_P 90
317#define SRST_GRF_P 91
318#define SRST_USBSD_DET_P 92
319#define SRST_PMU 93
320#define SRST_PMU_PVTM 94
321#define SRST_USB_GRF_P 95
322
323/* cru_softrst_con6 */
324#define SRST_CPU_BOOST 96
325#define SRST_CPU_BOOST_P 97
326#define SRST_PWM1_P 98
327#define SRST_PWM1 99
328#define SRST_PWM2_P 100
329#define SRST_PWM2 101
330#define SRST_PERI_NIU_A 104
331#define SRST_PERI_NIU_H 105
332#define SRST_PERI_NIU_p 106
333#define SRST_USB2OTG_H 107
334#define SRST_USB2OTG 108
335#define SRST_USB2OTG_ADP 109
336#define SRST_USB2HOST_H 110
337#define SRST_USB2HOST_ARB_H 111
338
339/* cru_softrst_con7 */
340#define SRST_USB2HOST_AUX_H 112
341#define SRST_USB2HOST_EHCI 113
342#define SRST_USB2HOST 114
343#define SRST_USBPHYPOR 115
344#define SRST_UTMI0 116
345#define SRST_UTMI1 117
346#define SRST_SDIO_H 118
347#define SRST_EMMC_H 119
348#define SRST_SFC_H 120
349#define SRST_SFC 121
350#define SRST_SD_H 122
351#define SRST_NANDC_H 123
352#define SRST_NANDC_N 124
353#define SRST_MAC_A 125
354#define SRST_CAN_P 126
355#define SRST_OWIRE_P 127
356
357/* cru_softrst_con8 */
358#define SRST_AUDIO_NIU_H 128
359#define SRST_AUDIO_NIU_P 129
360#define SRST_PDM_H 130
361#define SRST_PDM_M 131
362#define SRST_SPDIFTX_H 132
363#define SRST_SPDIFTX_M 133
364#define SRST_SPDIFRX_H 134
365#define SRST_SPDIFRX_M 135
366#define SRST_I2S0_8CH_H 136
367#define SRST_I2S0_8CH_TX_M 137
368#define SRST_I2S0_8CH_RX_M 138
369#define SRST_I2S1_8CH_H 139
370#define SRST_I2S1_8CH_TX_M 140
371#define SRST_I2S1_8CH_RX_M 141
372#define SRST_I2S2_8CH_H 142
373#define SRST_I2S2_8CH_TX_M 143
374
375/* cru_softrst_con9 */
376#define SRST_I2S2_8CH_RX_M 144
377#define SRST_I2S3_8CH_H 145
378#define SRST_I2S3_8CH_TX_M 146
379#define SRST_I2S3_8CH_RX_M 147
380#define SRST_I2S0_2CH_H 148
381#define SRST_I2S0_2CH_M 149
382#define SRST_I2S1_2CH_H 150
383#define SRST_I2S1_2CH_M 151
384#define SRST_VAD_H 152
385#define SRST_ACODEC_P 153
386
387#endif
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index c0d5d5599c87..014ac6123d17 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -104,4 +104,8 @@
104 104
105#define CLK_MIPI_CSI 73 105#define CLK_MIPI_CSI 73
106 106
107/* Clocks not available on V3s */
108#define CLK_BUS_I2S0 75
109#define CLK_I2S0 76
110
107#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ 111#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h
new file mode 100644
index 000000000000..8804e34ebdd4
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8183-resets.h
@@ -0,0 +1,81 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Yong Liang <yong.liang@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
8#define _DT_BINDINGS_RESET_CONTROLLER_MT8183
9
10/* INFRACFG AO resets */
11#define MT8183_INFRACFG_AO_THERM_SW_RST 0
12#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1
13#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3
14#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4
15#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5
16#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6
17#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7
18#define MT8183_INFRACFG_AO_APDMA_SW_RST 9
19#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10
20#define MT8183_INFRACFG_AO_BTIF_SW_RST 12
21#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14
22#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15
23
24#define MT8183_INFRACFG_AO_IRTX_SW_RST 32
25#define MT8183_INFRACFG_AO_SPI0_SW_RST 33
26#define MT8183_INFRACFG_AO_I2C0_SW_RST 34
27#define MT8183_INFRACFG_AO_I2C1_SW_RST 35
28#define MT8183_INFRACFG_AO_I2C2_SW_RST 36
29#define MT8183_INFRACFG_AO_I2C3_SW_RST 37
30#define MT8183_INFRACFG_AO_UART0_SW_RST 38
31#define MT8183_INFRACFG_AO_UART1_SW_RST 39
32#define MT8183_INFRACFG_AO_UART2_SW_RST 40
33#define MT8183_INFRACFG_AO_PWM_SW_RST 41
34#define MT8183_INFRACFG_AO_SPI1_SW_RST 42
35#define MT8183_INFRACFG_AO_I2C4_SW_RST 43
36#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44
37#define MT8183_INFRACFG_AO_SPI2_SW_RST 45
38#define MT8183_INFRACFG_AO_SPI3_SW_RST 46
39#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47
40
41#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64
42#define MT8183_INFRACFG_AO_SPM_SW_RST 65
43#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66
44#define MT8183_INFRACFG_AO_KP_SW_RST 68
45#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69
46#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70
47#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71
48#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72
49#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73
50
51#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96
52#define MT8183_INFRACFG_AO_GCE_SW_RST 97
53#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98
54#define MT8183_INFRACFG_AO_TRNG_SW_RST 99
55#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103
56#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104
57#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105
58#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106
59#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107
60#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108
61#define MT8183_INFRACFG_AO_I2C5_SW_RST 109
62#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110
63#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111
64#define MT8183_INFRACFG_AO_SPI4_SW_RST 112
65#define MT8183_INFRACFG_AO_SPI5_SW_RST 113
66#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114
67#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
68#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
69#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117
70#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118
71#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119
72#define MT8183_INFRACFG_AO_I2C6_SW_RST 120
73#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121
74#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122
75#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123
76#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124
77#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125
78#define MT8183_INFRACFG_AO_I2C7_SW_RST 126
79#define MT8183_INFRACFG_AO_I2C8_SW_RST 127
80
81#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
index b58ef21a2e18..b6790173afd6 100644
--- a/include/dt-bindings/reset/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -75,4 +75,7 @@
75#define RST_BUS_UART1 50 75#define RST_BUS_UART1 50
76#define RST_BUS_UART2 51 76#define RST_BUS_UART2 51
77 77
78/* Reset lines not available on V3s */
79#define RST_BUS_I2S0 52
80
78#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ 81#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index dce5521a9bf6..2fdfe8061363 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -299,7 +299,8 @@ struct clk_init_data {
299 * into the clk API 299 * into the clk API
300 * 300 *
301 * @init: pointer to struct clk_init_data that contains the init data shared 301 * @init: pointer to struct clk_init_data that contains the init data shared
302 * with the common clock framework. 302 * with the common clock framework. This pointer will be set to NULL once
303 * a clk_register() variant is called on this clk_hw pointer.
303 */ 304 */
304struct clk_hw { 305struct clk_hw {
305 struct clk_core *core; 306 struct clk_core *core;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 853a8f181394..18b7b95a8253 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -239,7 +239,8 @@ static inline int clk_prepare(struct clk *clk)
239 return 0; 239 return 0;
240} 240}
241 241
242static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) 242static inline int __must_check
243clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
243{ 244{
244 might_sleep(); 245 might_sleep();
245 return 0; 246 return 0;
@@ -263,7 +264,8 @@ static inline void clk_unprepare(struct clk *clk)
263{ 264{
264 might_sleep(); 265 might_sleep();
265} 266}
266static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks) 267static inline void clk_bulk_unprepare(int num_clks,
268 const struct clk_bulk_data *clks)
267{ 269{
268 might_sleep(); 270 might_sleep();
269} 271}
@@ -820,7 +822,8 @@ static inline int clk_enable(struct clk *clk)
820 return 0; 822 return 0;
821} 823}
822 824
823static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) 825static inline int __must_check clk_bulk_enable(int num_clks,
826 const struct clk_bulk_data *clks)
824{ 827{
825 return 0; 828 return 0;
826} 829}
@@ -829,7 +832,7 @@ static inline void clk_disable(struct clk *clk) {}
829 832
830 833
831static inline void clk_bulk_disable(int num_clks, 834static inline void clk_bulk_disable(int num_clks,
832 struct clk_bulk_data *clks) {} 835 const struct clk_bulk_data *clks) {}
833 836
834static inline unsigned long clk_get_rate(struct clk *clk) 837static inline unsigned long clk_get_rate(struct clk *clk)
835{ 838{
@@ -918,8 +921,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
918 clk_unprepare(clk); 921 clk_unprepare(clk);
919} 922}
920 923
921static inline int __must_check clk_bulk_prepare_enable(int num_clks, 924static inline int __must_check
922 struct clk_bulk_data *clks) 925clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks)
923{ 926{
924 int ret; 927 int ret;
925 928
@@ -934,7 +937,7 @@ static inline int __must_check clk_bulk_prepare_enable(int num_clks,
934} 937}
935 938
936static inline void clk_bulk_disable_unprepare(int num_clks, 939static inline void clk_bulk_disable_unprepare(int num_clks,
937 struct clk_bulk_data *clks) 940 const struct clk_bulk_data *clks)
938{ 941{
939 clk_bulk_disable(num_clks, clks); 942 clk_bulk_disable(num_clks, clks);
940 clk_bulk_unprepare(num_clks, clks); 943 clk_bulk_unprepare(num_clks, clks);
diff --git a/include/linux/clk/clk-conf.h b/include/linux/clk/clk-conf.h
index 85f8cf9d1226..eae9652c70cd 100644
--- a/include/linux/clk/clk-conf.h
+++ b/include/linux/clk/clk-conf.h
@@ -4,6 +4,9 @@
4 * Sylwester Nawrocki <s.nawrocki@samsung.com> 4 * Sylwester Nawrocki <s.nawrocki@samsung.com>
5 */ 5 */
6 6
7#ifndef __CLK_CONF_H
8#define __CLK_CONF_H
9
7#include <linux/types.h> 10#include <linux/types.h>
8 11
9struct device_node; 12struct device_node;
@@ -17,3 +20,5 @@ static inline int of_clk_set_defaults(struct device_node *node,
17 return 0; 20 return 0;
18} 21}
19#endif 22#endif
23
24#endif /* __CLK_CONF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 15:40:05 -0400