summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-09-02 13:20:57 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-09-02 13:20:57 -0400
commit96e46dcfb8534494859936b3da4f3018de53a53f (patch)
tree1341f4390933909c97a77be3cdbaf403b3f04bd8
parentb2fcb285ade36c2339ee6638223a65829ee9907f (diff)
parent18a93cd38be3e69ac5b067c570a78a369b79e31d (diff)
Merge tag 'usb-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes: USB: Changes for v5.4 merge window With only 45 non-merge commits, we have a small merge window from the Gadget perspective. The biggest change here is the addition of the Cadence USB3 DRD Driver. All other changes are small, non-critical fixes or smaller new features like the improvement to BESL handling in dwc3. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> * tag 'usb-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (45 commits) usb: gadget: net2280: Add workaround for AB chip Errata 11 usb: gadget: net2280: Move all "ll" registers in one structure usb: dwc3: gadget: Workaround Mirosoft's BESL check usb:cdns3 Fix for stuck packets in on-chip OUT buffer. usb: cdns3: Add Cadence USB3 DRD Driver usb: common: Simplify usb_decode_get_set_descriptor function. usb: common: Patch simplify usb_decode_set_clear_feature function. usb: common: Separated decoding functions from dwc3 driver. dt-bindings: add binding for USBSS-DRD controller. usb: gadget: composite: Set recommended BESL values usb: dwc3: gadget: Set BESL config parameter usb: dwc3: Separate field holding multiple properties usb: gadget: Export recommended BESL values usb: phy: phy-fsl-usb: Make structure fsl_otg_initdata constant usb: udc: lpc32xx: silence fall-through warning usb: dwc3: meson-g12a: fix suspend resume regulator unbalanced disables usb: udc: lpc32xx: remove set but not used 3 variables usb: gadget: udc: core: Fix segfault if udc_bind_to_driver() for pending driver fails usb: dwc3: st: Add of_dev_put() in probe function usb: dwc3: st: Add of_node_put() before return in probe function ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/usb/cdns-usb3.txt45
-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/Makefile2
-rw-r--r--drivers/usb/cdns3/Kconfig46
-rw-r--r--drivers/usb/cdns3/Makefile16
-rw-r--r--drivers/usb/cdns3/cdns3-pci-wrap.c203
-rw-r--r--drivers/usb/cdns3/core.c653
-rw-r--r--drivers/usb/cdns3/core.h98
-rw-r--r--drivers/usb/cdns3/debug.h161
-rw-r--r--drivers/usb/cdns3/drd.c381
-rw-r--r--drivers/usb/cdns3/drd.h167
-rw-r--r--drivers/usb/cdns3/ep0.c888
-rw-r--r--drivers/usb/cdns3/gadget-export.h28
-rw-r--r--drivers/usb/cdns3/gadget.c2751
-rw-r--r--drivers/usb/cdns3/gadget.h1338
-rw-r--r--drivers/usb/cdns3/host-export.h28
-rw-r--r--drivers/usb/cdns3/host.c74
-rw-r--r--drivers/usb/cdns3/trace.c11
-rw-r--r--drivers/usb/cdns3/trace.h493
-rw-r--r--drivers/usb/common/Makefile1
-rw-r--r--drivers/usb/common/debug.c268
-rw-r--r--drivers/usb/dwc2/gadget.c9
-rw-r--r--drivers/usb/dwc3/core.c56
-rw-r--r--drivers/usb/dwc3/core.h2
-rw-r--r--drivers/usb/dwc3/debug.h252
-rw-r--r--drivers/usb/dwc3/dwc3-keystone.c4
-rw-r--r--drivers/usb/dwc3/dwc3-meson-g12a.c14
-rw-r--r--drivers/usb/dwc3/dwc3-omap.c11
-rw-r--r--drivers/usb/dwc3/dwc3-st.c10
-rw-r--r--drivers/usb/dwc3/gadget.c24
-rw-r--r--drivers/usb/dwc3/host.c22
-rw-r--r--drivers/usb/dwc3/trace.h2
-rw-r--r--drivers/usb/gadget/composite.c38
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/core.c6
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/dev.c80
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/ep0.c59
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/epn.c2
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/hub.c15
-rw-r--r--drivers/usb/gadget/udc/aspeed-vhub/vhub.h3
-rw-r--r--drivers/usb/gadget/udc/core.c2
-rw-r--r--drivers/usb/gadget/udc/lpc32xx_udc.c11
-rw-r--r--drivers/usb/gadget/udc/net2280.c38
-rw-r--r--drivers/usb/gadget/udc/net2280.h3
-rw-r--r--drivers/usb/gadget/udc/pch_udc.c3
-rw-r--r--drivers/usb/phy/phy-fsl-usb.c2
-rw-r--r--include/linux/platform_data/dwc3-omap.h43
-rw-r--r--include/linux/usb/ch9.h27
-rw-r--r--include/linux/usb/gadget.h3
-rw-r--r--include/linux/usb/hcd.h4
-rw-r--r--include/linux/usb/usb338x.h35
-rw-r--r--include/uapi/linux/usb/ch9.h2
51 files changed, 7960 insertions, 476 deletions
diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
new file mode 100644
index 000000000000..b7dc606d37b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
@@ -0,0 +1,45 @@
1Binding for the Cadence USBSS-DRD controller
2
3Required properties:
4 - reg: Physical base address and size of the controller's register areas.
5 Controller has 3 different regions:
6 - HOST registers area
7 - DEVICE registers area
8 - OTG/DRD registers area
9 - reg-names - register memory area names:
10 "xhci" - for HOST registers space
11 "dev" - for DEVICE registers space
12 "otg" - for OTG/DRD registers space
13 - compatible: Should contain: "cdns,usb3"
14 - interrupts: Interrupts used by cdns3 controller:
15 "host" - interrupt used by XHCI driver.
16 "peripheral" - interrupt used by device driver
17 "otg" - interrupt used by DRD/OTG part of driver
18
19Optional properties:
20 - maximum-speed : valid arguments are "super-speed", "high-speed" and
21 "full-speed"; refer to usb/generic.txt
22 - dr_mode: Should be one of "host", "peripheral" or "otg".
23 - phys: reference to the USB PHY
24 - phy-names: from the *Generic PHY* bindings;
25 Supported names are:
26 - cdns3,usb2-phy
27 - cdns3,usb3-phy
28
29 - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints
30 buffers expressed in KB
31
32Example:
33 usb@f3000000 {
34 compatible = "cdns,usb3";
35 interrupts = <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_USB_IRQ 8 IRQ_TYPE_LEVEL_HIGH>;
38 interrupt-names = "host", "peripheral", "otg";
39 reg = <0xf3000000 0x10000>, /* memory area for HOST registers */
40 <0xf3010000 0x10000>, /* memory area for DEVICE registers */
41 <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */
42 reg-names = "xhci", "dev", "otg";
43 phys = <&usb2_phy>, <&usb3_phy>;
44 phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy";
45 };
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 9987c399819f..fc1c66af6f0a 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -112,6 +112,8 @@ source "drivers/usb/usbip/Kconfig"
112 112
113endif 113endif
114 114
115source "drivers/usb/cdns3/Kconfig"
116
115source "drivers/usb/mtu3/Kconfig" 117source "drivers/usb/mtu3/Kconfig"
116 118
117source "drivers/usb/musb/Kconfig" 119source "drivers/usb/musb/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index db064dd59e08..1c1c1d659394 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_USB_DWC3) += dwc3/
13obj-$(CONFIG_USB_DWC2) += dwc2/ 13obj-$(CONFIG_USB_DWC2) += dwc2/
14obj-$(CONFIG_USB_ISP1760) += isp1760/ 14obj-$(CONFIG_USB_ISP1760) += isp1760/
15 15
16obj-$(CONFIG_USB_CDNS3) += cdns3/
17
16obj-$(CONFIG_USB_MON) += mon/ 18obj-$(CONFIG_USB_MON) += mon/
17obj-$(CONFIG_USB_MTU3) += mtu3/ 19obj-$(CONFIG_USB_MTU3) += mtu3/
18 20
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
new file mode 100644
index 000000000000..d0331613a355
--- /dev/null
+++ b/drivers/usb/cdns3/Kconfig
@@ -0,0 +1,46 @@
1config USB_CDNS3
2 tristate "Cadence USB3 Dual-Role Controller"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
5 select USB_ROLE_SWITCH
6 help
7 Say Y here if your system has a Cadence USB3 dual-role controller.
8 It supports: dual-role switch, Host-only, and Peripheral-only.
9
10 If you choose to build this driver is a dynamically linked
11 as module, the module will be called cdns3.ko.
12
13if USB_CDNS3
14
15config USB_CDNS3_GADGET
16 bool "Cadence USB3 device controller"
17 depends on USB_GADGET=y || USB_GADGET=USB_CDNS3
18 help
19 Say Y here to enable device controller functionality of the
20 Cadence USBSS-DEV driver.
21
22 This controller supports FF, HS and SS mode. It doesn't support
23 LS and SSP mode.
24
25config USB_CDNS3_HOST
26 bool "Cadence USB3 host controller"
27 depends on USB=y || USB=USB_CDNS3
28 help
29 Say Y here to enable host controller functionality of the
30 Cadence driver.
31
32 Host controller is compliant with XHCI so it will use
33 standard XHCI driver.
34
35config USB_CDNS3_PCI_WRAP
36 tristate "Cadence USB3 support on PCIe-based platforms"
37 depends on USB_PCI && ACPI
38 default USB_CDNS3
39 help
40 If you're using the USBSS Core IP with a PCIe, please say
41 'Y' or 'M' here.
42
43 If you choose to build this driver as module it will
44 be dynamically linked and module will be called cdns3-pci.ko
45
46endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
new file mode 100644
index 000000000000..a703547350bb
--- /dev/null
+++ b/drivers/usb/cdns3/Makefile
@@ -0,0 +1,16 @@
1# SPDX-License-Identifier: GPL-2.0
2# define_trace.h needs to know how to find our header
3CFLAGS_trace.o := -I$(src)
4
5cdns3-y := core.o drd.o
6
7obj-$(CONFIG_USB_CDNS3) += cdns3.o
8cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o ep0.o
9
10ifneq ($(CONFIG_USB_CDNS3_GADGET),)
11cdns3-$(CONFIG_TRACING) += trace.o
12endif
13
14cdns3-$(CONFIG_USB_CDNS3_HOST) += host.o
15
16obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
diff --git a/drivers/usb/cdns3/cdns3-pci-wrap.c b/drivers/usb/cdns3/cdns3-pci-wrap.c
new file mode 100644
index 000000000000..c41ddb61b857
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-pci-wrap.c
@@ -0,0 +1,203 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS PCI Glue driver
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/slab.h>
16
17struct cdns3_wrap {
18 struct platform_device *plat_dev;
19 struct resource dev_res[6];
20 int devfn;
21};
22
23#define RES_IRQ_HOST_ID 0
24#define RES_IRQ_PERIPHERAL_ID 1
25#define RES_IRQ_OTG_ID 2
26#define RES_HOST_ID 3
27#define RES_DEV_ID 4
28#define RES_DRD_ID 5
29
30#define PCI_BAR_HOST 0
31#define PCI_BAR_DEV 2
32#define PCI_BAR_OTG 0
33
34#define PCI_DEV_FN_HOST_DEVICE 0
35#define PCI_DEV_FN_OTG 1
36
37#define PCI_DRIVER_NAME "cdns3-pci-usbss"
38#define PLAT_DRIVER_NAME "cdns-usb3"
39
40#define CDNS_VENDOR_ID 0x17cd
41#define CDNS_DEVICE_ID 0x0100
42
43static struct pci_dev *cdns3_get_second_fun(struct pci_dev *pdev)
44{
45 struct pci_dev *func;
46
47 /*
48 * Gets the second function.
49 * It's little tricky, but this platform has two function.
50 * The fist keeps resources for Host/Device while the second
51 * keeps resources for DRD/OTG.
52 */
53 func = pci_get_device(pdev->vendor, pdev->device, NULL);
54 if (unlikely(!func))
55 return NULL;
56
57 if (func->devfn == pdev->devfn) {
58 func = pci_get_device(pdev->vendor, pdev->device, func);
59 if (unlikely(!func))
60 return NULL;
61 }
62
63 return func;
64}
65
66static int cdns3_pci_probe(struct pci_dev *pdev,
67 const struct pci_device_id *id)
68{
69 struct platform_device_info plat_info;
70 struct cdns3_wrap *wrap;
71 struct resource *res;
72 struct pci_dev *func;
73 int err;
74
75 /*
76 * for GADGET/HOST PCI (devfn) function number is 0,
77 * for OTG PCI (devfn) function number is 1
78 */
79 if (!id || (pdev->devfn != PCI_DEV_FN_HOST_DEVICE &&
80 pdev->devfn != PCI_DEV_FN_OTG))
81 return -EINVAL;
82
83 func = cdns3_get_second_fun(pdev);
84 if (unlikely(!func))
85 return -EINVAL;
86
87 err = pcim_enable_device(pdev);
88 if (err) {
89 dev_err(&pdev->dev, "Enabling PCI device has failed %d\n", err);
90 return err;
91 }
92
93 pci_set_master(pdev);
94
95 if (pci_is_enabled(func)) {
96 wrap = pci_get_drvdata(func);
97 } else {
98 wrap = kzalloc(sizeof(*wrap), GFP_KERNEL);
99 if (!wrap) {
100 pci_disable_device(pdev);
101 return -ENOMEM;
102 }
103 }
104
105 res = wrap->dev_res;
106
107 if (pdev->devfn == PCI_DEV_FN_HOST_DEVICE) {
108 /* function 0: host(BAR_0) + device(BAR_1).*/
109 dev_dbg(&pdev->dev, "Initialize Device resources\n");
110 res[RES_DEV_ID].start = pci_resource_start(pdev, PCI_BAR_DEV);
111 res[RES_DEV_ID].end = pci_resource_end(pdev, PCI_BAR_DEV);
112 res[RES_DEV_ID].name = "dev";
113 res[RES_DEV_ID].flags = IORESOURCE_MEM;
114 dev_dbg(&pdev->dev, "USBSS-DEV physical base addr: %pa\n",
115 &res[RES_DEV_ID].start);
116
117 res[RES_HOST_ID].start = pci_resource_start(pdev, PCI_BAR_HOST);
118 res[RES_HOST_ID].end = pci_resource_end(pdev, PCI_BAR_HOST);
119 res[RES_HOST_ID].name = "xhci";
120 res[RES_HOST_ID].flags = IORESOURCE_MEM;
121 dev_dbg(&pdev->dev, "USBSS-XHCI physical base addr: %pa\n",
122 &res[RES_HOST_ID].start);
123
124 /* Interrupt for XHCI */
125 wrap->dev_res[RES_IRQ_HOST_ID].start = pdev->irq;
126 wrap->dev_res[RES_IRQ_HOST_ID].name = "host";
127 wrap->dev_res[RES_IRQ_HOST_ID].flags = IORESOURCE_IRQ;
128
129 /* Interrupt device. It's the same as for HOST. */
130 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].start = pdev->irq;
131 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].name = "peripheral";
132 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].flags = IORESOURCE_IRQ;
133 } else {
134 res[RES_DRD_ID].start = pci_resource_start(pdev, PCI_BAR_OTG);
135 res[RES_DRD_ID].end = pci_resource_end(pdev, PCI_BAR_OTG);
136 res[RES_DRD_ID].name = "otg";
137 res[RES_DRD_ID].flags = IORESOURCE_MEM;
138 dev_dbg(&pdev->dev, "USBSS-DRD physical base addr: %pa\n",
139 &res[RES_DRD_ID].start);
140
141 /* Interrupt for OTG/DRD. */
142 wrap->dev_res[RES_IRQ_OTG_ID].start = pdev->irq;
143 wrap->dev_res[RES_IRQ_OTG_ID].name = "otg";
144 wrap->dev_res[RES_IRQ_OTG_ID].flags = IORESOURCE_IRQ;
145 }
146
147 if (pci_is_enabled(func)) {
148 /* set up platform device info */
149 memset(&plat_info, 0, sizeof(plat_info));
150 plat_info.parent = &pdev->dev;
151 plat_info.fwnode = pdev->dev.fwnode;
152 plat_info.name = PLAT_DRIVER_NAME;
153 plat_info.id = pdev->devfn;
154 wrap->devfn = pdev->devfn;
155 plat_info.res = wrap->dev_res;
156 plat_info.num_res = ARRAY_SIZE(wrap->dev_res);
157 plat_info.dma_mask = pdev->dma_mask;
158 /* register platform device */
159 wrap->plat_dev = platform_device_register_full(&plat_info);
160 if (IS_ERR(wrap->plat_dev)) {
161 pci_disable_device(pdev);
162 kfree(wrap);
163 return PTR_ERR(wrap->plat_dev);
164 }
165 }
166
167 pci_set_drvdata(pdev, wrap);
168 return err;
169}
170
171static void cdns3_pci_remove(struct pci_dev *pdev)
172{
173 struct cdns3_wrap *wrap;
174 struct pci_dev *func;
175
176 func = cdns3_get_second_fun(pdev);
177
178 wrap = (struct cdns3_wrap *)pci_get_drvdata(pdev);
179 if (wrap->devfn == pdev->devfn)
180 platform_device_unregister(wrap->plat_dev);
181
182 if (!pci_is_enabled(func))
183 kfree(wrap);
184}
185
186static const struct pci_device_id cdns3_pci_ids[] = {
187 { PCI_DEVICE(CDNS_VENDOR_ID, CDNS_DEVICE_ID), },
188 { 0, }
189};
190
191static struct pci_driver cdns3_pci_driver = {
192 .name = PCI_DRIVER_NAME,
193 .id_table = cdns3_pci_ids,
194 .probe = cdns3_pci_probe,
195 .remove = cdns3_pci_remove,
196};
197
198module_pci_driver(cdns3_pci_driver);
199MODULE_DEVICE_TABLE(pci, cdns3_pci_ids);
200
201MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>");
202MODULE_LICENSE("GPL v2");
203MODULE_DESCRIPTION("Cadence USBSS PCI wrapperr");
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
new file mode 100644
index 000000000000..300df58a190b
--- /dev/null
+++ b/drivers/usb/cdns3/core.c
@@ -0,0 +1,653 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
7 * Copyright (C) 2019 Texas Instruments
8 *
9 * Author: Peter Chen <peter.chen@nxp.com>
10 * Pawel Laszczak <pawell@cadence.com>
11 * Roger Quadros <rogerq@ti.com>
12 */
13
14#include <linux/dma-mapping.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/pm_runtime.h>
21
22#include "gadget.h"
23#include "core.h"
24#include "host-export.h"
25#include "gadget-export.h"
26#include "drd.h"
27
28static int cdns3_idle_init(struct cdns3 *cdns);
29
30static inline
31struct cdns3_role_driver *cdns3_get_current_role_driver(struct cdns3 *cdns)
32{
33 WARN_ON(!cdns->roles[cdns->role]);
34 return cdns->roles[cdns->role];
35}
36
37static int cdns3_role_start(struct cdns3 *cdns, enum usb_role role)
38{
39 int ret;
40
41 if (WARN_ON(role > USB_ROLE_DEVICE))
42 return 0;
43
44 mutex_lock(&cdns->mutex);
45 cdns->role = role;
46 mutex_unlock(&cdns->mutex);
47
48 if (!cdns->roles[role])
49 return -ENXIO;
50
51 if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE)
52 return 0;
53
54 mutex_lock(&cdns->mutex);
55 ret = cdns->roles[role]->start(cdns);
56 if (!ret)
57 cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE;
58 mutex_unlock(&cdns->mutex);
59
60 return ret;
61}
62
63static void cdns3_role_stop(struct cdns3 *cdns)
64{
65 enum usb_role role = cdns->role;
66
67 if (WARN_ON(role > USB_ROLE_DEVICE))
68 return;
69
70 if (cdns->roles[role]->state == CDNS3_ROLE_STATE_INACTIVE)
71 return;
72
73 mutex_lock(&cdns->mutex);
74 cdns->roles[role]->stop(cdns);
75 cdns->roles[role]->state = CDNS3_ROLE_STATE_INACTIVE;
76 mutex_unlock(&cdns->mutex);
77}
78
79static void cdns3_exit_roles(struct cdns3 *cdns)
80{
81 cdns3_role_stop(cdns);
82 cdns3_drd_exit(cdns);
83}
84
85static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns);
86
87/**
88 * cdns3_core_init_role - initialize role of operation
89 * @cdns: Pointer to cdns3 structure
90 *
91 * Returns 0 on success otherwise negative errno
92 */
93static int cdns3_core_init_role(struct cdns3 *cdns)
94{
95 struct device *dev = cdns->dev;
96 enum usb_dr_mode best_dr_mode;
97 enum usb_dr_mode dr_mode;
98 int ret = 0;
99
100 dr_mode = usb_get_dr_mode(dev);
101 cdns->role = USB_ROLE_NONE;
102
103 /*
104 * If driver can't read mode by means of usb_get_dr_mode function then
105 * chooses mode according with Kernel configuration. This setting
106 * can be restricted later depending on strap pin configuration.
107 */
108 if (dr_mode == USB_DR_MODE_UNKNOWN) {
109 if (IS_ENABLED(CONFIG_USB_CDNS3_HOST) &&
110 IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
111 dr_mode = USB_DR_MODE_OTG;
112 else if (IS_ENABLED(CONFIG_USB_CDNS3_HOST))
113 dr_mode = USB_DR_MODE_HOST;
114 else if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
115 dr_mode = USB_DR_MODE_PERIPHERAL;
116 }
117
118 /*
119 * At this point cdns->dr_mode contains strap configuration.
120 * Driver try update this setting considering kernel configuration
121 */
122 best_dr_mode = cdns->dr_mode;
123
124 ret = cdns3_idle_init(cdns);
125 if (ret)
126 return ret;
127
128 if (dr_mode == USB_DR_MODE_OTG) {
129 best_dr_mode = cdns->dr_mode;
130 } else if (cdns->dr_mode == USB_DR_MODE_OTG) {
131 best_dr_mode = dr_mode;
132 } else if (cdns->dr_mode != dr_mode) {
133 dev_err(dev, "Incorrect DRD configuration\n");
134 return -EINVAL;
135 }
136
137 dr_mode = best_dr_mode;
138
139 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
140 ret = cdns3_host_init(cdns);
141 if (ret) {
142 dev_err(dev, "Host initialization failed with %d\n",
143 ret);
144 goto err;
145 }
146 }
147
148 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
149 ret = cdns3_gadget_init(cdns);
150 if (ret) {
151 dev_err(dev, "Device initialization failed with %d\n",
152 ret);
153 goto err;
154 }
155 }
156
157 cdns->dr_mode = dr_mode;
158
159 ret = cdns3_drd_update_mode(cdns);
160 if (ret)
161 goto err;
162
163 if (cdns->dr_mode != USB_DR_MODE_OTG) {
164 ret = cdns3_hw_role_switch(cdns);
165 if (ret)
166 goto err;
167 }
168
169 return ret;
170err:
171 cdns3_exit_roles(cdns);
172 return ret;
173}
174
175/**
176 * cdsn3_hw_role_state_machine - role switch state machine based on hw events.
177 * @cdns: Pointer to controller structure.
178 *
179 * Returns next role to be entered based on hw events.
180 */
181static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns)
182{
183 enum usb_role role;
184 int id, vbus;
185
186 if (cdns->dr_mode != USB_DR_MODE_OTG)
187 goto not_otg;
188
189 id = cdns3_get_id(cdns);
190 vbus = cdns3_get_vbus(cdns);
191
192 /*
193 * Role change state machine
194 * Inputs: ID, VBUS
195 * Previous state: cdns->role
196 * Next state: role
197 */
198 role = cdns->role;
199
200 switch (role) {
201 case USB_ROLE_NONE:
202 /*
203 * Driver treats USB_ROLE_NONE synonymous to IDLE state from
204 * controller specification.
205 */
206 if (!id)
207 role = USB_ROLE_HOST;
208 else if (vbus)
209 role = USB_ROLE_DEVICE;
210 break;
211 case USB_ROLE_HOST: /* from HOST, we can only change to NONE */
212 if (id)
213 role = USB_ROLE_NONE;
214 break;
215 case USB_ROLE_DEVICE: /* from GADGET, we can only change to NONE*/
216 if (!vbus)
217 role = USB_ROLE_NONE;
218 break;
219 }
220
221 dev_dbg(cdns->dev, "role %d -> %d\n", cdns->role, role);
222
223 return role;
224
225not_otg:
226 if (cdns3_is_host(cdns))
227 role = USB_ROLE_HOST;
228 if (cdns3_is_device(cdns))
229 role = USB_ROLE_DEVICE;
230
231 return role;
232}
233
234static int cdns3_idle_role_start(struct cdns3 *cdns)
235{
236 return 0;
237}
238
239static void cdns3_idle_role_stop(struct cdns3 *cdns)
240{
241 /* Program Lane swap and bring PHY out of RESET */
242 phy_reset(cdns->usb3_phy);
243}
244
245static int cdns3_idle_init(struct cdns3 *cdns)
246{
247 struct cdns3_role_driver *rdrv;
248
249 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
250 if (!rdrv)
251 return -ENOMEM;
252
253 rdrv->start = cdns3_idle_role_start;
254 rdrv->stop = cdns3_idle_role_stop;
255 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
256 rdrv->suspend = NULL;
257 rdrv->resume = NULL;
258 rdrv->name = "idle";
259
260 cdns->roles[USB_ROLE_NONE] = rdrv;
261
262 return 0;
263}
264
265/**
266 * cdns3_hw_role_switch - switch roles based on HW state
267 * @cdns3: controller
268 */
269int cdns3_hw_role_switch(struct cdns3 *cdns)
270{
271 enum usb_role real_role, current_role;
272 int ret = 0;
273
274 /* Do nothing if role based on syfs. */
275 if (cdns->role_override)
276 return 0;
277
278 pm_runtime_get_sync(cdns->dev);
279
280 current_role = cdns->role;
281 real_role = cdsn3_hw_role_state_machine(cdns);
282
283 /* Do nothing if nothing changed */
284 if (current_role == real_role)
285 goto exit;
286
287 cdns3_role_stop(cdns);
288
289 dev_dbg(cdns->dev, "Switching role %d -> %d", current_role, real_role);
290
291 ret = cdns3_role_start(cdns, real_role);
292 if (ret) {
293 /* Back to current role */
294 dev_err(cdns->dev, "set %d has failed, back to %d\n",
295 real_role, current_role);
296 ret = cdns3_role_start(cdns, current_role);
297 if (ret)
298 dev_err(cdns->dev, "back to %d failed too\n",
299 current_role);
300 }
301exit:
302 pm_runtime_put_sync(cdns->dev);
303 return ret;
304}
305
306/**
307 * cdsn3_role_get - get current role of controller.
308 *
309 * @dev: Pointer to device structure
310 *
311 * Returns role
312 */
313static enum usb_role cdns3_role_get(struct device *dev)
314{
315 struct cdns3 *cdns = dev_get_drvdata(dev);
316
317 return cdns->role;
318}
319
320/**
321 * cdns3_role_set - set current role of controller.
322 *
323 * @dev: pointer to device object
324 * @role - the previous role
325 * Handles below events:
326 * - Role switch for dual-role devices
327 * - USB_ROLE_GADGET <--> USB_ROLE_NONE for peripheral-only devices
328 */
329static int cdns3_role_set(struct device *dev, enum usb_role role)
330{
331 struct cdns3 *cdns = dev_get_drvdata(dev);
332 int ret = 0;
333
334 pm_runtime_get_sync(cdns->dev);
335
336 /*
337 * FIXME: switch role framework should be extended to meet
338 * requirements. Driver assumes that role can be controlled
339 * by SW or HW. Temporary workaround is to use USB_ROLE_NONE to
340 * switch from SW to HW control.
341 *
342 * For dr_mode == USB_DR_MODE_OTG:
343 * if user sets USB_ROLE_HOST or USB_ROLE_DEVICE then driver
344 * sets role_override flag and forces that role.
345 * if user sets USB_ROLE_NONE, driver clears role_override and lets
346 * HW state machine take over.
347 *
348 * For dr_mode != USB_DR_MODE_OTG:
349 * Assumptions:
350 * 1. Restricted user control between NONE and dr_mode.
351 * 2. Driver doesn't need to rely on role_override flag.
352 * 3. Driver needs to ensure that HW state machine is never called
353 * if dr_mode != USB_DR_MODE_OTG.
354 */
355 if (role == USB_ROLE_NONE)
356 cdns->role_override = 0;
357 else
358 cdns->role_override = 1;
359
360 /*
361 * HW state might have changed so driver need to trigger
362 * HW state machine if dr_mode == USB_DR_MODE_OTG.
363 */
364 if (!cdns->role_override && cdns->dr_mode == USB_DR_MODE_OTG) {
365 cdns3_hw_role_switch(cdns);
366 goto pm_put;
367 }
368
369 if (cdns->role == role)
370 goto pm_put;
371
372 if (cdns->dr_mode == USB_DR_MODE_HOST) {
373 switch (role) {
374 case USB_ROLE_NONE:
375 case USB_ROLE_HOST:
376 break;
377 default:
378 ret = -EPERM;
379 goto pm_put;
380 }
381 }
382
383 if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) {
384 switch (role) {
385 case USB_ROLE_NONE:
386 case USB_ROLE_DEVICE:
387 break;
388 default:
389 ret = -EPERM;
390 goto pm_put;
391 }
392 }
393
394 cdns3_role_stop(cdns);
395 ret = cdns3_role_start(cdns, role);
396 if (ret) {
397 dev_err(cdns->dev, "set role %d has failed\n", role);
398 ret = -EPERM;
399 }
400
401pm_put:
402 pm_runtime_put_sync(cdns->dev);
403 return ret;
404}
405
406static const struct usb_role_switch_desc cdns3_switch_desc = {
407 .set = cdns3_role_set,
408 .get = cdns3_role_get,
409 .allow_userspace_control = true,
410};
411
412/**
413 * cdns3_probe - probe for cdns3 core device
414 * @pdev: Pointer to cdns3 core platform device
415 *
416 * Returns 0 on success otherwise negative errno
417 */
418static int cdns3_probe(struct platform_device *pdev)
419{
420 struct device *dev = &pdev->dev;
421 struct resource *res;
422 struct cdns3 *cdns;
423 void __iomem *regs;
424 int ret;
425
426 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
427 if (ret) {
428 dev_err(dev, "error setting dma mask: %d\n", ret);
429 return -ENODEV;
430 }
431
432 cdns = devm_kzalloc(dev, sizeof(*cdns), GFP_KERNEL);
433 if (!cdns)
434 return -ENOMEM;
435
436 cdns->dev = dev;
437
438 platform_set_drvdata(pdev, cdns);
439
440 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
441 if (!res) {
442 dev_err(dev, "missing host IRQ\n");
443 return -ENODEV;
444 }
445
446 cdns->xhci_res[0] = *res;
447
448 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
449 if (!res) {
450 dev_err(dev, "couldn't get xhci resource\n");
451 return -ENXIO;
452 }
453
454 cdns->xhci_res[1] = *res;
455
456 cdns->dev_irq = platform_get_irq_byname(pdev, "peripheral");
457 if (cdns->dev_irq == -EPROBE_DEFER)
458 return cdns->dev_irq;
459
460 if (cdns->dev_irq < 0)
461 dev_err(dev, "couldn't get peripheral irq\n");
462
463 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dev");
464 regs = devm_ioremap_resource(dev, res);
465 if (IS_ERR(regs)) {
466 dev_err(dev, "couldn't iomap dev resource\n");
467 return PTR_ERR(regs);
468 }
469 cdns->dev_regs = regs;
470
471 cdns->otg_irq = platform_get_irq_byname(pdev, "otg");
472 if (cdns->otg_irq == -EPROBE_DEFER)
473 return cdns->otg_irq;
474
475 if (cdns->otg_irq < 0) {
476 dev_err(dev, "couldn't get otg irq\n");
477 return cdns->otg_irq;
478 }
479
480 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otg");
481 if (!res) {
482 dev_err(dev, "couldn't get otg resource\n");
483 return -ENXIO;
484 }
485
486 cdns->otg_res = *res;
487
488 mutex_init(&cdns->mutex);
489
490 cdns->usb2_phy = devm_phy_optional_get(dev, "cdns3,usb2-phy");
491 if (IS_ERR(cdns->usb2_phy))
492 return PTR_ERR(cdns->usb2_phy);
493
494 ret = phy_init(cdns->usb2_phy);
495 if (ret)
496 return ret;
497
498 cdns->usb3_phy = devm_phy_optional_get(dev, "cdns3,usb3-phy");
499 if (IS_ERR(cdns->usb3_phy))
500 return PTR_ERR(cdns->usb3_phy);
501
502 ret = phy_init(cdns->usb3_phy);
503 if (ret)
504 goto err1;
505
506 ret = phy_power_on(cdns->usb2_phy);
507 if (ret)
508 goto err2;
509
510 ret = phy_power_on(cdns->usb3_phy);
511 if (ret)
512 goto err3;
513
514 cdns->role_sw = usb_role_switch_register(dev, &cdns3_switch_desc);
515 if (IS_ERR(cdns->role_sw)) {
516 ret = PTR_ERR(cdns->role_sw);
517 dev_warn(dev, "Unable to register Role Switch\n");
518 goto err4;
519 }
520
521 ret = cdns3_drd_init(cdns);
522 if (ret)
523 goto err5;
524
525 ret = cdns3_core_init_role(cdns);
526 if (ret)
527 goto err5;
528
529 device_set_wakeup_capable(dev, true);
530 pm_runtime_set_active(dev);
531 pm_runtime_enable(dev);
532
533 /*
534 * The controller needs less time between bus and controller suspend,
535 * and we also needs a small delay to avoid frequently entering low
536 * power mode.
537 */
538 pm_runtime_set_autosuspend_delay(dev, 20);
539 pm_runtime_mark_last_busy(dev);
540 pm_runtime_use_autosuspend(dev);
541 dev_dbg(dev, "Cadence USB3 core: probe succeed\n");
542
543 return 0;
544err5:
545 cdns3_drd_exit(cdns);
546 usb_role_switch_unregister(cdns->role_sw);
547err4:
548 phy_power_off(cdns->usb3_phy);
549
550err3:
551 phy_power_off(cdns->usb2_phy);
552err2:
553 phy_exit(cdns->usb3_phy);
554err1:
555 phy_exit(cdns->usb2_phy);
556
557 return ret;
558}
559
560/**
561 * cdns3_remove - unbind drd driver and clean up
562 * @pdev: Pointer to Linux platform device
563 *
564 * Returns 0 on success otherwise negative errno
565 */
566static int cdns3_remove(struct platform_device *pdev)
567{
568 struct cdns3 *cdns = platform_get_drvdata(pdev);
569
570 pm_runtime_get_sync(&pdev->dev);
571 pm_runtime_disable(&pdev->dev);
572 pm_runtime_put_noidle(&pdev->dev);
573 cdns3_exit_roles(cdns);
574 usb_role_switch_unregister(cdns->role_sw);
575 phy_power_off(cdns->usb2_phy);
576 phy_power_off(cdns->usb3_phy);
577 phy_exit(cdns->usb2_phy);
578 phy_exit(cdns->usb3_phy);
579 return 0;
580}
581
582#ifdef CONFIG_PM_SLEEP
583
584static int cdns3_suspend(struct device *dev)
585{
586 struct cdns3 *cdns = dev_get_drvdata(dev);
587 unsigned long flags;
588
589 if (cdns->role == USB_ROLE_HOST)
590 return 0;
591
592 if (pm_runtime_status_suspended(dev))
593 pm_runtime_resume(dev);
594
595 if (cdns->roles[cdns->role]->suspend) {
596 spin_lock_irqsave(&cdns->gadget_dev->lock, flags);
597 cdns->roles[cdns->role]->suspend(cdns, false);
598 spin_unlock_irqrestore(&cdns->gadget_dev->lock, flags);
599 }
600
601 return 0;
602}
603
604static int cdns3_resume(struct device *dev)
605{
606 struct cdns3 *cdns = dev_get_drvdata(dev);
607 unsigned long flags;
608
609 if (cdns->role == USB_ROLE_HOST)
610 return 0;
611
612 if (cdns->roles[cdns->role]->resume) {
613 spin_lock_irqsave(&cdns->gadget_dev->lock, flags);
614 cdns->roles[cdns->role]->resume(cdns, false);
615 spin_unlock_irqrestore(&cdns->gadget_dev->lock, flags);
616 }
617
618 pm_runtime_disable(dev);
619 pm_runtime_set_active(dev);
620 pm_runtime_enable(dev);
621
622 return 0;
623}
624#endif
625
626static const struct dev_pm_ops cdns3_pm_ops = {
627 SET_SYSTEM_SLEEP_PM_OPS(cdns3_suspend, cdns3_resume)
628};
629
630#ifdef CONFIG_OF
631static const struct of_device_id of_cdns3_match[] = {
632 { .compatible = "cdns,usb3" },
633 { },
634};
635MODULE_DEVICE_TABLE(of, of_cdns3_match);
636#endif
637
638static struct platform_driver cdns3_driver = {
639 .probe = cdns3_probe,
640 .remove = cdns3_remove,
641 .driver = {
642 .name = "cdns-usb3",
643 .of_match_table = of_match_ptr(of_cdns3_match),
644 .pm = &cdns3_pm_ops,
645 },
646};
647
648module_platform_driver(cdns3_driver);
649
650MODULE_ALIAS("platform:cdns3");
651MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>");
652MODULE_LICENSE("GPL v2");
653MODULE_DESCRIPTION("Cadence USB3 DRD Controller Driver");
diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
new file mode 100644
index 000000000000..969eb94de204
--- /dev/null
+++ b/drivers/usb/cdns3/core.h
@@ -0,0 +1,98 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Header File.
4 *
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 * Pawel Laszczak <pawell@cadence.com>
10 */
11#include <linux/usb/otg.h>
12#include <linux/usb/role.h>
13
14#ifndef __LINUX_CDNS3_CORE_H
15#define __LINUX_CDNS3_CORE_H
16
17struct cdns3;
18
19/**
20 * struct cdns3_role_driver - host/gadget role driver
21 * @start: start this role
22 * @stop: stop this role
23 * @suspend: suspend callback for this role
24 * @resume: resume callback for this role
25 * @irq: irq handler for this role
26 * @name: role name string (host/gadget)
27 * @state: current state
28 */
29struct cdns3_role_driver {
30 int (*start)(struct cdns3 *cdns);
31 void (*stop)(struct cdns3 *cdns);
32 int (*suspend)(struct cdns3 *cdns, bool do_wakeup);
33 int (*resume)(struct cdns3 *cdns, bool hibernated);
34 const char *name;
35#define CDNS3_ROLE_STATE_INACTIVE 0
36#define CDNS3_ROLE_STATE_ACTIVE 1
37 int state;
38};
39
40#define CDNS3_XHCI_RESOURCES_NUM 2
41/**
42 * struct cdns3 - Representation of Cadence USB3 DRD controller.
43 * @dev: pointer to Cadence device struct
44 * @xhci_regs: pointer to base of xhci registers
45 * @xhci_res: the resource for xhci
46 * @dev_regs: pointer to base of dev registers
47 * @otg_res: the resource for otg
48 * @otg_v0_regs: pointer to base of v0 otg registers
49 * @otg_v1_regs: pointer to base of v1 otg registers
50 * @otg_regs: pointer to base of otg registers
51 * @otg_irq: irq number for otg controller
52 * @dev_irq: irq number for device controller
53 * @roles: array of supported roles for this controller
54 * @role: current role
55 * @host_dev: the child host device pointer for cdns3 core
56 * @gadget_dev: the child gadget device pointer for cdns3 core
57 * @usb2_phy: pointer to USB2 PHY
58 * @usb3_phy: pointer to USB3 PHY
59 * @mutex: the mutex for concurrent code at driver
60 * @dr_mode: supported mode of operation it can be only Host, only Device
61 * or OTG mode that allow to switch between Device and Host mode.
62 * This field based on firmware setting, kernel configuration
63 * and hardware configuration.
64 * @role_sw: pointer to role switch object.
65 * @role_override: set 1 if role rely on SW.
66 */
67struct cdns3 {
68 struct device *dev;
69 void __iomem *xhci_regs;
70 struct resource xhci_res[CDNS3_XHCI_RESOURCES_NUM];
71 struct cdns3_usb_regs __iomem *dev_regs;
72
73 struct resource otg_res;
74 struct cdns3_otg_legacy_regs *otg_v0_regs;
75 struct cdns3_otg_regs *otg_v1_regs;
76 struct cdns3_otg_common_regs *otg_regs;
77#define CDNS3_CONTROLLER_V0 0
78#define CDNS3_CONTROLLER_V1 1
79 u32 version;
80
81 int otg_irq;
82 int dev_irq;
83 struct cdns3_role_driver *roles[USB_ROLE_DEVICE + 1];
84 enum usb_role role;
85 struct platform_device *host_dev;
86 struct cdns3_device *gadget_dev;
87 struct phy *usb2_phy;
88 struct phy *usb3_phy;
89 /* mutext used in workqueue*/
90 struct mutex mutex;
91 enum usb_dr_mode dr_mode;
92 struct usb_role_switch *role_sw;
93 int role_override;
94};
95
96int cdns3_hw_role_switch(struct cdns3 *cdns);
97
98#endif /* __LINUX_CDNS3_CORE_H */
diff --git a/drivers/usb/cdns3/debug.h b/drivers/usb/cdns3/debug.h
new file mode 100644
index 000000000000..2c9afbfe988b
--- /dev/null
+++ b/drivers/usb/cdns3/debug.h
@@ -0,0 +1,161 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver.
4 * Debug header file.
5 *
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 */
10#ifndef __LINUX_CDNS3_DEBUG
11#define __LINUX_CDNS3_DEBUG
12
13#include "core.h"
14
15static inline char *cdns3_decode_usb_irq(char *str,
16 enum usb_device_speed speed,
17 u32 usb_ists)
18{
19 int ret;
20
21 ret = sprintf(str, "IRQ %08x = ", usb_ists);
22
23 if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
24 ret += sprintf(str + ret, "Connection %s\n",
25 usb_speed_string(speed));
26 }
27 if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI)
28 ret += sprintf(str + ret, "Disconnection ");
29 if (usb_ists & USB_ISTS_L2ENTI)
30 ret += sprintf(str + ret, "suspended ");
31 if (usb_ists & USB_ISTS_L1ENTI)
32 ret += sprintf(str + ret, "L1 enter ");
33 if (usb_ists & USB_ISTS_L1EXTI)
34 ret += sprintf(str + ret, "L1 exit ");
35 if (usb_ists & USB_ISTS_L2ENTI)
36 ret += sprintf(str + ret, "L2 enter ");
37 if (usb_ists & USB_ISTS_L2EXTI)
38 ret += sprintf(str + ret, "L2 exit ");
39 if (usb_ists & USB_ISTS_U3EXTI)
40 ret += sprintf(str + ret, "U3 exit ");
41 if (usb_ists & USB_ISTS_UWRESI)
42 ret += sprintf(str + ret, "Warm Reset ");
43 if (usb_ists & USB_ISTS_UHRESI)
44 ret += sprintf(str + ret, "Hot Reset ");
45 if (usb_ists & USB_ISTS_U2RESI)
46 ret += sprintf(str + ret, "Reset");
47
48 return str;
49}
50
51static inline char *cdns3_decode_ep_irq(char *str,
52 u32 ep_sts,
53 const char *ep_name)
54{
55 int ret;
56
57 ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts);
58
59 if (ep_sts & EP_STS_SETUP)
60 ret += sprintf(str + ret, "SETUP ");
61 if (ep_sts & EP_STS_IOC)
62 ret += sprintf(str + ret, "IOC ");
63 if (ep_sts & EP_STS_ISP)
64 ret += sprintf(str + ret, "ISP ");
65 if (ep_sts & EP_STS_DESCMIS)
66 ret += sprintf(str + ret, "DESCMIS ");
67 if (ep_sts & EP_STS_STREAMR)
68 ret += sprintf(str + ret, "STREAMR ");
69 if (ep_sts & EP_STS_MD_EXIT)
70 ret += sprintf(str + ret, "MD_EXIT ");
71 if (ep_sts & EP_STS_TRBERR)
72 ret += sprintf(str + ret, "TRBERR ");
73 if (ep_sts & EP_STS_NRDY)
74 ret += sprintf(str + ret, "NRDY ");
75 if (ep_sts & EP_STS_PRIME)
76 ret += sprintf(str + ret, "PRIME ");
77 if (ep_sts & EP_STS_SIDERR)
78 ret += sprintf(str + ret, "SIDERRT ");
79 if (ep_sts & EP_STS_OUTSMM)
80 ret += sprintf(str + ret, "OUTSMM ");
81 if (ep_sts & EP_STS_ISOERR)
82 ret += sprintf(str + ret, "ISOERR ");
83 if (ep_sts & EP_STS_IOT)
84 ret += sprintf(str + ret, "IOT ");
85
86 return str;
87}
88
89static inline char *cdns3_decode_epx_irq(char *str,
90 char *ep_name,
91 u32 ep_sts)
92{
93 return cdns3_decode_ep_irq(str, ep_sts, ep_name);
94}
95
96static inline char *cdns3_decode_ep0_irq(char *str,
97 int dir,
98 u32 ep_sts)
99{
100 return cdns3_decode_ep_irq(str, ep_sts,
101 dir ? "ep0IN" : "ep0OUT");
102}
103
104/**
105 * Debug a transfer ring.
106 *
107 * Prints out all TRBs in the endpoint ring, even those after the Link TRB.
108 *.
109 */
110static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep,
111 struct cdns3_trb *ring, char *str)
112{
113 dma_addr_t addr = priv_ep->trb_pool_dma;
114 struct cdns3_trb *trb;
115 int trb_per_sector;
116 int ret = 0;
117 int i;
118
119 trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type);
120
121 trb = &priv_ep->trb_pool[priv_ep->dequeue];
122 ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name);
123
124 ret += sprintf(str + ret,
125 "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n",
126 priv_ep->dequeue, trb,
127 (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
128
129 trb = &priv_ep->trb_pool[priv_ep->enqueue];
130 ret += sprintf(str + ret,
131 "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n",
132 priv_ep->enqueue, trb,
133 (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
134
135 ret += sprintf(str + ret,
136 "\t\tfree trbs: %d, CCS=%d, PCS=%d\n",
137 priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs);
138
139 if (trb_per_sector > TRBS_PER_SEGMENT)
140 trb_per_sector = TRBS_PER_SEGMENT;
141
142 if (trb_per_sector > TRBS_PER_SEGMENT) {
143 sprintf(str + ret, "\t\tTo big transfer ring %d\n",
144 trb_per_sector);
145 return str;
146 }
147
148 for (i = 0; i < trb_per_sector; ++i) {
149 trb = &ring[i];
150 ret += sprintf(str + ret,
151 "\t\t@%pad %08x %08x %08x\n", &addr,
152 le32_to_cpu(trb->buffer),
153 le32_to_cpu(trb->length),
154 le32_to_cpu(trb->control));
155 addr += sizeof(*trb);
156 }
157
158 return str;
159}
160
161#endif /*__LINUX_CDNS3_DEBUG*/
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
new file mode 100644
index 000000000000..16ad485f0b69
--- /dev/null
+++ b/drivers/usb/cdns3/drd.c
@@ -0,0 +1,381 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2019 Texas Instruments
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 * Roger Quadros <rogerq@ti.com>
10 *
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/delay.h>
16#include <linux/iopoll.h>
17#include <linux/usb/otg.h>
18
19#include "gadget.h"
20#include "drd.h"
21#include "core.h"
22
23/**
24 * cdns3_set_mode - change mode of OTG Core
25 * @cdns: pointer to context structure
26 * @mode: selected mode from cdns_role
27 *
28 * Returns 0 on success otherwise negative errno
29 */
30int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode)
31{
32 int ret = 0;
33 u32 reg;
34
35 switch (mode) {
36 case USB_DR_MODE_PERIPHERAL:
37 break;
38 case USB_DR_MODE_HOST:
39 break;
40 case USB_DR_MODE_OTG:
41 dev_dbg(cdns->dev, "Set controller to OTG mode\n");
42 if (cdns->version == CDNS3_CONTROLLER_V1) {
43 reg = readl(&cdns->otg_v1_regs->override);
44 reg |= OVERRIDE_IDPULLUP;
45 writel(reg, &cdns->otg_v1_regs->override);
46 } else {
47 reg = readl(&cdns->otg_v0_regs->ctrl1);
48 reg |= OVERRIDE_IDPULLUP_V0;
49 writel(reg, &cdns->otg_v0_regs->ctrl1);
50 }
51
52 /*
53 * Hardware specification says: "ID_VALUE must be valid within
54 * 50ms after idpullup is set to '1" so driver must wait
55 * 50ms before reading this pin.
56 */
57 usleep_range(50000, 60000);
58 break;
59 default:
60 dev_err(cdns->dev, "Unsupported mode of operation %d\n", mode);
61 return -EINVAL;
62 }
63
64 return ret;
65}
66
67int cdns3_get_id(struct cdns3 *cdns)
68{
69 int id;
70
71 id = readl(&cdns->otg_regs->sts) & OTGSTS_ID_VALUE;
72 dev_dbg(cdns->dev, "OTG ID: %d", id);
73
74 return id;
75}
76
77int cdns3_get_vbus(struct cdns3 *cdns)
78{
79 int vbus;
80
81 vbus = !!(readl(&cdns->otg_regs->sts) & OTGSTS_VBUS_VALID);
82 dev_dbg(cdns->dev, "OTG VBUS: %d", vbus);
83
84 return vbus;
85}
86
87int cdns3_is_host(struct cdns3 *cdns)
88{
89 if (cdns->dr_mode == USB_DR_MODE_HOST)
90 return 1;
91 else if (!cdns3_get_id(cdns))
92 return 1;
93
94 return 0;
95}
96
97int cdns3_is_device(struct cdns3 *cdns)
98{
99 if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL)
100 return 1;
101 else if (cdns->dr_mode == USB_DR_MODE_OTG)
102 if (cdns3_get_id(cdns))
103 return 1;
104
105 return 0;
106}
107
108/**
109 * cdns3_otg_disable_irq - Disable all OTG interrupts
110 * @cdns: Pointer to controller context structure
111 */
112static void cdns3_otg_disable_irq(struct cdns3 *cdns)
113{
114 writel(0, &cdns->otg_regs->ien);
115}
116
117/**
118 * cdns3_otg_enable_irq - enable id and sess_valid interrupts
119 * @cdns: Pointer to controller context structure
120 */
121static void cdns3_otg_enable_irq(struct cdns3 *cdns)
122{
123 writel(OTGIEN_ID_CHANGE_INT | OTGIEN_VBUSVALID_RISE_INT |
124 OTGIEN_VBUSVALID_FALL_INT, &cdns->otg_regs->ien);
125}
126
127/**
128 * cdns3_drd_switch_host - start/stop host
129 * @cdns: Pointer to controller context structure
130 * @on: 1 for start, 0 for stop
131 *
132 * Returns 0 on success otherwise negative errno
133 */
134int cdns3_drd_switch_host(struct cdns3 *cdns, int on)
135{
136 int ret, val;
137 u32 reg = OTGCMD_OTG_DIS;
138
139 /* switch OTG core */
140 if (on) {
141 writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd);
142
143 dev_dbg(cdns->dev, "Waiting till Host mode is turned on\n");
144 ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
145 val & OTGSTS_XHCI_READY,
146 1, 100000);
147 if (ret) {
148 dev_err(cdns->dev, "timeout waiting for xhci_ready\n");
149 return ret;
150 }
151 } else {
152 writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
153 OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
154 &cdns->otg_regs->cmd);
155 /* Waiting till H_IDLE state.*/
156 readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
157 !(val & OTGSTATE_HOST_STATE_MASK),
158 1, 2000000);
159 }
160
161 return 0;
162}
163
164/**
165 * cdns3_drd_switch_gadget - start/stop gadget
166 * @cdns: Pointer to controller context structure
167 * @on: 1 for start, 0 for stop
168 *
169 * Returns 0 on success otherwise negative errno
170 */
171int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on)
172{
173 int ret, val;
174 u32 reg = OTGCMD_OTG_DIS;
175
176 /* switch OTG core */
177 if (on) {
178 writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd);
179
180 dev_dbg(cdns->dev, "Waiting till Device mode is turned on\n");
181
182 ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
183 val & OTGSTS_DEV_READY,
184 1, 100000);
185 if (ret) {
186 dev_err(cdns->dev, "timeout waiting for dev_ready\n");
187 return ret;
188 }
189 } else {
190 /*
191 * driver should wait at least 10us after disabling Device
192 * before turning-off Device (DEV_BUS_DROP)
193 */
194 usleep_range(20, 30);
195 writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
196 OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
197 &cdns->otg_regs->cmd);
198 /* Waiting till DEV_IDLE state.*/
199 readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
200 !(val & OTGSTATE_DEV_STATE_MASK),
201 1, 2000000);
202 }
203
204 return 0;
205}
206
207/**
208 * cdns3_init_otg_mode - initialize drd controller
209 * @cdns: Pointer to controller context structure
210 *
211 * Returns 0 on success otherwise negative errno
212 */
213static int cdns3_init_otg_mode(struct cdns3 *cdns)
214{
215 int ret = 0;
216
217 cdns3_otg_disable_irq(cdns);
218 /* clear all interrupts */
219 writel(~0, &cdns->otg_regs->ivect);
220
221 ret = cdns3_set_mode(cdns, USB_DR_MODE_OTG);
222 if (ret)
223 return ret;
224
225 cdns3_otg_enable_irq(cdns);
226 return ret;
227}
228
229/**
230 * cdns3_drd_update_mode - initialize mode of operation
231 * @cdns: Pointer to controller context structure
232 *
233 * Returns 0 on success otherwise negative errno
234 */
235int cdns3_drd_update_mode(struct cdns3 *cdns)
236{
237 int ret = 0;
238
239 switch (cdns->dr_mode) {
240 case USB_DR_MODE_PERIPHERAL:
241 ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
242 break;
243 case USB_DR_MODE_HOST:
244 ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
245 break;
246 case USB_DR_MODE_OTG:
247 ret = cdns3_init_otg_mode(cdns);
248 break;
249 default:
250 dev_err(cdns->dev, "Unsupported mode of operation %d\n",
251 cdns->dr_mode);
252 return -EINVAL;
253 }
254
255 return ret;
256}
257
258static irqreturn_t cdns3_drd_thread_irq(int irq, void *data)
259{
260 struct cdns3 *cdns = data;
261
262 cdns3_hw_role_switch(cdns);
263
264 return IRQ_HANDLED;
265}
266
267/**
268 * cdns3_drd_irq - interrupt handler for OTG events
269 *
270 * @irq: irq number for cdns3 core device
271 * @data: structure of cdns3
272 *
273 * Returns IRQ_HANDLED or IRQ_NONE
274 */
275static irqreturn_t cdns3_drd_irq(int irq, void *data)
276{
277 irqreturn_t ret = IRQ_NONE;
278 struct cdns3 *cdns = data;
279 u32 reg;
280
281 if (cdns->dr_mode != USB_DR_MODE_OTG)
282 return ret;
283
284 reg = readl(&cdns->otg_regs->ivect);
285
286 if (!reg)
287 return ret;
288
289 if (reg & OTGIEN_ID_CHANGE_INT) {
290 dev_dbg(cdns->dev, "OTG IRQ: new ID: %d\n",
291 cdns3_get_id(cdns));
292
293 ret = IRQ_WAKE_THREAD;
294 }
295
296 if (reg & (OTGIEN_VBUSVALID_RISE_INT | OTGIEN_VBUSVALID_FALL_INT)) {
297 dev_dbg(cdns->dev, "OTG IRQ: new VBUS: %d\n",
298 cdns3_get_vbus(cdns));
299
300 ret = IRQ_WAKE_THREAD;
301 }
302
303 writel(~0, &cdns->otg_regs->ivect);
304 return ret;
305}
306
307int cdns3_drd_init(struct cdns3 *cdns)
308{
309 void __iomem *regs;
310 int ret = 0;
311 u32 state;
312
313 regs = devm_ioremap_resource(cdns->dev, &cdns->otg_res);
314 if (IS_ERR(regs))
315 return PTR_ERR(regs);
316
317 /* Detection of DRD version. Controller has been released
318 * in two versions. Both are similar, but they have same changes
319 * in register maps.
320 * The first register in old version is command register and it's read
321 * only, so driver should read 0 from it. On the other hand, in v1
322 * the first register contains device ID number which is not set to 0.
323 * Driver uses this fact to detect the proper version of
324 * controller.
325 */
326 cdns->otg_v0_regs = regs;
327 if (!readl(&cdns->otg_v0_regs->cmd)) {
328 cdns->version = CDNS3_CONTROLLER_V0;
329 cdns->otg_v1_regs = NULL;
330 cdns->otg_regs = regs;
331 writel(1, &cdns->otg_v0_regs->simulate);
332 dev_info(cdns->dev, "DRD version v0 (%08x)\n",
333 readl(&cdns->otg_v0_regs->version));
334 } else {
335 cdns->otg_v0_regs = NULL;
336 cdns->otg_v1_regs = regs;
337 cdns->otg_regs = (void *)&cdns->otg_v1_regs->cmd;
338 cdns->version = CDNS3_CONTROLLER_V1;
339 writel(1, &cdns->otg_v1_regs->simulate);
340 dev_info(cdns->dev, "DRD version v1 (ID: %08x, rev: %08x)\n",
341 readl(&cdns->otg_v1_regs->did),
342 readl(&cdns->otg_v1_regs->rid));
343 }
344
345 state = OTGSTS_STRAP(readl(&cdns->otg_regs->sts));
346
347 /* Update dr_mode according to STRAP configuration. */
348 cdns->dr_mode = USB_DR_MODE_OTG;
349 if (state == OTGSTS_STRAP_HOST) {
350 dev_dbg(cdns->dev, "Controller strapped to HOST\n");
351 cdns->dr_mode = USB_DR_MODE_HOST;
352 } else if (state == OTGSTS_STRAP_GADGET) {
353 dev_dbg(cdns->dev, "Controller strapped to PERIPHERAL\n");
354 cdns->dr_mode = USB_DR_MODE_PERIPHERAL;
355 }
356
357 ret = devm_request_threaded_irq(cdns->dev, cdns->otg_irq,
358 cdns3_drd_irq,
359 cdns3_drd_thread_irq,
360 IRQF_SHARED,
361 dev_name(cdns->dev), cdns);
362
363 if (ret) {
364 dev_err(cdns->dev, "couldn't get otg_irq\n");
365 return ret;
366 }
367
368 state = readl(&cdns->otg_regs->sts);
369 if (OTGSTS_OTG_NRDY(state) != 0) {
370 dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n");
371 return -ENODEV;
372 }
373
374 return ret;
375}
376
377int cdns3_drd_exit(struct cdns3 *cdns)
378{
379 cdns3_otg_disable_irq(cdns);
380 return 0;
381}
diff --git a/drivers/usb/cdns3/drd.h b/drivers/usb/cdns3/drd.h
new file mode 100644
index 000000000000..04e01c4d2377
--- /dev/null
+++ b/drivers/usb/cdns3/drd.h
@@ -0,0 +1,167 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USB3 DRD header file.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9#ifndef __LINUX_CDNS3_DRD
10#define __LINUX_CDNS3_DRD
11
12#include <linux/usb/otg.h>
13#include <linux/phy/phy.h>
14#include "core.h"
15
16/* DRD register interface for version v1. */
17struct cdns3_otg_regs {
18 __le32 did;
19 __le32 rid;
20 __le32 capabilities;
21 __le32 reserved1;
22 __le32 cmd;
23 __le32 sts;
24 __le32 state;
25 __le32 reserved2;
26 __le32 ien;
27 __le32 ivect;
28 __le32 refclk;
29 __le32 tmr;
30 __le32 reserved3[4];
31 __le32 simulate;
32 __le32 override;
33 __le32 susp_ctrl;
34 __le32 reserved4;
35 __le32 anasts;
36 __le32 adp_ramp_time;
37 __le32 ctrl1;
38 __le32 ctrl2;
39};
40
41/* DRD register interface for version v0. */
42struct cdns3_otg_legacy_regs {
43 __le32 cmd;
44 __le32 sts;
45 __le32 state;
46 __le32 refclk;
47 __le32 ien;
48 __le32 ivect;
49 __le32 reserved1[3];
50 __le32 tmr;
51 __le32 reserved2[2];
52 __le32 version;
53 __le32 capabilities;
54 __le32 reserved3[2];
55 __le32 simulate;
56 __le32 reserved4[5];
57 __le32 ctrl1;
58};
59
60/*
61 * Common registers interface for both version of DRD.
62 */
63struct cdns3_otg_common_regs {
64 __le32 cmd;
65 __le32 sts;
66 __le32 state;
67 __le32 different1;
68 __le32 ien;
69 __le32 ivect;
70};
71
72/* CDNS_RID - bitmasks */
73#define CDNS_RID(p) ((p) & GENMASK(15, 0))
74
75/* CDNS_VID - bitmasks */
76#define CDNS_DID(p) ((p) & GENMASK(31, 0))
77
78/* OTGCMD - bitmasks */
79/* "Request the bus for Device mode. */
80#define OTGCMD_DEV_BUS_REQ BIT(0)
81/* Request the bus for Host mode */
82#define OTGCMD_HOST_BUS_REQ BIT(1)
83/* Enable OTG mode. */
84#define OTGCMD_OTG_EN BIT(2)
85/* Disable OTG mode */
86#define OTGCMD_OTG_DIS BIT(3)
87/*"Configure OTG as A-Device. */
88#define OTGCMD_A_DEV_EN BIT(4)
89/*"Configure OTG as A-Device. */
90#define OTGCMD_A_DEV_DIS BIT(5)
91/* Drop the bus for Device mod e. */
92#define OTGCMD_DEV_BUS_DROP BIT(8)
93/* Drop the bus for Host mode*/
94#define OTGCMD_HOST_BUS_DROP BIT(9)
95/* Power Down USBSS-DEV. */
96#define OTGCMD_DEV_POWER_OFF BIT(11)
97/* Power Down CDNSXHCI. */
98#define OTGCMD_HOST_POWER_OFF BIT(12)
99
100/* OTGIEN - bitmasks */
101/* ID change interrupt enable */
102#define OTGIEN_ID_CHANGE_INT BIT(0)
103/* Vbusvalid fall detected interrupt enable.*/
104#define OTGIEN_VBUSVALID_RISE_INT BIT(4)
105/* Vbusvalid fall detected interrupt enable */
106#define OTGIEN_VBUSVALID_FALL_INT BIT(5)
107
108/* OTGSTS - bitmasks */
109/*
110 * Current value of the ID pin. It is only valid when idpullup in
111 * OTGCTRL1_TYPE register is set to '1'.
112 */
113#define OTGSTS_ID_VALUE BIT(0)
114/* Current value of the vbus_valid */
115#define OTGSTS_VBUS_VALID BIT(1)
116/* Current value of the b_sess_vld */
117#define OTGSTS_SESSION_VALID BIT(2)
118/*Device mode is active*/
119#define OTGSTS_DEV_ACTIVE BIT(3)
120/* Host mode is active. */
121#define OTGSTS_HOST_ACTIVE BIT(4)
122/* OTG Controller not ready. */
123#define OTGSTS_OTG_NRDY_MASK BIT(11)
124#define OTGSTS_OTG_NRDY(p) ((p) & OTGSTS_OTG_NRDY_MASK)
125/*
126 * Value of the strap pins.
127 * 000 - no default configuration
128 * 010 - Controller initiall configured as Host
129 * 100 - Controller initially configured as Device
130 */
131#define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12)
132#define OTGSTS_STRAP_NO_DEFAULT_CFG 0x00
133#define OTGSTS_STRAP_HOST_OTG 0x01
134#define OTGSTS_STRAP_HOST 0x02
135#define OTGSTS_STRAP_GADGET 0x04
136/* Host mode is turned on. */
137#define OTGSTS_XHCI_READY BIT(26)
138/* "Device mode is turned on .*/
139#define OTGSTS_DEV_READY BIT(27)
140
141/* OTGSTATE- bitmasks */
142#define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0)
143#define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3)
144#define OTGSTATE_HOST_STATE_IDLE 0x0
145#define OTGSTATE_HOST_STATE_VBUS_FALL 0x7
146#define OTGSTATE_HOST_STATE(p) (((p) & OTGSTATE_HOST_STATE_MASK) >> 3)
147
148/* OTGREFCLK - bitmasks */
149#define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31)
150
151/* OVERRIDE - bitmasks */
152#define OVERRIDE_IDPULLUP BIT(0)
153/* Only for CDNS3_CONTROLLER_V0 version */
154#define OVERRIDE_IDPULLUP_V0 BIT(24)
155
156int cdns3_is_host(struct cdns3 *cdns);
157int cdns3_is_device(struct cdns3 *cdns);
158int cdns3_get_id(struct cdns3 *cdns);
159int cdns3_get_vbus(struct cdns3 *cdns);
160int cdns3_drd_init(struct cdns3 *cdns);
161int cdns3_drd_exit(struct cdns3 *cdns);
162int cdns3_drd_update_mode(struct cdns3 *cdns);
163int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on);
164int cdns3_drd_switch_host(struct cdns3 *cdns, int on);
165int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode);
166
167#endif /* __LINUX_CDNS3_DRD */
diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
new file mode 100644
index 000000000000..e94f55d4729c
--- /dev/null
+++ b/drivers/usb/cdns3/ep0.c
@@ -0,0 +1,888 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - gadget side.
4 *
5 * Copyright (C) 2018 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Pawel Jez <pjez@cadence.com>,
9 * Pawel Laszczak <pawell@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12
13#include <linux/usb/composite.h>
14#include <linux/iopoll.h>
15
16#include "gadget.h"
17#include "trace.h"
18
19static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = {
20 .bLength = USB_DT_ENDPOINT_SIZE,
21 .bDescriptorType = USB_DT_ENDPOINT,
22 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
23};
24
25/**
26 * cdns3_ep0_run_transfer - Do transfer on default endpoint hardware
27 * @priv_dev: extended gadget object
28 * @dma_addr: physical address where data is/will be stored
29 * @length: data length
30 * @erdy: set it to 1 when ERDY packet should be sent -
31 * exit from flow control state
32 */
33static void cdns3_ep0_run_transfer(struct cdns3_device *priv_dev,
34 dma_addr_t dma_addr,
35 unsigned int length, int erdy, int zlp)
36{
37 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
38 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
39
40 priv_ep->trb_pool[0].buffer = TRB_BUFFER(dma_addr);
41 priv_ep->trb_pool[0].length = TRB_LEN(length);
42
43 if (zlp) {
44 priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_TYPE(TRB_NORMAL);
45 priv_ep->trb_pool[1].buffer = TRB_BUFFER(dma_addr);
46 priv_ep->trb_pool[1].length = TRB_LEN(0);
47 priv_ep->trb_pool[1].control = TRB_CYCLE | TRB_IOC |
48 TRB_TYPE(TRB_NORMAL);
49 } else {
50 priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_IOC |
51 TRB_TYPE(TRB_NORMAL);
52 priv_ep->trb_pool[1].control = 0;
53 }
54
55 trace_cdns3_prepare_trb(priv_ep, priv_ep->trb_pool);
56
57 cdns3_select_ep(priv_dev, priv_dev->ep0_data_dir);
58
59 writel(EP_STS_TRBERR, &regs->ep_sts);
60 writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), &regs->ep_traddr);
61 trace_cdns3_doorbell_ep0(priv_dev->ep0_data_dir ? "ep0in" : "ep0out",
62 readl(&regs->ep_traddr));
63
64 /* TRB should be prepared before starting transfer. */
65 writel(EP_CMD_DRDY, &regs->ep_cmd);
66
67 /* Resume controller before arming transfer. */
68 __cdns3_gadget_wakeup(priv_dev);
69
70 if (erdy)
71 writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd);
72}
73
74/**
75 * cdns3_ep0_delegate_req - Returns status of handling setup packet
76 * Setup is handled by gadget driver
77 * @priv_dev: extended gadget object
78 * @ctrl_req: pointer to received setup packet
79 *
80 * Returns zero on success or negative value on failure
81 */
82static int cdns3_ep0_delegate_req(struct cdns3_device *priv_dev,
83 struct usb_ctrlrequest *ctrl_req)
84{
85 int ret;
86
87 spin_unlock(&priv_dev->lock);
88 priv_dev->setup_pending = 1;
89 ret = priv_dev->gadget_driver->setup(&priv_dev->gadget, ctrl_req);
90 priv_dev->setup_pending = 0;
91 spin_lock(&priv_dev->lock);
92 return ret;
93}
94
95static void cdns3_prepare_setup_packet(struct cdns3_device *priv_dev)
96{
97 priv_dev->ep0_data_dir = 0;
98 priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
99 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
100 sizeof(struct usb_ctrlrequest), 0, 0);
101}
102
103static void cdns3_ep0_complete_setup(struct cdns3_device *priv_dev,
104 u8 send_stall, u8 send_erdy)
105{
106 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
107 struct usb_request *request;
108
109 request = cdns3_next_request(&priv_ep->pending_req_list);
110 if (request)
111 list_del_init(&request->list);
112
113 if (send_stall) {
114 trace_cdns3_halt(priv_ep, send_stall, 0);
115 /* set_stall on ep0 */
116 cdns3_select_ep(priv_dev, 0x00);
117 writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd);
118 } else {
119 cdns3_prepare_setup_packet(priv_dev);
120 }
121
122 priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
123 writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL,
124 &priv_dev->regs->ep_cmd);
125
126 cdns3_allow_enable_l1(priv_dev, 1);
127}
128
129/**
130 * cdns3_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request
131 * @priv_dev: extended gadget object
132 * @ctrl_req: pointer to received setup packet
133 *
134 * Returns 0 if success, USB_GADGET_DELAYED_STATUS on deferred status stage,
135 * error code on error
136 */
137static int cdns3_req_ep0_set_configuration(struct cdns3_device *priv_dev,
138 struct usb_ctrlrequest *ctrl_req)
139{
140 enum usb_device_state device_state = priv_dev->gadget.state;
141 struct cdns3_endpoint *priv_ep;
142 u32 config = le16_to_cpu(ctrl_req->wValue);
143 int result = 0;
144 int i;
145
146 switch (device_state) {
147 case USB_STATE_ADDRESS:
148 /* Configure non-control EPs */
149 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
150 priv_ep = priv_dev->eps[i];
151 if (!priv_ep)
152 continue;
153
154 if (priv_ep->flags & EP_CLAIMED)
155 cdns3_ep_config(priv_ep);
156 }
157
158 result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
159
160 if (result)
161 return result;
162
163 if (config) {
164 cdns3_set_hw_configuration(priv_dev);
165 } else {
166 cdns3_hw_reset_eps_config(priv_dev);
167 usb_gadget_set_state(&priv_dev->gadget,
168 USB_STATE_ADDRESS);
169 }
170 break;
171 case USB_STATE_CONFIGURED:
172 result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
173
174 if (!config && !result) {
175 cdns3_hw_reset_eps_config(priv_dev);
176 usb_gadget_set_state(&priv_dev->gadget,
177 USB_STATE_ADDRESS);
178 }
179 break;
180 default:
181 result = -EINVAL;
182 }
183
184 return result;
185}
186
187/**
188 * cdns3_req_ep0_set_address - Handling of SET_ADDRESS standard USB request
189 * @priv_dev: extended gadget object
190 * @ctrl_req: pointer to received setup packet
191 *
192 * Returns 0 if success, error code on error
193 */
194static int cdns3_req_ep0_set_address(struct cdns3_device *priv_dev,
195 struct usb_ctrlrequest *ctrl_req)
196{
197 enum usb_device_state device_state = priv_dev->gadget.state;
198 u32 reg;
199 u32 addr;
200
201 addr = le16_to_cpu(ctrl_req->wValue);
202
203 if (addr > USB_DEVICE_MAX_ADDRESS) {
204 dev_err(priv_dev->dev,
205 "Device address (%d) cannot be greater than %d\n",
206 addr, USB_DEVICE_MAX_ADDRESS);
207 return -EINVAL;
208 }
209
210 if (device_state == USB_STATE_CONFIGURED) {
211 dev_err(priv_dev->dev,
212 "can't set_address from configured state\n");
213 return -EINVAL;
214 }
215
216 reg = readl(&priv_dev->regs->usb_cmd);
217
218 writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR,
219 &priv_dev->regs->usb_cmd);
220
221 usb_gadget_set_state(&priv_dev->gadget,
222 (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT));
223
224 return 0;
225}
226
227/**
228 * cdns3_req_ep0_get_status - Handling of GET_STATUS standard USB request
229 * @priv_dev: extended gadget object
230 * @ctrl_req: pointer to received setup packet
231 *
232 * Returns 0 if success, error code on error
233 */
234static int cdns3_req_ep0_get_status(struct cdns3_device *priv_dev,
235 struct usb_ctrlrequest *ctrl)
236{
237 __le16 *response_pkt;
238 u16 usb_status = 0;
239 u32 recip;
240
241 recip = ctrl->bRequestType & USB_RECIP_MASK;
242
243 switch (recip) {
244 case USB_RECIP_DEVICE:
245 /* self powered */
246 if (priv_dev->is_selfpowered)
247 usb_status = BIT(USB_DEVICE_SELF_POWERED);
248
249 if (priv_dev->wake_up_flag)
250 usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP);
251
252 if (priv_dev->gadget.speed != USB_SPEED_SUPER)
253 break;
254
255 if (priv_dev->u1_allowed)
256 usb_status |= BIT(USB_DEV_STAT_U1_ENABLED);
257
258 if (priv_dev->u2_allowed)
259 usb_status |= BIT(USB_DEV_STAT_U2_ENABLED);
260
261 break;
262 case USB_RECIP_INTERFACE:
263 return cdns3_ep0_delegate_req(priv_dev, ctrl);
264 case USB_RECIP_ENDPOINT:
265 /* check if endpoint is stalled */
266 cdns3_select_ep(priv_dev, ctrl->wIndex);
267 if (EP_STS_STALL(readl(&priv_dev->regs->ep_sts)))
268 usb_status = BIT(USB_ENDPOINT_HALT);
269 break;
270 default:
271 return -EINVAL;
272 }
273
274 response_pkt = (__le16 *)priv_dev->setup_buf;
275 *response_pkt = cpu_to_le16(usb_status);
276
277 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
278 sizeof(*response_pkt), 1, 0);
279 return 0;
280}
281
282static int cdns3_ep0_feature_handle_device(struct cdns3_device *priv_dev,
283 struct usb_ctrlrequest *ctrl,
284 int set)
285{
286 enum usb_device_state state;
287 enum usb_device_speed speed;
288 int ret = 0;
289 u32 wValue;
290 u32 wIndex;
291 u16 tmode;
292
293 wValue = le16_to_cpu(ctrl->wValue);
294 wIndex = le16_to_cpu(ctrl->wIndex);
295 state = priv_dev->gadget.state;
296 speed = priv_dev->gadget.speed;
297
298 switch (ctrl->wValue) {
299 case USB_DEVICE_REMOTE_WAKEUP:
300 priv_dev->wake_up_flag = !!set;
301 break;
302 case USB_DEVICE_U1_ENABLE:
303 if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
304 return -EINVAL;
305
306 priv_dev->u1_allowed = !!set;
307 break;
308 case USB_DEVICE_U2_ENABLE:
309 if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
310 return -EINVAL;
311
312 priv_dev->u2_allowed = !!set;
313 break;
314 case USB_DEVICE_LTM_ENABLE:
315 ret = -EINVAL;
316 break;
317 case USB_DEVICE_TEST_MODE:
318 if (state != USB_STATE_CONFIGURED || speed > USB_SPEED_HIGH)
319 return -EINVAL;
320
321 tmode = le16_to_cpu(ctrl->wIndex);
322
323 if (!set || (tmode & 0xff) != 0)
324 return -EINVAL;
325
326 switch (tmode >> 8) {
327 case TEST_J:
328 case TEST_K:
329 case TEST_SE0_NAK:
330 case TEST_PACKET:
331 cdns3_ep0_complete_setup(priv_dev, 0, 1);
332 /**
333 * Little delay to give the controller some time
334 * for sending status stage.
335 * This time should be less then 3ms.
336 */
337 usleep_range(1000, 2000);
338 cdns3_set_register_bit(&priv_dev->regs->usb_cmd,
339 USB_CMD_STMODE |
340 USB_STS_TMODE_SEL(tmode - 1));
341 break;
342 default:
343 ret = -EINVAL;
344 }
345 break;
346 default:
347 ret = -EINVAL;
348 }
349
350 return ret;
351}
352
353static int cdns3_ep0_feature_handle_intf(struct cdns3_device *priv_dev,
354 struct usb_ctrlrequest *ctrl,
355 int set)
356{
357 u32 wValue;
358 int ret = 0;
359
360 wValue = le16_to_cpu(ctrl->wValue);
361
362 switch (wValue) {
363 case USB_INTRF_FUNC_SUSPEND:
364 break;
365 default:
366 ret = -EINVAL;
367 }
368
369 return ret;
370}
371
372static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
373 struct usb_ctrlrequest *ctrl,
374 int set)
375{
376 struct cdns3_endpoint *priv_ep;
377 int ret = 0;
378 u8 index;
379
380 if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT)
381 return -EINVAL;
382
383 if (!(ctrl->wIndex & ~USB_DIR_IN))
384 return 0;
385
386 index = cdns3_ep_addr_to_index(ctrl->wIndex);
387 priv_ep = priv_dev->eps[index];
388
389 cdns3_select_ep(priv_dev, ctrl->wIndex);
390
391 if (set)
392 __cdns3_gadget_ep_set_halt(priv_ep);
393 else if (!(priv_ep->flags & EP_WEDGE))
394 ret = __cdns3_gadget_ep_clear_halt(priv_ep);
395
396 cdns3_select_ep(priv_dev, 0x00);
397
398 return ret;
399}
400
401/**
402 * cdns3_req_ep0_handle_feature -
403 * Handling of GET/SET_FEATURE standard USB request
404 *
405 * @priv_dev: extended gadget object
406 * @ctrl_req: pointer to received setup packet
407 * @set: must be set to 1 for SET_FEATURE request
408 *
409 * Returns 0 if success, error code on error
410 */
411static int cdns3_req_ep0_handle_feature(struct cdns3_device *priv_dev,
412 struct usb_ctrlrequest *ctrl,
413 int set)
414{
415 int ret = 0;
416 u32 recip;
417
418 recip = ctrl->bRequestType & USB_RECIP_MASK;
419
420 switch (recip) {
421 case USB_RECIP_DEVICE:
422 ret = cdns3_ep0_feature_handle_device(priv_dev, ctrl, set);
423 break;
424 case USB_RECIP_INTERFACE:
425 ret = cdns3_ep0_feature_handle_intf(priv_dev, ctrl, set);
426 break;
427 case USB_RECIP_ENDPOINT:
428 ret = cdns3_ep0_feature_handle_endpoint(priv_dev, ctrl, set);
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 return ret;
435}
436
437/**
438 * cdns3_req_ep0_set_sel - Handling of SET_SEL standard USB request
439 * @priv_dev: extended gadget object
440 * @ctrl_req: pointer to received setup packet
441 *
442 * Returns 0 if success, error code on error
443 */
444static int cdns3_req_ep0_set_sel(struct cdns3_device *priv_dev,
445 struct usb_ctrlrequest *ctrl_req)
446{
447 if (priv_dev->gadget.state < USB_STATE_ADDRESS)
448 return -EINVAL;
449
450 if (ctrl_req->wLength != 6) {
451 dev_err(priv_dev->dev, "Set SEL should be 6 bytes, got %d\n",
452 ctrl_req->wLength);
453 return -EINVAL;
454 }
455
456 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 6, 1, 0);
457 return 0;
458}
459
460/**
461 * cdns3_req_ep0_set_isoch_delay -
462 * Handling of GET_ISOCH_DELAY standard USB request
463 * @priv_dev: extended gadget object
464 * @ctrl_req: pointer to received setup packet
465 *
466 * Returns 0 if success, error code on error
467 */
468static int cdns3_req_ep0_set_isoch_delay(struct cdns3_device *priv_dev,
469 struct usb_ctrlrequest *ctrl_req)
470{
471 if (ctrl_req->wIndex || ctrl_req->wLength)
472 return -EINVAL;
473
474 priv_dev->isoch_delay = ctrl_req->wValue;
475
476 return 0;
477}
478
479/**
480 * cdns3_ep0_standard_request - Handling standard USB requests
481 * @priv_dev: extended gadget object
482 * @ctrl_req: pointer to received setup packet
483 *
484 * Returns 0 if success, error code on error
485 */
486static int cdns3_ep0_standard_request(struct cdns3_device *priv_dev,
487 struct usb_ctrlrequest *ctrl_req)
488{
489 int ret;
490
491 switch (ctrl_req->bRequest) {
492 case USB_REQ_SET_ADDRESS:
493 ret = cdns3_req_ep0_set_address(priv_dev, ctrl_req);
494 break;
495 case USB_REQ_SET_CONFIGURATION:
496 ret = cdns3_req_ep0_set_configuration(priv_dev, ctrl_req);
497 break;
498 case USB_REQ_GET_STATUS:
499 ret = cdns3_req_ep0_get_status(priv_dev, ctrl_req);
500 break;
501 case USB_REQ_CLEAR_FEATURE:
502 ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 0);
503 break;
504 case USB_REQ_SET_FEATURE:
505 ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 1);
506 break;
507 case USB_REQ_SET_SEL:
508 ret = cdns3_req_ep0_set_sel(priv_dev, ctrl_req);
509 break;
510 case USB_REQ_SET_ISOCH_DELAY:
511 ret = cdns3_req_ep0_set_isoch_delay(priv_dev, ctrl_req);
512 break;
513 default:
514 ret = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
515 break;
516 }
517
518 return ret;
519}
520
521static void __pending_setup_status_handler(struct cdns3_device *priv_dev)
522{
523 struct usb_request *request = priv_dev->pending_status_request;
524
525 if (priv_dev->status_completion_no_call && request &&
526 request->complete) {
527 request->complete(&priv_dev->eps[0]->endpoint, request);
528 priv_dev->status_completion_no_call = 0;
529 }
530}
531
532void cdns3_pending_setup_status_handler(struct work_struct *work)
533{
534 struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
535 pending_status_wq);
536 unsigned long flags;
537
538 spin_lock_irqsave(&priv_dev->lock, flags);
539 __pending_setup_status_handler(priv_dev);
540 spin_unlock_irqrestore(&priv_dev->lock, flags);
541}
542
543/**
544 * cdns3_ep0_setup_phase - Handling setup USB requests
545 * @priv_dev: extended gadget object
546 */
547static void cdns3_ep0_setup_phase(struct cdns3_device *priv_dev)
548{
549 struct usb_ctrlrequest *ctrl = priv_dev->setup_buf;
550 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
551 int result;
552
553 priv_dev->ep0_data_dir = ctrl->bRequestType & USB_DIR_IN;
554
555 trace_cdns3_ctrl_req(ctrl);
556
557 if (!list_empty(&priv_ep->pending_req_list)) {
558 struct usb_request *request;
559
560 request = cdns3_next_request(&priv_ep->pending_req_list);
561 priv_ep->dir = priv_dev->ep0_data_dir;
562 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
563 -ECONNRESET);
564 }
565
566 if (le16_to_cpu(ctrl->wLength))
567 priv_dev->ep0_stage = CDNS3_DATA_STAGE;
568 else
569 priv_dev->ep0_stage = CDNS3_STATUS_STAGE;
570
571 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
572 result = cdns3_ep0_standard_request(priv_dev, ctrl);
573 else
574 result = cdns3_ep0_delegate_req(priv_dev, ctrl);
575
576 if (result == USB_GADGET_DELAYED_STATUS)
577 return;
578
579 if (result < 0)
580 cdns3_ep0_complete_setup(priv_dev, 1, 1);
581 else if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE)
582 cdns3_ep0_complete_setup(priv_dev, 0, 1);
583}
584
585static void cdns3_transfer_completed(struct cdns3_device *priv_dev)
586{
587 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
588
589 if (!list_empty(&priv_ep->pending_req_list)) {
590 struct usb_request *request;
591
592 trace_cdns3_complete_trb(priv_ep, priv_ep->trb_pool);
593 request = cdns3_next_request(&priv_ep->pending_req_list);
594
595 request->actual =
596 TRB_LEN(le32_to_cpu(priv_ep->trb_pool->length));
597
598 priv_ep->dir = priv_dev->ep0_data_dir;
599 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 0);
600 }
601
602 cdns3_ep0_complete_setup(priv_dev, 0, 0);
603}
604
605/**
606 * cdns3_check_new_setup - Check if controller receive new SETUP packet.
607 * @priv_dev: extended gadget object
608 *
609 * The SETUP packet can be kept in on-chip memory or in system memory.
610 */
611static bool cdns3_check_new_setup(struct cdns3_device *priv_dev)
612{
613 u32 ep_sts_reg;
614
615 cdns3_select_ep(priv_dev, 0 | USB_DIR_OUT);
616 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
617
618 return !!(ep_sts_reg & (EP_STS_SETUP | EP_STS_STPWAIT));
619}
620
621/**
622 * cdns3_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0
623 * @priv_dev: extended gadget object
624 * @dir: USB_DIR_IN for IN direction, USB_DIR_OUT for OUT direction
625 */
626void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir)
627{
628 u32 ep_sts_reg;
629
630 cdns3_select_ep(priv_dev, dir);
631
632 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
633 writel(ep_sts_reg, &priv_dev->regs->ep_sts);
634
635 trace_cdns3_ep0_irq(priv_dev, ep_sts_reg);
636
637 __pending_setup_status_handler(priv_dev);
638
639 if (ep_sts_reg & EP_STS_SETUP)
640 priv_dev->wait_for_setup = 1;
641
642 if (priv_dev->wait_for_setup && ep_sts_reg & EP_STS_IOC) {
643 priv_dev->wait_for_setup = 0;
644 cdns3_allow_enable_l1(priv_dev, 0);
645 cdns3_ep0_setup_phase(priv_dev);
646 } else if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
647 priv_dev->ep0_data_dir = dir;
648 cdns3_transfer_completed(priv_dev);
649 }
650
651 if (ep_sts_reg & EP_STS_DESCMIS) {
652 if (dir == 0 && !priv_dev->setup_pending)
653 cdns3_prepare_setup_packet(priv_dev);
654 }
655}
656
657/**
658 * cdns3_gadget_ep0_enable
659 * Function shouldn't be called by gadget driver,
660 * endpoint 0 is allways active
661 */
662static int cdns3_gadget_ep0_enable(struct usb_ep *ep,
663 const struct usb_endpoint_descriptor *desc)
664{
665 return -EINVAL;
666}
667
668/**
669 * cdns3_gadget_ep0_disable
670 * Function shouldn't be called by gadget driver,
671 * endpoint 0 is allways active
672 */
673static int cdns3_gadget_ep0_disable(struct usb_ep *ep)
674{
675 return -EINVAL;
676}
677
678/**
679 * cdns3_gadget_ep0_set_halt
680 * @ep: pointer to endpoint zero object
681 * @value: 1 for set stall, 0 for clear stall
682 *
683 * Returns 0
684 */
685static int cdns3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
686{
687 /* TODO */
688 return 0;
689}
690
691/**
692 * cdns3_gadget_ep0_queue Transfer data on endpoint zero
693 * @ep: pointer to endpoint zero object
694 * @request: pointer to request object
695 * @gfp_flags: gfp flags
696 *
697 * Returns 0 on success, error code elsewhere
698 */
699static int cdns3_gadget_ep0_queue(struct usb_ep *ep,
700 struct usb_request *request,
701 gfp_t gfp_flags)
702{
703 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
704 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
705 unsigned long flags;
706 int erdy_sent = 0;
707 int ret = 0;
708 u8 zlp = 0;
709
710 trace_cdns3_ep0_queue(priv_dev, request);
711
712 /* cancel the request if controller receive new SETUP packet. */
713 if (cdns3_check_new_setup(priv_dev))
714 return -ECONNRESET;
715
716 /* send STATUS stage. Should be called only for SET_CONFIGURATION */
717 if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) {
718 spin_lock_irqsave(&priv_dev->lock, flags);
719 cdns3_select_ep(priv_dev, 0x00);
720
721 erdy_sent = !priv_dev->hw_configured_flag;
722 cdns3_set_hw_configuration(priv_dev);
723
724 if (!erdy_sent)
725 cdns3_ep0_complete_setup(priv_dev, 0, 1);
726
727 cdns3_allow_enable_l1(priv_dev, 1);
728
729 request->actual = 0;
730 priv_dev->status_completion_no_call = true;
731 priv_dev->pending_status_request = request;
732 spin_unlock_irqrestore(&priv_dev->lock, flags);
733
734 /*
735 * Since there is no completion interrupt for status stage,
736 * it needs to call ->completion in software after
737 * ep0_queue is back.
738 */
739 queue_work(system_freezable_wq, &priv_dev->pending_status_wq);
740 return 0;
741 }
742
743 spin_lock_irqsave(&priv_dev->lock, flags);
744 if (!list_empty(&priv_ep->pending_req_list)) {
745 dev_err(priv_dev->dev,
746 "can't handle multiple requests for ep0\n");
747 spin_unlock_irqrestore(&priv_dev->lock, flags);
748 return -EBUSY;
749 }
750
751 ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request,
752 priv_dev->ep0_data_dir);
753 if (ret) {
754 spin_unlock_irqrestore(&priv_dev->lock, flags);
755 dev_err(priv_dev->dev, "failed to map request\n");
756 return -EINVAL;
757 }
758
759 request->status = -EINPROGRESS;
760 list_add_tail(&request->list, &priv_ep->pending_req_list);
761
762 if (request->zero && request->length &&
763 (request->length % ep->maxpacket == 0))
764 zlp = 1;
765
766 cdns3_ep0_run_transfer(priv_dev, request->dma, request->length, 1, zlp);
767
768 spin_unlock_irqrestore(&priv_dev->lock, flags);
769
770 return ret;
771}
772
773/**
774 * cdns3_gadget_ep_set_wedge Set wedge on selected endpoint
775 * @ep: endpoint object
776 *
777 * Returns 0
778 */
779int cdns3_gadget_ep_set_wedge(struct usb_ep *ep)
780{
781 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
782 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
783
784 dev_dbg(priv_dev->dev, "Wedge for %s\n", ep->name);
785 cdns3_gadget_ep_set_halt(ep, 1);
786 priv_ep->flags |= EP_WEDGE;
787
788 return 0;
789}
790
791const struct usb_ep_ops cdns3_gadget_ep0_ops = {
792 .enable = cdns3_gadget_ep0_enable,
793 .disable = cdns3_gadget_ep0_disable,
794 .alloc_request = cdns3_gadget_ep_alloc_request,
795 .free_request = cdns3_gadget_ep_free_request,
796 .queue = cdns3_gadget_ep0_queue,
797 .dequeue = cdns3_gadget_ep_dequeue,
798 .set_halt = cdns3_gadget_ep0_set_halt,
799 .set_wedge = cdns3_gadget_ep_set_wedge,
800};
801
802/**
803 * cdns3_ep0_config - Configures default endpoint
804 * @priv_dev: extended gadget object
805 *
806 * Functions sets parameters: maximal packet size and enables interrupts
807 */
808void cdns3_ep0_config(struct cdns3_device *priv_dev)
809{
810 struct cdns3_usb_regs __iomem *regs;
811 struct cdns3_endpoint *priv_ep;
812 u32 max_packet_size = 64;
813
814 regs = priv_dev->regs;
815
816 if (priv_dev->gadget.speed == USB_SPEED_SUPER)
817 max_packet_size = 512;
818
819 priv_ep = priv_dev->eps[0];
820
821 if (!list_empty(&priv_ep->pending_req_list)) {
822 struct usb_request *request;
823
824 request = cdns3_next_request(&priv_ep->pending_req_list);
825 list_del_init(&request->list);
826 }
827
828 priv_dev->u1_allowed = 0;
829 priv_dev->u2_allowed = 0;
830
831 priv_dev->gadget.ep0->maxpacket = max_packet_size;
832 cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(max_packet_size);
833
834 /* init ep out */
835 cdns3_select_ep(priv_dev, USB_DIR_OUT);
836
837 if (priv_dev->dev_ver >= DEV_VER_V3) {
838 cdns3_set_register_bit(&priv_dev->regs->dtrans,
839 BIT(0) | BIT(16));
840 cdns3_set_register_bit(&priv_dev->regs->tdl_from_trb,
841 BIT(0) | BIT(16));
842 }
843
844 writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
845 &regs->ep_cfg);
846
847 writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN,
848 &regs->ep_sts_en);
849
850 /* init ep in */
851 cdns3_select_ep(priv_dev, USB_DIR_IN);
852
853 writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
854 &regs->ep_cfg);
855
856 writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, &regs->ep_sts_en);
857
858 cdns3_set_register_bit(&regs->usb_conf, USB_CONF_U1DS | USB_CONF_U2DS);
859}
860
861/**
862 * cdns3_init_ep0 Initializes software endpoint 0 of gadget
863 * @priv_dev: extended gadget object
864 * @ep_priv: extended endpoint object
865 *
866 * Returns 0 on success else error code.
867 */
868int cdns3_init_ep0(struct cdns3_device *priv_dev,
869 struct cdns3_endpoint *priv_ep)
870{
871 sprintf(priv_ep->name, "ep0");
872
873 /* fill linux fields */
874 priv_ep->endpoint.ops = &cdns3_gadget_ep0_ops;
875 priv_ep->endpoint.maxburst = 1;
876 usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
877 CDNS3_EP0_MAX_PACKET_LIMIT);
878 priv_ep->endpoint.address = 0;
879 priv_ep->endpoint.caps.type_control = 1;
880 priv_ep->endpoint.caps.dir_in = 1;
881 priv_ep->endpoint.caps.dir_out = 1;
882 priv_ep->endpoint.name = priv_ep->name;
883 priv_ep->endpoint.desc = &cdns3_gadget_ep0_desc;
884 priv_dev->gadget.ep0 = &priv_ep->endpoint;
885 priv_ep->type = USB_ENDPOINT_XFER_CONTROL;
886
887 return cdns3_allocate_trb_pool(priv_ep);
888}
diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h
new file mode 100644
index 000000000000..577469eee961
--- /dev/null
+++ b/drivers/usb/cdns3/gadget-export.h
@@ -0,0 +1,28 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver - Gadget Export APIs.
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 */
10#ifndef __LINUX_CDNS3_GADGET_EXPORT
11#define __LINUX_CDNS3_GADGET_EXPORT
12
13#ifdef CONFIG_USB_CDNS3_GADGET
14
15int cdns3_gadget_init(struct cdns3 *cdns);
16void cdns3_gadget_exit(struct cdns3 *cdns);
17#else
18
19static inline int cdns3_gadget_init(struct cdns3 *cdns)
20{
21 return -ENXIO;
22}
23
24static inline void cdns3_gadget_exit(struct cdns3 *cdns) { }
25
26#endif
27
28#endif /* __LINUX_CDNS3_GADGET_EXPORT */
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
new file mode 100644
index 000000000000..3094ad65ffc9
--- /dev/null
+++ b/drivers/usb/cdns3/gadget.c
@@ -0,0 +1,2751 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - gadget side.
4 *
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Pawel Jez <pjez@cadence.com>,
9 * Pawel Laszczak <pawell@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12
13/*
14 * Work around 1:
15 * At some situations, the controller may get stale data address in TRB
16 * at below sequences:
17 * 1. Controller read TRB includes data address
18 * 2. Software updates TRBs includes data address and Cycle bit
19 * 3. Controller read TRB which includes Cycle bit
20 * 4. DMA run with stale data address
21 *
22 * To fix this problem, driver needs to make the first TRB in TD as invalid.
23 * After preparing all TRBs driver needs to check the position of DMA and
24 * if the DMA point to the first just added TRB and doorbell is 1,
25 * then driver must defer making this TRB as valid. This TRB will be make
26 * as valid during adding next TRB only if DMA is stopped or at TRBERR
27 * interrupt.
28 *
29 * Issue has been fixed in DEV_VER_V3 version of controller.
30 *
31 * Work around 2:
32 * Controller for OUT endpoints has shared on-chip buffers for all incoming
33 * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA
34 * in correct order. If the first packet in the buffer will not be handled,
35 * then the following packets directed for other endpoints and functions
36 * will be blocked.
37 * Additionally the packets directed to one endpoint can block entire on-chip
38 * buffers. In this case transfer to other endpoints also will blocked.
39 *
40 * To resolve this issue after raising the descriptor missing interrupt
41 * driver prepares internal usb_request object and use it to arm DMA transfer.
42 *
43 * The problematic situation was observed in case when endpoint has been enabled
44 * but no usb_request were queued. Driver try detects such endpoints and will
45 * use this workaround only for these endpoint.
46 *
47 * Driver use limited number of buffer. This number can be set by macro
48 * CDNS3_WA2_NUM_BUFFERS.
49 *
50 * Such blocking situation was observed on ACM gadget. For this function
51 * host send OUT data packet but ACM function is not prepared for this packet.
52 * It's cause that buffer placed in on chip memory block transfer to other
53 * endpoints.
54 *
55 * Issue has been fixed in DEV_VER_V2 version of controller.
56 *
57 */
58
59#include <linux/dma-mapping.h>
60#include <linux/usb/gadget.h>
61#include <linux/module.h>
62#include <linux/iopoll.h>
63
64#include "core.h"
65#include "gadget-export.h"
66#include "gadget.h"
67#include "trace.h"
68#include "drd.h"
69
70static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
71 struct usb_request *request,
72 gfp_t gfp_flags);
73
74/**
75 * cdns3_set_register_bit - set bit in given register.
76 * @ptr: address of device controller register to be read and changed
77 * @mask: bits requested to set
78 */
79void cdns3_set_register_bit(void __iomem *ptr, u32 mask)
80{
81 mask = readl(ptr) | mask;
82 writel(mask, ptr);
83}
84
85/**
86 * cdns3_ep_addr_to_index - Macro converts endpoint address to
87 * index of endpoint object in cdns3_device.eps[] container
88 * @ep_addr: endpoint address for which endpoint object is required
89 *
90 */
91u8 cdns3_ep_addr_to_index(u8 ep_addr)
92{
93 return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0));
94}
95
96static int cdns3_get_dma_pos(struct cdns3_device *priv_dev,
97 struct cdns3_endpoint *priv_ep)
98{
99 int dma_index;
100
101 dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma;
102
103 return dma_index / TRB_SIZE;
104}
105
106/**
107 * cdns3_next_request - returns next request from list
108 * @list: list containing requests
109 *
110 * Returns request or NULL if no requests in list
111 */
112struct usb_request *cdns3_next_request(struct list_head *list)
113{
114 return list_first_entry_or_null(list, struct usb_request, list);
115}
116
117/**
118 * cdns3_next_align_buf - returns next buffer from list
119 * @list: list containing buffers
120 *
121 * Returns buffer or NULL if no buffers in list
122 */
123struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list)
124{
125 return list_first_entry_or_null(list, struct cdns3_aligned_buf, list);
126}
127
128/**
129 * cdns3_next_priv_request - returns next request from list
130 * @list: list containing requests
131 *
132 * Returns request or NULL if no requests in list
133 */
134struct cdns3_request *cdns3_next_priv_request(struct list_head *list)
135{
136 return list_first_entry_or_null(list, struct cdns3_request, list);
137}
138
139/**
140 * select_ep - selects endpoint
141 * @priv_dev: extended gadget object
142 * @ep: endpoint address
143 */
144void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep)
145{
146 if (priv_dev->selected_ep == ep)
147 return;
148
149 priv_dev->selected_ep = ep;
150 writel(ep, &priv_dev->regs->ep_sel);
151}
152
153dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
154 struct cdns3_trb *trb)
155{
156 u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
157
158 return priv_ep->trb_pool_dma + offset;
159}
160
161int cdns3_ring_size(struct cdns3_endpoint *priv_ep)
162{
163 switch (priv_ep->type) {
164 case USB_ENDPOINT_XFER_ISOC:
165 return TRB_ISO_RING_SIZE;
166 case USB_ENDPOINT_XFER_CONTROL:
167 return TRB_CTRL_RING_SIZE;
168 default:
169 return TRB_RING_SIZE;
170 }
171}
172
173/**
174 * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint
175 * @priv_ep: endpoint object
176 *
177 * Function will return 0 on success or -ENOMEM on allocation error
178 */
179int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep)
180{
181 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
182 int ring_size = cdns3_ring_size(priv_ep);
183 struct cdns3_trb *link_trb;
184
185 if (!priv_ep->trb_pool) {
186 priv_ep->trb_pool = dma_alloc_coherent(priv_dev->sysdev,
187 ring_size,
188 &priv_ep->trb_pool_dma,
189 GFP_DMA32 | GFP_ATOMIC);
190 if (!priv_ep->trb_pool)
191 return -ENOMEM;
192 } else {
193 memset(priv_ep->trb_pool, 0, ring_size);
194 }
195
196 if (!priv_ep->num)
197 return 0;
198
199 priv_ep->num_trbs = ring_size / TRB_SIZE;
200 /* Initialize the last TRB as Link TRB. */
201 link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1));
202 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma);
203 link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE;
204
205 return 0;
206}
207
208static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep)
209{
210 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
211
212 if (priv_ep->trb_pool) {
213 dma_free_coherent(priv_dev->sysdev,
214 cdns3_ring_size(priv_ep),
215 priv_ep->trb_pool, priv_ep->trb_pool_dma);
216 priv_ep->trb_pool = NULL;
217 }
218}
219
220/**
221 * cdns3_ep_stall_flush - Stalls and flushes selected endpoint
222 * @priv_ep: endpoint object
223 *
224 * Endpoint must be selected before call to this function
225 */
226static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep)
227{
228 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
229 int val;
230
231 trace_cdns3_halt(priv_ep, 1, 1);
232
233 writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
234 &priv_dev->regs->ep_cmd);
235
236 /* wait for DFLUSH cleared */
237 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
238 !(val & EP_CMD_DFLUSH), 1, 1000);
239 priv_ep->flags |= EP_STALLED;
240 priv_ep->flags &= ~EP_STALL_PENDING;
241}
242
243/**
244 * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller.
245 * @priv_dev: extended gadget object
246 */
247void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev)
248{
249 writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
250
251 cdns3_allow_enable_l1(priv_dev, 0);
252 priv_dev->hw_configured_flag = 0;
253 priv_dev->onchip_used_size = 0;
254 priv_dev->out_mem_is_allocated = 0;
255 priv_dev->wait_for_setup = 0;
256}
257
258/**
259 * cdns3_ep_inc_trb - increment a trb index.
260 * @index: Pointer to the TRB index to increment.
261 * @cs: Cycle state
262 * @trb_in_seg: number of TRBs in segment
263 *
264 * The index should never point to the link TRB. After incrementing,
265 * if it is point to the link TRB, wrap around to the beginning and revert
266 * cycle state bit The
267 * link TRB is always at the last TRB entry.
268 */
269static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg)
270{
271 (*index)++;
272 if (*index == (trb_in_seg - 1)) {
273 *index = 0;
274 *cs ^= 1;
275 }
276}
277
278/**
279 * cdns3_ep_inc_enq - increment endpoint's enqueue pointer
280 * @priv_ep: The endpoint whose enqueue pointer we're incrementing
281 */
282static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep)
283{
284 priv_ep->free_trbs--;
285 cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs);
286}
287
288/**
289 * cdns3_ep_inc_deq - increment endpoint's dequeue pointer
290 * @priv_ep: The endpoint whose dequeue pointer we're incrementing
291 */
292static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep)
293{
294 priv_ep->free_trbs++;
295 cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs);
296}
297
298void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req)
299{
300 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
301 int current_trb = priv_req->start_trb;
302
303 while (current_trb != priv_req->end_trb) {
304 cdns3_ep_inc_deq(priv_ep);
305 current_trb = priv_ep->dequeue;
306 }
307
308 cdns3_ep_inc_deq(priv_ep);
309}
310
311/**
312 * cdns3_allow_enable_l1 - enable/disable permits to transition to L1.
313 * @priv_dev: Extended gadget object
314 * @enable: Enable/disable permit to transition to L1.
315 *
316 * If bit USB_CONF_L1EN is set and device receive Extended Token packet,
317 * then controller answer with ACK handshake.
318 * If bit USB_CONF_L1DS is set and device receive Extended Token packet,
319 * then controller answer with NYET handshake.
320 */
321void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable)
322{
323 if (enable)
324 writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
325 else
326 writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
327}
328
329enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev)
330{
331 u32 reg;
332
333 reg = readl(&priv_dev->regs->usb_sts);
334
335 if (DEV_SUPERSPEED(reg))
336 return USB_SPEED_SUPER;
337 else if (DEV_HIGHSPEED(reg))
338 return USB_SPEED_HIGH;
339 else if (DEV_FULLSPEED(reg))
340 return USB_SPEED_FULL;
341 else if (DEV_LOWSPEED(reg))
342 return USB_SPEED_LOW;
343 return USB_SPEED_UNKNOWN;
344}
345
346/**
347 * cdns3_start_all_request - add to ring all request not started
348 * @priv_dev: Extended gadget object
349 * @priv_ep: The endpoint for whom request will be started.
350 *
351 * Returns return ENOMEM if transfer ring i not enough TRBs to start
352 * all requests.
353 */
354static int cdns3_start_all_request(struct cdns3_device *priv_dev,
355 struct cdns3_endpoint *priv_ep)
356{
357 struct cdns3_request *priv_req;
358 struct usb_request *request;
359 int ret = 0;
360
361 while (!list_empty(&priv_ep->deferred_req_list)) {
362 request = cdns3_next_request(&priv_ep->deferred_req_list);
363 priv_req = to_cdns3_request(request);
364
365 ret = cdns3_ep_run_transfer(priv_ep, request);
366 if (ret)
367 return ret;
368
369 list_del(&request->list);
370 list_add_tail(&request->list,
371 &priv_ep->pending_req_list);
372 }
373
374 priv_ep->flags &= ~EP_RING_FULL;
375 return ret;
376}
377
378/*
379 * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set
380 * driver try to detect whether endpoint need additional internal
381 * buffer for unblocking on-chip FIFO buffer. This flag will be cleared
382 * if before first DESCMISS interrupt the DMA will be armed.
383 */
384#define cdns3_wa2_enable_detection(priv_dev, ep_priv, reg) do { \
385 if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \
386 priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \
387 (reg) |= EP_STS_EN_DESCMISEN; \
388 } } while (0)
389
390/**
391 * cdns3_wa2_descmiss_copy_data copy data from internal requests to
392 * request queued by class driver.
393 * @priv_ep: extended endpoint object
394 * @request: request object
395 */
396static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep,
397 struct usb_request *request)
398{
399 struct usb_request *descmiss_req;
400 struct cdns3_request *descmiss_priv_req;
401
402 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
403 int chunk_end;
404 int length;
405
406 descmiss_priv_req =
407 cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
408 descmiss_req = &descmiss_priv_req->request;
409
410 /* driver can't touch pending request */
411 if (descmiss_priv_req->flags & REQUEST_PENDING)
412 break;
413
414 chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH;
415 length = request->actual + descmiss_req->actual;
416
417 request->status = descmiss_req->status;
418
419 if (length <= request->length) {
420 memcpy(&((u8 *)request->buf)[request->actual],
421 descmiss_req->buf,
422 descmiss_req->actual);
423 request->actual = length;
424 } else {
425 /* It should never occures */
426 request->status = -ENOMEM;
427 }
428
429 list_del_init(&descmiss_priv_req->list);
430
431 kfree(descmiss_req->buf);
432 cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req);
433 --priv_ep->wa2_counter;
434
435 if (!chunk_end)
436 break;
437 }
438}
439
440struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev,
441 struct cdns3_endpoint *priv_ep,
442 struct cdns3_request *priv_req)
443{
444 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN &&
445 priv_req->flags & REQUEST_INTERNAL) {
446 struct usb_request *req;
447
448 req = cdns3_next_request(&priv_ep->deferred_req_list);
449
450 priv_ep->descmis_req = NULL;
451
452 if (!req)
453 return NULL;
454
455 cdns3_wa2_descmiss_copy_data(priv_ep, req);
456 if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) &&
457 req->length != req->actual) {
458 /* wait for next part of transfer */
459 return NULL;
460 }
461
462 if (req->status == -EINPROGRESS)
463 req->status = 0;
464
465 list_del_init(&req->list);
466 cdns3_start_all_request(priv_dev, priv_ep);
467 return req;
468 }
469
470 return &priv_req->request;
471}
472
473int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev,
474 struct cdns3_endpoint *priv_ep,
475 struct cdns3_request *priv_req)
476{
477 int deferred = 0;
478
479 /*
480 * If transfer was queued before DESCMISS appear than we
481 * can disable handling of DESCMISS interrupt. Driver assumes that it
482 * can disable special treatment for this endpoint.
483 */
484 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
485 u32 reg;
486
487 cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir);
488 priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
489 reg = readl(&priv_dev->regs->ep_sts_en);
490 reg &= ~EP_STS_EN_DESCMISEN;
491 trace_cdns3_wa2(priv_ep, "workaround disabled\n");
492 writel(reg, &priv_dev->regs->ep_sts_en);
493 }
494
495 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
496 u8 pending_empty = list_empty(&priv_ep->pending_req_list);
497 u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list);
498
499 /*
500 * DESCMISS transfer has been finished, so data will be
501 * directly copied from internal allocated usb_request
502 * objects.
503 */
504 if (pending_empty && !descmiss_empty &&
505 !(priv_req->flags & REQUEST_INTERNAL)) {
506 cdns3_wa2_descmiss_copy_data(priv_ep,
507 &priv_req->request);
508
509 trace_cdns3_wa2(priv_ep, "get internal stored data");
510
511 list_add_tail(&priv_req->request.list,
512 &priv_ep->pending_req_list);
513 cdns3_gadget_giveback(priv_ep, priv_req,
514 priv_req->request.status);
515
516 /*
517 * Intentionally driver returns positive value as
518 * correct value. It informs that transfer has
519 * been finished.
520 */
521 return EINPROGRESS;
522 }
523
524 /*
525 * Driver will wait for completion DESCMISS transfer,
526 * before starts new, not DESCMISS transfer.
527 */
528 if (!pending_empty && !descmiss_empty) {
529 trace_cdns3_wa2(priv_ep, "wait for pending transfer\n");
530 deferred = 1;
531 }
532
533 if (priv_req->flags & REQUEST_INTERNAL)
534 list_add_tail(&priv_req->list,
535 &priv_ep->wa2_descmiss_req_list);
536 }
537
538 return deferred;
539}
540
541static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep)
542{
543 struct cdns3_request *priv_req;
544
545 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
546 u8 chain;
547
548 priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
549 chain = !!(priv_req->flags & REQUEST_INTERNAL_CH);
550
551 trace_cdns3_wa2(priv_ep, "removes eldest request");
552
553 kfree(priv_req->request.buf);
554 cdns3_gadget_ep_free_request(&priv_ep->endpoint,
555 &priv_req->request);
556 list_del_init(&priv_req->list);
557 --priv_ep->wa2_counter;
558
559 if (!chain)
560 break;
561 }
562}
563
564/**
565 * cdns3_wa2_descmissing_packet - handles descriptor missing event.
566 * @priv_dev: extended gadget object
567 *
568 * This function is used only for WA2. For more information see Work around 2
569 * description.
570 */
571static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep)
572{
573 struct cdns3_request *priv_req;
574 struct usb_request *request;
575
576 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
577 priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
578 priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN;
579 }
580
581 trace_cdns3_wa2(priv_ep, "Description Missing detected\n");
582
583 if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS)
584 cdns3_wa2_remove_old_request(priv_ep);
585
586 request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint,
587 GFP_ATOMIC);
588 if (!request)
589 goto err;
590
591 priv_req = to_cdns3_request(request);
592 priv_req->flags |= REQUEST_INTERNAL;
593
594 /* if this field is still assigned it indicate that transfer related
595 * with this request has not been finished yet. Driver in this
596 * case simply allocate next request and assign flag REQUEST_INTERNAL_CH
597 * flag to previous one. It will indicate that current request is
598 * part of the previous one.
599 */
600 if (priv_ep->descmis_req)
601 priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH;
602
603 priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE,
604 GFP_ATOMIC);
605 priv_ep->wa2_counter++;
606
607 if (!priv_req->request.buf) {
608 cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
609 goto err;
610 }
611
612 priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE;
613 priv_ep->descmis_req = priv_req;
614
615 __cdns3_gadget_ep_queue(&priv_ep->endpoint,
616 &priv_ep->descmis_req->request,
617 GFP_ATOMIC);
618
619 return;
620
621err:
622 dev_err(priv_ep->cdns3_dev->dev,
623 "Failed: No sufficient memory for DESCMIS\n");
624}
625
626/**
627 * cdns3_gadget_giveback - call struct usb_request's ->complete callback
628 * @priv_ep: The endpoint to whom the request belongs to
629 * @priv_req: The request we're giving back
630 * @status: completion code for the request
631 *
632 * Must be called with controller's lock held and interrupts disabled. This
633 * function will unmap @req and call its ->complete() callback to notify upper
634 * layers that it has completed.
635 */
636void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
637 struct cdns3_request *priv_req,
638 int status)
639{
640 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
641 struct usb_request *request = &priv_req->request;
642
643 list_del_init(&request->list);
644
645 if (request->status == -EINPROGRESS)
646 request->status = status;
647
648 usb_gadget_unmap_request_by_dev(priv_dev->sysdev, request,
649 priv_ep->dir);
650
651 if ((priv_req->flags & REQUEST_UNALIGNED) &&
652 priv_ep->dir == USB_DIR_OUT && !request->status)
653 memcpy(request->buf, priv_req->aligned_buf->buf,
654 request->length);
655
656 priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED);
657 trace_cdns3_gadget_giveback(priv_req);
658
659 if (priv_dev->dev_ver < DEV_VER_V2) {
660 request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep,
661 priv_req);
662 if (!request)
663 return;
664 }
665
666 if (request->complete) {
667 spin_unlock(&priv_dev->lock);
668 usb_gadget_giveback_request(&priv_ep->endpoint,
669 request);
670 spin_lock(&priv_dev->lock);
671 }
672
673 if (request->buf == priv_dev->zlp_buf)
674 cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
675}
676
677void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep)
678{
679 /* Work around for stale data address in TRB*/
680 if (priv_ep->wa1_set) {
681 trace_cdns3_wa1(priv_ep, "restore cycle bit");
682
683 priv_ep->wa1_set = 0;
684 priv_ep->wa1_trb_index = 0xFFFF;
685 if (priv_ep->wa1_cycle_bit) {
686 priv_ep->wa1_trb->control =
687 priv_ep->wa1_trb->control | 0x1;
688 } else {
689 priv_ep->wa1_trb->control =
690 priv_ep->wa1_trb->control & ~0x1;
691 }
692 }
693}
694
695static void cdns3_free_aligned_request_buf(struct work_struct *work)
696{
697 struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
698 aligned_buf_wq);
699 struct cdns3_aligned_buf *buf, *tmp;
700 unsigned long flags;
701
702 spin_lock_irqsave(&priv_dev->lock, flags);
703
704 list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) {
705 if (!buf->in_use) {
706 list_del(&buf->list);
707
708 /*
709 * Re-enable interrupts to free DMA capable memory.
710 * Driver can't free this memory with disabled
711 * interrupts.
712 */
713 spin_unlock_irqrestore(&priv_dev->lock, flags);
714 dma_free_coherent(priv_dev->sysdev, buf->size,
715 buf->buf, buf->dma);
716 kfree(buf);
717 spin_lock_irqsave(&priv_dev->lock, flags);
718 }
719 }
720
721 spin_unlock_irqrestore(&priv_dev->lock, flags);
722}
723
724static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req)
725{
726 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
727 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
728 struct cdns3_aligned_buf *buf;
729
730 /* check if buffer is aligned to 8. */
731 if (!((uintptr_t)priv_req->request.buf & 0x7))
732 return 0;
733
734 buf = priv_req->aligned_buf;
735
736 if (!buf || priv_req->request.length > buf->size) {
737 buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
738 if (!buf)
739 return -ENOMEM;
740
741 buf->size = priv_req->request.length;
742
743 buf->buf = dma_alloc_coherent(priv_dev->sysdev,
744 buf->size,
745 &buf->dma,
746 GFP_ATOMIC);
747 if (!buf->buf) {
748 kfree(buf);
749 return -ENOMEM;
750 }
751
752 if (priv_req->aligned_buf) {
753 trace_cdns3_free_aligned_request(priv_req);
754 priv_req->aligned_buf->in_use = 0;
755 queue_work(system_freezable_wq,
756 &priv_dev->aligned_buf_wq);
757 }
758
759 buf->in_use = 1;
760 priv_req->aligned_buf = buf;
761
762 list_add_tail(&buf->list,
763 &priv_dev->aligned_buf_list);
764 }
765
766 if (priv_ep->dir == USB_DIR_IN) {
767 memcpy(buf->buf, priv_req->request.buf,
768 priv_req->request.length);
769 }
770
771 priv_req->flags |= REQUEST_UNALIGNED;
772 trace_cdns3_prepare_aligned_request(priv_req);
773
774 return 0;
775}
776
777static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep,
778 struct cdns3_trb *trb)
779{
780 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
781
782 if (!priv_ep->wa1_set) {
783 u32 doorbell;
784
785 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
786
787 if (doorbell) {
788 priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0;
789 priv_ep->wa1_set = 1;
790 priv_ep->wa1_trb = trb;
791 priv_ep->wa1_trb_index = priv_ep->enqueue;
792 trace_cdns3_wa1(priv_ep, "set guard");
793 return 0;
794 }
795 }
796 return 1;
797}
798
799static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev,
800 struct cdns3_endpoint *priv_ep)
801{
802 int dma_index;
803 u32 doorbell;
804
805 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
806 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
807
808 if (!doorbell || dma_index != priv_ep->wa1_trb_index)
809 cdns3_wa1_restore_cycle_bit(priv_ep);
810}
811
812/**
813 * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
814 * @priv_ep: endpoint object
815 *
816 * Returns zero on success or negative value on failure
817 */
818int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
819 struct usb_request *request)
820{
821 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
822 struct cdns3_request *priv_req;
823 struct cdns3_trb *trb;
824 dma_addr_t trb_dma;
825 u32 togle_pcs = 1;
826 int sg_iter = 0;
827 int num_trb;
828 int address;
829 u32 control;
830 int pcs;
831
832 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC)
833 num_trb = priv_ep->interval;
834 else
835 num_trb = request->num_sgs ? request->num_sgs : 1;
836
837 if (num_trb > priv_ep->free_trbs) {
838 priv_ep->flags |= EP_RING_FULL;
839 return -ENOBUFS;
840 }
841
842 priv_req = to_cdns3_request(request);
843 address = priv_ep->endpoint.desc->bEndpointAddress;
844
845 priv_ep->flags |= EP_PENDING_REQUEST;
846
847 /* must allocate buffer aligned to 8 */
848 if (priv_req->flags & REQUEST_UNALIGNED)
849 trb_dma = priv_req->aligned_buf->dma;
850 else
851 trb_dma = request->dma;
852
853 trb = priv_ep->trb_pool + priv_ep->enqueue;
854 priv_req->start_trb = priv_ep->enqueue;
855 priv_req->trb = trb;
856
857 cdns3_select_ep(priv_ep->cdns3_dev, address);
858
859 /* prepare ring */
860 if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) {
861 struct cdns3_trb *link_trb;
862 int doorbell, dma_index;
863 u32 ch_bit = 0;
864
865 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
866 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
867
868 /* Driver can't update LINK TRB if it is current processed. */
869 if (doorbell && dma_index == priv_ep->num_trbs - 1) {
870 priv_ep->flags |= EP_DEFERRED_DRDY;
871 return -ENOBUFS;
872 }
873
874 /*updating C bt in Link TRB before starting DMA*/
875 link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1);
876 /*
877 * For TRs size equal 2 enabling TRB_CHAIN for epXin causes
878 * that DMA stuck at the LINK TRB.
879 * On the other hand, removing TRB_CHAIN for longer TRs for
880 * epXout cause that DMA stuck after handling LINK TRB.
881 * To eliminate this strange behavioral driver set TRB_CHAIN
882 * bit only for TR size > 2.
883 */
884 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC ||
885 TRBS_PER_SEGMENT > 2)
886 ch_bit = TRB_CHAIN;
887
888 link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) |
889 TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit;
890 }
891
892 if (priv_dev->dev_ver <= DEV_VER_V2)
893 togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
894
895 /* set incorrect Cycle Bit for first trb*/
896 control = priv_ep->pcs ? 0 : TRB_CYCLE;
897
898 do {
899 u32 length;
900 u16 td_size = 0;
901
902 /* fill TRB */
903 control |= TRB_TYPE(TRB_NORMAL);
904 trb->buffer = TRB_BUFFER(request->num_sgs == 0
905 ? trb_dma : request->sg[sg_iter].dma_address);
906
907 if (likely(!request->num_sgs))
908 length = request->length;
909 else
910 length = request->sg[sg_iter].length;
911
912 if (likely(priv_dev->dev_ver >= DEV_VER_V2))
913 td_size = DIV_ROUND_UP(length,
914 priv_ep->endpoint.maxpacket);
915
916 trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) |
917 TRB_LEN(length);
918 if (priv_dev->gadget.speed == USB_SPEED_SUPER)
919 trb->length |= TRB_TDL_SS_SIZE(td_size);
920 else
921 control |= TRB_TDL_HS_SIZE(td_size);
922
923 pcs = priv_ep->pcs ? TRB_CYCLE : 0;
924
925 /*
926 * first trb should be prepared as last to avoid processing
927 * transfer to early
928 */
929 if (sg_iter != 0)
930 control |= pcs;
931
932 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) {
933 control |= TRB_IOC | TRB_ISP;
934 } else {
935 /* for last element in TD or in SG list */
936 if (sg_iter == (num_trb - 1) && sg_iter != 0)
937 control |= pcs | TRB_IOC | TRB_ISP;
938 }
939
940 if (sg_iter)
941 trb->control = control;
942 else
943 priv_req->trb->control = control;
944
945 control = 0;
946 ++sg_iter;
947 priv_req->end_trb = priv_ep->enqueue;
948 cdns3_ep_inc_enq(priv_ep);
949 trb = priv_ep->trb_pool + priv_ep->enqueue;
950 } while (sg_iter < num_trb);
951
952 trb = priv_req->trb;
953
954 priv_req->flags |= REQUEST_PENDING;
955
956 if (sg_iter == 1)
957 trb->control |= TRB_IOC | TRB_ISP;
958
959 /*
960 * Memory barrier - cycle bit must be set before other filds in trb.
961 */
962 wmb();
963
964 /* give the TD to the consumer*/
965 if (togle_pcs)
966 trb->control = trb->control ^ 1;
967
968 if (priv_dev->dev_ver <= DEV_VER_V2)
969 cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
970
971 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
972
973 /*
974 * Memory barrier - Cycle Bit must be set before trb->length and
975 * trb->buffer fields.
976 */
977 wmb();
978
979 /*
980 * For DMULT mode we can set address to transfer ring only once after
981 * enabling endpoint.
982 */
983 if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) {
984 /*
985 * Until SW is not ready to handle the OUT transfer the ISO OUT
986 * Endpoint should be disabled (EP_CFG.ENABLE = 0).
987 * EP_CFG_ENABLE must be set before updating ep_traddr.
988 */
989 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir &&
990 !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) {
991 priv_ep->flags |= EP_QUIRK_ISO_OUT_EN;
992 cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
993 EP_CFG_ENABLE);
994 }
995
996 writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
997 priv_req->start_trb * TRB_SIZE),
998 &priv_dev->regs->ep_traddr);
999
1000 priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR;
1001 }
1002
1003 if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) {
1004 trace_cdns3_ring(priv_ep);
1005 /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
1006 writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
1007 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
1008 trace_cdns3_doorbell_epx(priv_ep->name,
1009 readl(&priv_dev->regs->ep_traddr));
1010 }
1011
1012 /* WORKAROUND for transition to L0 */
1013 __cdns3_gadget_wakeup(priv_dev);
1014
1015 return 0;
1016}
1017
1018void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
1019{
1020 struct cdns3_endpoint *priv_ep;
1021 struct usb_ep *ep;
1022 int val;
1023
1024 if (priv_dev->hw_configured_flag)
1025 return;
1026
1027 writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
1028 writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd);
1029
1030 cdns3_set_register_bit(&priv_dev->regs->usb_conf,
1031 USB_CONF_U1EN | USB_CONF_U2EN);
1032
1033 /* wait until configuration set */
1034 readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val,
1035 val & USB_STS_CFGSTS_MASK, 1, 100);
1036
1037 priv_dev->hw_configured_flag = 1;
1038
1039 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
1040 if (ep->enabled) {
1041 priv_ep = ep_to_cdns3_ep(ep);
1042 cdns3_start_all_request(priv_dev, priv_ep);
1043 }
1044 }
1045}
1046
1047/**
1048 * cdns3_request_handled - check whether request has been handled by DMA
1049 *
1050 * @priv_ep: extended endpoint object.
1051 * @priv_req: request object for checking
1052 *
1053 * Endpoint must be selected before invoking this function.
1054 *
1055 * Returns false if request has not been handled by DMA, else returns true.
1056 *
1057 * SR - start ring
1058 * ER - end ring
1059 * DQ = priv_ep->dequeue - dequeue position
1060 * EQ = priv_ep->enqueue - enqueue position
1061 * ST = priv_req->start_trb - index of first TRB in transfer ring
1062 * ET = priv_req->end_trb - index of last TRB in transfer ring
1063 * CI = current_index - index of processed TRB by DMA.
1064 *
1065 * As first step, function checks if cycle bit for priv_req->start_trb is
1066 * correct.
1067 *
1068 * some rules:
1069 * 1. priv_ep->dequeue never exceed current_index.
1070 * 2 priv_ep->enqueue never exceed priv_ep->dequeue
1071 * 3. exception: priv_ep->enqueue == priv_ep->dequeue
1072 * and priv_ep->free_trbs is zero.
1073 * This case indicate that TR is full.
1074 *
1075 * Then We can split recognition into two parts:
1076 * Case 1 - priv_ep->dequeue < current_index
1077 * SR ... EQ ... DQ ... CI ... ER
1078 * SR ... DQ ... CI ... EQ ... ER
1079 *
1080 * Request has been handled by DMA if ST and ET is between DQ and CI.
1081 *
1082 * Case 2 - priv_ep->dequeue > current_index
1083 * This situation take place when CI go through the LINK TRB at the end of
1084 * transfer ring.
1085 * SR ... CI ... EQ ... DQ ... ER
1086 *
1087 * Request has been handled by DMA if ET is less then CI or
1088 * ET is greater or equal DQ.
1089 */
1090static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep,
1091 struct cdns3_request *priv_req)
1092{
1093 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1094 struct cdns3_trb *trb = priv_req->trb;
1095 int current_index = 0;
1096 int handled = 0;
1097 int doorbell;
1098
1099 current_index = cdns3_get_dma_pos(priv_dev, priv_ep);
1100 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
1101
1102 trb = &priv_ep->trb_pool[priv_req->start_trb];
1103
1104 if ((trb->control & TRB_CYCLE) != priv_ep->ccs)
1105 goto finish;
1106
1107 if (doorbell == 1 && current_index == priv_ep->dequeue)
1108 goto finish;
1109
1110 /* The corner case for TRBS_PER_SEGMENT equal 2). */
1111 if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
1112 handled = 1;
1113 goto finish;
1114 }
1115
1116 if (priv_ep->enqueue == priv_ep->dequeue &&
1117 priv_ep->free_trbs == 0) {
1118 handled = 1;
1119 } else if (priv_ep->dequeue < current_index) {
1120 if ((current_index == (priv_ep->num_trbs - 1)) &&
1121 !priv_ep->dequeue)
1122 goto finish;
1123
1124 if (priv_req->end_trb >= priv_ep->dequeue &&
1125 priv_req->end_trb < current_index)
1126 handled = 1;
1127 } else if (priv_ep->dequeue > current_index) {
1128 if (priv_req->end_trb < current_index ||
1129 priv_req->end_trb >= priv_ep->dequeue)
1130 handled = 1;
1131 }
1132
1133finish:
1134 trace_cdns3_request_handled(priv_req, current_index, handled);
1135
1136 return handled;
1137}
1138
1139static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
1140 struct cdns3_endpoint *priv_ep)
1141{
1142 struct cdns3_request *priv_req;
1143 struct usb_request *request;
1144 struct cdns3_trb *trb;
1145
1146 while (!list_empty(&priv_ep->pending_req_list)) {
1147 request = cdns3_next_request(&priv_ep->pending_req_list);
1148 priv_req = to_cdns3_request(request);
1149
1150 /* Re-select endpoint. It could be changed by other CPU during
1151 * handling usb_gadget_giveback_request.
1152 */
1153 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
1154
1155 if (!cdns3_request_handled(priv_ep, priv_req))
1156 goto prepare_next_td;
1157
1158 trb = priv_ep->trb_pool + priv_ep->dequeue;
1159 trace_cdns3_complete_trb(priv_ep, trb);
1160
1161 if (trb != priv_req->trb)
1162 dev_warn(priv_dev->dev,
1163 "request_trb=0x%p, queue_trb=0x%p\n",
1164 priv_req->trb, trb);
1165
1166 request->actual = TRB_LEN(le32_to_cpu(trb->length));
1167 cdns3_move_deq_to_next_trb(priv_req);
1168 cdns3_gadget_giveback(priv_ep, priv_req, 0);
1169
1170 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC &&
1171 TRBS_PER_SEGMENT == 2)
1172 break;
1173 }
1174 priv_ep->flags &= ~EP_PENDING_REQUEST;
1175
1176prepare_next_td:
1177 if (!(priv_ep->flags & EP_STALLED) &&
1178 !(priv_ep->flags & EP_STALL_PENDING))
1179 cdns3_start_all_request(priv_dev, priv_ep);
1180}
1181
1182void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm)
1183{
1184 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1185
1186 cdns3_wa1_restore_cycle_bit(priv_ep);
1187
1188 if (rearm) {
1189 trace_cdns3_ring(priv_ep);
1190
1191 /* Cycle Bit must be updated before arming DMA. */
1192 wmb();
1193 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
1194
1195 __cdns3_gadget_wakeup(priv_dev);
1196
1197 trace_cdns3_doorbell_epx(priv_ep->name,
1198 readl(&priv_dev->regs->ep_traddr));
1199 }
1200}
1201
1202/**
1203 * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint
1204 * @priv_ep: endpoint object
1205 *
1206 * Returns 0
1207 */
1208static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep)
1209{
1210 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1211 u32 ep_sts_reg;
1212
1213 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
1214
1215 trace_cdns3_epx_irq(priv_dev, priv_ep);
1216
1217 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
1218 writel(ep_sts_reg, &priv_dev->regs->ep_sts);
1219
1220 if (ep_sts_reg & EP_STS_TRBERR) {
1221 if (priv_ep->flags & EP_STALL_PENDING &&
1222 !(ep_sts_reg & EP_STS_DESCMIS &&
1223 priv_dev->dev_ver < DEV_VER_V2)) {
1224 cdns3_ep_stall_flush(priv_ep);
1225 }
1226
1227 /*
1228 * For isochronous transfer driver completes request on
1229 * IOC or on TRBERR. IOC appears only when device receive
1230 * OUT data packet. If host disable stream or lost some packet
1231 * then the only way to finish all queued transfer is to do it
1232 * on TRBERR event.
1233 */
1234 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC &&
1235 !priv_ep->wa1_set) {
1236 if (!priv_ep->dir) {
1237 u32 ep_cfg = readl(&priv_dev->regs->ep_cfg);
1238
1239 ep_cfg &= ~EP_CFG_ENABLE;
1240 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1241 priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN;
1242 }
1243 cdns3_transfer_completed(priv_dev, priv_ep);
1244 } else if (!(priv_ep->flags & EP_STALLED) &&
1245 !(priv_ep->flags & EP_STALL_PENDING)) {
1246 if (priv_ep->flags & EP_DEFERRED_DRDY) {
1247 priv_ep->flags &= ~EP_DEFERRED_DRDY;
1248 cdns3_start_all_request(priv_dev, priv_ep);
1249 } else {
1250 cdns3_rearm_transfer(priv_ep,
1251 priv_ep->wa1_set);
1252 }
1253 }
1254 }
1255
1256 if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
1257 if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
1258 if (ep_sts_reg & EP_STS_ISP)
1259 priv_ep->flags |= EP_QUIRK_END_TRANSFER;
1260 else
1261 priv_ep->flags &= ~EP_QUIRK_END_TRANSFER;
1262 }
1263
1264 cdns3_transfer_completed(priv_dev, priv_ep);
1265 }
1266
1267 /*
1268 * WA2: this condition should only be meet when
1269 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or
1270 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN.
1271 * In other cases this interrupt will be disabled/
1272 */
1273 if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 &&
1274 !(priv_ep->flags & EP_STALLED))
1275 cdns3_wa2_descmissing_packet(priv_ep);
1276
1277 return 0;
1278}
1279
1280static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev)
1281{
1282 if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) {
1283 spin_unlock(&priv_dev->lock);
1284 priv_dev->gadget_driver->disconnect(&priv_dev->gadget);
1285 spin_lock(&priv_dev->lock);
1286 }
1287}
1288
1289/**
1290 * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device
1291 * @priv_dev: extended gadget object
1292 * @usb_ists: bitmap representation of device's reported interrupts
1293 * (usb_ists register value)
1294 */
1295static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
1296 u32 usb_ists)
1297{
1298 int speed = 0;
1299
1300 trace_cdns3_usb_irq(priv_dev, usb_ists);
1301 if (usb_ists & USB_ISTS_L1ENTI) {
1302 /*
1303 * WORKAROUND: CDNS3 controller has issue with hardware resuming
1304 * from L1. To fix it, if any DMA transfer is pending driver
1305 * must starts driving resume signal immediately.
1306 */
1307 if (readl(&priv_dev->regs->drbl))
1308 __cdns3_gadget_wakeup(priv_dev);
1309 }
1310
1311 /* Connection detected */
1312 if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
1313 speed = cdns3_get_speed(priv_dev);
1314 priv_dev->gadget.speed = speed;
1315 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED);
1316 cdns3_ep0_config(priv_dev);
1317 }
1318
1319 /* Disconnection detected */
1320 if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
1321 cdns3_disconnect_gadget(priv_dev);
1322 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
1323 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
1324 cdns3_hw_reset_eps_config(priv_dev);
1325 }
1326
1327 if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) {
1328 if (priv_dev->gadget_driver &&
1329 priv_dev->gadget_driver->suspend) {
1330 spin_unlock(&priv_dev->lock);
1331 priv_dev->gadget_driver->suspend(&priv_dev->gadget);
1332 spin_lock(&priv_dev->lock);
1333 }
1334 }
1335
1336 if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) {
1337 if (priv_dev->gadget_driver &&
1338 priv_dev->gadget_driver->resume) {
1339 spin_unlock(&priv_dev->lock);
1340 priv_dev->gadget_driver->resume(&priv_dev->gadget);
1341 spin_lock(&priv_dev->lock);
1342 }
1343 }
1344
1345 /* reset*/
1346 if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) {
1347 if (priv_dev->gadget_driver) {
1348 spin_unlock(&priv_dev->lock);
1349 usb_gadget_udc_reset(&priv_dev->gadget,
1350 priv_dev->gadget_driver);
1351 spin_lock(&priv_dev->lock);
1352
1353 /*read again to check the actual speed*/
1354 speed = cdns3_get_speed(priv_dev);
1355 priv_dev->gadget.speed = speed;
1356 cdns3_hw_reset_eps_config(priv_dev);
1357 cdns3_ep0_config(priv_dev);
1358 }
1359 }
1360}
1361
1362/**
1363 * cdns3_device_irq_handler- interrupt handler for device part of controller
1364 *
1365 * @irq: irq number for cdns3 core device
1366 * @data: structure of cdns3
1367 *
1368 * Returns IRQ_HANDLED or IRQ_NONE
1369 */
1370static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
1371{
1372 struct cdns3_device *priv_dev;
1373 struct cdns3 *cdns = data;
1374 irqreturn_t ret = IRQ_NONE;
1375 u32 reg;
1376
1377 priv_dev = cdns->gadget_dev;
1378
1379 /* check USB device interrupt */
1380 reg = readl(&priv_dev->regs->usb_ists);
1381 if (reg) {
1382 /* After masking interrupts the new interrupts won't be
1383 * reported in usb_ists/ep_ists. In order to not lose some
1384 * of them driver disables only detected interrupts.
1385 * They will be enabled ASAP after clearing source of
1386 * interrupt. This an unusual behavior only applies to
1387 * usb_ists register.
1388 */
1389 reg = ~reg & readl(&priv_dev->regs->usb_ien);
1390 /* mask deferred interrupt. */
1391 writel(reg, &priv_dev->regs->usb_ien);
1392 ret = IRQ_WAKE_THREAD;
1393 }
1394
1395 /* check endpoint interrupt */
1396 reg = readl(&priv_dev->regs->ep_ists);
1397 if (reg) {
1398 writel(0, &priv_dev->regs->ep_ien);
1399 ret = IRQ_WAKE_THREAD;
1400 }
1401
1402 return ret;
1403}
1404
1405/**
1406 * cdns3_device_thread_irq_handler- interrupt handler for device part
1407 * of controller
1408 *
1409 * @irq: irq number for cdns3 core device
1410 * @data: structure of cdns3
1411 *
1412 * Returns IRQ_HANDLED or IRQ_NONE
1413 */
1414static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data)
1415{
1416 struct cdns3_device *priv_dev;
1417 struct cdns3 *cdns = data;
1418 irqreturn_t ret = IRQ_NONE;
1419 unsigned long flags;
1420 int bit;
1421 u32 reg;
1422
1423 priv_dev = cdns->gadget_dev;
1424 spin_lock_irqsave(&priv_dev->lock, flags);
1425
1426 reg = readl(&priv_dev->regs->usb_ists);
1427 if (reg) {
1428 writel(reg, &priv_dev->regs->usb_ists);
1429 writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
1430 cdns3_check_usb_interrupt_proceed(priv_dev, reg);
1431 ret = IRQ_HANDLED;
1432 }
1433
1434 reg = readl(&priv_dev->regs->ep_ists);
1435
1436 /* handle default endpoint OUT */
1437 if (reg & EP_ISTS_EP_OUT0) {
1438 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT);
1439 ret = IRQ_HANDLED;
1440 }
1441
1442 /* handle default endpoint IN */
1443 if (reg & EP_ISTS_EP_IN0) {
1444 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN);
1445 ret = IRQ_HANDLED;
1446 }
1447
1448 /* check if interrupt from non default endpoint, if no exit */
1449 reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0);
1450 if (!reg)
1451 goto irqend;
1452
1453 for_each_set_bit(bit, (unsigned long *)&reg,
1454 sizeof(u32) * BITS_PER_BYTE) {
1455 cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]);
1456 ret = IRQ_HANDLED;
1457 }
1458
1459irqend:
1460 writel(~0, &priv_dev->regs->ep_ien);
1461 spin_unlock_irqrestore(&priv_dev->lock, flags);
1462
1463 return ret;
1464}
1465
1466/**
1467 * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP
1468 *
1469 * The real reservation will occur during write to EP_CFG register,
1470 * this function is used to check if the 'size' reservation is allowed.
1471 *
1472 * @priv_dev: extended gadget object
1473 * @size: the size (KB) for EP would like to allocate
1474 * @is_in: endpoint direction
1475 *
1476 * Return 0 if the required size can met or negative value on failure
1477 */
1478static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev,
1479 int size, int is_in)
1480{
1481 int remained;
1482
1483 /* 2KB are reserved for EP0*/
1484 remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2;
1485
1486 if (is_in) {
1487 if (remained < size)
1488 return -EPERM;
1489
1490 priv_dev->onchip_used_size += size;
1491 } else {
1492 int required;
1493
1494 /**
1495 * ALL OUT EPs are shared the same chunk onchip memory, so
1496 * driver checks if it already has assigned enough buffers
1497 */
1498 if (priv_dev->out_mem_is_allocated >= size)
1499 return 0;
1500
1501 required = size - priv_dev->out_mem_is_allocated;
1502
1503 if (required > remained)
1504 return -EPERM;
1505
1506 priv_dev->out_mem_is_allocated += required;
1507 priv_dev->onchip_used_size += required;
1508 }
1509
1510 return 0;
1511}
1512
1513void cdns3_configure_dmult(struct cdns3_device *priv_dev,
1514 struct cdns3_endpoint *priv_ep)
1515{
1516 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
1517
1518 /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
1519 if (priv_dev->dev_ver <= DEV_VER_V2)
1520 writel(USB_CONF_DMULT, &regs->usb_conf);
1521
1522 if (priv_dev->dev_ver == DEV_VER_V2)
1523 writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2);
1524
1525 if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) {
1526 u32 mask;
1527
1528 if (priv_ep->dir)
1529 mask = BIT(priv_ep->num + 16);
1530 else
1531 mask = BIT(priv_ep->num);
1532
1533 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
1534 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1535 cdns3_set_register_bit(&regs->tdl_beh, mask);
1536 cdns3_set_register_bit(&regs->tdl_beh2, mask);
1537 cdns3_set_register_bit(&regs->dma_adv_td, mask);
1538 }
1539
1540 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1541 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1542
1543 cdns3_set_register_bit(&regs->dtrans, mask);
1544 }
1545}
1546
1547/**
1548 * cdns3_ep_config Configure hardware endpoint
1549 * @priv_ep: extended endpoint object
1550 */
1551void cdns3_ep_config(struct cdns3_endpoint *priv_ep)
1552{
1553 bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC);
1554 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1555 u32 bEndpointAddress = priv_ep->num | priv_ep->dir;
1556 u32 max_packet_size = 0;
1557 u8 maxburst = 0;
1558 u32 ep_cfg = 0;
1559 u8 buffering;
1560 u8 mult = 0;
1561 int ret;
1562
1563 buffering = CDNS3_EP_BUF_SIZE - 1;
1564
1565 cdns3_configure_dmult(priv_dev, priv_ep);
1566
1567 switch (priv_ep->type) {
1568 case USB_ENDPOINT_XFER_INT:
1569 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT);
1570
1571 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1572 priv_dev->dev_ver > DEV_VER_V2)
1573 ep_cfg |= EP_CFG_TDL_CHK;
1574 break;
1575 case USB_ENDPOINT_XFER_BULK:
1576 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK);
1577
1578 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1579 priv_dev->dev_ver > DEV_VER_V2)
1580 ep_cfg |= EP_CFG_TDL_CHK;
1581 break;
1582 default:
1583 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
1584 mult = CDNS3_EP_ISO_HS_MULT - 1;
1585 buffering = mult + 1;
1586 }
1587
1588 switch (priv_dev->gadget.speed) {
1589 case USB_SPEED_FULL:
1590 max_packet_size = is_iso_ep ? 1023 : 64;
1591 break;
1592 case USB_SPEED_HIGH:
1593 max_packet_size = is_iso_ep ? 1024 : 512;
1594 break;
1595 case USB_SPEED_SUPER:
1596 /* It's limitation that driver assumes in driver. */
1597 mult = 0;
1598 max_packet_size = 1024;
1599 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1600 maxburst = CDNS3_EP_ISO_SS_BURST - 1;
1601 buffering = (mult + 1) *
1602 (maxburst + 1);
1603
1604 if (priv_ep->interval > 1)
1605 buffering++;
1606 } else {
1607 maxburst = CDNS3_EP_BUF_SIZE - 1;
1608 }
1609 break;
1610 default:
1611 /* all other speed are not supported */
1612 return;
1613 }
1614
1615 if (max_packet_size == 1024)
1616 priv_ep->trb_burst_size = 128;
1617 else if (max_packet_size >= 512)
1618 priv_ep->trb_burst_size = 64;
1619 else
1620 priv_ep->trb_burst_size = 16;
1621
1622 ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
1623 !!priv_ep->dir);
1624 if (ret) {
1625 dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n");
1626 return;
1627 }
1628
1629 ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) |
1630 EP_CFG_MULT(mult) |
1631 EP_CFG_BUFFERING(buffering) |
1632 EP_CFG_MAXBURST(maxburst);
1633
1634 cdns3_select_ep(priv_dev, bEndpointAddress);
1635 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1636
1637 dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n",
1638 priv_ep->name, ep_cfg);
1639}
1640
1641/* Find correct direction for HW endpoint according to description */
1642static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc,
1643 struct cdns3_endpoint *priv_ep)
1644{
1645 return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) ||
1646 (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc));
1647}
1648
1649static struct
1650cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev,
1651 struct usb_endpoint_descriptor *desc)
1652{
1653 struct usb_ep *ep;
1654 struct cdns3_endpoint *priv_ep;
1655
1656 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
1657 unsigned long num;
1658 int ret;
1659 /* ep name pattern likes epXin or epXout */
1660 char c[2] = {ep->name[2], '\0'};
1661
1662 ret = kstrtoul(c, 10, &num);
1663 if (ret)
1664 return ERR_PTR(ret);
1665
1666 priv_ep = ep_to_cdns3_ep(ep);
1667 if (cdns3_ep_dir_is_correct(desc, priv_ep)) {
1668 if (!(priv_ep->flags & EP_CLAIMED)) {
1669 priv_ep->num = num;
1670 return priv_ep;
1671 }
1672 }
1673 }
1674
1675 return ERR_PTR(-ENOENT);
1676}
1677
1678/*
1679 * Cadence IP has one limitation that all endpoints must be configured
1680 * (Type & MaxPacketSize) before setting configuration through hardware
1681 * register, it means we can't change endpoints configuration after
1682 * set_configuration.
1683 *
1684 * This function set EP_CLAIMED flag which is added when the gadget driver
1685 * uses usb_ep_autoconfig to configure specific endpoint;
1686 * When the udc driver receives set_configurion request,
1687 * it goes through all claimed endpoints, and configure all endpoints
1688 * accordingly.
1689 *
1690 * At usb_ep_ops.enable/disable, we only enable and disable endpoint through
1691 * ep_cfg register which can be changed after set_configuration, and do
1692 * some software operation accordingly.
1693 */
1694static struct
1695usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget,
1696 struct usb_endpoint_descriptor *desc,
1697 struct usb_ss_ep_comp_descriptor *comp_desc)
1698{
1699 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1700 struct cdns3_endpoint *priv_ep;
1701 unsigned long flags;
1702
1703 priv_ep = cdns3_find_available_ep(priv_dev, desc);
1704 if (IS_ERR(priv_ep)) {
1705 dev_err(priv_dev->dev, "no available ep\n");
1706 return NULL;
1707 }
1708
1709 dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name);
1710
1711 spin_lock_irqsave(&priv_dev->lock, flags);
1712 priv_ep->endpoint.desc = desc;
1713 priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
1714 priv_ep->type = usb_endpoint_type(desc);
1715 priv_ep->flags |= EP_CLAIMED;
1716 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1717
1718 spin_unlock_irqrestore(&priv_dev->lock, flags);
1719 return &priv_ep->endpoint;
1720}
1721
1722/**
1723 * cdns3_gadget_ep_alloc_request Allocates request
1724 * @ep: endpoint object associated with request
1725 * @gfp_flags: gfp flags
1726 *
1727 * Returns allocated request address, NULL on allocation error
1728 */
1729struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1730 gfp_t gfp_flags)
1731{
1732 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1733 struct cdns3_request *priv_req;
1734
1735 priv_req = kzalloc(sizeof(*priv_req), gfp_flags);
1736 if (!priv_req)
1737 return NULL;
1738
1739 priv_req->priv_ep = priv_ep;
1740
1741 trace_cdns3_alloc_request(priv_req);
1742 return &priv_req->request;
1743}
1744
1745/**
1746 * cdns3_gadget_ep_free_request Free memory occupied by request
1747 * @ep: endpoint object associated with request
1748 * @request: request to free memory
1749 */
1750void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1751 struct usb_request *request)
1752{
1753 struct cdns3_request *priv_req = to_cdns3_request(request);
1754
1755 if (priv_req->aligned_buf)
1756 priv_req->aligned_buf->in_use = 0;
1757
1758 trace_cdns3_free_request(priv_req);
1759 kfree(priv_req);
1760}
1761
1762/**
1763 * cdns3_gadget_ep_enable Enable endpoint
1764 * @ep: endpoint object
1765 * @desc: endpoint descriptor
1766 *
1767 * Returns 0 on success, error code elsewhere
1768 */
1769static int cdns3_gadget_ep_enable(struct usb_ep *ep,
1770 const struct usb_endpoint_descriptor *desc)
1771{
1772 struct cdns3_endpoint *priv_ep;
1773 struct cdns3_device *priv_dev;
1774 u32 reg = EP_STS_EN_TRBERREN;
1775 u32 bEndpointAddress;
1776 unsigned long flags;
1777 int enable = 1;
1778 int ret;
1779 int val;
1780
1781 priv_ep = ep_to_cdns3_ep(ep);
1782 priv_dev = priv_ep->cdns3_dev;
1783
1784 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1785 dev_dbg(priv_dev->dev, "usbss: invalid parameters\n");
1786 return -EINVAL;
1787 }
1788
1789 if (!desc->wMaxPacketSize) {
1790 dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n");
1791 return -EINVAL;
1792 }
1793
1794 if (dev_WARN_ONCE(priv_dev->dev, priv_ep->flags & EP_ENABLED,
1795 "%s is already enabled\n", priv_ep->name))
1796 return 0;
1797
1798 spin_lock_irqsave(&priv_dev->lock, flags);
1799
1800 priv_ep->endpoint.desc = desc;
1801 priv_ep->type = usb_endpoint_type(desc);
1802 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1803
1804 if (priv_ep->interval > ISO_MAX_INTERVAL &&
1805 priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1806 dev_err(priv_dev->dev, "Driver is limited to %d period\n",
1807 ISO_MAX_INTERVAL);
1808
1809 ret = -EINVAL;
1810 goto exit;
1811 }
1812
1813 ret = cdns3_allocate_trb_pool(priv_ep);
1814
1815 if (ret)
1816 goto exit;
1817
1818 bEndpointAddress = priv_ep->num | priv_ep->dir;
1819 cdns3_select_ep(priv_dev, bEndpointAddress);
1820
1821 trace_cdns3_gadget_ep_enable(priv_ep);
1822
1823 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1824
1825 ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1826 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1827 1, 1000);
1828
1829 if (unlikely(ret)) {
1830 cdns3_free_trb_pool(priv_ep);
1831 ret = -EINVAL;
1832 goto exit;
1833 }
1834
1835 /* enable interrupt for selected endpoint */
1836 cdns3_set_register_bit(&priv_dev->regs->ep_ien,
1837 BIT(cdns3_ep_addr_to_index(bEndpointAddress)));
1838
1839 if (priv_dev->dev_ver < DEV_VER_V2)
1840 cdns3_wa2_enable_detection(priv_dev, priv_ep, reg);
1841
1842 writel(reg, &priv_dev->regs->ep_sts_en);
1843
1844 /*
1845 * For some versions of controller at some point during ISO OUT traffic
1846 * DMA reads Transfer Ring for the EP which has never got doorbell.
1847 * This issue was detected only on simulation, but to avoid this issue
1848 * driver add protection against it. To fix it driver enable ISO OUT
1849 * endpoint before setting DRBL. This special treatment of ISO OUT
1850 * endpoints are recommended by controller specification.
1851 */
1852 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1853 enable = 0;
1854
1855 if (enable)
1856 cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE);
1857
1858 ep->desc = desc;
1859 priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING |
1860 EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN);
1861 priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR;
1862 priv_ep->wa1_set = 0;
1863 priv_ep->enqueue = 0;
1864 priv_ep->dequeue = 0;
1865 reg = readl(&priv_dev->regs->ep_sts);
1866 priv_ep->pcs = !!EP_STS_CCS(reg);
1867 priv_ep->ccs = !!EP_STS_CCS(reg);
1868 /* one TRB is reserved for link TRB used in DMULT mode*/
1869 priv_ep->free_trbs = priv_ep->num_trbs - 1;
1870exit:
1871 spin_unlock_irqrestore(&priv_dev->lock, flags);
1872
1873 return ret;
1874}
1875
1876/**
1877 * cdns3_gadget_ep_disable Disable endpoint
1878 * @ep: endpoint object
1879 *
1880 * Returns 0 on success, error code elsewhere
1881 */
1882static int cdns3_gadget_ep_disable(struct usb_ep *ep)
1883{
1884 struct cdns3_endpoint *priv_ep;
1885 struct cdns3_request *priv_req;
1886 struct cdns3_device *priv_dev;
1887 struct usb_request *request;
1888 unsigned long flags;
1889 int ret = 0;
1890 u32 ep_cfg;
1891 int val;
1892
1893 if (!ep) {
1894 pr_err("usbss: invalid parameters\n");
1895 return -EINVAL;
1896 }
1897
1898 priv_ep = ep_to_cdns3_ep(ep);
1899 priv_dev = priv_ep->cdns3_dev;
1900
1901 if (dev_WARN_ONCE(priv_dev->dev, !(priv_ep->flags & EP_ENABLED),
1902 "%s is already disabled\n", priv_ep->name))
1903 return 0;
1904
1905 spin_lock_irqsave(&priv_dev->lock, flags);
1906
1907 trace_cdns3_gadget_ep_disable(priv_ep);
1908
1909 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
1910
1911 ep_cfg = readl(&priv_dev->regs->ep_cfg);
1912 ep_cfg &= ~EP_CFG_ENABLE;
1913 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1914
1915 /**
1916 * Driver needs some time before resetting endpoint.
1917 * It need waits for clearing DBUSY bit or for timeout expired.
1918 * 10us is enough time for controller to stop transfer.
1919 */
1920 readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val,
1921 !(val & EP_STS_DBUSY), 1, 10);
1922 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1923
1924 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1925 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1926 1, 1000);
1927 if (unlikely(ret))
1928 dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n",
1929 priv_ep->name);
1930
1931 while (!list_empty(&priv_ep->pending_req_list)) {
1932 request = cdns3_next_request(&priv_ep->pending_req_list);
1933
1934 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1935 -ESHUTDOWN);
1936 }
1937
1938 while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
1939 priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
1940
1941 kfree(priv_req->request.buf);
1942 cdns3_gadget_ep_free_request(&priv_ep->endpoint,
1943 &priv_req->request);
1944 list_del_init(&priv_req->list);
1945 --priv_ep->wa2_counter;
1946 }
1947
1948 while (!list_empty(&priv_ep->deferred_req_list)) {
1949 request = cdns3_next_request(&priv_ep->deferred_req_list);
1950
1951 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1952 -ESHUTDOWN);
1953 }
1954
1955 priv_ep->descmis_req = NULL;
1956
1957 ep->desc = NULL;
1958 priv_ep->flags &= ~EP_ENABLED;
1959
1960 spin_unlock_irqrestore(&priv_dev->lock, flags);
1961
1962 return ret;
1963}
1964
1965/**
1966 * cdns3_gadget_ep_queue Transfer data on endpoint
1967 * @ep: endpoint object
1968 * @request: request object
1969 * @gfp_flags: gfp flags
1970 *
1971 * Returns 0 on success, error code elsewhere
1972 */
1973static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
1974 struct usb_request *request,
1975 gfp_t gfp_flags)
1976{
1977 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1978 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1979 struct cdns3_request *priv_req;
1980 int ret = 0;
1981
1982 request->actual = 0;
1983 request->status = -EINPROGRESS;
1984 priv_req = to_cdns3_request(request);
1985 trace_cdns3_ep_queue(priv_req);
1986
1987 if (priv_dev->dev_ver < DEV_VER_V2) {
1988 ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep,
1989 priv_req);
1990
1991 if (ret == EINPROGRESS)
1992 return 0;
1993 }
1994
1995 ret = cdns3_prepare_aligned_request_buf(priv_req);
1996 if (ret < 0)
1997 return ret;
1998
1999 ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request,
2000 usb_endpoint_dir_in(ep->desc));
2001 if (ret)
2002 return ret;
2003
2004 list_add_tail(&request->list, &priv_ep->deferred_req_list);
2005
2006 /*
2007 * If hardware endpoint configuration has not been set yet then
2008 * just queue request in deferred list. Transfer will be started in
2009 * cdns3_set_hw_configuration.
2010 */
2011 if (priv_dev->hw_configured_flag && !(priv_ep->flags & EP_STALLED) &&
2012 !(priv_ep->flags & EP_STALL_PENDING))
2013 cdns3_start_all_request(priv_dev, priv_ep);
2014
2015 return 0;
2016}
2017
2018static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2019 gfp_t gfp_flags)
2020{
2021 struct usb_request *zlp_request;
2022 struct cdns3_endpoint *priv_ep;
2023 struct cdns3_device *priv_dev;
2024 unsigned long flags;
2025 int ret;
2026
2027 if (!request || !ep)
2028 return -EINVAL;
2029
2030 priv_ep = ep_to_cdns3_ep(ep);
2031 priv_dev = priv_ep->cdns3_dev;
2032
2033 spin_lock_irqsave(&priv_dev->lock, flags);
2034
2035 ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags);
2036
2037 if (ret == 0 && request->zero && request->length &&
2038 (request->length % ep->maxpacket == 0)) {
2039 struct cdns3_request *priv_req;
2040
2041 zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
2042 zlp_request->buf = priv_dev->zlp_buf;
2043 zlp_request->length = 0;
2044
2045 priv_req = to_cdns3_request(zlp_request);
2046 priv_req->flags |= REQUEST_ZLP;
2047
2048 dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n",
2049 priv_ep->name);
2050 ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags);
2051 }
2052
2053 spin_unlock_irqrestore(&priv_dev->lock, flags);
2054 return ret;
2055}
2056
2057/**
2058 * cdns3_gadget_ep_dequeue Remove request from transfer queue
2059 * @ep: endpoint object associated with request
2060 * @request: request object
2061 *
2062 * Returns 0 on success, error code elsewhere
2063 */
2064int cdns3_gadget_ep_dequeue(struct usb_ep *ep,
2065 struct usb_request *request)
2066{
2067 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
2068 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2069 struct usb_request *req, *req_temp;
2070 struct cdns3_request *priv_req;
2071 struct cdns3_trb *link_trb;
2072 unsigned long flags;
2073 int ret = 0;
2074
2075 if (!ep || !request || !ep->desc)
2076 return -EINVAL;
2077
2078 spin_lock_irqsave(&priv_dev->lock, flags);
2079
2080 priv_req = to_cdns3_request(request);
2081
2082 trace_cdns3_ep_dequeue(priv_req);
2083
2084 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
2085
2086 list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list,
2087 list) {
2088 if (request == req)
2089 goto found;
2090 }
2091
2092 list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list,
2093 list) {
2094 if (request == req)
2095 goto found;
2096 }
2097
2098 goto not_found;
2099
2100found:
2101
2102 if (priv_ep->wa1_trb == priv_req->trb)
2103 cdns3_wa1_restore_cycle_bit(priv_ep);
2104
2105 link_trb = priv_req->trb;
2106 cdns3_move_deq_to_next_trb(priv_req);
2107 cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET);
2108
2109 /* Update ring */
2110 request = cdns3_next_request(&priv_ep->deferred_req_list);
2111 if (request) {
2112 priv_req = to_cdns3_request(request);
2113
2114 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
2115 (priv_req->start_trb * TRB_SIZE));
2116 link_trb->control = (link_trb->control & TRB_CYCLE) |
2117 TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE;
2118 } else {
2119 priv_ep->flags |= EP_UPDATE_EP_TRBADDR;
2120 }
2121
2122not_found:
2123 spin_unlock_irqrestore(&priv_dev->lock, flags);
2124 return ret;
2125}
2126
2127/**
2128 * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint
2129 * Should be called after acquiring spin_lock and selecting ep
2130 * @ep: endpoint object to set stall on.
2131 */
2132void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep)
2133{
2134 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2135
2136 trace_cdns3_halt(priv_ep, 1, 0);
2137
2138 if (!(priv_ep->flags & EP_STALLED)) {
2139 u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
2140
2141 if (!(ep_sts_reg & EP_STS_DBUSY))
2142 cdns3_ep_stall_flush(priv_ep);
2143 else
2144 priv_ep->flags |= EP_STALL_PENDING;
2145 }
2146}
2147
2148/**
2149 * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint
2150 * Should be called after acquiring spin_lock and selecting ep
2151 * @ep: endpoint object to clear stall on
2152 */
2153int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
2154{
2155 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2156 struct usb_request *request;
2157 int ret = 0;
2158 int val;
2159
2160 trace_cdns3_halt(priv_ep, 0, 0);
2161
2162 writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2163
2164 /* wait for EPRST cleared */
2165 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
2166 !(val & EP_CMD_EPRST), 1, 100);
2167 if (ret)
2168 return -EINVAL;
2169
2170 priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
2171
2172 request = cdns3_next_request(&priv_ep->pending_req_list);
2173
2174 if (request)
2175 cdns3_rearm_transfer(priv_ep, 1);
2176
2177 cdns3_start_all_request(priv_dev, priv_ep);
2178 return ret;
2179}
2180
2181/**
2182 * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint
2183 * @ep: endpoint object to set/clear stall on
2184 * @value: 1 for set stall, 0 for clear stall
2185 *
2186 * Returns 0 on success, error code elsewhere
2187 */
2188int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2189{
2190 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
2191 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
2192 unsigned long flags;
2193 int ret = 0;
2194
2195 if (!(priv_ep->flags & EP_ENABLED))
2196 return -EPERM;
2197
2198 spin_lock_irqsave(&priv_dev->lock, flags);
2199
2200 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
2201
2202 if (!value) {
2203 priv_ep->flags &= ~EP_WEDGE;
2204 ret = __cdns3_gadget_ep_clear_halt(priv_ep);
2205 } else {
2206 __cdns3_gadget_ep_set_halt(priv_ep);
2207 }
2208
2209 spin_unlock_irqrestore(&priv_dev->lock, flags);
2210
2211 return ret;
2212}
2213
2214extern const struct usb_ep_ops cdns3_gadget_ep0_ops;
2215
2216static const struct usb_ep_ops cdns3_gadget_ep_ops = {
2217 .enable = cdns3_gadget_ep_enable,
2218 .disable = cdns3_gadget_ep_disable,
2219 .alloc_request = cdns3_gadget_ep_alloc_request,
2220 .free_request = cdns3_gadget_ep_free_request,
2221 .queue = cdns3_gadget_ep_queue,
2222 .dequeue = cdns3_gadget_ep_dequeue,
2223 .set_halt = cdns3_gadget_ep_set_halt,
2224 .set_wedge = cdns3_gadget_ep_set_wedge,
2225};
2226
2227/**
2228 * cdns3_gadget_get_frame Returns number of actual ITP frame
2229 * @gadget: gadget object
2230 *
2231 * Returns number of actual ITP frame
2232 */
2233static int cdns3_gadget_get_frame(struct usb_gadget *gadget)
2234{
2235 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2236
2237 return readl(&priv_dev->regs->usb_itpn);
2238}
2239
2240int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
2241{
2242 enum usb_device_speed speed;
2243
2244 speed = cdns3_get_speed(priv_dev);
2245
2246 if (speed >= USB_SPEED_SUPER)
2247 return 0;
2248
2249 /* Start driving resume signaling to indicate remote wakeup. */
2250 writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
2251
2252 return 0;
2253}
2254
2255static int cdns3_gadget_wakeup(struct usb_gadget *gadget)
2256{
2257 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2258 unsigned long flags;
2259 int ret = 0;
2260
2261 spin_lock_irqsave(&priv_dev->lock, flags);
2262 ret = __cdns3_gadget_wakeup(priv_dev);
2263 spin_unlock_irqrestore(&priv_dev->lock, flags);
2264 return ret;
2265}
2266
2267static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget,
2268 int is_selfpowered)
2269{
2270 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2271 unsigned long flags;
2272
2273 spin_lock_irqsave(&priv_dev->lock, flags);
2274 priv_dev->is_selfpowered = !!is_selfpowered;
2275 spin_unlock_irqrestore(&priv_dev->lock, flags);
2276 return 0;
2277}
2278
2279static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
2280{
2281 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2282
2283 if (is_on)
2284 writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
2285 else
2286 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
2287
2288 return 0;
2289}
2290
2291static void cdns3_gadget_config(struct cdns3_device *priv_dev)
2292{
2293 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
2294 u32 reg;
2295
2296 cdns3_ep0_config(priv_dev);
2297
2298 /* enable interrupts for endpoint 0 (in and out) */
2299 writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, &regs->ep_ien);
2300
2301 /*
2302 * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
2303 * revision of controller.
2304 */
2305 if (priv_dev->dev_ver == DEV_VER_TI_V1) {
2306 reg = readl(&regs->dbg_link1);
2307
2308 reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
2309 reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
2310 DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
2311 writel(reg, &regs->dbg_link1);
2312 }
2313
2314 /*
2315 * By default some platforms has set protected access to memory.
2316 * This cause problem with cache, so driver restore non-secure
2317 * access to memory.
2318 */
2319 reg = readl(&regs->dma_axi_ctrl);
2320 reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
2321 DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
2322 writel(reg, &regs->dma_axi_ctrl);
2323
2324 /* enable generic interrupt*/
2325 writel(USB_IEN_INIT, &regs->usb_ien);
2326 writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf);
2327
2328 cdns3_configure_dmult(priv_dev, NULL);
2329
2330 cdns3_gadget_pullup(&priv_dev->gadget, 1);
2331}
2332
2333/**
2334 * cdns3_gadget_udc_start Gadget start
2335 * @gadget: gadget object
2336 * @driver: driver which operates on this gadget
2337 *
2338 * Returns 0 on success, error code elsewhere
2339 */
2340static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
2341 struct usb_gadget_driver *driver)
2342{
2343 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2344 unsigned long flags;
2345
2346 spin_lock_irqsave(&priv_dev->lock, flags);
2347 priv_dev->gadget_driver = driver;
2348 cdns3_gadget_config(priv_dev);
2349 spin_unlock_irqrestore(&priv_dev->lock, flags);
2350 return 0;
2351}
2352
2353/**
2354 * cdns3_gadget_udc_stop Stops gadget
2355 * @gadget: gadget object
2356 *
2357 * Returns 0
2358 */
2359static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
2360{
2361 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2362 struct cdns3_endpoint *priv_ep;
2363 u32 bEndpointAddress;
2364 struct usb_ep *ep;
2365 int ret = 0;
2366 int val;
2367
2368 priv_dev->gadget_driver = NULL;
2369
2370 priv_dev->onchip_used_size = 0;
2371 priv_dev->out_mem_is_allocated = 0;
2372 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2373
2374 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
2375 priv_ep = ep_to_cdns3_ep(ep);
2376 bEndpointAddress = priv_ep->num | priv_ep->dir;
2377 cdns3_select_ep(priv_dev, bEndpointAddress);
2378 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2379 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
2380 !(val & EP_CMD_EPRST), 1, 100);
2381 }
2382
2383 /* disable interrupt for device */
2384 writel(0, &priv_dev->regs->usb_ien);
2385 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
2386
2387 return ret;
2388}
2389
2390static const struct usb_gadget_ops cdns3_gadget_ops = {
2391 .get_frame = cdns3_gadget_get_frame,
2392 .wakeup = cdns3_gadget_wakeup,
2393 .set_selfpowered = cdns3_gadget_set_selfpowered,
2394 .pullup = cdns3_gadget_pullup,
2395 .udc_start = cdns3_gadget_udc_start,
2396 .udc_stop = cdns3_gadget_udc_stop,
2397 .match_ep = cdns3_gadget_match_ep,
2398};
2399
2400static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
2401{
2402 int i;
2403
2404 /* ep0 OUT point to ep0 IN. */
2405 priv_dev->eps[16] = NULL;
2406
2407 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
2408 if (priv_dev->eps[i]) {
2409 cdns3_free_trb_pool(priv_dev->eps[i]);
2410 devm_kfree(priv_dev->dev, priv_dev->eps[i]);
2411 }
2412}
2413
2414/**
2415 * cdns3_init_eps Initializes software endpoints of gadget
2416 * @cdns3: extended gadget object
2417 *
2418 * Returns 0 on success, error code elsewhere
2419 */
2420static int cdns3_init_eps(struct cdns3_device *priv_dev)
2421{
2422 u32 ep_enabled_reg, iso_ep_reg;
2423 struct cdns3_endpoint *priv_ep;
2424 int ep_dir, ep_number;
2425 u32 ep_mask;
2426 int ret = 0;
2427 int i;
2428
2429 /* Read it from USB_CAP3 to USB_CAP5 */
2430 ep_enabled_reg = readl(&priv_dev->regs->usb_cap3);
2431 iso_ep_reg = readl(&priv_dev->regs->usb_cap4);
2432
2433 dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n");
2434
2435 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
2436 ep_dir = i >> 4; /* i div 16 */
2437 ep_number = i & 0xF; /* i % 16 */
2438 ep_mask = BIT(i);
2439
2440 if (!(ep_enabled_reg & ep_mask))
2441 continue;
2442
2443 if (ep_dir && !ep_number) {
2444 priv_dev->eps[i] = priv_dev->eps[0];
2445 continue;
2446 }
2447
2448 priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep),
2449 GFP_KERNEL);
2450 if (!priv_ep) {
2451 ret = -ENOMEM;
2452 goto err;
2453 }
2454
2455 /* set parent of endpoint object */
2456 priv_ep->cdns3_dev = priv_dev;
2457 priv_dev->eps[i] = priv_ep;
2458 priv_ep->num = ep_number;
2459 priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT;
2460
2461 if (!ep_number) {
2462 ret = cdns3_init_ep0(priv_dev, priv_ep);
2463 if (ret) {
2464 dev_err(priv_dev->dev, "Failed to init ep0\n");
2465 goto err;
2466 }
2467 } else {
2468 snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s",
2469 ep_number, !!ep_dir ? "in" : "out");
2470 priv_ep->endpoint.name = priv_ep->name;
2471
2472 usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
2473 CDNS3_EP_MAX_PACKET_LIMIT);
2474 priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS;
2475 priv_ep->endpoint.ops = &cdns3_gadget_ep_ops;
2476 if (ep_dir)
2477 priv_ep->endpoint.caps.dir_in = 1;
2478 else
2479 priv_ep->endpoint.caps.dir_out = 1;
2480
2481 if (iso_ep_reg & ep_mask)
2482 priv_ep->endpoint.caps.type_iso = 1;
2483
2484 priv_ep->endpoint.caps.type_bulk = 1;
2485 priv_ep->endpoint.caps.type_int = 1;
2486
2487 list_add_tail(&priv_ep->endpoint.ep_list,
2488 &priv_dev->gadget.ep_list);
2489 }
2490
2491 priv_ep->flags = 0;
2492
2493 dev_info(priv_dev->dev, "Initialized %s support: %s %s\n",
2494 priv_ep->name,
2495 priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "",
2496 priv_ep->endpoint.caps.type_iso ? "ISO" : "");
2497
2498 INIT_LIST_HEAD(&priv_ep->pending_req_list);
2499 INIT_LIST_HEAD(&priv_ep->deferred_req_list);
2500 INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list);
2501 }
2502
2503 return 0;
2504err:
2505 cdns3_free_all_eps(priv_dev);
2506 return -ENOMEM;
2507}
2508
2509void cdns3_gadget_exit(struct cdns3 *cdns)
2510{
2511 struct cdns3_device *priv_dev;
2512
2513 priv_dev = cdns->gadget_dev;
2514
2515 devm_free_irq(cdns->dev, cdns->dev_irq, cdns);
2516
2517 pm_runtime_mark_last_busy(cdns->dev);
2518 pm_runtime_put_autosuspend(cdns->dev);
2519
2520 usb_del_gadget_udc(&priv_dev->gadget);
2521
2522 cdns3_free_all_eps(priv_dev);
2523
2524 while (!list_empty(&priv_dev->aligned_buf_list)) {
2525 struct cdns3_aligned_buf *buf;
2526
2527 buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list);
2528 dma_free_coherent(priv_dev->sysdev, buf->size,
2529 buf->buf,
2530 buf->dma);
2531
2532 list_del(&buf->list);
2533 kfree(buf);
2534 }
2535
2536 dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
2537 priv_dev->setup_dma);
2538
2539 kfree(priv_dev->zlp_buf);
2540 kfree(priv_dev);
2541 cdns->gadget_dev = NULL;
2542 cdns3_drd_switch_gadget(cdns, 0);
2543}
2544
2545static int cdns3_gadget_start(struct cdns3 *cdns)
2546{
2547 struct cdns3_device *priv_dev;
2548 u32 max_speed;
2549 int ret;
2550
2551 priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
2552 if (!priv_dev)
2553 return -ENOMEM;
2554
2555 cdns->gadget_dev = priv_dev;
2556 priv_dev->sysdev = cdns->dev;
2557 priv_dev->dev = cdns->dev;
2558 priv_dev->regs = cdns->dev_regs;
2559
2560 device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size",
2561 &priv_dev->onchip_buffers);
2562
2563 if (priv_dev->onchip_buffers <= 0) {
2564 u32 reg = readl(&priv_dev->regs->usb_cap2);
2565
2566 priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
2567 }
2568
2569 if (!priv_dev->onchip_buffers)
2570 priv_dev->onchip_buffers = 256;
2571
2572 max_speed = usb_get_maximum_speed(cdns->dev);
2573
2574 /* Check the maximum_speed parameter */
2575 switch (max_speed) {
2576 case USB_SPEED_FULL:
2577 writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
2578 break;
2579 case USB_SPEED_HIGH:
2580 writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
2581 break;
2582 case USB_SPEED_SUPER:
2583 break;
2584 default:
2585 dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
2586 max_speed);
2587 /* fall through */
2588 case USB_SPEED_UNKNOWN:
2589 /* default to superspeed */
2590 max_speed = USB_SPEED_SUPER;
2591 break;
2592 }
2593
2594 /* fill gadget fields */
2595 priv_dev->gadget.max_speed = max_speed;
2596 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2597 priv_dev->gadget.ops = &cdns3_gadget_ops;
2598 priv_dev->gadget.name = "usb-ss-gadget";
2599 priv_dev->gadget.sg_supported = 1;
2600 priv_dev->gadget.quirk_avoids_skb_reserve = 1;
2601
2602 spin_lock_init(&priv_dev->lock);
2603 INIT_WORK(&priv_dev->pending_status_wq,
2604 cdns3_pending_setup_status_handler);
2605
2606 INIT_WORK(&priv_dev->aligned_buf_wq,
2607 cdns3_free_aligned_request_buf);
2608
2609 /* initialize endpoint container */
2610 INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
2611 INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
2612
2613 ret = cdns3_init_eps(priv_dev);
2614 if (ret) {
2615 dev_err(priv_dev->dev, "Failed to create endpoints\n");
2616 goto err1;
2617 }
2618
2619 /* allocate memory for setup packet buffer */
2620 priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8,
2621 &priv_dev->setup_dma, GFP_DMA);
2622 if (!priv_dev->setup_buf) {
2623 ret = -ENOMEM;
2624 goto err2;
2625 }
2626
2627 priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
2628
2629 dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
2630 readl(&priv_dev->regs->usb_cap6));
2631 dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
2632 readl(&priv_dev->regs->usb_cap1));
2633 dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n",
2634 readl(&priv_dev->regs->usb_cap2));
2635
2636 priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
2637
2638 priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
2639 if (!priv_dev->zlp_buf) {
2640 ret = -ENOMEM;
2641 goto err3;
2642 }
2643
2644 /* add USB gadget device */
2645 ret = usb_add_gadget_udc(priv_dev->dev, &priv_dev->gadget);
2646 if (ret < 0) {
2647 dev_err(priv_dev->dev,
2648 "Failed to register USB device controller\n");
2649 goto err4;
2650 }
2651
2652 return 0;
2653err4:
2654 kfree(priv_dev->zlp_buf);
2655err3:
2656 dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
2657 priv_dev->setup_dma);
2658err2:
2659 cdns3_free_all_eps(priv_dev);
2660err1:
2661 cdns->gadget_dev = NULL;
2662 return ret;
2663}
2664
2665static int __cdns3_gadget_init(struct cdns3 *cdns)
2666{
2667 struct cdns3_device *priv_dev;
2668 int ret = 0;
2669
2670 cdns3_drd_switch_gadget(cdns, 1);
2671 pm_runtime_get_sync(cdns->dev);
2672
2673 ret = cdns3_gadget_start(cdns);
2674 if (ret)
2675 return ret;
2676
2677 priv_dev = cdns->gadget_dev;
2678
2679 /*
2680 * Because interrupt line can be shared with other components in
2681 * driver it can't use IRQF_ONESHOT flag here.
2682 */
2683 ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq,
2684 cdns3_device_irq_handler,
2685 cdns3_device_thread_irq_handler,
2686 IRQF_SHARED, dev_name(cdns->dev), cdns);
2687
2688 if (ret)
2689 goto err0;
2690
2691 return 0;
2692err0:
2693 cdns3_gadget_exit(cdns);
2694 return ret;
2695}
2696
2697static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup)
2698{
2699 struct cdns3_device *priv_dev = cdns->gadget_dev;
2700
2701 cdns3_disconnect_gadget(priv_dev);
2702
2703 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2704 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
2705 cdns3_hw_reset_eps_config(priv_dev);
2706
2707 /* disable interrupt for device */
2708 writel(0, &priv_dev->regs->usb_ien);
2709
2710 cdns3_gadget_pullup(&priv_dev->gadget, 0);
2711
2712 return 0;
2713}
2714
2715static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated)
2716{
2717 struct cdns3_device *priv_dev = cdns->gadget_dev;
2718
2719 if (!priv_dev->gadget_driver)
2720 return 0;
2721
2722 cdns3_gadget_config(priv_dev);
2723
2724 return 0;
2725}
2726
2727/**
2728 * cdns3_gadget_init - initialize device structure
2729 *
2730 * cdns: cdns3 instance
2731 *
2732 * This function initializes the gadget.
2733 */
2734int cdns3_gadget_init(struct cdns3 *cdns)
2735{
2736 struct cdns3_role_driver *rdrv;
2737
2738 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
2739 if (!rdrv)
2740 return -ENOMEM;
2741
2742 rdrv->start = __cdns3_gadget_init;
2743 rdrv->stop = cdns3_gadget_exit;
2744 rdrv->suspend = cdns3_gadget_suspend;
2745 rdrv->resume = cdns3_gadget_resume;
2746 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
2747 rdrv->name = "gadget";
2748 cdns->roles[USB_ROLE_DEVICE] = rdrv;
2749
2750 return 0;
2751}
diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h
new file mode 100644
index 000000000000..bc4024041ef2
--- /dev/null
+++ b/drivers/usb/cdns3/gadget.h
@@ -0,0 +1,1338 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * USBSS device controller driver header file
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 * Pawel Jez <pjez@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12#ifndef __LINUX_CDNS3_GADGET
13#define __LINUX_CDNS3_GADGET
14#include <linux/usb/gadget.h>
15
16/*
17 * USBSS-DEV register interface.
18 * This corresponds to the USBSS Device Controller Interface
19 */
20
21/**
22 * struct cdns3_usb_regs - device controller registers.
23 * @usb_conf: Global Configuration.
24 * @usb_sts: Global Status.
25 * @usb_cmd: Global Command.
26 * @usb_itpn: ITP/SOF number.
27 * @usb_lpm: Global Command.
28 * @usb_ien: USB Interrupt Enable.
29 * @usb_ists: USB Interrupt Status.
30 * @ep_sel: Endpoint Select.
31 * @ep_traddr: Endpoint Transfer Ring Address.
32 * @ep_cfg: Endpoint Configuration.
33 * @ep_cmd: Endpoint Command.
34 * @ep_sts: Endpoint Status.
35 * @ep_sts_sid: Endpoint Status.
36 * @ep_sts_en: Endpoint Status Enable.
37 * @drbl: Doorbell.
38 * @ep_ien: EP Interrupt Enable.
39 * @ep_ists: EP Interrupt Status.
40 * @usb_pwr: Global Power Configuration.
41 * @usb_conf2: Global Configuration 2.
42 * @usb_cap1: Capability 1.
43 * @usb_cap2: Capability 2.
44 * @usb_cap3: Capability 3.
45 * @usb_cap4: Capability 4.
46 * @usb_cap5: Capability 5.
47 * @usb_cap6: Capability 6.
48 * @usb_cpkt1: Custom Packet 1.
49 * @usb_cpkt2: Custom Packet 2.
50 * @usb_cpkt3: Custom Packet 3.
51 * @ep_dma_ext_addr: Upper address for DMA operations.
52 * @buf_addr: Address for On-chip Buffer operations.
53 * @buf_data: Data for On-chip Buffer operations.
54 * @buf_ctrl: On-chip Buffer Access Control.
55 * @dtrans: DMA Transfer Mode.
56 * @tdl_from_trb: Source of TD Configuration.
57 * @tdl_beh: TDL Behavior Configuration.
58 * @ep_tdl: Endpoint TDL.
59 * @tdl_beh2: TDL Behavior 2 Configuration.
60 * @dma_adv_td: DMA Advance TD Configuration.
61 * @reserved1: Reserved.
62 * @cfg_regs: Configuration.
63 * @reserved2: Reserved.
64 * @dma_axi_ctrl: AXI Control.
65 * @dma_axi_id: AXI ID register.
66 * @dma_axi_cap: AXI Capability.
67 * @dma_axi_ctrl0: AXI Control 0.
68 * @dma_axi_ctrl1: AXI Control 1.
69 */
70struct cdns3_usb_regs {
71 __le32 usb_conf;
72 __le32 usb_sts;
73 __le32 usb_cmd;
74 __le32 usb_itpn;
75 __le32 usb_lpm;
76 __le32 usb_ien;
77 __le32 usb_ists;
78 __le32 ep_sel;
79 __le32 ep_traddr;
80 __le32 ep_cfg;
81 __le32 ep_cmd;
82 __le32 ep_sts;
83 __le32 ep_sts_sid;
84 __le32 ep_sts_en;
85 __le32 drbl;
86 __le32 ep_ien;
87 __le32 ep_ists;
88 __le32 usb_pwr;
89 __le32 usb_conf2;
90 __le32 usb_cap1;
91 __le32 usb_cap2;
92 __le32 usb_cap3;
93 __le32 usb_cap4;
94 __le32 usb_cap5;
95 __le32 usb_cap6;
96 __le32 usb_cpkt1;
97 __le32 usb_cpkt2;
98 __le32 usb_cpkt3;
99 __le32 ep_dma_ext_addr;
100 __le32 buf_addr;
101 __le32 buf_data;
102 __le32 buf_ctrl;
103 __le32 dtrans;
104 __le32 tdl_from_trb;
105 __le32 tdl_beh;
106 __le32 ep_tdl;
107 __le32 tdl_beh2;
108 __le32 dma_adv_td;
109 __le32 reserved1[26];
110 __le32 cfg_reg1;
111 __le32 dbg_link1;
112 __le32 dbg_link2;
113 __le32 cfg_regs[74];
114 __le32 reserved2[51];
115 __le32 dma_axi_ctrl;
116 __le32 dma_axi_id;
117 __le32 dma_axi_cap;
118 __le32 dma_axi_ctrl0;
119 __le32 dma_axi_ctrl1;
120};
121
122/* USB_CONF - bitmasks */
123/* Reset USB device configuration. */
124#define USB_CONF_CFGRST BIT(0)
125/* Set Configuration. */
126#define USB_CONF_CFGSET BIT(1)
127/* Disconnect USB device in SuperSpeed. */
128#define USB_CONF_USB3DIS BIT(3)
129/* Disconnect USB device in HS/FS */
130#define USB_CONF_USB2DIS BIT(4)
131/* Little Endian access - default */
132#define USB_CONF_LENDIAN BIT(5)
133/*
134 * Big Endian access. Driver assume that byte order for
135 * SFRs access always is as Little Endian so this bit
136 * is not used.
137 */
138#define USB_CONF_BENDIAN BIT(6)
139/* Device software reset. */
140#define USB_CONF_SWRST BIT(7)
141/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
142#define USB_CONF_DSING BIT(8)
143/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
144#define USB_CONF_DMULT BIT(9)
145/* DMA clock turn-off enable. */
146#define USB_CONF_DMAOFFEN BIT(10)
147/* DMA clock turn-off disable. */
148#define USB_CONF_DMAOFFDS BIT(11)
149/* Clear Force Full Speed. */
150#define USB_CONF_CFORCE_FS BIT(12)
151/* Set Force Full Speed. */
152#define USB_CONF_SFORCE_FS BIT(13)
153/* Device enable. */
154#define USB_CONF_DEVEN BIT(14)
155/* Device disable. */
156#define USB_CONF_DEVDS BIT(15)
157/* L1 LPM state entry enable (used in HS/FS mode). */
158#define USB_CONF_L1EN BIT(16)
159/* L1 LPM state entry disable (used in HS/FS mode). */
160#define USB_CONF_L1DS BIT(17)
161/* USB 2.0 clock gate disable. */
162#define USB_CONF_CLK2OFFEN BIT(18)
163/* USB 2.0 clock gate enable. */
164#define USB_CONF_CLK2OFFDS BIT(19)
165/* L0 LPM state entry request (used in HS/FS mode). */
166#define USB_CONF_LGO_L0 BIT(20)
167/* USB 3.0 clock gate disable. */
168#define USB_CONF_CLK3OFFEN BIT(21)
169/* USB 3.0 clock gate enable. */
170#define USB_CONF_CLK3OFFDS BIT(22)
171/* Bit 23 is reserved*/
172/* U1 state entry enable (used in SS mode). */
173#define USB_CONF_U1EN BIT(24)
174/* U1 state entry disable (used in SS mode). */
175#define USB_CONF_U1DS BIT(25)
176/* U2 state entry enable (used in SS mode). */
177#define USB_CONF_U2EN BIT(26)
178/* U2 state entry disable (used in SS mode). */
179#define USB_CONF_U2DS BIT(27)
180/* U0 state entry request (used in SS mode). */
181#define USB_CONF_LGO_U0 BIT(28)
182/* U1 state entry request (used in SS mode). */
183#define USB_CONF_LGO_U1 BIT(29)
184/* U2 state entry request (used in SS mode). */
185#define USB_CONF_LGO_U2 BIT(30)
186/* SS.Inactive state entry request (used in SS mode) */
187#define USB_CONF_LGO_SSINACT BIT(31)
188
189/* USB_STS - bitmasks */
190/*
191 * Configuration status.
192 * 1 - device is in the configured state.
193 * 0 - device is not configured.
194 */
195#define USB_STS_CFGSTS_MASK BIT(0)
196#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
197/*
198 * On-chip memory overflow.
199 * 0 - On-chip memory status OK.
200 * 1 - On-chip memory overflow.
201 */
202#define USB_STS_OV_MASK BIT(1)
203#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
204/*
205 * SuperSpeed connection status.
206 * 0 - USB in SuperSpeed mode disconnected.
207 * 1 - USB in SuperSpeed mode connected.
208 */
209#define USB_STS_USB3CONS_MASK BIT(2)
210#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
211/*
212 * DMA transfer configuration status.
213 * 0 - single request.
214 * 1 - multiple TRB chain
215 * Supported only for controller version < DEV_VER_V3
216 */
217#define USB_STS_DTRANS_MASK BIT(3)
218#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
219/*
220 * Device speed.
221 * 0 - Undefined (value after reset).
222 * 1 - Low speed
223 * 2 - Full speed
224 * 3 - High speed
225 * 4 - Super speed
226 */
227#define USB_STS_USBSPEED_MASK GENMASK(6, 4)
228#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
229#define USB_STS_LS (0x1 << 4)
230#define USB_STS_FS (0x2 << 4)
231#define USB_STS_HS (0x3 << 4)
232#define USB_STS_SS (0x4 << 4)
233#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
234#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
235#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
236#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
237#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
238/*
239 * Endianness for SFR access.
240 * 0 - Little Endian order (default after hardware reset).
241 * 1 - Big Endian order
242 */
243#define USB_STS_ENDIAN_MASK BIT(7)
244#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
245/*
246 * HS/FS clock turn-off status.
247 * 0 - hsfs clock is always on.
248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
249 * (default after hardware reset).
250 */
251#define USB_STS_CLK2OFF_MASK BIT(8)
252#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
253/*
254 * PCLK clock turn-off status.
255 * 0 - pclk clock is always on.
256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
257 * (default after hardware reset).
258 */
259#define USB_STS_CLK3OFF_MASK BIT(9)
260#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
261/*
262 * Controller in reset state.
263 * 0 - Internal reset is active.
264 * 1 - Internal reset is not active and controller is fully operational.
265 */
266#define USB_STS_IN_RST_MASK BIT(10)
267#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
268/*
269 * Status of the "TDL calculation basing on TRB" feature.
270 * 0 - disabled
271 * 1 - enabled
272 * Supported only for DEV_VER_V2 controller version.
273 */
274#define USB_STS_TDL_TRB_ENABLED BIT(11)
275/*
276 * Device enable Status.
277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
278 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
279 */
280#define USB_STS_DEVS_MASK BIT(14)
281#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
282/*
283 * Address status.
284 * 0 - USB device is default state.
285 * 1 - USB device is at least in address state.
286 */
287#define USB_STS_ADDRESSED_MASK BIT(15)
288#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
289/*
290 * L1 LPM state enable status (used in HS/FS mode).
291 * 0 - Entering to L1 LPM state disabled.
292 * 1 - Entering to L1 LPM state enabled.
293 */
294#define USB_STS_L1ENS_MASK BIT(16)
295#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
296/*
297 * Internal VBUS connection status (used both in HS/FS and SS mode).
298 * 0 - internal VBUS is not detected.
299 * 1 - internal VBUS is detected.
300 */
301#define USB_STS_VBUSS_MASK BIT(17)
302#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
303/*
304 * HS/FS LPM state (used in FS/HS mode).
305 * 0 - L0 State
306 * 1 - L1 State
307 * 2 - L2 State
308 * 3 - L3 State
309 */
310#define USB_STS_LPMST_MASK GENMASK(19, 18)
311#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
312#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
313#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
314#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
315/*
316 * Disable HS status (used in FS/HS mode).
317 * 0 - the disconnect bit for HS/FS mode is set .
318 * 1 - the disconnect bit for HS/FS mode is not set.
319 */
320#define USB_STS_USB2CONS_MASK BIT(20)
321#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
322/*
323 * HS/FS mode connection status (used in FS/HS mode).
324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
325 * 1 - High Speed operations in USB2.0 (FS/HS).
326 */
327#define USB_STS_DISABLE_HS_MASK BIT(21)
328#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
329/*
330 * U1 state enable status (used in SS mode).
331 * 0 - Entering to U1 state disabled.
332 * 1 - Entering to U1 state enabled.
333 */
334#define USB_STS_U1ENS_MASK BIT(24)
335#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
336/*
337 * U2 state enable status (used in SS mode).
338 * 0 - Entering to U2 state disabled.
339 * 1 - Entering to U2 state enabled.
340 */
341#define USB_STS_U2ENS_MASK BIT(25)
342#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
343/*
344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
345 * SuperSpeed link state
346 */
347#define USB_STS_LST_MASK GENMASK(29, 26)
348#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
349#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
350#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
351#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
352#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
353#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
354#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
355#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
356#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
357#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
358#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
359#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
360/*
361 * DMA clock turn-off status.
362 * 0 - DMA clock is always on (default after hardware reset).
363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
364 */
365#define USB_STS_DMAOFF_MASK BIT(30)
366#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
367/*
368 * SFR Endian status.
369 * 0 - Little Endian order (default after hardware reset).
370 * 1 - Big Endian order.
371 */
372#define USB_STS_ENDIAN2_MASK BIT(31)
373#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
374
375/* USB_CMD - bitmasks */
376/* Set Function Address */
377#define USB_CMD_SET_ADDR BIT(0)
378/*
379 * Function Address This field is saved to the device only when the field
380 * SET_ADDR is set '1 ' during write to USB_CMD register.
381 * Software is responsible for entering the address of the device during
382 * SET_ADDRESS request service. This field should be set immediately after
383 * the SETUP packet is decoded, and prior to confirmation of the status phase
384 */
385#define USB_CMD_FADDR_MASK GENMASK(7, 1)
386#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
387/* Send Function Wake Device Notification TP (used only in SS mode). */
388#define USB_CMD_SDNFW BIT(8)
389/* Set Test Mode (used only in HS/FS mode). */
390#define USB_CMD_STMODE BIT(9)
391/* Test mode selector (used only in HS/FS mode) */
392#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
393#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
394/*
395 * Send Latency Tolerance Message Device Notification TP (used only
396 * in SS mode).
397 */
398#define USB_CMD_SDNLTM BIT(12)
399/* Send Custom Transaction Packet (used only in SS mode) */
400#define USB_CMD_SPKT BIT(13)
401/*Device Notification 'Function Wake' - Interface value (only in SS mode. */
402#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
403#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
404/*
405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
406 * (used only in SS mode).
407 */
408#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
409#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
410
411/* USB_ITPN - bitmasks */
412/*
413 * ITP(SS) / SOF (HS/FS) number
414 * In SS mode this field represent number of last ITP received from host.
415 * In HS/FS mode this field represent number of last SOF received from host.
416 */
417#define USB_ITPN_MASK GENMASK(13, 0)
418#define USB_ITPN(p) ((p) & USB_ITPN_MASK)
419
420/* USB_LPM - bitmasks */
421/* Host Initiated Resume Duration. */
422#define USB_LPM_HIRD_MASK GENMASK(3, 0)
423#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
424/* Remote Wakeup Enable (bRemoteWake). */
425#define USB_LPM_BRW BIT(4)
426
427/* USB_IEN - bitmasks */
428/* SS connection interrupt enable */
429#define USB_IEN_CONIEN BIT(0)
430/* SS disconnection interrupt enable. */
431#define USB_IEN_DISIEN BIT(1)
432/* USB SS warm reset interrupt enable. */
433#define USB_IEN_UWRESIEN BIT(2)
434/* USB SS hot reset interrupt enable */
435#define USB_IEN_UHRESIEN BIT(3)
436/* SS link U3 state enter interrupt enable (suspend).*/
437#define USB_IEN_U3ENTIEN BIT(4)
438/* SS link U3 state exit interrupt enable (wakeup). */
439#define USB_IEN_U3EXTIEN BIT(5)
440/* SS link U2 state enter interrupt enable.*/
441#define USB_IEN_U2ENTIEN BIT(6)
442/* SS link U2 state exit interrupt enable.*/
443#define USB_IEN_U2EXTIEN BIT(7)
444/* SS link U1 state enter interrupt enable.*/
445#define USB_IEN_U1ENTIEN BIT(8)
446/* SS link U1 state exit interrupt enable.*/
447#define USB_IEN_U1EXTIEN BIT(9)
448/* ITP/SOF packet detected interrupt enable.*/
449#define USB_IEN_ITPIEN BIT(10)
450/* Wakeup interrupt enable.*/
451#define USB_IEN_WAKEIEN BIT(11)
452/* Send Custom Packet interrupt enable.*/
453#define USB_IEN_SPKTIEN BIT(12)
454/* HS/FS mode connection interrupt enable.*/
455#define USB_IEN_CON2IEN BIT(16)
456/* HS/FS mode disconnection interrupt enable.*/
457#define USB_IEN_DIS2IEN BIT(17)
458/* USB reset (HS/FS mode) interrupt enable.*/
459#define USB_IEN_U2RESIEN BIT(18)
460/* LPM L2 state enter interrupt enable.*/
461#define USB_IEN_L2ENTIEN BIT(20)
462/* LPM L2 state exit interrupt enable.*/
463#define USB_IEN_L2EXTIEN BIT(21)
464/* LPM L1 state enter interrupt enable.*/
465#define USB_IEN_L1ENTIEN BIT(24)
466/* LPM L1 state exit interrupt enable.*/
467#define USB_IEN_L1EXTIEN BIT(25)
468/* Configuration reset interrupt enable.*/
469#define USB_IEN_CFGRESIEN BIT(26)
470/* Start of the USB SS warm reset interrupt enable.*/
471#define USB_IEN_UWRESSIEN BIT(28)
472/* End of the USB SS warm reset interrupt enable.*/
473#define USB_IEN_UWRESEIEN BIT(29)
474
475#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
476 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
477 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
478 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
479
480/* USB_ISTS - bitmasks */
481/* SS Connection detected. */
482#define USB_ISTS_CONI BIT(0)
483/* SS Disconnection detected. */
484#define USB_ISTS_DISI BIT(1)
485/* UUSB warm reset detectede. */
486#define USB_ISTS_UWRESI BIT(2)
487/* USB hot reset detected. */
488#define USB_ISTS_UHRESI BIT(3)
489/* U3 link state enter detected (suspend).*/
490#define USB_ISTS_U3ENTI BIT(4)
491/* U3 link state exit detected (wakeup). */
492#define USB_ISTS_U3EXTI BIT(5)
493/* U2 link state enter detected.*/
494#define USB_ISTS_U2ENTI BIT(6)
495/* U2 link state exit detected.*/
496#define USB_ISTS_U2EXTI BIT(7)
497/* U1 link state enter detected.*/
498#define USB_ISTS_U1ENTI BIT(8)
499/* U1 link state exit detected.*/
500#define USB_ISTS_U1EXTI BIT(9)
501/* ITP/SOF packet detected.*/
502#define USB_ISTS_ITPI BIT(10)
503/* Wakeup detected.*/
504#define USB_ISTS_WAKEI BIT(11)
505/* Send Custom Packet detected.*/
506#define USB_ISTS_SPKTI BIT(12)
507/* HS/FS mode connection detected.*/
508#define USB_ISTS_CON2I BIT(16)
509/* HS/FS mode disconnection detected.*/
510#define USB_ISTS_DIS2I BIT(17)
511/* USB reset (HS/FS mode) detected.*/
512#define USB_ISTS_U2RESI BIT(18)
513/* LPM L2 state enter detected.*/
514#define USB_ISTS_L2ENTI BIT(20)
515/* LPM L2 state exit detected.*/
516#define USB_ISTS_L2EXTI BIT(21)
517/* LPM L1 state enter detected.*/
518#define USB_ISTS_L1ENTI BIT(24)
519/* LPM L1 state exit detected.*/
520#define USB_ISTS_L1EXTI BIT(25)
521/* USB configuration reset detected.*/
522#define USB_ISTS_CFGRESI BIT(26)
523/* Start of the USB warm reset detected.*/
524#define USB_ISTS_UWRESSI BIT(28)
525/* End of the USB warm reset detected.*/
526#define USB_ISTS_UWRESEI BIT(29)
527
528/* USB_SEL - bitmasks */
529#define EP_SEL_EPNO_MASK GENMASK(3, 0)
530/* Endpoint number. */
531#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
532/* Endpoint direction bit - 0 - OUT, 1 - IN. */
533#define EP_SEL_DIR BIT(7)
534
535#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
536#define select_ep_out (EP_SEL_EPNO(p))
537
538/* EP_TRADDR - bitmasks */
539/* Transfer Ring address. */
540#define EP_TRADDR_TRADDR(p) ((p))
541
542/* EP_CFG - bitmasks */
543/* Endpoint enable */
544#define EP_CFG_ENABLE BIT(0)
545/*
546 * Endpoint type.
547 * 1 - isochronous
548 * 2 - bulk
549 * 3 - interrupt
550 */
551#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
552#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
553/* Stream support enable (only in SS mode). */
554#define EP_CFG_STREAM_EN BIT(3)
555/* TDL check (only in SS mode for BULK EP). */
556#define EP_CFG_TDL_CHK BIT(4)
557/* SID check (only in SS mode for BULK OUT EP). */
558#define EP_CFG_SID_CHK BIT(5)
559/* DMA transfer endianness. */
560#define EP_CFG_EPENDIAN BIT(7)
561/* Max burst size (used only in SS mode). */
562#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
563#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
564/* ISO max burst. */
565#define EP_CFG_MULT_MASK GENMASK(15, 14)
566#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
567/* ISO max burst. */
568#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
569#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
570/* Max number of buffered packets. */
571#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
572#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
573
574/* EP_CMD - bitmasks */
575/* Endpoint reset. */
576#define EP_CMD_EPRST BIT(0)
577/* Endpoint STALL set. */
578#define EP_CMD_SSTALL BIT(1)
579/* Endpoint STALL clear. */
580#define EP_CMD_CSTALL BIT(2)
581/* Send ERDY TP. */
582#define EP_CMD_ERDY BIT(3)
583/* Request complete. */
584#define EP_CMD_REQ_CMPL BIT(5)
585/* Transfer descriptor ready. */
586#define EP_CMD_DRDY BIT(6)
587/* Data flush. */
588#define EP_CMD_DFLUSH BIT(7)
589/*
590 * Transfer Descriptor Length write (used only for Bulk Stream capable
591 * endpoints in SS mode).
592 * Bit Removed from DEV_VER_V3 controller version.
593 */
594#define EP_CMD_STDL BIT(8)
595/*
596 * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
597 * Bits Removed from DEV_VER_V3 controller version.
598 */
599#define EP_CMD_TDL_MASK GENMASK(15, 9)
600#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
601#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
602
603/* ERDY Stream ID value (used in SS mode). */
604#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
605#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
606
607/* EP_STS - bitmasks */
608/* Setup transfer complete. */
609#define EP_STS_SETUP BIT(0)
610/* Endpoint STALL status. */
611#define EP_STS_STALL(p) ((p) & BIT(1))
612/* Interrupt On Complete. */
613#define EP_STS_IOC BIT(2)
614/* Interrupt on Short Packet. */
615#define EP_STS_ISP BIT(3)
616/* Transfer descriptor missing. */
617#define EP_STS_DESCMIS BIT(4)
618/* Stream Rejected (used only in SS mode) */
619#define EP_STS_STREAMR BIT(5)
620/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
621#define EP_STS_MD_EXIT BIT(6)
622/* TRB error. */
623#define EP_STS_TRBERR BIT(7)
624/* Not ready (used only in SS mode). */
625#define EP_STS_NRDY BIT(8)
626/* DMA busy bit. */
627#define EP_STS_DBUSY BIT(9)
628/* Endpoint Buffer Empty */
629#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
630/* Current Cycle Status */
631#define EP_STS_CCS(p) ((p) & BIT(11))
632/* Prime (used only in SS mode. */
633#define EP_STS_PRIME BIT(12)
634/* Stream error (used only in SS mode). */
635#define EP_STS_SIDERR BIT(13)
636/* OUT size mismatch. */
637#define EP_STS_OUTSMM BIT(14)
638/* ISO transmission error. */
639#define EP_STS_ISOERR BIT(15)
640/* Host Packet Pending (only for SS mode). */
641#define EP_STS_HOSTPP(p) ((p) & BIT(16))
642/* Stream Protocol State Machine State (only for Bulk stream endpoints). */
643#define EP_STS_SPSMST_MASK GENMASK(18, 17)
644#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
645#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
646#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
647#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
648/* Interrupt On Transfer complete. */
649#define EP_STS_IOT BIT(19)
650/* OUT queue endpoint number. */
651#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
652#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
653/* OUT queue valid flag. */
654#define EP_STS_OUTQ_VAL_MASK BIT(28)
655#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
656/* SETUP WAIT. */
657#define EP_STS_STPWAIT BIT(31)
658
659/* EP_STS_SID - bitmasks */
660/* Stream ID (used only in SS mode). */
661#define EP_STS_SID_MASK GENMASK(15, 0)
662#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
663
664/* EP_STS_EN - bitmasks */
665/* SETUP interrupt enable. */
666#define EP_STS_EN_SETUPEN BIT(0)
667/* OUT transfer missing descriptor enable. */
668#define EP_STS_EN_DESCMISEN BIT(4)
669/* Stream Rejected enable. */
670#define EP_STS_EN_STREAMREN BIT(5)
671/* Move Data Exit enable.*/
672#define EP_STS_EN_MD_EXITEN BIT(6)
673/* TRB enable. */
674#define EP_STS_EN_TRBERREN BIT(7)
675/* NRDY enable. */
676#define EP_STS_EN_NRDYEN BIT(8)
677/* Prime enable. */
678#define EP_STS_EN_PRIMEEEN BIT(12)
679/* Stream error enable. */
680#define EP_STS_EN_SIDERREN BIT(13)
681/* OUT size mismatch enable. */
682#define EP_STS_EN_OUTSMMEN BIT(14)
683/* ISO transmission error enable. */
684#define EP_STS_EN_ISOERREN BIT(15)
685/* Interrupt on Transmission complete enable. */
686#define EP_STS_EN_IOTEN BIT(19)
687/* Setup Wait interrupt enable. */
688#define EP_STS_EN_STPWAITEN BIT(31)
689
690/* DRBL- bitmasks */
691#define DB_VALUE_BY_INDEX(index) (1 << (index))
692#define DB_VALUE_EP0_OUT BIT(0)
693#define DB_VALUE_EP0_IN BIT(16)
694
695/* EP_IEN - bitmasks */
696#define EP_IEN(index) (1 << (index))
697#define EP_IEN_EP_OUT0 BIT(0)
698#define EP_IEN_EP_IN0 BIT(16)
699
700/* EP_ISTS - bitmasks */
701#define EP_ISTS(index) (1 << (index))
702#define EP_ISTS_EP_OUT0 BIT(0)
703#define EP_ISTS_EP_IN0 BIT(16)
704
705/* USB_PWR- bitmasks */
706/*Power Shut Off capability enable*/
707#define PUSB_PWR_PSO_EN BIT(0)
708/*Power Shut Off capability disable*/
709#define PUSB_PWR_PSO_DS BIT(1)
710/*
711 * Enables turning-off Reference Clock.
712 * This bit is optional and implemented only when support for OTG is
713 * implemented (indicated by OTG_READY bit set to '1').
714 */
715#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
716/*
717 * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
718 * is completed
719 */
720#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
721/* This bit informs if Fast Registers Access is enabled. */
722#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
723/* Fast Registers Access Enable. */
724#define PUSB_PWR_FST_REG_ACCESS BIT(31)
725
726/* USB_CONF2- bitmasks */
727/*
728 * Writing 1 disables TDL calculation basing on TRB feature in controller
729 * for DMULT mode.
730 * Bit supported only for DEV_VER_V2 version.
731 */
732#define USB_CONF2_DIS_TDL_TRB BIT(1)
733/*
734 * Writing 1 enables TDL calculation basing on TRB feature in controller
735 * for DMULT mode.
736 * Bit supported only for DEV_VER_V2 version.
737 */
738#define USB_CONF2_EN_TDL_TRB BIT(2)
739
740/* USB_CAP1- bitmasks */
741/*
742 * SFR Interface type
743 * These field reflects type of SFR interface implemented:
744 * 0x0 - OCP
745 * 0x1 - AHB,
746 * 0x2 - PLB
747 * 0x3 - AXI
748 * 0x4-0xF - reserved
749 */
750#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
751#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
752#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
753#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
754#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
755/*
756 * SFR Interface width
757 * These field reflects width of SFR interface implemented:
758 * 0x0 - 8 bit interface,
759 * 0x1 - 16 bit interface,
760 * 0x2 - 32 bit interface
761 * 0x3 - 64 bit interface
762 * 0x4-0xF - reserved
763 */
764#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
765#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
766#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
767#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
768#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
769/*
770 * DMA Interface type
771 * These field reflects type of DMA interface implemented:
772 * 0x0 - OCP
773 * 0x1 - AHB,
774 * 0x2 - PLB
775 * 0x3 - AXI
776 * 0x4-0xF - reserved
777 */
778#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
779#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
780#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
781#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
782#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
783/*
784 * DMA Interface width
785 * These field reflects width of DMA interface implemented:
786 * 0x0 - reserved,
787 * 0x1 - reserved,
788 * 0x2 - 32 bit interface
789 * 0x3 - 64 bit interface
790 * 0x4-0xF - reserved
791 */
792#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
793#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
794#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
795/*
796 * USB3 PHY Interface type
797 * These field reflects type of USB3 PHY interface implemented:
798 * 0x0 - USB PIPE,
799 * 0x1 - RMMI,
800 * 0x2-0xF - reserved
801 */
802#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
803#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
804#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
805/*
806 * USB3 PHY Interface width
807 * These field reflects width of USB3 PHY interface implemented:
808 * 0x0 - 8 bit PIPE interface,
809 * 0x1 - 16 bit PIPE interface,
810 * 0x2 - 32 bit PIPE interface,
811 * 0x3 - 64 bit PIPE interface
812 * 0x4-0xF - reserved
813 * Note: When SSIC interface is implemented this field shows the width of
814 * internal PIPE interface. The RMMI interface is always 20bit wide.
815 */
816#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
817#define DEV_U3PHY_WIDTH_8(p) \
818 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
819#define DEV_U3PHY_WIDTH_16(p) \
820 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
821#define DEV_U3PHY_WIDTH_32(p) \
822 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
823#define DEV_U3PHY_WIDTH_64(p) \
824 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
825
826/*
827 * USB2 PHY Interface enable
828 * These field informs if USB2 PHY interface is implemented:
829 * 0x0 - interface NOT implemented,
830 * 0x1 - interface implemented
831 */
832#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
833/*
834 * USB2 PHY Interface type
835 * These field reflects type of USB2 PHY interface implemented:
836 * 0x0 - UTMI,
837 * 0x1 - ULPI
838 */
839#define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
840/*
841 * USB2 PHY Interface width
842 * These field reflects width of USB2 PHY interface implemented:
843 * 0x0 - 8 bit interface,
844 * 0x1 - 16 bit interface,
845 * Note: The ULPI interface is always 8bit wide.
846 */
847#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
848/*
849 * OTG Ready
850 * 0x0 - pure device mode
851 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
852 */
853#define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
854
855/*
856 * When set, indicates that controller supports automatic internal TDL
857 * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
858 * Supported only for DEV_VER_V2 controller version.
859 */
860#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
861
862/* USB_CAP2- bitmasks */
863/*
864 * The actual size of the connected On-chip RAM memory in kB:
865 * - 0 means 256 kB (max supported mem size)
866 * - value other than 0 reflects the mem size in kB
867 */
868#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
869/*
870 * Max supported mem size
871 * These field reflects width of on-chip RAM address bus width,
872 * which determines max supported mem size:
873 * 0x0-0x7 - reserved,
874 * 0x8 - support for 4kB mem,
875 * 0x9 - support for 8kB mem,
876 * 0xA - support for 16kB mem,
877 * 0xB - support for 32kB mem,
878 * 0xC - support for 64kB mem,
879 * 0xD - support for 128kB mem,
880 * 0xE - support for 256kB mem,
881 * 0xF - reserved
882 */
883#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
884
885/* USB_CAP3- bitmasks */
886#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
887
888/* USB_CAP4- bitmasks */
889#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
890
891/* USB_CAP5- bitmasks */
892#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
893
894/* USB_CAP6- bitmasks */
895/* The USBSS-DEV Controller Internal build number. */
896#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
897/* The USBSS-DEV Controller version number. */
898#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
899
900#define DEV_VER_NXP_V1 0x00024502
901#define DEV_VER_TI_V1 0x00024509
902#define DEV_VER_V2 0x0002450C
903#define DEV_VER_V3 0x0002450d
904
905/* DBG_LINK1- bitmasks */
906/*
907 * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
908 * time required for decoding the received LFPS as an LFPS.U1_Exit.
909 */
910#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
911/*
912 * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
913 * phytxelecidle deassertion when LFPS.U1_Exit
914 */
915#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
916#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
917/*
918 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
919 * Receiver termination detection sequence:
920 * 0: it is possible that USBSS_DEV will terminate Farend receiver
921 * termination detection sequence
922 * 1: USBSS_DEV will not terminate Far-end receiver termination
923 * detection sequence
924 */
925#define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
926/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
927#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
928/*
929 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
930 * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
931 * cleared. Writing '0' has no effect
932 */
933#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
934/*
935 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
936 * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
937 * cleared. Writing '0' has no effect
938 */
939#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
940/*
941 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
942 * the RXDET_BREAK_DIS field value to the device. This bit is automatically
943 * cleared. Writing '0' has no effect
944 */
945#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
946/*
947 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
948 * the LFPS_GEN_PING field value to the device. This bit is automatically
949 * cleared. Writing '0' has no effect."
950 */
951#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
952
953/* DMA_AXI_CTRL- bitmasks */
954/* The mawprot pin configuration. */
955#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
956/* The marprot pin configuration. */
957#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
958#define DMA_AXI_CTRL_NON_SECURE 0x02
959
960#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
961
962#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
963
964/*-------------------------------------------------------------------------*/
965/*
966 * USBSS-DEV DMA interface.
967 */
968#define TRBS_PER_SEGMENT 40
969
970#define ISO_MAX_INTERVAL 10
971
972#if TRBS_PER_SEGMENT < 2
973#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
974#endif
975
976/*
977 *Only for ISOC endpoints - maximum number of TRBs is calculated as
978 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
979 * driver to save memory. Controller must prepare TRB for each ITP even
980 * if bInterval > 1. It's the reason why driver needs so many TRBs for
981 * isochronous endpoints.
982 */
983#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
984
985#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
986 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
987/**
988 * struct cdns3_trb - represent Transfer Descriptor block.
989 * @buffer: pointer to buffer data
990 * @length: length of data
991 * @control: control flags.
992 *
993 * This structure describes transfer block serviced by DMA module.
994 */
995struct cdns3_trb {
996 __le32 buffer;
997 __le32 length;
998 __le32 control;
999};
1000
1001#define TRB_SIZE (sizeof(struct cdns3_trb))
1002#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
1003#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1004#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
1005
1006/* TRB bit mask */
1007#define TRB_TYPE_BITMASK GENMASK(15, 10)
1008#define TRB_TYPE(p) ((p) << 10)
1009#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1010
1011/* TRB type IDs */
1012/* bulk, interrupt, isoc , and control data stage */
1013#define TRB_NORMAL 1
1014/* TRB for linking ring segments */
1015#define TRB_LINK 6
1016
1017/* Cycle bit - indicates TRB ownership by driver or hw*/
1018#define TRB_CYCLE BIT(0)
1019/*
1020 * When set to '1', the device will toggle its interpretation of the Cycle bit
1021 */
1022#define TRB_TOGGLE BIT(1)
1023
1024/*
1025 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1026 * processed while USB short packet was received. No more buffers defined by
1027 * the TD will be used. DMA will automatically advance to next TD.
1028 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1029 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1030 * is detected independent if ISP is set or not.
1031 */
1032#define TRB_SP BIT(1)
1033
1034/* Interrupt on short packet*/
1035#define TRB_ISP BIT(2)
1036/*Setting this bit enables FIFO DMA operation mode*/
1037#define TRB_FIFO_MODE BIT(3)
1038/* Set PCIe no snoop attribute */
1039#define TRB_CHAIN BIT(4)
1040/* Interrupt on completion */
1041#define TRB_IOC BIT(5)
1042
1043/* stream ID bitmasks. */
1044#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
1045#define TRB_STREAM_ID(p) ((p) << 16)
1046#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1047
1048/* Size of TD expressed in USB packets for HS/FS mode. */
1049#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
1050#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
1051
1052/* transfer_len bitmasks. */
1053#define TRB_LEN(p) ((p) & GENMASK(16, 0))
1054
1055/* Size of TD expressed in USB packets for SS mode. */
1056#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
1057#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
1058
1059/* transfer_len bitmasks - bits 31:24 */
1060#define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24))
1061#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
1062
1063/* Data buffer pointer bitmasks*/
1064#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
1065
1066/*-------------------------------------------------------------------------*/
1067/* Driver numeric constants */
1068
1069/* Such declaration should be added to ch9.h */
1070#define USB_DEVICE_MAX_ADDRESS 127
1071
1072/* Endpoint init values */
1073#define CDNS3_EP_MAX_PACKET_LIMIT 1024
1074#define CDNS3_EP_MAX_STREAMS 15
1075#define CDNS3_EP0_MAX_PACKET_LIMIT 512
1076
1077/* All endpoints including EP0 */
1078#define CDNS3_ENDPOINTS_MAX_COUNT 32
1079#define CDNS3_EP_ZLP_BUF_SIZE 1024
1080
1081#define CDNS3_EP_BUF_SIZE 2 /* KB */
1082#define CDNS3_EP_ISO_HS_MULT 3
1083#define CDNS3_EP_ISO_SS_BURST 3
1084#define CDNS3_MAX_NUM_DESCMISS_BUF 32
1085#define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */
1086#define CDNS3_WA2_NUM_BUFFERS 128
1087/*-------------------------------------------------------------------------*/
1088/* Used structs */
1089
1090struct cdns3_device;
1091
1092/**
1093 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1094 * @endpoint: usb endpoint
1095 * @pending_req_list: list of requests queuing on transfer ring.
1096 * @deferred_req_list: list of requests waiting for queuing on transfer ring.
1097 * @wa2_descmiss_req_list: list of requests internally allocated by driver.
1098 * @trb_pool: transfer ring - array of transaction buffers
1099 * @trb_pool_dma: dma address of transfer ring
1100 * @cdns3_dev: device associated with this endpoint
1101 * @name: a human readable name e.g. ep1out
1102 * @flags: specify the current state of endpoint
1103 * @descmis_req: internal transfer object used for getting data from on-chip
1104 * buffer. It can happen only if function driver doesn't send usb_request
1105 * object on time.
1106 * @dir: endpoint direction
1107 * @num: endpoint number (1 - 15)
1108 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
1109 * @interval: interval between packets used for ISOC endpoint.
1110 * @free_trbs: number of free TRBs in transfer ring
1111 * @num_trbs: number of all TRBs in transfer ring
1112 * @pcs: producer cycle state
1113 * @ccs: consumer cycle state
1114 * @enqueue: enqueue index in transfer ring
1115 * @dequeue: dequeue index in transfer ring
1116 * @trb_burst_size: number of burst used in trb.
1117 */
1118struct cdns3_endpoint {
1119 struct usb_ep endpoint;
1120 struct list_head pending_req_list;
1121 struct list_head deferred_req_list;
1122 struct list_head wa2_descmiss_req_list;
1123 int wa2_counter;
1124
1125 struct cdns3_trb *trb_pool;
1126 dma_addr_t trb_pool_dma;
1127
1128 struct cdns3_device *cdns3_dev;
1129 char name[20];
1130
1131#define EP_ENABLED BIT(0)
1132#define EP_STALLED BIT(1)
1133#define EP_STALL_PENDING BIT(2)
1134#define EP_WEDGE BIT(3)
1135#define EP_TRANSFER_STARTED BIT(4)
1136#define EP_UPDATE_EP_TRBADDR BIT(5)
1137#define EP_PENDING_REQUEST BIT(6)
1138#define EP_RING_FULL BIT(7)
1139#define EP_CLAIMED BIT(8)
1140#define EP_DEFERRED_DRDY BIT(9)
1141#define EP_QUIRK_ISO_OUT_EN BIT(10)
1142#define EP_QUIRK_END_TRANSFER BIT(11)
1143#define EP_QUIRK_EXTRA_BUF_DET BIT(12)
1144#define EP_QUIRK_EXTRA_BUF_EN BIT(13)
1145 u32 flags;
1146
1147 struct cdns3_request *descmis_req;
1148
1149 u8 dir;
1150 u8 num;
1151 u8 type;
1152 int interval;
1153
1154 int free_trbs;
1155 int num_trbs;
1156 u8 pcs;
1157 u8 ccs;
1158 int enqueue;
1159 int dequeue;
1160 u8 trb_burst_size;
1161
1162 unsigned int wa1_set:1;
1163 struct cdns3_trb *wa1_trb;
1164 unsigned int wa1_trb_index;
1165 unsigned int wa1_cycle_bit:1;
1166};
1167
1168/**
1169 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1170 * @buf: aligned to 8 bytes data buffer. Buffer address used in
1171 * TRB shall be aligned to 8.
1172 * @dma: dma address
1173 * @size: size of buffer
1174 * @in_use: inform if this buffer is associated with usb_request
1175 * @list: used to adding instance of this object to list
1176 */
1177struct cdns3_aligned_buf {
1178 void *buf;
1179 dma_addr_t dma;
1180 u32 size;
1181 int in_use:1;
1182 struct list_head list;
1183};
1184
1185/**
1186 * struct cdns3_request - extended device side representation of usb_request
1187 * object .
1188 * @request: generic usb_request object describing single I/O request.
1189 * @priv_ep: extended representation of usb_ep object
1190 * @trb: the first TRB association with this request
1191 * @start_trb: number of the first TRB in transfer ring
1192 * @end_trb: number of the last TRB in transfer ring
1193 * @aligned_buf: object holds information about aligned buffer associated whit
1194 * this endpoint
1195 * @flags: flag specifying special usage of request
1196 * @list: used by internally allocated request to add to wa2_descmiss_req_list.
1197 */
1198struct cdns3_request {
1199 struct usb_request request;
1200 struct cdns3_endpoint *priv_ep;
1201 struct cdns3_trb *trb;
1202 int start_trb;
1203 int end_trb;
1204 struct cdns3_aligned_buf *aligned_buf;
1205#define REQUEST_PENDING BIT(0)
1206#define REQUEST_INTERNAL BIT(1)
1207#define REQUEST_INTERNAL_CH BIT(2)
1208#define REQUEST_ZLP BIT(3)
1209#define REQUEST_UNALIGNED BIT(4)
1210 u32 flags;
1211 struct list_head list;
1212};
1213
1214#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1215
1216/*Stages used during enumeration process.*/
1217#define CDNS3_SETUP_STAGE 0x0
1218#define CDNS3_DATA_STAGE 0x1
1219#define CDNS3_STATUS_STAGE 0x2
1220
1221/**
1222 * struct cdns3_device - represent USB device.
1223 * @dev: pointer to device structure associated whit this controller
1224 * @sysdev: pointer to the DMA capable device
1225 * @gadget: device side representation of the peripheral controller
1226 * @gadget_driver: pointer to the gadget driver
1227 * @dev_ver: device controller version.
1228 * @lock: for synchronizing
1229 * @regs: base address for device side registers
1230 * @setup_buf: used while processing usb control requests
1231 * @setup_dma: dma address for setup_buf
1232 * @zlp_buf - zlp buffer
1233 * @ep0_stage: ep0 stage during enumeration process.
1234 * @ep0_data_dir: direction for control transfer
1235 * @eps: array of pointers to all endpoints with exclusion ep0
1236 * @aligned_buf_list: list of aligned buffers internally allocated by driver
1237 * @aligned_buf_wq: workqueue freeing no longer used aligned buf.
1238 * @selected_ep: actually selected endpoint. It's used only to improve
1239 * performance.
1240 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1241 * @u1_allowed: allow device transition to u1 state
1242 * @u2_allowed: allow device transition to u2 state
1243 * @is_selfpowered: device is self powered
1244 * @setup_pending: setup packet is processing by gadget driver
1245 * @hw_configured_flag: hardware endpoint configuration was set.
1246 * @wake_up_flag: allow device to remote up the host
1247 * @status_completion_no_call: indicate that driver is waiting for status s
1248 * stage completion. It's used in deferred SET_CONFIGURATION request.
1249 * @onchip_buffers: number of available on-chip buffers.
1250 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1251 * @pending_status_wq: workqueue handling status stage for deferred requests.
1252 * @pending_status_request: request for which status stage was deferred
1253 */
1254struct cdns3_device {
1255 struct device *dev;
1256 struct device *sysdev;
1257
1258 struct usb_gadget gadget;
1259 struct usb_gadget_driver *gadget_driver;
1260
1261#define CDNS_REVISION_V0 0x00024501
1262#define CDNS_REVISION_V1 0x00024509
1263 u32 dev_ver;
1264
1265 /* generic spin-lock for drivers */
1266 spinlock_t lock;
1267
1268 struct cdns3_usb_regs __iomem *regs;
1269
1270 struct usb_ctrlrequest *setup_buf;
1271 dma_addr_t setup_dma;
1272 void *zlp_buf;
1273
1274 u8 ep0_stage;
1275 int ep0_data_dir;
1276
1277 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1278
1279 struct list_head aligned_buf_list;
1280 struct work_struct aligned_buf_wq;
1281
1282 u32 selected_ep;
1283 u16 isoch_delay;
1284
1285 unsigned wait_for_setup:1;
1286 unsigned u1_allowed:1;
1287 unsigned u2_allowed:1;
1288 unsigned is_selfpowered:1;
1289 unsigned setup_pending:1;
1290 int hw_configured_flag:1;
1291 int wake_up_flag:1;
1292 unsigned status_completion_no_call:1;
1293 int out_mem_is_allocated;
1294
1295 struct work_struct pending_status_wq;
1296 struct usb_request *pending_status_request;
1297
1298 /*in KB */
1299 u16 onchip_buffers;
1300 u16 onchip_used_size;
1301};
1302
1303void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1304dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1305 struct cdns3_trb *trb);
1306enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1307void cdns3_pending_setup_status_handler(struct work_struct *work);
1308void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1309void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1310void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1311void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1312struct usb_request *cdns3_next_request(struct list_head *list);
1313int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
1314 struct usb_request *request);
1315void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1316int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1317u8 cdns3_ep_addr_to_index(u8 ep_addr);
1318int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1319int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1320void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1321int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1322struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1323 gfp_t gfp_flags);
1324void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1325 struct usb_request *request);
1326int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1327void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1328 struct cdns3_request *priv_req,
1329 int status);
1330
1331int cdns3_init_ep0(struct cdns3_device *priv_dev,
1332 struct cdns3_endpoint *priv_ep);
1333void cdns3_ep0_config(struct cdns3_device *priv_dev);
1334void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
1335void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1336int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1337
1338#endif /* __LINUX_CDNS3_GADGET */
diff --git a/drivers/usb/cdns3/host-export.h b/drivers/usb/cdns3/host-export.h
new file mode 100644
index 000000000000..b498a170b7e8
--- /dev/null
+++ b/drivers/usb/cdns3/host-export.h
@@ -0,0 +1,28 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver - Host Export APIs
4 *
5 * Copyright (C) 2017-2018 NXP
6 *
7 * Authors: Peter Chen <peter.chen@nxp.com>
8 */
9#ifndef __LINUX_CDNS3_HOST_EXPORT
10#define __LINUX_CDNS3_HOST_EXPORT
11
12#ifdef CONFIG_USB_CDNS3_HOST
13
14int cdns3_host_init(struct cdns3 *cdns);
15void cdns3_host_exit(struct cdns3 *cdns);
16
17#else
18
19static inline int cdns3_host_init(struct cdns3 *cdns)
20{
21 return -ENXIO;
22}
23
24static inline void cdns3_host_exit(struct cdns3 *cdns) { }
25
26#endif /* CONFIG_USB_CDNS3_HOST */
27
28#endif /* __LINUX_CDNS3_HOST_EXPORT */
diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c
new file mode 100644
index 000000000000..2733a8f71fcd
--- /dev/null
+++ b/drivers/usb/cdns3/host.c
@@ -0,0 +1,74 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - host side
4 *
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 * Pawel Laszczak <pawell@cadence.com>
10 */
11
12#include <linux/platform_device.h>
13#include "core.h"
14#include "drd.h"
15
16static int __cdns3_host_init(struct cdns3 *cdns)
17{
18 struct platform_device *xhci;
19 int ret;
20
21 cdns3_drd_switch_host(cdns, 1);
22
23 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
24 if (!xhci) {
25 dev_err(cdns->dev, "couldn't allocate xHCI device\n");
26 return -ENOMEM;
27 }
28
29 xhci->dev.parent = cdns->dev;
30 cdns->host_dev = xhci;
31
32 ret = platform_device_add_resources(xhci, cdns->xhci_res,
33 CDNS3_XHCI_RESOURCES_NUM);
34 if (ret) {
35 dev_err(cdns->dev, "couldn't add resources to xHCI device\n");
36 goto err1;
37 }
38
39 ret = platform_device_add(xhci);
40 if (ret) {
41 dev_err(cdns->dev, "failed to register xHCI device\n");
42 goto err1;
43 }
44
45 return 0;
46err1:
47 platform_device_put(xhci);
48 return ret;
49}
50
51static void cdns3_host_exit(struct cdns3 *cdns)
52{
53 platform_device_unregister(cdns->host_dev);
54 cdns->host_dev = NULL;
55 cdns3_drd_switch_host(cdns, 0);
56}
57
58int cdns3_host_init(struct cdns3 *cdns)
59{
60 struct cdns3_role_driver *rdrv;
61
62 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
63 if (!rdrv)
64 return -ENOMEM;
65
66 rdrv->start = __cdns3_host_init;
67 rdrv->stop = cdns3_host_exit;
68 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
69 rdrv->name = "host";
70
71 cdns->roles[USB_ROLE_HOST] = rdrv;
72
73 return 0;
74}
diff --git a/drivers/usb/cdns3/trace.c b/drivers/usb/cdns3/trace.c
new file mode 100644
index 000000000000..459fa72d9c74
--- /dev/null
+++ b/drivers/usb/cdns3/trace.c
@@ -0,0 +1,11 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * USBSS device controller driver Trace Support
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9
10#define CREATE_TRACE_POINTS
11#include "trace.h"
diff --git a/drivers/usb/cdns3/trace.h b/drivers/usb/cdns3/trace.h
new file mode 100644
index 000000000000..e92348c9b4d7
--- /dev/null
+++ b/drivers/usb/cdns3/trace.h
@@ -0,0 +1,493 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * USBSS device controller driver.
4 * Trace support header file.
5 *
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 */
10
11#undef TRACE_SYSTEM
12#define TRACE_SYSTEM cdns3
13
14#if !defined(__LINUX_CDNS3_TRACE) || defined(TRACE_HEADER_MULTI_READ)
15#define __LINUX_CDNS3_TRACE
16
17#include <linux/types.h>
18#include <linux/tracepoint.h>
19#include <asm/byteorder.h>
20#include <linux/usb/ch9.h>
21#include "core.h"
22#include "gadget.h"
23#include "debug.h"
24
25#define CDNS3_MSG_MAX 500
26
27TRACE_EVENT(cdns3_halt,
28 TP_PROTO(struct cdns3_endpoint *ep_priv, u8 halt, u8 flush),
29 TP_ARGS(ep_priv, halt, flush),
30 TP_STRUCT__entry(
31 __string(name, ep_priv->name)
32 __field(u8, halt)
33 __field(u8, flush)
34 ),
35 TP_fast_assign(
36 __assign_str(name, ep_priv->name);
37 __entry->halt = halt;
38 __entry->flush = flush;
39 ),
40 TP_printk("Halt %s for %s: %s", __entry->flush ? " and flush" : "",
41 __get_str(name), __entry->halt ? "set" : "cleared")
42);
43
44TRACE_EVENT(cdns3_wa1,
45 TP_PROTO(struct cdns3_endpoint *ep_priv, char *msg),
46 TP_ARGS(ep_priv, msg),
47 TP_STRUCT__entry(
48 __string(ep_name, ep_priv->name)
49 __string(msg, msg)
50 ),
51 TP_fast_assign(
52 __assign_str(ep_name, ep_priv->name);
53 __assign_str(msg, msg);
54 ),
55 TP_printk("WA1: %s %s", __get_str(ep_name), __get_str(msg))
56);
57
58TRACE_EVENT(cdns3_wa2,
59 TP_PROTO(struct cdns3_endpoint *ep_priv, char *msg),
60 TP_ARGS(ep_priv, msg),
61 TP_STRUCT__entry(
62 __string(ep_name, ep_priv->name)
63 __string(msg, msg)
64 ),
65 TP_fast_assign(
66 __assign_str(ep_name, ep_priv->name);
67 __assign_str(msg, msg);
68 ),
69 TP_printk("WA2: %s %s", __get_str(ep_name), __get_str(msg))
70);
71
72DECLARE_EVENT_CLASS(cdns3_log_doorbell,
73 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
74 TP_ARGS(ep_name, ep_trbaddr),
75 TP_STRUCT__entry(
76 __string(name, ep_name)
77 __field(u32, ep_trbaddr)
78 ),
79 TP_fast_assign(
80 __assign_str(name, ep_name);
81 __entry->ep_trbaddr = ep_trbaddr;
82 ),
83 TP_printk("%s, ep_trbaddr %08x", __get_str(name),
84 __entry->ep_trbaddr)
85);
86
87DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_ep0,
88 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
89 TP_ARGS(ep_name, ep_trbaddr)
90);
91
92DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_epx,
93 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
94 TP_ARGS(ep_name, ep_trbaddr)
95);
96
97DECLARE_EVENT_CLASS(cdns3_log_usb_irq,
98 TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists),
99 TP_ARGS(priv_dev, usb_ists),
100 TP_STRUCT__entry(
101 __field(enum usb_device_speed, speed)
102 __field(u32, usb_ists)
103 __dynamic_array(char, str, CDNS3_MSG_MAX)
104 ),
105 TP_fast_assign(
106 __entry->speed = cdns3_get_speed(priv_dev);
107 __entry->usb_ists = usb_ists;
108 ),
109 TP_printk("%s", cdns3_decode_usb_irq(__get_str(str), __entry->speed,
110 __entry->usb_ists))
111);
112
113DEFINE_EVENT(cdns3_log_usb_irq, cdns3_usb_irq,
114 TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists),
115 TP_ARGS(priv_dev, usb_ists)
116);
117
118DECLARE_EVENT_CLASS(cdns3_log_epx_irq,
119 TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep),
120 TP_ARGS(priv_dev, priv_ep),
121 TP_STRUCT__entry(
122 __string(ep_name, priv_ep->name)
123 __field(u32, ep_sts)
124 __field(u32, ep_traddr)
125 __dynamic_array(char, str, CDNS3_MSG_MAX)
126 ),
127 TP_fast_assign(
128 __assign_str(ep_name, priv_ep->name);
129 __entry->ep_sts = readl(&priv_dev->regs->ep_sts);
130 __entry->ep_traddr = readl(&priv_dev->regs->ep_traddr);
131 ),
132 TP_printk("%s, ep_traddr: %08x",
133 cdns3_decode_epx_irq(__get_str(str),
134 __get_str(ep_name),
135 __entry->ep_sts),
136 __entry->ep_traddr)
137);
138
139DEFINE_EVENT(cdns3_log_epx_irq, cdns3_epx_irq,
140 TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep),
141 TP_ARGS(priv_dev, priv_ep)
142);
143
144DECLARE_EVENT_CLASS(cdns3_log_ep0_irq,
145 TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts),
146 TP_ARGS(priv_dev, ep_sts),
147 TP_STRUCT__entry(
148 __field(int, ep_dir)
149 __field(u32, ep_sts)
150 __dynamic_array(char, str, CDNS3_MSG_MAX)
151 ),
152 TP_fast_assign(
153 __entry->ep_dir = priv_dev->ep0_data_dir;
154 __entry->ep_sts = ep_sts;
155 ),
156 TP_printk("%s", cdns3_decode_ep0_irq(__get_str(str),
157 __entry->ep_dir,
158 __entry->ep_sts))
159);
160
161DEFINE_EVENT(cdns3_log_ep0_irq, cdns3_ep0_irq,
162 TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts),
163 TP_ARGS(priv_dev, ep_sts)
164);
165
166DECLARE_EVENT_CLASS(cdns3_log_ctrl,
167 TP_PROTO(struct usb_ctrlrequest *ctrl),
168 TP_ARGS(ctrl),
169 TP_STRUCT__entry(
170 __field(u8, bRequestType)
171 __field(u8, bRequest)
172 __field(u16, wValue)
173 __field(u16, wIndex)
174 __field(u16, wLength)
175 __dynamic_array(char, str, CDNS3_MSG_MAX)
176 ),
177 TP_fast_assign(
178 __entry->bRequestType = ctrl->bRequestType;
179 __entry->bRequest = ctrl->bRequest;
180 __entry->wValue = le16_to_cpu(ctrl->wValue);
181 __entry->wIndex = le16_to_cpu(ctrl->wIndex);
182 __entry->wLength = le16_to_cpu(ctrl->wLength);
183 ),
184 TP_printk("%s", usb_decode_ctrl(__get_str(str), CDNS3_MSG_MAX,
185 __entry->bRequestType,
186 __entry->bRequest, __entry->wValue,
187 __entry->wIndex, __entry->wLength)
188 )
189);
190
191DEFINE_EVENT(cdns3_log_ctrl, cdns3_ctrl_req,
192 TP_PROTO(struct usb_ctrlrequest *ctrl),
193 TP_ARGS(ctrl)
194);
195
196DECLARE_EVENT_CLASS(cdns3_log_request,
197 TP_PROTO(struct cdns3_request *req),
198 TP_ARGS(req),
199 TP_STRUCT__entry(
200 __string(name, req->priv_ep->name)
201 __field(struct cdns3_request *, req)
202 __field(void *, buf)
203 __field(unsigned int, actual)
204 __field(unsigned int, length)
205 __field(int, status)
206 __field(int, zero)
207 __field(int, short_not_ok)
208 __field(int, no_interrupt)
209 __field(int, start_trb)
210 __field(int, end_trb)
211 __field(struct cdns3_trb *, start_trb_addr)
212 __field(int, flags)
213 ),
214 TP_fast_assign(
215 __assign_str(name, req->priv_ep->name);
216 __entry->req = req;
217 __entry->buf = req->request.buf;
218 __entry->actual = req->request.actual;
219 __entry->length = req->request.length;
220 __entry->status = req->request.status;
221 __entry->zero = req->request.zero;
222 __entry->short_not_ok = req->request.short_not_ok;
223 __entry->no_interrupt = req->request.no_interrupt;
224 __entry->start_trb = req->start_trb;
225 __entry->end_trb = req->end_trb;
226 __entry->start_trb_addr = req->trb;
227 __entry->flags = req->flags;
228 ),
229 TP_printk("%s: req: %p, req buff %p, length: %u/%u %s%s%s, status: %d,"
230 " trb: [start:%d, end:%d: virt addr %pa], flags:%x ",
231 __get_str(name), __entry->req, __entry->buf, __entry->actual,
232 __entry->length,
233 __entry->zero ? "Z" : "z",
234 __entry->short_not_ok ? "S" : "s",
235 __entry->no_interrupt ? "I" : "i",
236 __entry->status,
237 __entry->start_trb,
238 __entry->end_trb,
239 __entry->start_trb_addr,
240 __entry->flags
241 )
242);
243
244DEFINE_EVENT(cdns3_log_request, cdns3_alloc_request,
245 TP_PROTO(struct cdns3_request *req),
246 TP_ARGS(req)
247);
248
249DEFINE_EVENT(cdns3_log_request, cdns3_free_request,
250 TP_PROTO(struct cdns3_request *req),
251 TP_ARGS(req)
252);
253
254DEFINE_EVENT(cdns3_log_request, cdns3_ep_queue,
255 TP_PROTO(struct cdns3_request *req),
256 TP_ARGS(req)
257);
258
259DEFINE_EVENT(cdns3_log_request, cdns3_ep_dequeue,
260 TP_PROTO(struct cdns3_request *req),
261 TP_ARGS(req)
262);
263
264DEFINE_EVENT(cdns3_log_request, cdns3_gadget_giveback,
265 TP_PROTO(struct cdns3_request *req),
266 TP_ARGS(req)
267);
268
269TRACE_EVENT(cdns3_ep0_queue,
270 TP_PROTO(struct cdns3_device *dev_priv, struct usb_request *request),
271 TP_ARGS(dev_priv, request),
272 TP_STRUCT__entry(
273 __field(int, dir)
274 __field(int, length)
275 ),
276 TP_fast_assign(
277 __entry->dir = dev_priv->ep0_data_dir;
278 __entry->length = request->length;
279 ),
280 TP_printk("Queue to ep0%s length: %u", __entry->dir ? "in" : "out",
281 __entry->length)
282);
283
284DECLARE_EVENT_CLASS(cdns3_log_aligned_request,
285 TP_PROTO(struct cdns3_request *priv_req),
286 TP_ARGS(priv_req),
287 TP_STRUCT__entry(
288 __string(name, priv_req->priv_ep->name)
289 __field(struct usb_request *, req)
290 __field(void *, buf)
291 __field(dma_addr_t, dma)
292 __field(void *, aligned_buf)
293 __field(dma_addr_t, aligned_dma)
294 __field(u32, aligned_buf_size)
295 ),
296 TP_fast_assign(
297 __assign_str(name, priv_req->priv_ep->name);
298 __entry->req = &priv_req->request;
299 __entry->buf = priv_req->request.buf;
300 __entry->dma = priv_req->request.dma;
301 __entry->aligned_buf = priv_req->aligned_buf->buf;
302 __entry->aligned_dma = priv_req->aligned_buf->dma;
303 __entry->aligned_buf_size = priv_req->aligned_buf->size;
304 ),
305 TP_printk("%s: req: %p, req buf %p, dma %pad a_buf %p a_dma %pad, size %d",
306 __get_str(name), __entry->req, __entry->buf, &__entry->dma,
307 __entry->aligned_buf, &__entry->aligned_dma,
308 __entry->aligned_buf_size
309 )
310);
311
312DEFINE_EVENT(cdns3_log_aligned_request, cdns3_free_aligned_request,
313 TP_PROTO(struct cdns3_request *req),
314 TP_ARGS(req)
315);
316
317DEFINE_EVENT(cdns3_log_aligned_request, cdns3_prepare_aligned_request,
318 TP_PROTO(struct cdns3_request *req),
319 TP_ARGS(req)
320);
321
322DECLARE_EVENT_CLASS(cdns3_log_trb,
323 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
324 TP_ARGS(priv_ep, trb),
325 TP_STRUCT__entry(
326 __string(name, priv_ep->name)
327 __field(struct cdns3_trb *, trb)
328 __field(u32, buffer)
329 __field(u32, length)
330 __field(u32, control)
331 __field(u32, type)
332 ),
333 TP_fast_assign(
334 __assign_str(name, priv_ep->name);
335 __entry->trb = trb;
336 __entry->buffer = trb->buffer;
337 __entry->length = trb->length;
338 __entry->control = trb->control;
339 __entry->type = usb_endpoint_type(priv_ep->endpoint.desc);
340 ),
341 TP_printk("%s: trb %p, dma buf: 0x%08x, size: %ld, burst: %d ctrl: 0x%08x (%s%s%s%s%s%s%s)",
342 __get_str(name), __entry->trb, __entry->buffer,
343 TRB_LEN(__entry->length),
344 (u8)TRB_BURST_LEN_GET(__entry->length),
345 __entry->control,
346 __entry->control & TRB_CYCLE ? "C=1, " : "C=0, ",
347 __entry->control & TRB_TOGGLE ? "T=1, " : "T=0, ",
348 __entry->control & TRB_ISP ? "ISP, " : "",
349 __entry->control & TRB_FIFO_MODE ? "FIFO, " : "",
350 __entry->control & TRB_CHAIN ? "CHAIN, " : "",
351 __entry->control & TRB_IOC ? "IOC, " : "",
352 TRB_FIELD_TO_TYPE(__entry->control) == TRB_NORMAL ? "Normal" : "LINK"
353 )
354);
355
356DEFINE_EVENT(cdns3_log_trb, cdns3_prepare_trb,
357 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
358 TP_ARGS(priv_ep, trb)
359);
360
361DEFINE_EVENT(cdns3_log_trb, cdns3_complete_trb,
362 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
363 TP_ARGS(priv_ep, trb)
364);
365
366DECLARE_EVENT_CLASS(cdns3_log_ring,
367 TP_PROTO(struct cdns3_endpoint *priv_ep),
368 TP_ARGS(priv_ep),
369 TP_STRUCT__entry(
370 __dynamic_array(u8, ring, TRB_RING_SIZE)
371 __dynamic_array(u8, priv_ep, sizeof(struct cdns3_endpoint))
372 __dynamic_array(char, buffer,
373 (TRBS_PER_SEGMENT * 65) + CDNS3_MSG_MAX)
374 ),
375 TP_fast_assign(
376 memcpy(__get_dynamic_array(priv_ep), priv_ep,
377 sizeof(struct cdns3_endpoint));
378 memcpy(__get_dynamic_array(ring), priv_ep->trb_pool,
379 TRB_RING_SIZE);
380 ),
381
382 TP_printk("%s",
383 cdns3_dbg_ring((struct cdns3_endpoint *)__get_str(priv_ep),
384 (struct cdns3_trb *)__get_str(ring),
385 __get_str(buffer)))
386);
387
388DEFINE_EVENT(cdns3_log_ring, cdns3_ring,
389 TP_PROTO(struct cdns3_endpoint *priv_ep),
390 TP_ARGS(priv_ep)
391);
392
393DECLARE_EVENT_CLASS(cdns3_log_ep,
394 TP_PROTO(struct cdns3_endpoint *priv_ep),
395 TP_ARGS(priv_ep),
396 TP_STRUCT__entry(
397 __string(name, priv_ep->name)
398 __field(unsigned int, maxpacket)
399 __field(unsigned int, maxpacket_limit)
400 __field(unsigned int, max_streams)
401 __field(unsigned int, maxburst)
402 __field(unsigned int, flags)
403 __field(unsigned int, dir)
404 __field(u8, enqueue)
405 __field(u8, dequeue)
406 ),
407 TP_fast_assign(
408 __assign_str(name, priv_ep->name);
409 __entry->maxpacket = priv_ep->endpoint.maxpacket;
410 __entry->maxpacket_limit = priv_ep->endpoint.maxpacket_limit;
411 __entry->max_streams = priv_ep->endpoint.max_streams;
412 __entry->maxburst = priv_ep->endpoint.maxburst;
413 __entry->flags = priv_ep->flags;
414 __entry->dir = priv_ep->dir;
415 __entry->enqueue = priv_ep->enqueue;
416 __entry->dequeue = priv_ep->dequeue;
417 ),
418 TP_printk("%s: mps: %d/%d. streams: %d, burst: %d, enq idx: %d, "
419 "deq idx: %d, flags %s%s%s%s%s%s%s%s, dir: %s",
420 __get_str(name), __entry->maxpacket,
421 __entry->maxpacket_limit, __entry->max_streams,
422 __entry->maxburst, __entry->enqueue,
423 __entry->dequeue,
424 __entry->flags & EP_ENABLED ? "EN | " : "",
425 __entry->flags & EP_STALLED ? "STALLED | " : "",
426 __entry->flags & EP_WEDGE ? "WEDGE | " : "",
427 __entry->flags & EP_TRANSFER_STARTED ? "STARTED | " : "",
428 __entry->flags & EP_UPDATE_EP_TRBADDR ? "UPD TRB | " : "",
429 __entry->flags & EP_PENDING_REQUEST ? "REQ PEN | " : "",
430 __entry->flags & EP_RING_FULL ? "RING FULL |" : "",
431 __entry->flags & EP_CLAIMED ? "CLAIMED " : "",
432 __entry->dir ? "IN" : "OUT"
433 )
434);
435
436DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_enable,
437 TP_PROTO(struct cdns3_endpoint *priv_ep),
438 TP_ARGS(priv_ep)
439);
440
441DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_disable,
442 TP_PROTO(struct cdns3_endpoint *priv_ep),
443 TP_ARGS(priv_ep)
444);
445
446DECLARE_EVENT_CLASS(cdns3_log_request_handled,
447 TP_PROTO(struct cdns3_request *priv_req, int current_index,
448 int handled),
449 TP_ARGS(priv_req, current_index, handled),
450 TP_STRUCT__entry(
451 __field(struct cdns3_request *, priv_req)
452 __field(unsigned int, dma_position)
453 __field(unsigned int, handled)
454 __field(unsigned int, dequeue_idx)
455 __field(unsigned int, enqueue_idx)
456 __field(unsigned int, start_trb)
457 __field(unsigned int, end_trb)
458 ),
459 TP_fast_assign(
460 __entry->priv_req = priv_req;
461 __entry->dma_position = current_index;
462 __entry->handled = handled;
463 __entry->dequeue_idx = priv_req->priv_ep->dequeue;
464 __entry->enqueue_idx = priv_req->priv_ep->enqueue;
465 __entry->start_trb = priv_req->start_trb;
466 __entry->end_trb = priv_req->end_trb;
467 ),
468 TP_printk("Req: %p %s, DMA pos: %d, ep deq: %d, ep enq: %d,"
469 " start trb: %d, end trb: %d",
470 __entry->priv_req,
471 __entry->handled ? "handled" : "not handled",
472 __entry->dma_position, __entry->dequeue_idx,
473 __entry->enqueue_idx, __entry->start_trb,
474 __entry->end_trb
475 )
476);
477
478DEFINE_EVENT(cdns3_log_request_handled, cdns3_request_handled,
479 TP_PROTO(struct cdns3_request *priv_req, int current_index,
480 int handled),
481 TP_ARGS(priv_req, current_index, handled)
482);
483#endif /* __LINUX_CDNS3_TRACE */
484
485/* this part must be outside header guard */
486
487#undef TRACE_INCLUDE_PATH
488#define TRACE_INCLUDE_PATH .
489
490#undef TRACE_INCLUDE_FILE
491#define TRACE_INCLUDE_FILE trace
492
493#include <trace/define_trace.h>
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index 0a7c45e85481..76f3e80623db 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -5,6 +5,7 @@
5 5
6obj-$(CONFIG_USB_COMMON) += usb-common.o 6obj-$(CONFIG_USB_COMMON) += usb-common.o
7usb-common-y += common.o 7usb-common-y += common.o
8usb-common-$(CONFIG_TRACING) += debug.o
8usb-common-$(CONFIG_USB_LED_TRIG) += led.o 9usb-common-$(CONFIG_USB_LED_TRIG) += led.o
9 10
10obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o 11obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
diff --git a/drivers/usb/common/debug.c b/drivers/usb/common/debug.c
new file mode 100644
index 000000000000..92a986aeaa5d
--- /dev/null
+++ b/drivers/usb/common/debug.c
@@ -0,0 +1,268 @@
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * Common USB debugging functions
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/usb/ch9.h>
12
13static void usb_decode_get_status(__u8 bRequestType, __u16 wIndex,
14 __u16 wLength, char *str, size_t size)
15{
16 switch (bRequestType & USB_RECIP_MASK) {
17 case USB_RECIP_DEVICE:
18 snprintf(str, size, "Get Device Status(Length = %d)", wLength);
19 break;
20 case USB_RECIP_INTERFACE:
21 snprintf(str, size,
22 "Get Interface Status(Intf = %d, Length = %d)",
23 wIndex, wLength);
24 break;
25 case USB_RECIP_ENDPOINT:
26 snprintf(str, size, "Get Endpoint Status(ep%d%s)",
27 wIndex & ~USB_DIR_IN,
28 wIndex & USB_DIR_IN ? "in" : "out");
29 break;
30 }
31}
32
33static const char *usb_decode_device_feature(u16 wValue)
34{
35 switch (wValue) {
36 case USB_DEVICE_SELF_POWERED:
37 return "Self Powered";
38 case USB_DEVICE_REMOTE_WAKEUP:
39 return "Remote Wakeup";
40 case USB_DEVICE_TEST_MODE:
41 return "Test Mode";
42 case USB_DEVICE_U1_ENABLE:
43 return "U1 Enable";
44 case USB_DEVICE_U2_ENABLE:
45 return "U2 Enable";
46 case USB_DEVICE_LTM_ENABLE:
47 return "LTM Enable";
48 default:
49 return "UNKNOWN";
50 }
51}
52
53static const char *usb_decode_test_mode(u16 wIndex)
54{
55 switch (wIndex) {
56 case TEST_J:
57 return ": TEST_J";
58 case TEST_K:
59 return ": TEST_K";
60 case TEST_SE0_NAK:
61 return ": TEST_SE0_NAK";
62 case TEST_PACKET:
63 return ": TEST_PACKET";
64 case TEST_FORCE_EN:
65 return ": TEST_FORCE_EN";
66 default:
67 return ": UNKNOWN";
68 }
69}
70
71static void usb_decode_set_clear_feature(__u8 bRequestType,
72 __u8 bRequest, __u16 wValue,
73 __u16 wIndex, char *str, size_t size)
74{
75 switch (bRequestType & USB_RECIP_MASK) {
76 case USB_RECIP_DEVICE:
77 snprintf(str, size, "%s Device Feature(%s%s)",
78 bRequest == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
79 usb_decode_device_feature(wValue),
80 wValue == USB_DEVICE_TEST_MODE ?
81 usb_decode_test_mode(wIndex) : "");
82 break;
83 case USB_RECIP_INTERFACE:
84 snprintf(str, size, "%s Interface Feature(%s)",
85 bRequest == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
86 wValue == USB_INTRF_FUNC_SUSPEND ?
87 "Function Suspend" : "UNKNOWN");
88 break;
89 case USB_RECIP_ENDPOINT:
90 snprintf(str, size, "%s Endpoint Feature(%s ep%d%s)",
91 bRequest == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
92 wValue == USB_ENDPOINT_HALT ? "Halt" : "UNKNOWN",
93 wIndex & ~USB_DIR_IN,
94 wIndex & USB_DIR_IN ? "in" : "out");
95 break;
96 }
97}
98
99static void usb_decode_set_address(__u16 wValue, char *str, size_t size)
100{
101 snprintf(str, size, "Set Address(Addr = %02x)", wValue);
102}
103
104static void usb_decode_get_set_descriptor(__u8 bRequestType, __u8 bRequest,
105 __u16 wValue, __u16 wIndex,
106 __u16 wLength, char *str, size_t size)
107{
108 char *s;
109
110 switch (wValue >> 8) {
111 case USB_DT_DEVICE:
112 s = "Device";
113 break;
114 case USB_DT_CONFIG:
115 s = "Configuration";
116 break;
117 case USB_DT_STRING:
118 s = "String";
119 break;
120 case USB_DT_INTERFACE:
121 s = "Interface";
122 break;
123 case USB_DT_ENDPOINT:
124 s = "Endpoint";
125 break;
126 case USB_DT_DEVICE_QUALIFIER:
127 s = "Device Qualifier";
128 break;
129 case USB_DT_OTHER_SPEED_CONFIG:
130 s = "Other Speed Config";
131 break;
132 case USB_DT_INTERFACE_POWER:
133 s = "Interface Power";
134 break;
135 case USB_DT_OTG:
136 s = "OTG";
137 break;
138 case USB_DT_DEBUG:
139 s = "Debug";
140 break;
141 case USB_DT_INTERFACE_ASSOCIATION:
142 s = "Interface Association";
143 break;
144 case USB_DT_BOS:
145 s = "BOS";
146 break;
147 case USB_DT_DEVICE_CAPABILITY:
148 s = "Device Capability";
149 break;
150 case USB_DT_PIPE_USAGE:
151 s = "Pipe Usage";
152 break;
153 case USB_DT_SS_ENDPOINT_COMP:
154 s = "SS Endpoint Companion";
155 break;
156 case USB_DT_SSP_ISOC_ENDPOINT_COMP:
157 s = "SSP Isochronous Endpoint Companion";
158 break;
159 default:
160 s = "UNKNOWN";
161 break;
162 }
163
164 snprintf(str, size, "%s %s Descriptor(Index = %d, Length = %d)",
165 bRequest == USB_REQ_GET_DESCRIPTOR ? "Get" : "Set",
166 s, wValue & 0xff, wLength);
167}
168
169static void usb_decode_get_configuration(__u16 wLength, char *str, size_t size)
170{
171 snprintf(str, size, "Get Configuration(Length = %d)", wLength);
172}
173
174static void usb_decode_set_configuration(__u8 wValue, char *str, size_t size)
175{
176 snprintf(str, size, "Set Configuration(Config = %d)", wValue);
177}
178
179static void usb_decode_get_intf(__u16 wIndex, __u16 wLength, char *str,
180 size_t size)
181{
182 snprintf(str, size, "Get Interface(Intf = %d, Length = %d)",
183 wIndex, wLength);
184}
185
186static void usb_decode_set_intf(__u8 wValue, __u16 wIndex, char *str,
187 size_t size)
188{
189 snprintf(str, size, "Set Interface(Intf = %d, Alt.Setting = %d)",
190 wIndex, wValue);
191}
192
193static void usb_decode_synch_frame(__u16 wIndex, __u16 wLength,
194 char *str, size_t size)
195{
196 snprintf(str, size, "Synch Frame(Endpoint = %d, Length = %d)",
197 wIndex, wLength);
198}
199
200static void usb_decode_set_sel(__u16 wLength, char *str, size_t size)
201{
202 snprintf(str, size, "Set SEL(Length = %d)", wLength);
203}
204
205static void usb_decode_set_isoch_delay(__u8 wValue, char *str, size_t size)
206{
207 snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", wValue);
208}
209
210/**
211 * usb_decode_ctrl - returns a string representation of ctrl request
212 */
213const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
214 __u8 bRequest, __u16 wValue, __u16 wIndex,
215 __u16 wLength)
216{
217 switch (bRequest) {
218 case USB_REQ_GET_STATUS:
219 usb_decode_get_status(bRequestType, wIndex, wLength, str, size);
220 break;
221 case USB_REQ_CLEAR_FEATURE:
222 case USB_REQ_SET_FEATURE:
223 usb_decode_set_clear_feature(bRequestType, bRequest, wValue,
224 wIndex, str, size);
225 break;
226 case USB_REQ_SET_ADDRESS:
227 usb_decode_set_address(wValue, str, size);
228 break;
229 case USB_REQ_GET_DESCRIPTOR:
230 case USB_REQ_SET_DESCRIPTOR:
231 usb_decode_get_set_descriptor(bRequestType, bRequest, wValue,
232 wIndex, wLength, str, size);
233 break;
234 case USB_REQ_GET_CONFIGURATION:
235 usb_decode_get_configuration(wLength, str, size);
236 break;
237 case USB_REQ_SET_CONFIGURATION:
238 usb_decode_set_configuration(wValue, str, size);
239 break;
240 case USB_REQ_GET_INTERFACE:
241 usb_decode_get_intf(wIndex, wLength, str, size);
242 break;
243 case USB_REQ_SET_INTERFACE:
244 usb_decode_set_intf(wValue, wIndex, str, size);
245 break;
246 case USB_REQ_SYNCH_FRAME:
247 usb_decode_synch_frame(wIndex, wLength, str, size);
248 break;
249 case USB_REQ_SET_SEL:
250 usb_decode_set_sel(wLength, str, size);
251 break;
252 case USB_REQ_SET_ISOCH_DELAY:
253 usb_decode_set_isoch_delay(wValue, str, size);
254 break;
255 default:
256 snprintf(str, size, "%02x %02x %02x %02x %02x %02x %02x %02x",
257 bRequestType, bRequest,
258 (u8)(cpu_to_le16(wValue) & 0xff),
259 (u8)(cpu_to_le16(wValue) >> 8),
260 (u8)(cpu_to_le16(wIndex) & 0xff),
261 (u8)(cpu_to_le16(wIndex) >> 8),
262 (u8)(cpu_to_le16(wLength) & 0xff),
263 (u8)(cpu_to_le16(wLength) >> 8));
264 }
265
266 return str;
267}
268EXPORT_SYMBOL_GPL(usb_decode_ctrl);
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index bff48a8a1984..6be10e496e10 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -3224,14 +3224,15 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg,
3224 struct dwc2_hsotg_ep *ep, 3224 struct dwc2_hsotg_ep *ep,
3225 int result) 3225 int result)
3226{ 3226{
3227 struct dwc2_hsotg_req *req, *treq;
3228 unsigned int size; 3227 unsigned int size;
3229 3228
3230 ep->req = NULL; 3229 ep->req = NULL;
3231 3230
3232 list_for_each_entry_safe(req, treq, &ep->queue, queue) 3231 while (!list_empty(&ep->queue)) {
3233 dwc2_hsotg_complete_request(hsotg, ep, req, 3232 struct dwc2_hsotg_req *req = get_ep_head(ep);
3234 result); 3233
3234 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3235 }
3235 3236
3236 if (!hsotg->dedicated_fifos) 3237 if (!hsotg->dedicated_fifos)
3237 return; 3238 return;
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 98bce85c29d0..f56d5058a66c 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -252,12 +252,25 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
252 reg |= DWC3_DCTL_CSFTRST; 252 reg |= DWC3_DCTL_CSFTRST;
253 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 253 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
254 254
255 /*
256 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
257 * is cleared only after all the clocks are synchronized. This can
258 * take a little more than 50ms. Set the polling rate at 20ms
259 * for 10 times instead.
260 */
261 if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
262 retries = 10;
263
255 do { 264 do {
256 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 265 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
257 if (!(reg & DWC3_DCTL_CSFTRST)) 266 if (!(reg & DWC3_DCTL_CSFTRST))
258 goto done; 267 goto done;
259 268
260 udelay(1); 269 if (dwc3_is_usb31(dwc) &&
270 dwc->revision >= DWC3_USB31_REVISION_190A)
271 msleep(20);
272 else
273 udelay(1);
261 } while (--retries); 274 } while (--retries);
262 275
263 phy_exit(dwc->usb3_generic_phy); 276 phy_exit(dwc->usb3_generic_phy);
@@ -267,11 +280,11 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
267 280
268done: 281done:
269 /* 282 /*
270 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, 283 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
271 * we must wait at least 50ms before accessing the PHY domain 284 * is cleared, we must wait at least 50ms before accessing the PHY
272 * (synchronization delay). DWC_usb31 programming guide section 1.3.2. 285 * domain (synchronization delay).
273 */ 286 */
274 if (dwc3_is_usb31(dwc)) 287 if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
275 msleep(50); 288 msleep(50);
276 289
277 return 0; 290 return 0;
@@ -686,8 +699,7 @@ static void dwc3_core_exit(struct dwc3 *dwc)
686 usb_phy_set_suspend(dwc->usb3_phy, 1); 699 usb_phy_set_suspend(dwc->usb3_phy, 1);
687 phy_power_off(dwc->usb2_generic_phy); 700 phy_power_off(dwc->usb2_generic_phy);
688 phy_power_off(dwc->usb3_generic_phy); 701 phy_power_off(dwc->usb3_generic_phy);
689 clk_bulk_disable(dwc->num_clks, dwc->clks); 702 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
690 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
691 reset_control_assert(dwc->reset); 703 reset_control_assert(dwc->reset);
692} 704}
693 705
@@ -1309,8 +1321,7 @@ static void dwc3_get_properties(struct dwc3 *dwc)
1309 dwc->lpm_nyet_threshold = lpm_nyet_threshold; 1321 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1310 dwc->tx_de_emphasis = tx_de_emphasis; 1322 dwc->tx_de_emphasis = tx_de_emphasis;
1311 1323
1312 dwc->hird_threshold = hird_threshold 1324 dwc->hird_threshold = hird_threshold;
1313 | (dwc->is_utmi_l1_suspend << 4);
1314 1325
1315 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1326 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1316 dwc->rx_max_burst_prd = rx_max_burst_prd; 1327 dwc->rx_max_burst_prd = rx_max_burst_prd;
@@ -1435,7 +1446,7 @@ static int dwc3_probe(struct platform_device *pdev)
1435 if (dev->of_node) { 1446 if (dev->of_node) {
1436 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); 1447 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1437 1448
1438 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks); 1449 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1439 if (ret == -EPROBE_DEFER) 1450 if (ret == -EPROBE_DEFER)
1440 return ret; 1451 return ret;
1441 /* 1452 /*
@@ -1448,16 +1459,12 @@ static int dwc3_probe(struct platform_device *pdev)
1448 1459
1449 ret = reset_control_deassert(dwc->reset); 1460 ret = reset_control_deassert(dwc->reset);
1450 if (ret) 1461 if (ret)
1451 goto put_clks; 1462 return ret;
1452 1463
1453 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); 1464 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1454 if (ret) 1465 if (ret)
1455 goto assert_reset; 1466 goto assert_reset;
1456 1467
1457 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1458 if (ret)
1459 goto unprepare_clks;
1460
1461 if (!dwc3_core_is_valid(dwc)) { 1468 if (!dwc3_core_is_valid(dwc)) {
1462 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1469 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1463 ret = -ENODEV; 1470 ret = -ENODEV;
@@ -1530,13 +1537,9 @@ err1:
1530 pm_runtime_disable(&pdev->dev); 1537 pm_runtime_disable(&pdev->dev);
1531 1538
1532disable_clks: 1539disable_clks:
1533 clk_bulk_disable(dwc->num_clks, dwc->clks); 1540 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1534unprepare_clks:
1535 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1536assert_reset: 1541assert_reset:
1537 reset_control_assert(dwc->reset); 1542 reset_control_assert(dwc->reset);
1538put_clks:
1539 clk_bulk_put(dwc->num_clks, dwc->clks);
1540 1543
1541 return ret; 1544 return ret;
1542} 1545}
@@ -1559,7 +1562,6 @@ static int dwc3_remove(struct platform_device *pdev)
1559 1562
1560 dwc3_free_event_buffers(dwc); 1563 dwc3_free_event_buffers(dwc);
1561 dwc3_free_scratch_buffers(dwc); 1564 dwc3_free_scratch_buffers(dwc);
1562 clk_bulk_put(dwc->num_clks, dwc->clks);
1563 1565
1564 return 0; 1566 return 0;
1565} 1567}
@@ -1573,14 +1575,10 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1573 if (ret) 1575 if (ret)
1574 return ret; 1576 return ret;
1575 1577
1576 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); 1578 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1577 if (ret) 1579 if (ret)
1578 goto assert_reset; 1580 goto assert_reset;
1579 1581
1580 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1581 if (ret)
1582 goto unprepare_clks;
1583
1584 ret = dwc3_core_init(dwc); 1582 ret = dwc3_core_init(dwc);
1585 if (ret) 1583 if (ret)
1586 goto disable_clks; 1584 goto disable_clks;
@@ -1588,9 +1586,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1588 return 0; 1586 return 0;
1589 1587
1590disable_clks: 1588disable_clks:
1591 clk_bulk_disable(dwc->num_clks, dwc->clks); 1589 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1592unprepare_clks:
1593 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1594assert_reset: 1590assert_reset:
1595 reset_control_assert(dwc->reset); 1591 reset_control_assert(dwc->reset);
1596 1592
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 3dd783b889cb..1c8b349379af 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1137,6 +1137,8 @@ struct dwc3 {
1137#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) 1137#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1138#define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31) 1138#define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31)
1139#define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31) 1139#define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31)
1140#define DWC3_USB31_REVISION_180A (0x3138302a | DWC3_REVISION_IS_DWC31)
1141#define DWC3_USB31_REVISION_190A (0x3139302a | DWC3_REVISION_IS_DWC31)
1140 1142
1141 u32 version_type; 1143 u32 version_type;
1142 1144
diff --git a/drivers/usb/dwc3/debug.h b/drivers/usb/dwc3/debug.h
index 068259fdfb0c..9baabed87d61 100644
--- a/drivers/usb/dwc3/debug.h
+++ b/drivers/usb/dwc3/debug.h
@@ -246,258 +246,6 @@ static inline const char *dwc3_gadget_event_string(char *str, size_t size,
246 return str; 246 return str;
247} 247}
248 248
249static inline void dwc3_decode_get_status(__u8 t, __u16 i, __u16 l, char *str,
250 size_t size)
251{
252 switch (t & USB_RECIP_MASK) {
253 case USB_RECIP_DEVICE:
254 snprintf(str, size, "Get Device Status(Length = %d)", l);
255 break;
256 case USB_RECIP_INTERFACE:
257 snprintf(str, size, "Get Interface Status(Intf = %d, Length = %d)",
258 i, l);
259 break;
260 case USB_RECIP_ENDPOINT:
261 snprintf(str, size, "Get Endpoint Status(ep%d%s)",
262 i & ~USB_DIR_IN,
263 i & USB_DIR_IN ? "in" : "out");
264 break;
265 }
266}
267
268static inline void dwc3_decode_set_clear_feature(__u8 t, __u8 b, __u16 v,
269 __u16 i, char *str, size_t size)
270{
271 switch (t & USB_RECIP_MASK) {
272 case USB_RECIP_DEVICE:
273 snprintf(str, size, "%s Device Feature(%s%s)",
274 b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
275 ({char *s;
276 switch (v) {
277 case USB_DEVICE_SELF_POWERED:
278 s = "Self Powered";
279 break;
280 case USB_DEVICE_REMOTE_WAKEUP:
281 s = "Remote Wakeup";
282 break;
283 case USB_DEVICE_TEST_MODE:
284 s = "Test Mode";
285 break;
286 case USB_DEVICE_U1_ENABLE:
287 s = "U1 Enable";
288 break;
289 case USB_DEVICE_U2_ENABLE:
290 s = "U2 Enable";
291 break;
292 case USB_DEVICE_LTM_ENABLE:
293 s = "LTM Enable";
294 break;
295 default:
296 s = "UNKNOWN";
297 } s; }),
298 v == USB_DEVICE_TEST_MODE ?
299 ({ char *s;
300 switch (i) {
301 case TEST_J:
302 s = ": TEST_J";
303 break;
304 case TEST_K:
305 s = ": TEST_K";
306 break;
307 case TEST_SE0_NAK:
308 s = ": TEST_SE0_NAK";
309 break;
310 case TEST_PACKET:
311 s = ": TEST_PACKET";
312 break;
313 case TEST_FORCE_EN:
314 s = ": TEST_FORCE_EN";
315 break;
316 default:
317 s = ": UNKNOWN";
318 } s; }) : "");
319 break;
320 case USB_RECIP_INTERFACE:
321 snprintf(str, size, "%s Interface Feature(%s)",
322 b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
323 v == USB_INTRF_FUNC_SUSPEND ?
324 "Function Suspend" : "UNKNOWN");
325 break;
326 case USB_RECIP_ENDPOINT:
327 snprintf(str, size, "%s Endpoint Feature(%s ep%d%s)",
328 b == USB_REQ_CLEAR_FEATURE ? "Clear" : "Set",
329 v == USB_ENDPOINT_HALT ? "Halt" : "UNKNOWN",
330 i & ~USB_DIR_IN,
331 i & USB_DIR_IN ? "in" : "out");
332 break;
333 }
334}
335
336static inline void dwc3_decode_set_address(__u16 v, char *str, size_t size)
337{
338 snprintf(str, size, "Set Address(Addr = %02x)", v);
339}
340
341static inline void dwc3_decode_get_set_descriptor(__u8 t, __u8 b, __u16 v,
342 __u16 i, __u16 l, char *str, size_t size)
343{
344 snprintf(str, size, "%s %s Descriptor(Index = %d, Length = %d)",
345 b == USB_REQ_GET_DESCRIPTOR ? "Get" : "Set",
346 ({ char *s;
347 switch (v >> 8) {
348 case USB_DT_DEVICE:
349 s = "Device";
350 break;
351 case USB_DT_CONFIG:
352 s = "Configuration";
353 break;
354 case USB_DT_STRING:
355 s = "String";
356 break;
357 case USB_DT_INTERFACE:
358 s = "Interface";
359 break;
360 case USB_DT_ENDPOINT:
361 s = "Endpoint";
362 break;
363 case USB_DT_DEVICE_QUALIFIER:
364 s = "Device Qualifier";
365 break;
366 case USB_DT_OTHER_SPEED_CONFIG:
367 s = "Other Speed Config";
368 break;
369 case USB_DT_INTERFACE_POWER:
370 s = "Interface Power";
371 break;
372 case USB_DT_OTG:
373 s = "OTG";
374 break;
375 case USB_DT_DEBUG:
376 s = "Debug";
377 break;
378 case USB_DT_INTERFACE_ASSOCIATION:
379 s = "Interface Association";
380 break;
381 case USB_DT_BOS:
382 s = "BOS";
383 break;
384 case USB_DT_DEVICE_CAPABILITY:
385 s = "Device Capability";
386 break;
387 case USB_DT_PIPE_USAGE:
388 s = "Pipe Usage";
389 break;
390 case USB_DT_SS_ENDPOINT_COMP:
391 s = "SS Endpoint Companion";
392 break;
393 case USB_DT_SSP_ISOC_ENDPOINT_COMP:
394 s = "SSP Isochronous Endpoint Companion";
395 break;
396 default:
397 s = "UNKNOWN";
398 break;
399 } s; }), v & 0xff, l);
400}
401
402
403static inline void dwc3_decode_get_configuration(__u16 l, char *str,
404 size_t size)
405{
406 snprintf(str, size, "Get Configuration(Length = %d)", l);
407}
408
409static inline void dwc3_decode_set_configuration(__u8 v, char *str, size_t size)
410{
411 snprintf(str, size, "Set Configuration(Config = %d)", v);
412}
413
414static inline void dwc3_decode_get_intf(__u16 i, __u16 l, char *str,
415 size_t size)
416{
417 snprintf(str, size, "Get Interface(Intf = %d, Length = %d)", i, l);
418}
419
420static inline void dwc3_decode_set_intf(__u8 v, __u16 i, char *str, size_t size)
421{
422 snprintf(str, size, "Set Interface(Intf = %d, Alt.Setting = %d)", i, v);
423}
424
425static inline void dwc3_decode_synch_frame(__u16 i, __u16 l, char *str,
426 size_t size)
427{
428 snprintf(str, size, "Synch Frame(Endpoint = %d, Length = %d)", i, l);
429}
430
431static inline void dwc3_decode_set_sel(__u16 l, char *str, size_t size)
432{
433 snprintf(str, size, "Set SEL(Length = %d)", l);
434}
435
436static inline void dwc3_decode_set_isoch_delay(__u8 v, char *str, size_t size)
437{
438 snprintf(str, size, "Set Isochronous Delay(Delay = %d ns)", v);
439}
440
441/**
442 * dwc3_decode_ctrl - returns a string represetion of ctrl request
443 */
444static inline const char *dwc3_decode_ctrl(char *str, size_t size,
445 __u8 bRequestType, __u8 bRequest, __u16 wValue, __u16 wIndex,
446 __u16 wLength)
447{
448 switch (bRequest) {
449 case USB_REQ_GET_STATUS:
450 dwc3_decode_get_status(bRequestType, wIndex, wLength, str,
451 size);
452 break;
453 case USB_REQ_CLEAR_FEATURE:
454 case USB_REQ_SET_FEATURE:
455 dwc3_decode_set_clear_feature(bRequestType, bRequest, wValue,
456 wIndex, str, size);
457 break;
458 case USB_REQ_SET_ADDRESS:
459 dwc3_decode_set_address(wValue, str, size);
460 break;
461 case USB_REQ_GET_DESCRIPTOR:
462 case USB_REQ_SET_DESCRIPTOR:
463 dwc3_decode_get_set_descriptor(bRequestType, bRequest, wValue,
464 wIndex, wLength, str, size);
465 break;
466 case USB_REQ_GET_CONFIGURATION:
467 dwc3_decode_get_configuration(wLength, str, size);
468 break;
469 case USB_REQ_SET_CONFIGURATION:
470 dwc3_decode_set_configuration(wValue, str, size);
471 break;
472 case USB_REQ_GET_INTERFACE:
473 dwc3_decode_get_intf(wIndex, wLength, str, size);
474 break;
475 case USB_REQ_SET_INTERFACE:
476 dwc3_decode_set_intf(wValue, wIndex, str, size);
477 break;
478 case USB_REQ_SYNCH_FRAME:
479 dwc3_decode_synch_frame(wIndex, wLength, str, size);
480 break;
481 case USB_REQ_SET_SEL:
482 dwc3_decode_set_sel(wLength, str, size);
483 break;
484 case USB_REQ_SET_ISOCH_DELAY:
485 dwc3_decode_set_isoch_delay(wValue, str, size);
486 break;
487 default:
488 snprintf(str, size, "%02x %02x %02x %02x %02x %02x %02x %02x",
489 bRequestType, bRequest,
490 cpu_to_le16(wValue) & 0xff,
491 cpu_to_le16(wValue) >> 8,
492 cpu_to_le16(wIndex) & 0xff,
493 cpu_to_le16(wIndex) >> 8,
494 cpu_to_le16(wLength) & 0xff,
495 cpu_to_le16(wLength) >> 8);
496 }
497
498 return str;
499}
500
501/** 249/**
502 * dwc3_ep_event_string - returns event name 250 * dwc3_ep_event_string - returns event name
503 * @event: then event code 251 * @event: then event code
diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c
index a69eb4a7b832..1e14a6f4884b 100644
--- a/drivers/usb/dwc3/dwc3-keystone.c
+++ b/drivers/usb/dwc3/dwc3-keystone.c
@@ -81,7 +81,6 @@ static int kdwc3_probe(struct platform_device *pdev)
81 struct device *dev = &pdev->dev; 81 struct device *dev = &pdev->dev;
82 struct device_node *node = pdev->dev.of_node; 82 struct device_node *node = pdev->dev.of_node;
83 struct dwc3_keystone *kdwc; 83 struct dwc3_keystone *kdwc;
84 struct resource *res;
85 int error, irq; 84 int error, irq;
86 85
87 kdwc = devm_kzalloc(dev, sizeof(*kdwc), GFP_KERNEL); 86 kdwc = devm_kzalloc(dev, sizeof(*kdwc), GFP_KERNEL);
@@ -92,8 +91,7 @@ static int kdwc3_probe(struct platform_device *pdev)
92 91
93 kdwc->dev = dev; 92 kdwc->dev = dev;
94 93
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 94 kdwc->usbss = devm_platform_ioremap_resource(pdev, 0);
96 kdwc->usbss = devm_ioremap_resource(dev, res);
97 if (IS_ERR(kdwc->usbss)) 95 if (IS_ERR(kdwc->usbss))
98 return PTR_ERR(kdwc->usbss); 96 return PTR_ERR(kdwc->usbss);
99 97
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index d73ccd9e1366..8a3ec1a951fe 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -562,7 +562,13 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
562static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev) 562static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
563{ 563{
564 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev); 564 struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
565 int i; 565 int i, ret;
566
567 if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
568 ret = regulator_disable(priv->vbus);
569 if (ret)
570 return ret;
571 }
566 572
567 for (i = 0 ; i < PHY_COUNT ; ++i) { 573 for (i = 0 ; i < PHY_COUNT ; ++i) {
568 phy_power_off(priv->phys[i]); 574 phy_power_off(priv->phys[i]);
@@ -597,6 +603,12 @@ static int __maybe_unused dwc3_meson_g12a_resume(struct device *dev)
597 return ret; 603 return ret;
598 } 604 }
599 605
606 if (priv->vbus && priv->otg_phy_mode == PHY_MODE_USB_HOST) {
607 ret = regulator_enable(priv->vbus);
608 if (ret)
609 return ret;
610 }
611
600 return 0; 612 return 0;
601} 613}
602 614
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 6f711d58d82f..8c3de2d258bf 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -14,7 +14,6 @@
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/platform_data/dwc3-omap.h>
18#include <linux/pm_runtime.h> 17#include <linux/pm_runtime.h>
19#include <linux/dma-mapping.h> 18#include <linux/dma-mapping.h>
20#include <linux/ioport.h> 19#include <linux/ioport.h>
@@ -106,6 +105,12 @@
106#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) 105#define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
107#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) 106#define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
108 107
108enum dwc3_omap_utmi_mode {
109 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
110 DWC3_OMAP_UTMI_MODE_HW,
111 DWC3_OMAP_UTMI_MODE_SW,
112};
113
109struct dwc3_omap { 114struct dwc3_omap {
110 struct device *dev; 115 struct device *dev;
111 116
@@ -446,7 +451,6 @@ static int dwc3_omap_probe(struct platform_device *pdev)
446 struct device_node *node = pdev->dev.of_node; 451 struct device_node *node = pdev->dev.of_node;
447 452
448 struct dwc3_omap *omap; 453 struct dwc3_omap *omap;
449 struct resource *res;
450 struct device *dev = &pdev->dev; 454 struct device *dev = &pdev->dev;
451 struct regulator *vbus_reg = NULL; 455 struct regulator *vbus_reg = NULL;
452 456
@@ -472,8 +476,7 @@ static int dwc3_omap_probe(struct platform_device *pdev)
472 if (irq < 0) 476 if (irq < 0)
473 return irq; 477 return irq;
474 478
475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 479 base = devm_platform_ioremap_resource(pdev, 0);
476 base = devm_ioremap_resource(dev, res);
477 if (IS_ERR(base)) 480 if (IS_ERR(base))
478 return PTR_ERR(base); 481 return PTR_ERR(base);
479 482
diff --git a/drivers/usb/dwc3/dwc3-st.c b/drivers/usb/dwc3/dwc3-st.c
index 16081383c401..c682420f25ca 100644
--- a/drivers/usb/dwc3/dwc3-st.c
+++ b/drivers/usb/dwc3/dwc3-st.c
@@ -255,24 +255,26 @@ static int st_dwc3_probe(struct platform_device *pdev)
255 if (!child) { 255 if (!child) {
256 dev_err(&pdev->dev, "failed to find dwc3 core node\n"); 256 dev_err(&pdev->dev, "failed to find dwc3 core node\n");
257 ret = -ENODEV; 257 ret = -ENODEV;
258 goto undo_softreset; 258 goto err_node_put;
259 } 259 }
260 260
261 /* Allocate and initialize the core */ 261 /* Allocate and initialize the core */
262 ret = of_platform_populate(node, NULL, NULL, dev); 262 ret = of_platform_populate(node, NULL, NULL, dev);
263 if (ret) { 263 if (ret) {
264 dev_err(dev, "failed to add dwc3 core\n"); 264 dev_err(dev, "failed to add dwc3 core\n");
265 goto undo_softreset; 265 goto err_node_put;
266 } 266 }
267 267
268 child_pdev = of_find_device_by_node(child); 268 child_pdev = of_find_device_by_node(child);
269 if (!child_pdev) { 269 if (!child_pdev) {
270 dev_err(dev, "failed to find dwc3 core device\n"); 270 dev_err(dev, "failed to find dwc3 core device\n");
271 ret = -ENODEV; 271 ret = -ENODEV;
272 goto undo_softreset; 272 goto err_node_put;
273 } 273 }
274 274
275 dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev); 275 dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev);
276 of_node_put(child);
277 of_dev_put(child_pdev);
276 278
277 /* 279 /*
278 * Configure the USB port as device or host according to the static 280 * Configure the USB port as device or host according to the static
@@ -292,6 +294,8 @@ static int st_dwc3_probe(struct platform_device *pdev)
292 platform_set_drvdata(pdev, dwc3_data); 294 platform_set_drvdata(pdev, dwc3_data);
293 return 0; 295 return 0;
294 296
297err_node_put:
298 of_node_put(child);
295undo_softreset: 299undo_softreset:
296 reset_control_assert(dwc3_data->rstc_rst); 300 reset_control_assert(dwc3_data->rstc_rst);
297undo_powerdown: 301undo_powerdown:
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 173f5329d3d9..8adb59f8e4f1 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2078,6 +2078,26 @@ static void dwc3_gadget_config_params(struct usb_gadget *g,
2078{ 2078{
2079 struct dwc3 *dwc = gadget_to_dwc(g); 2079 struct dwc3 *dwc = gadget_to_dwc(g);
2080 2080
2081 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2082 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2083
2084 /* Recommended BESL */
2085 if (!dwc->dis_enblslpm_quirk) {
2086 /*
2087 * If the recommended BESL baseline is 0 or if the BESL deep is
2088 * less than 2, Microsoft's Windows 10 host usb stack will issue
2089 * a usb reset immediately after it receives the extended BOS
2090 * descriptor and the enumeration will fail. To maintain
2091 * compatibility with the Windows' usb stack, let's set the
2092 * recommended BESL baseline to 1 and clamp the BESL deep to be
2093 * within 2 to 15.
2094 */
2095 params->besl_baseline = 1;
2096 if (dwc->is_utmi_l1_suspend)
2097 params->besl_deep =
2098 clamp_t(u8, dwc->hird_threshold, 2, 15);
2099 }
2100
2081 /* U1 Device exit Latency */ 2101 /* U1 Device exit Latency */
2082 if (dwc->dis_u1_entry_quirk) 2102 if (dwc->dis_u1_entry_quirk)
2083 params->bU1devExitLat = 0; 2103 params->bU1devExitLat = 0;
@@ -2868,7 +2888,8 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2868 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2888 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2869 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2889 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2870 2890
2871 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold); 2891 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2892 (dwc->is_utmi_l1_suspend << 4));
2872 2893
2873 /* 2894 /*
2874 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and 2895 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
@@ -3318,7 +3339,6 @@ int dwc3_gadget_init(struct dwc3 *dwc)
3318 dwc->gadget.speed = USB_SPEED_UNKNOWN; 3339 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3319 dwc->gadget.sg_supported = true; 3340 dwc->gadget.sg_supported = true;
3320 dwc->gadget.name = "dwc3-gadget"; 3341 dwc->gadget.name = "dwc3-gadget";
3321 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3322 dwc->gadget.lpm_capable = true; 3342 dwc->gadget.lpm_capable = true;
3323 3343
3324 /* 3344 /*
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index f55947294f7c..8deea8c91e03 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -85,7 +85,7 @@ int dwc3_host_init(struct dwc3 *dwc)
85 DWC3_XHCI_RESOURCES_NUM); 85 DWC3_XHCI_RESOURCES_NUM);
86 if (ret) { 86 if (ret) {
87 dev_err(dwc->dev, "couldn't add resources to xHCI device\n"); 87 dev_err(dwc->dev, "couldn't add resources to xHCI device\n");
88 goto err1; 88 goto err;
89 } 89 }
90 90
91 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props)); 91 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
@@ -112,37 +112,23 @@ int dwc3_host_init(struct dwc3 *dwc)
112 ret = platform_device_add_properties(xhci, props); 112 ret = platform_device_add_properties(xhci, props);
113 if (ret) { 113 if (ret) {
114 dev_err(dwc->dev, "failed to add properties to xHCI\n"); 114 dev_err(dwc->dev, "failed to add properties to xHCI\n");
115 goto err1; 115 goto err;
116 } 116 }
117 } 117 }
118 118
119 phy_create_lookup(dwc->usb2_generic_phy, "usb2-phy",
120 dev_name(dwc->dev));
121 phy_create_lookup(dwc->usb3_generic_phy, "usb3-phy",
122 dev_name(dwc->dev));
123
124 ret = platform_device_add(xhci); 119 ret = platform_device_add(xhci);
125 if (ret) { 120 if (ret) {
126 dev_err(dwc->dev, "failed to register xHCI device\n"); 121 dev_err(dwc->dev, "failed to register xHCI device\n");
127 goto err2; 122 goto err;
128 } 123 }
129 124
130 return 0; 125 return 0;
131err2: 126err:
132 phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
133 dev_name(dwc->dev));
134 phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
135 dev_name(dwc->dev));
136err1:
137 platform_device_put(xhci); 127 platform_device_put(xhci);
138 return ret; 128 return ret;
139} 129}
140 130
141void dwc3_host_exit(struct dwc3 *dwc) 131void dwc3_host_exit(struct dwc3 *dwc)
142{ 132{
143 phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
144 dev_name(dwc->dev));
145 phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
146 dev_name(dwc->dev));
147 platform_device_unregister(dwc->xhci); 133 platform_device_unregister(dwc->xhci);
148} 134}
diff --git a/drivers/usb/dwc3/trace.h b/drivers/usb/dwc3/trace.h
index 818a63da1a44..9edff17111f7 100644
--- a/drivers/usb/dwc3/trace.h
+++ b/drivers/usb/dwc3/trace.h
@@ -86,7 +86,7 @@ DECLARE_EVENT_CLASS(dwc3_log_ctrl,
86 __entry->wIndex = le16_to_cpu(ctrl->wIndex); 86 __entry->wIndex = le16_to_cpu(ctrl->wIndex);
87 __entry->wLength = le16_to_cpu(ctrl->wLength); 87 __entry->wLength = le16_to_cpu(ctrl->wLength);
88 ), 88 ),
89 TP_printk("%s", dwc3_decode_ctrl(__get_str(str), DWC3_MSG_MAX, 89 TP_printk("%s", usb_decode_ctrl(__get_str(str), DWC3_MSG_MAX,
90 __entry->bRequestType, 90 __entry->bRequestType,
91 __entry->bRequest, __entry->wValue, 91 __entry->bRequest, __entry->wValue,
92 __entry->wIndex, __entry->wLength) 92 __entry->wIndex, __entry->wLength)
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 76883ff4f5bb..d516e8d6cd7f 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -612,6 +612,7 @@ static int bos_desc(struct usb_composite_dev *cdev)
612 struct usb_ext_cap_descriptor *usb_ext; 612 struct usb_ext_cap_descriptor *usb_ext;
613 struct usb_dcd_config_params dcd_config_params; 613 struct usb_dcd_config_params dcd_config_params;
614 struct usb_bos_descriptor *bos = cdev->req->buf; 614 struct usb_bos_descriptor *bos = cdev->req->buf;
615 unsigned int besl = 0;
615 616
616 bos->bLength = USB_DT_BOS_SIZE; 617 bos->bLength = USB_DT_BOS_SIZE;
617 bos->bDescriptorType = USB_DT_BOS; 618 bos->bDescriptorType = USB_DT_BOS;
@@ -619,6 +620,29 @@ static int bos_desc(struct usb_composite_dev *cdev)
619 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE); 620 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE);
620 bos->bNumDeviceCaps = 0; 621 bos->bNumDeviceCaps = 0;
621 622
623 /* Get Controller configuration */
624 if (cdev->gadget->ops->get_config_params) {
625 cdev->gadget->ops->get_config_params(cdev->gadget,
626 &dcd_config_params);
627 } else {
628 dcd_config_params.besl_baseline =
629 USB_DEFAULT_BESL_UNSPECIFIED;
630 dcd_config_params.besl_deep =
631 USB_DEFAULT_BESL_UNSPECIFIED;
632 dcd_config_params.bU1devExitLat =
633 USB_DEFAULT_U1_DEV_EXIT_LAT;
634 dcd_config_params.bU2DevExitLat =
635 cpu_to_le16(USB_DEFAULT_U2_DEV_EXIT_LAT);
636 }
637
638 if (dcd_config_params.besl_baseline != USB_DEFAULT_BESL_UNSPECIFIED)
639 besl = USB_BESL_BASELINE_VALID |
640 USB_SET_BESL_BASELINE(dcd_config_params.besl_baseline);
641
642 if (dcd_config_params.besl_deep != USB_DEFAULT_BESL_UNSPECIFIED)
643 besl |= USB_BESL_DEEP_VALID |
644 USB_SET_BESL_DEEP(dcd_config_params.besl_deep);
645
622 /* 646 /*
623 * A SuperSpeed device shall include the USB2.0 extension descriptor 647 * A SuperSpeed device shall include the USB2.0 extension descriptor
624 * and shall support LPM when operating in USB2.0 HS mode. 648 * and shall support LPM when operating in USB2.0 HS mode.
@@ -629,7 +653,8 @@ static int bos_desc(struct usb_composite_dev *cdev)
629 usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE; 653 usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE;
630 usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY; 654 usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
631 usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT; 655 usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT;
632 usb_ext->bmAttributes = cpu_to_le32(USB_LPM_SUPPORT | USB_BESL_SUPPORT); 656 usb_ext->bmAttributes = cpu_to_le32(USB_LPM_SUPPORT |
657 USB_BESL_SUPPORT | besl);
633 658
634 /* 659 /*
635 * The Superspeed USB Capability descriptor shall be implemented by all 660 * The Superspeed USB Capability descriptor shall be implemented by all
@@ -650,17 +675,6 @@ static int bos_desc(struct usb_composite_dev *cdev)
650 USB_HIGH_SPEED_OPERATION | 675 USB_HIGH_SPEED_OPERATION |
651 USB_5GBPS_OPERATION); 676 USB_5GBPS_OPERATION);
652 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION; 677 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
653
654 /* Get Controller configuration */
655 if (cdev->gadget->ops->get_config_params) {
656 cdev->gadget->ops->get_config_params(cdev->gadget,
657 &dcd_config_params);
658 } else {
659 dcd_config_params.bU1devExitLat =
660 USB_DEFAULT_U1_DEV_EXIT_LAT;
661 dcd_config_params.bU2DevExitLat =
662 cpu_to_le16(USB_DEFAULT_U2_DEV_EXIT_LAT);
663 }
664 ss_cap->bU1devExitLat = dcd_config_params.bU1devExitLat; 678 ss_cap->bU1devExitLat = dcd_config_params.bU1devExitLat;
665 ss_cap->bU2DevExitLat = dcd_config_params.bU2DevExitLat; 679 ss_cap->bU2DevExitLat = dcd_config_params.bU2DevExitLat;
666 } 680 }
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/core.c b/drivers/usb/gadget/udc/aspeed-vhub/core.c
index c08d385e2723..90b134d5dca9 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/core.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/core.c
@@ -65,14 +65,16 @@ void ast_vhub_done(struct ast_vhub_ep *ep, struct ast_vhub_req *req,
65void ast_vhub_nuke(struct ast_vhub_ep *ep, int status) 65void ast_vhub_nuke(struct ast_vhub_ep *ep, int status)
66{ 66{
67 struct ast_vhub_req *req; 67 struct ast_vhub_req *req;
68 68 int count = 0;
69 EPDBG(ep, "Nuking\n");
70 69
71 /* Beware, lock will be dropped & req-acquired by done() */ 70 /* Beware, lock will be dropped & req-acquired by done() */
72 while (!list_empty(&ep->queue)) { 71 while (!list_empty(&ep->queue)) {
73 req = list_first_entry(&ep->queue, struct ast_vhub_req, queue); 72 req = list_first_entry(&ep->queue, struct ast_vhub_req, queue);
74 ast_vhub_done(ep, req, status); 73 ast_vhub_done(ep, req, status);
74 count++;
75 } 75 }
76 if (count)
77 EPDBG(ep, "Nuked %d request(s)\n", count);
76} 78}
77 79
78struct usb_request *ast_vhub_alloc_request(struct usb_ep *u_ep, 80struct usb_request *ast_vhub_alloc_request(struct usb_ep *u_ep,
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/dev.c b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
index 6b1b16b17d7d..4008e7a51188 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/dev.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/dev.c
@@ -50,11 +50,14 @@ void ast_vhub_dev_irq(struct ast_vhub_dev *d)
50 50
51static void ast_vhub_dev_enable(struct ast_vhub_dev *d) 51static void ast_vhub_dev_enable(struct ast_vhub_dev *d)
52{ 52{
53 u32 reg, hmsk; 53 u32 reg, hmsk, i;
54 54
55 if (d->enabled) 55 if (d->enabled)
56 return; 56 return;
57 57
58 /* Cleanup EP0 state */
59 ast_vhub_reset_ep0(d);
60
58 /* Enable device and its EP0 interrupts */ 61 /* Enable device and its EP0 interrupts */
59 reg = VHUB_DEV_EN_ENABLE_PORT | 62 reg = VHUB_DEV_EN_ENABLE_PORT |
60 VHUB_DEV_EN_EP0_IN_ACK_IRQEN | 63 VHUB_DEV_EN_EP0_IN_ACK_IRQEN |
@@ -73,6 +76,19 @@ static void ast_vhub_dev_enable(struct ast_vhub_dev *d)
73 /* Set EP0 DMA buffer address */ 76 /* Set EP0 DMA buffer address */
74 writel(d->ep0.buf_dma, d->regs + AST_VHUB_DEV_EP0_DATA); 77 writel(d->ep0.buf_dma, d->regs + AST_VHUB_DEV_EP0_DATA);
75 78
79 /* Clear stall on all EPs */
80 for (i = 0; i < AST_VHUB_NUM_GEN_EPs; i++) {
81 struct ast_vhub_ep *ep = d->epns[i];
82
83 if (ep && (ep->epn.stalled || ep->epn.wedged)) {
84 ep->epn.stalled = false;
85 ep->epn.wedged = false;
86 ast_vhub_update_epn_stall(ep);
87 }
88 }
89
90 /* Additional cleanups */
91 d->wakeup_en = false;
76 d->enabled = true; 92 d->enabled = true;
77} 93}
78 94
@@ -93,7 +109,6 @@ static void ast_vhub_dev_disable(struct ast_vhub_dev *d)
93 writel(0, d->regs + AST_VHUB_DEV_EN_CTRL); 109 writel(0, d->regs + AST_VHUB_DEV_EN_CTRL);
94 d->gadget.speed = USB_SPEED_UNKNOWN; 110 d->gadget.speed = USB_SPEED_UNKNOWN;
95 d->enabled = false; 111 d->enabled = false;
96 d->suspended = false;
97} 112}
98 113
99static int ast_vhub_dev_feature(struct ast_vhub_dev *d, 114static int ast_vhub_dev_feature(struct ast_vhub_dev *d,
@@ -201,14 +216,19 @@ int ast_vhub_std_dev_request(struct ast_vhub_ep *ep,
201 u16 wValue, wIndex; 216 u16 wValue, wIndex;
202 217
203 /* No driver, we shouldn't be enabled ... */ 218 /* No driver, we shouldn't be enabled ... */
204 if (!d->driver || !d->enabled || d->suspended) { 219 if (!d->driver || !d->enabled) {
205 EPDBG(ep, 220 EPDBG(ep,
206 "Device is wrong state driver=%p enabled=%d" 221 "Device is wrong state driver=%p enabled=%d\n",
207 " suspended=%d\n", 222 d->driver, d->enabled);
208 d->driver, d->enabled, d->suspended);
209 return std_req_stall; 223 return std_req_stall;
210 } 224 }
211 225
226 /*
227 * Note: we used to reject/stall requests while suspended,
228 * we don't do that anymore as we seem to have cases of
229 * mass storage getting very upset.
230 */
231
212 /* First packet, grab speed */ 232 /* First packet, grab speed */
213 if (d->gadget.speed == USB_SPEED_UNKNOWN) { 233 if (d->gadget.speed == USB_SPEED_UNKNOWN) {
214 d->gadget.speed = ep->vhub->speed; 234 d->gadget.speed = ep->vhub->speed;
@@ -449,8 +469,7 @@ static const struct usb_gadget_ops ast_vhub_udc_ops = {
449 469
450void ast_vhub_dev_suspend(struct ast_vhub_dev *d) 470void ast_vhub_dev_suspend(struct ast_vhub_dev *d)
451{ 471{
452 d->suspended = true; 472 if (d->driver && d->driver->suspend) {
453 if (d->driver) {
454 spin_unlock(&d->vhub->lock); 473 spin_unlock(&d->vhub->lock);
455 d->driver->suspend(&d->gadget); 474 d->driver->suspend(&d->gadget);
456 spin_lock(&d->vhub->lock); 475 spin_lock(&d->vhub->lock);
@@ -459,8 +478,7 @@ void ast_vhub_dev_suspend(struct ast_vhub_dev *d)
459 478
460void ast_vhub_dev_resume(struct ast_vhub_dev *d) 479void ast_vhub_dev_resume(struct ast_vhub_dev *d)
461{ 480{
462 d->suspended = false; 481 if (d->driver && d->driver->resume) {
463 if (d->driver) {
464 spin_unlock(&d->vhub->lock); 482 spin_unlock(&d->vhub->lock);
465 d->driver->resume(&d->gadget); 483 d->driver->resume(&d->gadget);
466 spin_lock(&d->vhub->lock); 484 spin_lock(&d->vhub->lock);
@@ -469,46 +487,28 @@ void ast_vhub_dev_resume(struct ast_vhub_dev *d)
469 487
470void ast_vhub_dev_reset(struct ast_vhub_dev *d) 488void ast_vhub_dev_reset(struct ast_vhub_dev *d)
471{ 489{
472 /* 490 /* No driver, just disable the device and return */
473 * If speed is not set, we enable the port. If it is, 491 if (!d->driver) {
474 * send reset to the gadget and reset "speed". 492 ast_vhub_dev_disable(d);
475 * 493 return;
476 * Speed is an indication that we have got the first
477 * setup packet to the device.
478 */
479 if (d->gadget.speed == USB_SPEED_UNKNOWN && !d->enabled) {
480 DDBG(d, "Reset at unknown speed of disabled device, enabling...\n");
481 ast_vhub_dev_enable(d);
482 d->suspended = false;
483 } 494 }
484 if (d->gadget.speed != USB_SPEED_UNKNOWN && d->driver) {
485 unsigned int i;
486 495
487 DDBG(d, "Reset at known speed of bound device, resetting...\n"); 496 /* If the port isn't enabled, just enable it */
497 if (!d->enabled) {
498 DDBG(d, "Reset of disabled device, enabling...\n");
499 ast_vhub_dev_enable(d);
500 } else {
501 DDBG(d, "Reset of enabled device, resetting...\n");
488 spin_unlock(&d->vhub->lock); 502 spin_unlock(&d->vhub->lock);
489 d->driver->reset(&d->gadget); 503 usb_gadget_udc_reset(&d->gadget, d->driver);
490 spin_lock(&d->vhub->lock); 504 spin_lock(&d->vhub->lock);
491 505
492 /* 506 /*
493 * Disable/re-enable HW, this will clear the address 507 * Disable and maybe re-enable HW, this will clear the address
494 * and speed setting. 508 * and speed setting.
495 */ 509 */
496 ast_vhub_dev_disable(d); 510 ast_vhub_dev_disable(d);
497 ast_vhub_dev_enable(d); 511 ast_vhub_dev_enable(d);
498
499 /* Clear stall on all EPs */
500 for (i = 0; i < AST_VHUB_NUM_GEN_EPs; i++) {
501 struct ast_vhub_ep *ep = d->epns[i];
502
503 if (ep && ep->epn.stalled) {
504 ep->epn.stalled = false;
505 ast_vhub_update_epn_stall(ep);
506 }
507 }
508
509 /* Additional cleanups */
510 d->wakeup_en = false;
511 d->suspended = false;
512 } 512 }
513} 513}
514 514
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/ep0.c b/drivers/usb/gadget/udc/aspeed-vhub/ep0.c
index e2927fb083cf..022b777b85f8 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/ep0.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/ep0.c
@@ -105,18 +105,20 @@ void ast_vhub_ep0_handle_setup(struct ast_vhub_ep *ep)
105 (crq.bRequestType & USB_DIR_IN) ? "in" : "out", 105 (crq.bRequestType & USB_DIR_IN) ? "in" : "out",
106 ep->ep0.state); 106 ep->ep0.state);
107 107
108 /* Check our state, cancel pending requests if needed */ 108 /*
109 if (ep->ep0.state != ep0_state_token) { 109 * Check our state, cancel pending requests if needed
110 *
111 * Note: Under some circumstances, we can get a new setup
112 * packet while waiting for the stall ack, just accept it.
113 *
114 * In any case, a SETUP packet in wrong state should have
115 * reset the HW state machine, so let's just log, nuke
116 * requests, move on.
117 */
118 if (ep->ep0.state != ep0_state_token &&
119 ep->ep0.state != ep0_state_stall) {
110 EPDBG(ep, "wrong state\n"); 120 EPDBG(ep, "wrong state\n");
111 ast_vhub_nuke(ep, -EIO); 121 ast_vhub_nuke(ep, -EIO);
112
113 /*
114 * Accept the packet regardless, this seems to happen
115 * when stalling a SETUP packet that has an OUT data
116 * phase.
117 */
118 ast_vhub_nuke(ep, 0);
119 goto stall;
120 } 122 }
121 123
122 /* Calculate next state for EP0 */ 124 /* Calculate next state for EP0 */
@@ -165,7 +167,7 @@ void ast_vhub_ep0_handle_setup(struct ast_vhub_ep *ep)
165 stall: 167 stall:
166 EPDBG(ep, "stalling\n"); 168 EPDBG(ep, "stalling\n");
167 writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat); 169 writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat);
168 ep->ep0.state = ep0_state_status; 170 ep->ep0.state = ep0_state_stall;
169 ep->ep0.dir_in = false; 171 ep->ep0.dir_in = false;
170 return; 172 return;
171 173
@@ -299,8 +301,8 @@ void ast_vhub_ep0_handle_ack(struct ast_vhub_ep *ep, bool in_ack)
299 if ((ep->ep0.dir_in && (stat & VHUB_EP0_TX_BUFF_RDY)) || 301 if ((ep->ep0.dir_in && (stat & VHUB_EP0_TX_BUFF_RDY)) ||
300 (!ep->ep0.dir_in && (stat & VHUB_EP0_RX_BUFF_RDY)) || 302 (!ep->ep0.dir_in && (stat & VHUB_EP0_RX_BUFF_RDY)) ||
301 (ep->ep0.dir_in != in_ack)) { 303 (ep->ep0.dir_in != in_ack)) {
304 /* In that case, ignore interrupt */
302 dev_warn(dev, "irq state mismatch"); 305 dev_warn(dev, "irq state mismatch");
303 stall = true;
304 break; 306 break;
305 } 307 }
306 /* 308 /*
@@ -335,12 +337,22 @@ void ast_vhub_ep0_handle_ack(struct ast_vhub_ep *ep, bool in_ack)
335 dev_warn(dev, "status direction mismatch\n"); 337 dev_warn(dev, "status direction mismatch\n");
336 stall = true; 338 stall = true;
337 } 339 }
340 break;
341 case ep0_state_stall:
342 /*
343 * There shouldn't be any request left, but nuke just in case
344 * otherwise the stale request will block subsequent ones
345 */
346 ast_vhub_nuke(ep, -EIO);
347 break;
338 } 348 }
339 349
340 /* Reset to token state */ 350 /* Reset to token state or stall */
341 ep->ep0.state = ep0_state_token; 351 if (stall) {
342 if (stall)
343 writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat); 352 writel(VHUB_EP0_CTRL_STALL, ep->ep0.ctlstat);
353 ep->ep0.state = ep0_state_stall;
354 } else
355 ep->ep0.state = ep0_state_token;
344} 356}
345 357
346static int ast_vhub_ep0_queue(struct usb_ep* u_ep, struct usb_request *u_req, 358static int ast_vhub_ep0_queue(struct usb_ep* u_ep, struct usb_request *u_req,
@@ -367,7 +379,7 @@ static int ast_vhub_ep0_queue(struct usb_ep* u_ep, struct usb_request *u_req,
367 return -EINVAL; 379 return -EINVAL;
368 380
369 /* Disabled device */ 381 /* Disabled device */
370 if (ep->dev && (!ep->dev->enabled || ep->dev->suspended)) 382 if (ep->dev && !ep->dev->enabled)
371 return -ESHUTDOWN; 383 return -ESHUTDOWN;
372 384
373 /* Data, no buffer and not internal ? */ 385 /* Data, no buffer and not internal ? */
@@ -390,8 +402,12 @@ static int ast_vhub_ep0_queue(struct usb_ep* u_ep, struct usb_request *u_req,
390 spin_lock_irqsave(&vhub->lock, flags); 402 spin_lock_irqsave(&vhub->lock, flags);
391 403
392 /* EP0 can only support a single request at a time */ 404 /* EP0 can only support a single request at a time */
393 if (!list_empty(&ep->queue) || ep->ep0.state == ep0_state_token) { 405 if (!list_empty(&ep->queue) ||
406 ep->ep0.state == ep0_state_token ||
407 ep->ep0.state == ep0_state_stall) {
394 dev_warn(dev, "EP0: Request in wrong state\n"); 408 dev_warn(dev, "EP0: Request in wrong state\n");
409 EPVDBG(ep, "EP0: list_empty=%d state=%d\n",
410 list_empty(&ep->queue), ep->ep0.state);
395 spin_unlock_irqrestore(&vhub->lock, flags); 411 spin_unlock_irqrestore(&vhub->lock, flags);
396 return -EBUSY; 412 return -EBUSY;
397 } 413 }
@@ -459,6 +475,15 @@ static const struct usb_ep_ops ast_vhub_ep0_ops = {
459 .free_request = ast_vhub_free_request, 475 .free_request = ast_vhub_free_request,
460}; 476};
461 477
478void ast_vhub_reset_ep0(struct ast_vhub_dev *dev)
479{
480 struct ast_vhub_ep *ep = &dev->ep0;
481
482 ast_vhub_nuke(ep, -EIO);
483 ep->ep0.state = ep0_state_token;
484}
485
486
462void ast_vhub_init_ep0(struct ast_vhub *vhub, struct ast_vhub_ep *ep, 487void ast_vhub_init_ep0(struct ast_vhub *vhub, struct ast_vhub_ep *ep,
463 struct ast_vhub_dev *dev) 488 struct ast_vhub_dev *dev)
464{ 489{
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/epn.c b/drivers/usb/gadget/udc/aspeed-vhub/epn.c
index 35941dc125f9..7475c74aa5c5 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/epn.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/epn.c
@@ -352,7 +352,7 @@ static int ast_vhub_epn_queue(struct usb_ep* u_ep, struct usb_request *u_req,
352 352
353 /* Endpoint enabled ? */ 353 /* Endpoint enabled ? */
354 if (!ep->epn.enabled || !u_ep->desc || !ep->dev || !ep->d_idx || 354 if (!ep->epn.enabled || !u_ep->desc || !ep->dev || !ep->d_idx ||
355 !ep->dev->enabled || ep->dev->suspended) { 355 !ep->dev->enabled) {
356 EPDBG(ep, "Enqueuing request on wrong or disabled EP\n"); 356 EPDBG(ep, "Enqueuing request on wrong or disabled EP\n");
357 return -ESHUTDOWN; 357 return -ESHUTDOWN;
358 } 358 }
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/hub.c b/drivers/usb/gadget/udc/aspeed-vhub/hub.c
index 7c040f56100e..19b3517e04c0 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/hub.c
+++ b/drivers/usb/gadget/udc/aspeed-vhub/hub.c
@@ -449,8 +449,15 @@ static void ast_vhub_change_port_stat(struct ast_vhub *vhub,
449 USB_PORT_STAT_C_OVERCURRENT | 449 USB_PORT_STAT_C_OVERCURRENT |
450 USB_PORT_STAT_C_RESET | 450 USB_PORT_STAT_C_RESET |
451 USB_PORT_STAT_C_L1; 451 USB_PORT_STAT_C_L1;
452 p->change |= chg;
453 452
453 /*
454 * We only set USB_PORT_STAT_C_ENABLE if we are disabling
455 * the port as per USB spec, otherwise MacOS gets upset
456 */
457 if (p->status & USB_PORT_STAT_ENABLE)
458 chg &= ~USB_PORT_STAT_C_ENABLE;
459
460 p->change = chg;
454 ast_vhub_update_hub_ep1(vhub, port); 461 ast_vhub_update_hub_ep1(vhub, port);
455 } 462 }
456} 463}
@@ -723,6 +730,12 @@ enum std_req_rc ast_vhub_class_hub_request(struct ast_vhub_ep *ep,
723 case ClearPortFeature: 730 case ClearPortFeature:
724 EPDBG(ep, "ClearPortFeature(%d,%d)\n", wIndex & 0xf, wValue); 731 EPDBG(ep, "ClearPortFeature(%d,%d)\n", wIndex & 0xf, wValue);
725 return ast_vhub_clr_port_feature(ep, wIndex & 0xf, wValue); 732 return ast_vhub_clr_port_feature(ep, wIndex & 0xf, wValue);
733 case ClearTTBuffer:
734 case ResetTT:
735 case StopTT:
736 return std_req_complete;
737 case GetTTState:
738 return ast_vhub_simple_reply(ep, 0, 0, 0, 0);
726 default: 739 default:
727 EPDBG(ep, "Unknown class request\n"); 740 EPDBG(ep, "Unknown class request\n");
728 } 741 }
diff --git a/drivers/usb/gadget/udc/aspeed-vhub/vhub.h b/drivers/usb/gadget/udc/aspeed-vhub/vhub.h
index 4ed03d33a5a9..761919e220d3 100644
--- a/drivers/usb/gadget/udc/aspeed-vhub/vhub.h
+++ b/drivers/usb/gadget/udc/aspeed-vhub/vhub.h
@@ -257,6 +257,7 @@ enum ep0_state {
257 ep0_state_token, 257 ep0_state_token,
258 ep0_state_data, 258 ep0_state_data,
259 ep0_state_status, 259 ep0_state_status,
260 ep0_state_stall,
260}; 261};
261 262
262/* 263/*
@@ -353,7 +354,6 @@ struct ast_vhub_dev {
353 struct usb_gadget_driver *driver; 354 struct usb_gadget_driver *driver;
354 bool registered : 1; 355 bool registered : 1;
355 bool wakeup_en : 1; 356 bool wakeup_en : 1;
356 bool suspended : 1;
357 bool enabled : 1; 357 bool enabled : 1;
358 358
359 /* Endpoint structures */ 359 /* Endpoint structures */
@@ -507,6 +507,7 @@ void ast_vhub_init_hw(struct ast_vhub *vhub);
507/* ep0.c */ 507/* ep0.c */
508void ast_vhub_ep0_handle_ack(struct ast_vhub_ep *ep, bool in_ack); 508void ast_vhub_ep0_handle_ack(struct ast_vhub_ep *ep, bool in_ack);
509void ast_vhub_ep0_handle_setup(struct ast_vhub_ep *ep); 509void ast_vhub_ep0_handle_setup(struct ast_vhub_ep *ep);
510void ast_vhub_reset_ep0(struct ast_vhub_dev *dev);
510void ast_vhub_init_ep0(struct ast_vhub *vhub, struct ast_vhub_ep *ep, 511void ast_vhub_init_ep0(struct ast_vhub *vhub, struct ast_vhub_ep *ep,
511 struct ast_vhub_dev *dev); 512 struct ast_vhub_dev *dev);
512int ast_vhub_reply(struct ast_vhub_ep *ep, char *ptr, int len); 513int ast_vhub_reply(struct ast_vhub_ep *ep, char *ptr, int len);
diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
index 7cf34beb50df..92af8dc98c3d 100644
--- a/drivers/usb/gadget/udc/core.c
+++ b/drivers/usb/gadget/udc/core.c
@@ -1143,7 +1143,7 @@ static int check_pending_gadget_drivers(struct usb_udc *udc)
1143 dev_name(&udc->dev)) == 0) { 1143 dev_name(&udc->dev)) == 0) {
1144 ret = udc_bind_to_driver(udc, driver); 1144 ret = udc_bind_to_driver(udc, driver);
1145 if (ret != -EPROBE_DEFER) 1145 if (ret != -EPROBE_DEFER)
1146 list_del(&driver->pending); 1146 list_del_init(&driver->pending);
1147 break; 1147 break;
1148 } 1148 }
1149 1149
diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c
index e9cf20979bf6..338c606b7c27 100644
--- a/drivers/usb/gadget/udc/lpc32xx_udc.c
+++ b/drivers/usb/gadget/udc/lpc32xx_udc.c
@@ -742,7 +742,6 @@ static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
742 * response data */ 742 * response data */
743static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) 743static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
744{ 744{
745 u32 tmp;
746 int to = 1000; 745 int to = 1000;
747 746
748 /* Write a command and read data from the protocol engine */ 747 /* Write a command and read data from the protocol engine */
@@ -752,7 +751,6 @@ static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
752 /* Write command code */ 751 /* Write command code */
753 udc_protocol_cmd_w(udc, cmd); 752 udc_protocol_cmd_w(udc, cmd);
754 753
755 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
756 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) 754 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
757 && (to > 0)) 755 && (to > 0))
758 to--; 756 to--;
@@ -1992,7 +1990,7 @@ void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1992/* DMA end of transfer completion */ 1990/* DMA end of transfer completion */
1993static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1991static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1994{ 1992{
1995 u32 status, epstatus; 1993 u32 status;
1996 struct lpc32xx_request *req; 1994 struct lpc32xx_request *req;
1997 struct lpc32xx_usbd_dd_gad *dd; 1995 struct lpc32xx_usbd_dd_gad *dd;
1998 1996
@@ -2086,7 +2084,7 @@ static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2086 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { 2084 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2087 udc_clearep_getsts(udc, ep->hwep_num); 2085 udc_clearep_getsts(udc, ep->hwep_num);
2088 uda_enable_hwepint(udc, ep->hwep_num); 2086 uda_enable_hwepint(udc, ep->hwep_num);
2089 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 2087 udc_clearep_getsts(udc, ep->hwep_num);
2090 2088
2091 /* Let the EP interrupt handle the ZLP */ 2089 /* Let the EP interrupt handle the ZLP */
2092 return; 2090 return;
@@ -2198,7 +2196,7 @@ static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2198 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; 2196 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2199 struct usb_ctrlrequest ctrlpkt; 2197 struct usb_ctrlrequest ctrlpkt;
2200 int i, bytes; 2198 int i, bytes;
2201 u16 wIndex, wValue, wLength, reqtype, req, tmp; 2199 u16 wIndex, wValue, reqtype, req, tmp;
2202 2200
2203 /* Nuke previous transfers */ 2201 /* Nuke previous transfers */
2204 nuke(ep0, -EPROTO); 2202 nuke(ep0, -EPROTO);
@@ -2214,7 +2212,6 @@ static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2214 /* Native endianness */ 2212 /* Native endianness */
2215 wIndex = le16_to_cpu(ctrlpkt.wIndex); 2213 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2216 wValue = le16_to_cpu(ctrlpkt.wValue); 2214 wValue = le16_to_cpu(ctrlpkt.wValue);
2217 wLength = le16_to_cpu(ctrlpkt.wLength);
2218 reqtype = le16_to_cpu(ctrlpkt.bRequestType); 2215 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2219 2216
2220 /* Set direction of EP0 */ 2217 /* Set direction of EP0 */
@@ -2265,7 +2262,7 @@ static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2265 default: 2262 default:
2266 break; 2263 break;
2267 } 2264 }
2268 2265 break;
2269 2266
2270 case USB_REQ_SET_ADDRESS: 2267 case USB_REQ_SET_ADDRESS:
2271 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { 2268 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
diff --git a/drivers/usb/gadget/udc/net2280.c b/drivers/usb/gadget/udc/net2280.c
index b6bbe2e448ba..51efee21915f 100644
--- a/drivers/usb/gadget/udc/net2280.c
+++ b/drivers/usb/gadget/udc/net2280.c
@@ -2244,30 +2244,40 @@ static void usb_reinit_338x(struct net2280 *dev)
2244 } 2244 }
2245 2245
2246 /* Hardware Defect and Workaround */ 2246 /* Hardware Defect and Workaround */
2247 val = readl(&dev->ll_lfps_regs->ll_lfps_5); 2247 val = readl(&dev->llregs->ll_lfps_5);
2248 val &= ~(0xf << TIMER_LFPS_6US); 2248 val &= ~(0xf << TIMER_LFPS_6US);
2249 val |= 0x5 << TIMER_LFPS_6US; 2249 val |= 0x5 << TIMER_LFPS_6US;
2250 writel(val, &dev->ll_lfps_regs->ll_lfps_5); 2250 writel(val, &dev->llregs->ll_lfps_5);
2251 2251
2252 val = readl(&dev->ll_lfps_regs->ll_lfps_6); 2252 val = readl(&dev->llregs->ll_lfps_6);
2253 val &= ~(0xffff << TIMER_LFPS_80US); 2253 val &= ~(0xffff << TIMER_LFPS_80US);
2254 val |= 0x0100 << TIMER_LFPS_80US; 2254 val |= 0x0100 << TIMER_LFPS_80US;
2255 writel(val, &dev->ll_lfps_regs->ll_lfps_6); 2255 writel(val, &dev->llregs->ll_lfps_6);
2256 2256
2257 /* 2257 /*
2258 * AA_AB Errata. Issue 4. Workaround for SuperSpeed USB 2258 * AA_AB Errata. Issue 4. Workaround for SuperSpeed USB
2259 * Hot Reset Exit Handshake may Fail in Specific Case using 2259 * Hot Reset Exit Handshake may Fail in Specific Case using
2260 * Default Register Settings. Workaround for Enumeration test. 2260 * Default Register Settings. Workaround for Enumeration test.
2261 */ 2261 */
2262 val = readl(&dev->ll_tsn_regs->ll_tsn_counters_2); 2262 val = readl(&dev->llregs->ll_tsn_counters_2);
2263 val &= ~(0x1f << HOT_TX_NORESET_TS2); 2263 val &= ~(0x1f << HOT_TX_NORESET_TS2);
2264 val |= 0x10 << HOT_TX_NORESET_TS2; 2264 val |= 0x10 << HOT_TX_NORESET_TS2;
2265 writel(val, &dev->ll_tsn_regs->ll_tsn_counters_2); 2265 writel(val, &dev->llregs->ll_tsn_counters_2);
2266 2266
2267 val = readl(&dev->ll_tsn_regs->ll_tsn_counters_3); 2267 val = readl(&dev->llregs->ll_tsn_counters_3);
2268 val &= ~(0x1f << HOT_RX_RESET_TS2); 2268 val &= ~(0x1f << HOT_RX_RESET_TS2);
2269 val |= 0x3 << HOT_RX_RESET_TS2; 2269 val |= 0x3 << HOT_RX_RESET_TS2;
2270 writel(val, &dev->ll_tsn_regs->ll_tsn_counters_3); 2270 writel(val, &dev->llregs->ll_tsn_counters_3);
2271
2272 /*
2273 * AB errata. Errata 11. Workaround for Default Duration of LFPS
2274 * Handshake Signaling for Device-Initiated U1 Exit is too short.
2275 * Without this, various enumeration failures observed with
2276 * modern superspeed hosts.
2277 */
2278 val = readl(&dev->llregs->ll_lfps_timers_2);
2279 writel((val & 0xffff0000) | LFPS_TIMERS_2_WORKAROUND_VALUE,
2280 &dev->llregs->ll_lfps_timers_2);
2271 2281
2272 /* 2282 /*
2273 * Set Recovery Idle to Recover bit: 2283 * Set Recovery Idle to Recover bit:
@@ -2276,10 +2286,10 @@ static void usb_reinit_338x(struct net2280 *dev)
2276 * - It is safe to set for all connection speeds; all chip revisions. 2286 * - It is safe to set for all connection speeds; all chip revisions.
2277 * - R-M-W to leave other bits undisturbed. 2287 * - R-M-W to leave other bits undisturbed.
2278 * - Reference PLX TT-7372 2288 * - Reference PLX TT-7372
2279 */ 2289 */
2280 val = readl(&dev->ll_chicken_reg->ll_tsn_chicken_bit); 2290 val = readl(&dev->llregs->ll_tsn_chicken_bit);
2281 val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW); 2291 val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW);
2282 writel(val, &dev->ll_chicken_reg->ll_tsn_chicken_bit); 2292 writel(val, &dev->llregs->ll_tsn_chicken_bit);
2283 2293
2284 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); 2294 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2285 2295
@@ -3669,12 +3679,6 @@ static int net2280_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3669 (base + 0x00b4); 3679 (base + 0x00b4);
3670 dev->llregs = (struct usb338x_ll_regs __iomem *) 3680 dev->llregs = (struct usb338x_ll_regs __iomem *)
3671 (base + 0x0700); 3681 (base + 0x0700);
3672 dev->ll_lfps_regs = (struct usb338x_ll_lfps_regs __iomem *)
3673 (base + 0x0748);
3674 dev->ll_tsn_regs = (struct usb338x_ll_tsn_regs __iomem *)
3675 (base + 0x077c);
3676 dev->ll_chicken_reg = (struct usb338x_ll_chi_regs __iomem *)
3677 (base + 0x079c);
3678 dev->plregs = (struct usb338x_pl_regs __iomem *) 3682 dev->plregs = (struct usb338x_pl_regs __iomem *)
3679 (base + 0x0800); 3683 (base + 0x0800);
3680 usbstat = readl(&dev->usb->usbstat); 3684 usbstat = readl(&dev->usb->usbstat);
diff --git a/drivers/usb/gadget/udc/net2280.h b/drivers/usb/gadget/udc/net2280.h
index b65a797544d7..85d3ca1698ba 100644
--- a/drivers/usb/gadget/udc/net2280.h
+++ b/drivers/usb/gadget/udc/net2280.h
@@ -178,9 +178,6 @@ struct net2280 {
178 struct net2280_dep_regs __iomem *dep; 178 struct net2280_dep_regs __iomem *dep;
179 struct net2280_ep_regs __iomem *epregs; 179 struct net2280_ep_regs __iomem *epregs;
180 struct usb338x_ll_regs __iomem *llregs; 180 struct usb338x_ll_regs __iomem *llregs;
181 struct usb338x_ll_lfps_regs __iomem *ll_lfps_regs;
182 struct usb338x_ll_tsn_regs __iomem *ll_tsn_regs;
183 struct usb338x_ll_chi_regs __iomem *ll_chicken_reg;
184 struct usb338x_pl_regs __iomem *plregs; 181 struct usb338x_pl_regs __iomem *plregs;
185 182
186 struct dma_pool *requests; 183 struct dma_pool *requests;
diff --git a/drivers/usb/gadget/udc/pch_udc.c b/drivers/usb/gadget/udc/pch_udc.c
index cded51f36fc1..265dab2bbfac 100644
--- a/drivers/usb/gadget/udc/pch_udc.c
+++ b/drivers/usb/gadget/udc/pch_udc.c
@@ -3046,8 +3046,7 @@ static void pch_udc_remove(struct pci_dev *pdev)
3046#ifdef CONFIG_PM_SLEEP 3046#ifdef CONFIG_PM_SLEEP
3047static int pch_udc_suspend(struct device *d) 3047static int pch_udc_suspend(struct device *d)
3048{ 3048{
3049 struct pci_dev *pdev = to_pci_dev(d); 3049 struct pch_udc_dev *dev = dev_get_drvdata(d);
3050 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3051 3050
3052 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); 3051 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3053 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); 3052 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index f6a037b5e9ef..b451f4695f3f 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -65,7 +65,7 @@ struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
65 65
66static struct list_head active_timers; 66static struct list_head active_timers;
67 67
68static struct fsl_otg_config fsl_otg_initdata = { 68static const struct fsl_otg_config fsl_otg_initdata = {
69 .otg_port = 1, 69 .otg_port = 1,
70}; 70};
71 71
diff --git a/include/linux/platform_data/dwc3-omap.h b/include/linux/platform_data/dwc3-omap.h
deleted file mode 100644
index 1d36ca874cc8..000000000000
--- a/include/linux/platform_data/dwc3-omap.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/**
2 * dwc3-omap.h - OMAP Specific Glue layer, header.
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Author: Felipe Balbi <balbi@ti.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39enum dwc3_omap_utmi_mode {
40 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
41 DWC3_OMAP_UTMI_MODE_HW,
42 DWC3_OMAP_UTMI_MODE_SW,
43};
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index da82606be605..58b83066bea4 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -70,4 +70,31 @@ extern enum usb_device_speed usb_get_maximum_speed(struct device *dev);
70 */ 70 */
71extern const char *usb_state_string(enum usb_device_state state); 71extern const char *usb_state_string(enum usb_device_state state);
72 72
73#ifdef CONFIG_TRACING
74/**
75 * usb_decode_ctrl - Returns human readable representation of control request.
76 * @str: buffer to return a human-readable representation of control request.
77 * This buffer should have about 200 bytes.
78 * @size: size of str buffer.
79 * @bRequestType: matches the USB bmRequestType field
80 * @bRequest: matches the USB bRequest field
81 * @wValue: matches the USB wValue field (CPU byte order)
82 * @wIndex: matches the USB wIndex field (CPU byte order)
83 * @wLength: matches the USB wLength field (CPU byte order)
84 *
85 * Function returns decoded, formatted and human-readable description of
86 * control request packet.
87 *
88 * The usage scenario for this is for tracepoints, so function as a return
89 * use the same value as in parameters. This approach allows to use this
90 * function in TP_printk
91 *
92 * Important: wValue, wIndex, wLength parameters before invoking this function
93 * should be processed by le16_to_cpu macro.
94 */
95extern const char *usb_decode_ctrl(char *str, size_t size, __u8 bRequestType,
96 __u8 bRequest, __u16 wValue, __u16 wIndex,
97 __u16 wLength);
98#endif
99
73#endif /* __LINUX_USB_CH9_H */ 100#endif /* __LINUX_USB_CH9_H */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index fb19141151d8..124462d65eac 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -291,6 +291,9 @@ struct usb_dcd_config_params {
291#define USB_DEFAULT_U1_DEV_EXIT_LAT 0x01 /* Less then 1 microsec */ 291#define USB_DEFAULT_U1_DEV_EXIT_LAT 0x01 /* Less then 1 microsec */
292 __le16 bU2DevExitLat; /* U2 Device exit Latency */ 292 __le16 bU2DevExitLat; /* U2 Device exit Latency */
293#define USB_DEFAULT_U2_DEV_EXIT_LAT 0x1F4 /* Less then 500 microsec */ 293#define USB_DEFAULT_U2_DEV_EXIT_LAT 0x1F4 /* Less then 500 microsec */
294 __u8 besl_baseline; /* Recommended baseline BESL (0-15) */
295 __u8 besl_deep; /* Recommended deep BESL (0-15) */
296#define USB_DEFAULT_BESL_UNSPECIFIED 0xFF /* No recommended value */
294}; 297};
295 298
296 299
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index 8d3869c7de85..712b2a603645 100644
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -597,6 +597,10 @@ extern void usb_ep0_reinit(struct usb_device *);
597#define GetPortStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, USB_REQ_GET_STATUS) 597#define GetPortStatus HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, USB_REQ_GET_STATUS)
598#define SetHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, USB_REQ_SET_FEATURE) 598#define SetHubFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, USB_REQ_SET_FEATURE)
599#define SetPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, USB_REQ_SET_FEATURE) 599#define SetPortFeature HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, USB_REQ_SET_FEATURE)
600#define ClearTTBuffer HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, HUB_CLEAR_TT_BUFFER)
601#define ResetTT HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, HUB_RESET_TT)
602#define GetTTState HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, HUB_GET_TT_STATE)
603#define StopTT HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, HUB_STOP_TT)
600 604
601 605
602/*-------------------------------------------------------------------------*/ 606/*-------------------------------------------------------------------------*/
diff --git a/include/linux/usb/usb338x.h b/include/linux/usb/usb338x.h
index 7189e3387bf9..20020c1336d5 100644
--- a/include/linux/usb/usb338x.h
+++ b/include/linux/usb/usb338x.h
@@ -113,7 +113,10 @@ struct usb338x_ll_regs {
113 u32 ll_ltssm_ctrl1; 113 u32 ll_ltssm_ctrl1;
114 u32 ll_ltssm_ctrl2; 114 u32 ll_ltssm_ctrl2;
115 u32 ll_ltssm_ctrl3; 115 u32 ll_ltssm_ctrl3;
116 u32 unused[2]; 116 u32 unused1;
117
118 /* 0x710 */
119 u32 unused2;
117 u32 ll_general_ctrl0; 120 u32 ll_general_ctrl0;
118 u32 ll_general_ctrl1; 121 u32 ll_general_ctrl1;
119#define PM_U3_AUTO_EXIT 29 122#define PM_U3_AUTO_EXIT 29
@@ -136,29 +139,41 @@ struct usb338x_ll_regs {
136 u32 ll_general_ctrl2; 139 u32 ll_general_ctrl2;
137#define SELECT_INVERT_LANE_POLARITY 7 140#define SELECT_INVERT_LANE_POLARITY 7
138#define FORCE_INVERT_LANE_POLARITY 6 141#define FORCE_INVERT_LANE_POLARITY 6
142
143 /* 0x720 */
139 u32 ll_general_ctrl3; 144 u32 ll_general_ctrl3;
140 u32 ll_general_ctrl4; 145 u32 ll_general_ctrl4;
141 u32 ll_error_gen; 146 u32 ll_error_gen;
142} __packed; 147 u32 unused3;
148
149 /* 0x730 */
150 u32 unused4[4];
143 151
144struct usb338x_ll_lfps_regs { 152 /* 0x740 */
145 /* offset 0x748 */ 153 u32 unused5[2];
146 u32 ll_lfps_5; 154 u32 ll_lfps_5;
147#define TIMER_LFPS_6US 16 155#define TIMER_LFPS_6US 16
148 u32 ll_lfps_6; 156 u32 ll_lfps_6;
149#define TIMER_LFPS_80US 0 157#define TIMER_LFPS_80US 0
150} __packed;
151 158
152struct usb338x_ll_tsn_regs { 159 /* 0x750 */
153 /* offset 0x77C */ 160 u32 unused6[8];
161
162 /* 0x770 */
163 u32 unused7[3];
154 u32 ll_tsn_counters_2; 164 u32 ll_tsn_counters_2;
155#define HOT_TX_NORESET_TS2 24 165#define HOT_TX_NORESET_TS2 24
166
167 /* 0x780 */
156 u32 ll_tsn_counters_3; 168 u32 ll_tsn_counters_3;
157#define HOT_RX_RESET_TS2 0 169#define HOT_RX_RESET_TS2 0
158} __packed; 170 u32 unused8[3];
159 171
160struct usb338x_ll_chi_regs { 172 /* 0x790 */
161 /* offset 0x79C */ 173 u32 unused9;
174 u32 ll_lfps_timers_2;
175#define LFPS_TIMERS_2_WORKAROUND_VALUE 0x084d
176 u32 unused10;
162 u32 ll_tsn_chicken_bit; 177 u32 ll_tsn_chicken_bit;
163#define RECOVERY_IDLE_TO_RECOVER_FMW 3 178#define RECOVERY_IDLE_TO_RECOVER_FMW 3
164} __packed; 179} __packed;
diff --git a/include/uapi/linux/usb/ch9.h b/include/uapi/linux/usb/ch9.h
index d5a5caec8fbc..2b623f36af6b 100644
--- a/include/uapi/linux/usb/ch9.h
+++ b/include/uapi/linux/usb/ch9.h
@@ -894,6 +894,8 @@ struct usb_ext_cap_descriptor { /* Link Power Management */
894#define USB_BESL_SUPPORT (1 << 2) /* supports BESL */ 894#define USB_BESL_SUPPORT (1 << 2) /* supports BESL */
895#define USB_BESL_BASELINE_VALID (1 << 3) /* Baseline BESL valid*/ 895#define USB_BESL_BASELINE_VALID (1 << 3) /* Baseline BESL valid*/
896#define USB_BESL_DEEP_VALID (1 << 4) /* Deep BESL valid */ 896#define USB_BESL_DEEP_VALID (1 << 4) /* Deep BESL valid */
897#define USB_SET_BESL_BASELINE(p) (((p) & 0xf) << 8)
898#define USB_SET_BESL_DEEP(p) (((p) & 0xf) << 12)
897#define USB_GET_BESL_BASELINE(p) (((p) & (0xf << 8)) >> 8) 899#define USB_GET_BESL_BASELINE(p) (((p) & (0xf << 8)) >> 8)
898#define USB_GET_BESL_DEEP(p) (((p) & (0xf << 12)) >> 12) 900#define USB_GET_BESL_DEEP(p) (((p) & (0xf << 12)) >> 12)
899} __attribute__((packed)); 901} __attribute__((packed));
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 05:20:32 -0400