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authorMauro Carvalho Chehab <mchehab+samsung@kernel.org>2019-04-18 13:34:34 -0400
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>2019-07-15 08:20:26 -0400
commit8ea0afa3b801e9fe3ff676c3e60e74afa1a0848a (patch)
tree443bd51a72db01596ceacd710567060706201d75
parentb0a4aa950c68b5010831ecfc450510c64e4d80ba (diff)
docs: xtensa: convert to ReST
Rename the xtensa documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat
-rw-r--r--Documentation/xtensa/atomctl.rst (renamed from Documentation/xtensa/atomctl.txt)13
-rw-r--r--Documentation/xtensa/booting.rst (renamed from Documentation/xtensa/booting.txt)5
-rw-r--r--Documentation/xtensa/index.rst12
-rw-r--r--Documentation/xtensa/mmu.rst195
-rw-r--r--Documentation/xtensa/mmu.txt189
-rw-r--r--arch/xtensa/include/asm/initialize_mmu.h2
6 files changed, 222 insertions, 194 deletions
diff --git a/Documentation/xtensa/atomctl.txt b/Documentation/xtensa/atomctl.rst
index 1da783ac200c..1ecbd0ba9a2e 100644
--- a/Documentation/xtensa/atomctl.txt
+++ b/Documentation/xtensa/atomctl.rst
@@ -1,3 +1,7 @@
1===========================================
2Atomic Operation Control (ATOMCTL) Register
3===========================================
4
1We Have Atomic Operation Control (ATOMCTL) Register. 5We Have Atomic Operation Control (ATOMCTL) Register.
2This register determines the effect of using a S32C1I instruction 6This register determines the effect of using a S32C1I instruction
3with various combinations of: 7with various combinations of:
@@ -8,7 +12,7 @@ with various combinations of:
8 2. With and without An Intelligent Memory Controller which 12 2. With and without An Intelligent Memory Controller which
9 can do Atomic Transactions itself. 13 can do Atomic Transactions itself.
10 14
11The Core comes up with a default value of for the three types of cache ops: 15The Core comes up with a default value of for the three types of cache ops::
12 16
13 0x28: (WB: Internal, WT: Internal, BY:Exception) 17 0x28: (WB: Internal, WT: Internal, BY:Exception)
14 18
@@ -30,15 +34,18 @@ CUSTOMER-WARNING:
30Developers might find using RCW in Bypass mode convenient when testing 34Developers might find using RCW in Bypass mode convenient when testing
31with the cache being bypassed; for example studying cache alias problems. 35with the cache being bypassed; for example studying cache alias problems.
32 36
33See Section 4.3.12.4 of ISA; Bits: 37See Section 4.3.12.4 of ISA; Bits::
34 38
35 WB WT BY 39 WB WT BY
36 5 4 | 3 2 | 1 0 40 5 4 | 3 2 | 1 0
41
42========= ================== ================== ===============
37 2 Bit 43 2 Bit
38 Field 44 Field
39 Values WB - Write Back WT - Write Thru BY - Bypass 45 Values WB - Write Back WT - Write Thru BY - Bypass
40--------- --------------- ----------------- ---------------- 46========= ================== ================== ===============
41 0 Exception Exception Exception 47 0 Exception Exception Exception
42 1 RCW Transaction RCW Transaction RCW Transaction 48 1 RCW Transaction RCW Transaction RCW Transaction
43 2 Internal Operation Internal Operation Reserved 49 2 Internal Operation Internal Operation Reserved
44 3 Reserved Reserved Reserved 50 3 Reserved Reserved Reserved
51========= ================== ================== ===============
diff --git a/Documentation/xtensa/booting.txt b/Documentation/xtensa/booting.rst
index 402b33a2619f..e1b83707e5b6 100644
--- a/Documentation/xtensa/booting.txt
+++ b/Documentation/xtensa/booting.rst
@@ -1,10 +1,13 @@
1Passing boot parameters to the kernel. 1=====================================
2Passing boot parameters to the kernel
3=====================================
2 4
3Boot parameters are represented as a TLV list in the memory. Please see 5Boot parameters are represented as a TLV list in the memory. Please see
4arch/xtensa/include/asm/bootparam.h for definition of the bp_tag structure and 6arch/xtensa/include/asm/bootparam.h for definition of the bp_tag structure and
5tag value constants. First entry in the list must have type BP_TAG_FIRST, last 7tag value constants. First entry in the list must have type BP_TAG_FIRST, last
6entry must have type BP_TAG_LAST. The address of the first list entry is 8entry must have type BP_TAG_LAST. The address of the first list entry is
7passed to the kernel in the register a2. The address type depends on MMU type: 9passed to the kernel in the register a2. The address type depends on MMU type:
10
8- For configurations without MMU, with region protection or with MPU the 11- For configurations without MMU, with region protection or with MPU the
9 address must be the physical address. 12 address must be the physical address.
10- For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n 13- For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n
diff --git a/Documentation/xtensa/index.rst b/Documentation/xtensa/index.rst
new file mode 100644
index 000000000000..5a24e365e35f
--- /dev/null
+++ b/Documentation/xtensa/index.rst
@@ -0,0 +1,12 @@
1:orphan:
2
3===================
4Xtensa Architecture
5===================
6
7.. toctree::
8 :maxdepth: 1
9
10 atomctl
11 booting
12 mmu
diff --git a/Documentation/xtensa/mmu.rst b/Documentation/xtensa/mmu.rst
new file mode 100644
index 000000000000..e52a12960fdc
--- /dev/null
+++ b/Documentation/xtensa/mmu.rst
@@ -0,0 +1,195 @@
1=============================
2MMUv3 initialization sequence
3=============================
4
5The code in the initialize_mmu macro sets up MMUv3 memory mapping
6identically to MMUv2 fixed memory mapping. Depending on
7CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
8located in addresses it was linked for (symbol undefined), or not
9(symbol defined), so it needs to be position-independent.
10
11The code has the following assumptions:
12
13 - This code fragment is run only on an MMU v3.
14 - TLBs are in their reset state.
15 - ITLBCFG and DTLBCFG are zero (reset state).
16 - RASID is 0x04030201 (reset state).
17 - PS.RING is zero (reset state).
18 - LITBASE is zero (reset state, PC-relative literals); required to be PIC.
19
20TLB setup proceeds along the following steps.
21
22 Legend:
23
24 - VA = virtual address (two upper nibbles of it);
25 - PA = physical address (two upper nibbles of it);
26 - pc = physical range that contains this code;
27
28After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
300x40000000 or above. That address corresponds to next instruction to execute
31in this code. After step 4, we jump to intended (linked) address of this code.
32The scheme below assumes that the kernel is loaded below 0x40000000.
33
34 ====== ===== ===== ===== ===== ====== ===== =====
35 - Step0 Step1 Step2 Step3 Step4 Step5
36
37 VA PA PA PA PA VA PA PA
38 ====== ===== ===== ===== ===== ====== ===== =====
39 E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
40 C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
41 A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
42 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
43 60..7F -> 60 -> 60 -> 60
44 40..5F -> 40 -> pc -> pc 40..5F -> pc
45 20..3F -> 20 -> 20 -> 20
46 00..1F -> 00 -> 00 -> 00
47 ====== ===== ===== ===== ===== ====== ===== =====
48
49The default location of IO peripherals is above 0xf0000000. This may be changed
50using a "ranges" property in a device tree simple-bus node. See the Devicetree
51Specification, section 4.5 for details on the syntax and semantics of
52simple-bus nodes. The following limitations apply:
53
541. Only top level simple-bus nodes are considered
55
562. Only one (first) simple-bus node is considered
57
583. Empty "ranges" properties are not supported
59
604. Only the first triplet in the "ranges" property is considered
61
625. The parent-bus-address value is rounded down to the nearest 256MB boundary
63
646. The IO area covers the entire 256MB segment of parent-bus-address; the
65 "ranges" triplet length field is ignored
66
67
68MMUv3 address space layouts.
69============================
70
71Default MMUv2-compatible layout::
72
73 Symbol VADDR Size
74 +------------------+
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
77 +------------------+
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
79 +------------------+
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
81 +------------------+ 0x8e400000
82 +------------------+
83 | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
84 +------------------+ VMALLOC_END
85 | Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
86 | remap area 1 |
87 +------------------+
88 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
89 | remap area 2 |
90 +------------------+
91 +------------------+
92 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
93 | | DCACHE_N_COLORS *
94 | | PAGE_SIZE
95 | | (4MB * DCACHE_N_COLORS)
96 +------------------+
97 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
98 | | NR_CPUS *
99 | | DCACHE_N_COLORS *
100 | | PAGE_SIZE
101 +------------------+ FIXADDR_TOP 0xcffff000
102 +------------------+
103 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
104 +------------------+
105 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
106 +------------------+
107 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
108 +------------------+
109 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
110 +------------------+
111
112
113256MB cached + 256MB uncached layout::
114
115 Symbol VADDR Size
116 +------------------+
117 | Userspace | 0x00000000 TASK_SIZE
118 +------------------+ 0x40000000
119 +------------------+
120 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
121 +------------------+
122 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
123 +------------------+ 0x8e400000
124 +------------------+
125 | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
126 +------------------+ VMALLOC_END
127 | Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
128 | remap area 1 |
129 +------------------+
130 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
131 | remap area 2 |
132 +------------------+
133 +------------------+
134 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
135 | | DCACHE_N_COLORS *
136 | | PAGE_SIZE
137 | | (4MB * DCACHE_N_COLORS)
138 +------------------+
139 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
140 | | NR_CPUS *
141 | | DCACHE_N_COLORS *
142 | | PAGE_SIZE
143 +------------------+ FIXADDR_TOP 0xaffff000
144 +------------------+
145 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
146 +------------------+
147 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
148 +------------------+
149 +------------------+
150 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
151 +------------------+
152 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
153 +------------------+
154
155
156512MB cached + 512MB uncached layout::
157
158 Symbol VADDR Size
159 +------------------+
160 | Userspace | 0x00000000 TASK_SIZE
161 +------------------+ 0x40000000
162 +------------------+
163 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
164 +------------------+
165 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
166 +------------------+ 0x8e400000
167 +------------------+
168 | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
169 +------------------+ VMALLOC_END
170 | Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
171 | remap area 1 |
172 +------------------+
173 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
174 | remap area 2 |
175 +------------------+
176 +------------------+
177 | KMAP area | PKMAP_BASE PTRS_PER_PTE *
178 | | DCACHE_N_COLORS *
179 | | PAGE_SIZE
180 | | (4MB * DCACHE_N_COLORS)
181 +------------------+
182 | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
183 | | NR_CPUS *
184 | | DCACHE_N_COLORS *
185 | | PAGE_SIZE
186 +------------------+ FIXADDR_TOP 0x9ffff000
187 +------------------+
188 | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
189 +------------------+
190 | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
191 +------------------+
192 | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
193 +------------------+
194 | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
195 +------------------+
diff --git a/Documentation/xtensa/mmu.txt b/Documentation/xtensa/mmu.txt
deleted file mode 100644
index 318114de63f3..000000000000
--- a/Documentation/xtensa/mmu.txt
+++ /dev/null
@@ -1,189 +0,0 @@
1MMUv3 initialization sequence.
2
3The code in the initialize_mmu macro sets up MMUv3 memory mapping
4identically to MMUv2 fixed memory mapping. Depending on
5CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
6located in addresses it was linked for (symbol undefined), or not
7(symbol defined), so it needs to be position-independent.
8
9The code has the following assumptions:
10 This code fragment is run only on an MMU v3.
11 TLBs are in their reset state.
12 ITLBCFG and DTLBCFG are zero (reset state).
13 RASID is 0x04030201 (reset state).
14 PS.RING is zero (reset state).
15 LITBASE is zero (reset state, PC-relative literals); required to be PIC.
16
17TLB setup proceeds along the following steps.
18
19 Legend:
20 VA = virtual address (two upper nibbles of it);
21 PA = physical address (two upper nibbles of it);
22 pc = physical range that contains this code;
23
24After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
25or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
260x40000000 or above. That address corresponds to next instruction to execute
27in this code. After step 4, we jump to intended (linked) address of this code.
28The scheme below assumes that the kernel is loaded below 0x40000000.
29
30 Step0 Step1 Step2 Step3 Step4 Step5
31 ===== ===== ===== ===== ===== =====
32 VA PA PA PA PA VA PA PA
33 ------ -- -- -- -- ------ -- --
34 E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
35 C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
36 A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
37 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
38 60..7F -> 60 -> 60 -> 60
39 40..5F -> 40 -> pc -> pc 40..5F -> pc
40 20..3F -> 20 -> 20 -> 20
41 00..1F -> 00 -> 00 -> 00
42
43The default location of IO peripherals is above 0xf0000000. This may be changed
44using a "ranges" property in a device tree simple-bus node. See the Devicetree
45Specification, section 4.5 for details on the syntax and semantics of
46simple-bus nodes. The following limitations apply:
47
481. Only top level simple-bus nodes are considered
49
502. Only one (first) simple-bus node is considered
51
523. Empty "ranges" properties are not supported
53
544. Only the first triplet in the "ranges" property is considered
55
565. The parent-bus-address value is rounded down to the nearest 256MB boundary
57
586. The IO area covers the entire 256MB segment of parent-bus-address; the
59 "ranges" triplet length field is ignored
60
61
62MMUv3 address space layouts.
63============================
64
65Default MMUv2-compatible layout.
66
67 Symbol VADDR Size
68+------------------+
69| Userspace | 0x00000000 TASK_SIZE
70+------------------+ 0x40000000
71+------------------+
72| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
73+------------------+
74| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
75+------------------+ 0x8e400000
76+------------------+
77| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
78+------------------+ VMALLOC_END
79| Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
80| remap area 1 |
81+------------------+
82| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
83| remap area 2 |
84+------------------+
85+------------------+
86| KMAP area | PKMAP_BASE PTRS_PER_PTE *
87| | DCACHE_N_COLORS *
88| | PAGE_SIZE
89| | (4MB * DCACHE_N_COLORS)
90+------------------+
91| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
92| | NR_CPUS *
93| | DCACHE_N_COLORS *
94| | PAGE_SIZE
95+------------------+ FIXADDR_TOP 0xcffff000
96+------------------+
97| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
98+------------------+
99| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
100+------------------+
101| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
102+------------------+
103| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
104+------------------+
105
106
107256MB cached + 256MB uncached layout.
108
109 Symbol VADDR Size
110+------------------+
111| Userspace | 0x00000000 TASK_SIZE
112+------------------+ 0x40000000
113+------------------+
114| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
115+------------------+
116| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
117+------------------+ 0x8e400000
118+------------------+
119| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
120+------------------+ VMALLOC_END
121| Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
122| remap area 1 |
123+------------------+
124| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
125| remap area 2 |
126+------------------+
127+------------------+
128| KMAP area | PKMAP_BASE PTRS_PER_PTE *
129| | DCACHE_N_COLORS *
130| | PAGE_SIZE
131| | (4MB * DCACHE_N_COLORS)
132+------------------+
133| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
134| | NR_CPUS *
135| | DCACHE_N_COLORS *
136| | PAGE_SIZE
137+------------------+ FIXADDR_TOP 0xaffff000
138+------------------+
139| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
140+------------------+
141| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
142+------------------+
143+------------------+
144| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
145+------------------+
146| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
147+------------------+
148
149
150512MB cached + 512MB uncached layout.
151
152 Symbol VADDR Size
153+------------------+
154| Userspace | 0x00000000 TASK_SIZE
155+------------------+ 0x40000000
156+------------------+
157| Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
158+------------------+
159| KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
160+------------------+ 0x8e400000
161+------------------+
162| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
163+------------------+ VMALLOC_END
164| Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
165| remap area 1 |
166+------------------+
167| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
168| remap area 2 |
169+------------------+
170+------------------+
171| KMAP area | PKMAP_BASE PTRS_PER_PTE *
172| | DCACHE_N_COLORS *
173| | PAGE_SIZE
174| | (4MB * DCACHE_N_COLORS)
175+------------------+
176| Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
177| | NR_CPUS *
178| | DCACHE_N_COLORS *
179| | PAGE_SIZE
180+------------------+ FIXADDR_TOP 0x9ffff000
181+------------------+
182| Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
183+------------------+
184| Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
185+------------------+
186| Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
187+------------------+
188| Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
189+------------------+
diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index 323d05789159..3b054d2bede0 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -42,7 +42,7 @@
42#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) 42#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
43/* 43/*
44 * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it. 44 * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
45 * For details see Documentation/xtensa/atomctl.txt 45 * For details see Documentation/xtensa/atomctl.rst
46 */ 46 */
47#if XCHAL_DCACHE_IS_COHERENT 47#if XCHAL_DCACHE_IS_COHERENT
48 movi a3, 0x25 /* For SMP/MX -- internal for writeback, 48 movi a3, 0x25 /* For SMP/MX -- internal for writeback,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 09:14:17 -0400