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authorBjorn Helgaas <bhelgaas@google.com>2019-09-23 17:10:24 -0400
committerBjorn Helgaas <bhelgaas@google.com>2019-09-23 17:10:24 -0400
commit8b38b5f2cf928b80f83daff55e2242f40565ce02 (patch)
tree1920aae393d955a680f09006dfbd7d2143b63b89
parent5adc7d510627fa940cde9beafba49c889c5656a7 (diff)
parent0cccd42e6193e168cbecc271dae464e4a53fd7b3 (diff)
Merge branch 'remotes/lorenzo/pci/mediatek'
- Add mediatek support for MT7629 (Jianjun Wang) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Add controller support for MT7629 dt-bindings: PCI: Add support for MT7629
-rw-r--r--Documentation/devicetree/bindings/pci/mediatek-pcie.txt1
-rw-r--r--drivers/pci/controller/pcie-mediatek.c18
-rw-r--r--include/linux/pci_ids.h1
3 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 92437a366e5f..7468d666763a 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -6,6 +6,7 @@ Required properties:
6 "mediatek,mt2712-pcie" 6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie" 7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie" 8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
9- device_type: Must be "pci" 10- device_type: Must be "pci"
10- reg: Base addresses and lengths of the PCIe subsys and root ports. 11- reg: Base addresses and lengths of the PCIe subsys and root ports.
11- reg-names: Names of the above areas to use during resource lookup. 12- reg-names: Names of the above areas to use during resource lookup.
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 80601e1b939e..3eaa7081ab2a 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -73,6 +73,7 @@
73#define PCIE_MSI_VECTOR 0x0c0 73#define PCIE_MSI_VECTOR 0x0c0
74 74
75#define PCIE_CONF_VEND_ID 0x100 75#define PCIE_CONF_VEND_ID 0x100
76#define PCIE_CONF_DEVICE_ID 0x102
76#define PCIE_CONF_CLASS_ID 0x106 77#define PCIE_CONF_CLASS_ID 0x106
77 78
78#define PCIE_INT_MASK 0x420 79#define PCIE_INT_MASK 0x420
@@ -141,12 +142,16 @@ struct mtk_pcie_port;
141/** 142/**
142 * struct mtk_pcie_soc - differentiate between host generations 143 * struct mtk_pcie_soc - differentiate between host generations
143 * @need_fix_class_id: whether this host's class ID needed to be fixed or not 144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146 * @device_id: device ID which this host need to be fixed
144 * @ops: pointer to configuration access functions 147 * @ops: pointer to configuration access functions
145 * @startup: pointer to controller setting functions 148 * @startup: pointer to controller setting functions
146 * @setup_irq: pointer to initialize IRQ functions 149 * @setup_irq: pointer to initialize IRQ functions
147 */ 150 */
148struct mtk_pcie_soc { 151struct mtk_pcie_soc {
149 bool need_fix_class_id; 152 bool need_fix_class_id;
153 bool need_fix_device_id;
154 unsigned int device_id;
150 struct pci_ops *ops; 155 struct pci_ops *ops;
151 int (*startup)(struct mtk_pcie_port *port); 156 int (*startup)(struct mtk_pcie_port *port);
152 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
@@ -696,6 +701,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
696 writew(val, port->base + PCIE_CONF_CLASS_ID); 701 writew(val, port->base + PCIE_CONF_CLASS_ID);
697 } 702 }
698 703
704 if (soc->need_fix_device_id)
705 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
706
699 /* 100ms timeout value should be enough for Gen1/2 training */ 707 /* 100ms timeout value should be enough for Gen1/2 training */
700 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 708 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
701 !!(val & PCIE_PORT_LINKUP_V2), 20, 709 !!(val & PCIE_PORT_LINKUP_V2), 20,
@@ -1216,11 +1224,21 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1216 .setup_irq = mtk_pcie_setup_irq, 1224 .setup_irq = mtk_pcie_setup_irq,
1217}; 1225};
1218 1226
1227static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1228 .need_fix_class_id = true,
1229 .need_fix_device_id = true,
1230 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1231 .ops = &mtk_pcie_ops_v2,
1232 .startup = mtk_pcie_startup_port_v2,
1233 .setup_irq = mtk_pcie_setup_irq,
1234};
1235
1219static const struct of_device_id mtk_pcie_ids[] = { 1236static const struct of_device_id mtk_pcie_ids[] = {
1220 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1237 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1221 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1238 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1222 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1239 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1223 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1240 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1241 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1224 {}, 1242 {},
1225}; 1243};
1226 1244
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 5ce83544f38b..f3130542c752 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2132,6 +2132,7 @@
2132#define PCI_VENDOR_ID_MYRICOM 0x14c1 2132#define PCI_VENDOR_ID_MYRICOM 0x14c1
2133 2133
2134#define PCI_VENDOR_ID_MEDIATEK 0x14c3 2134#define PCI_VENDOR_ID_MEDIATEK 0x14c3
2135#define PCI_DEVICE_ID_MEDIATEK_7629 0x7629
2135 2136
2136#define PCI_VENDOR_ID_TITAN 0x14D2 2137#define PCI_VENDOR_ID_TITAN 0x14D2
2137#define PCI_DEVICE_ID_TITAN_010L 0x8001 2138#define PCI_DEVICE_ID_TITAN_010L 0x8001