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authorPawel Laszczak <pawell@cadence.com>2019-08-26 07:19:30 -0400
committerFelipe Balbi <felipe.balbi@linux.intel.com>2019-08-29 03:57:04 -0400
commit7733f6c32e36ff9d7adadf40001039bf219b1cbe (patch)
tree5cdaa653c1764993c4009d9e8c9daf04c070bb41
parentf72429fc88b5f48ee9ff2617224bbe098e40e86f (diff)
usb: cdns3: Add Cadence USB3 DRD Driver
This patch introduce new Cadence USBSS DRD driver to Linux kernel. The Cadence USBSS DRD Controller is a highly configurable IP Core which can be instantiated as Dual-Role Device (DRD), Peripheral Only and Host Only (XHCI)configurations. The current driver has been validated with FPGA platform. We have support for PCIe bus, which is used on FPGA prototyping. The host side of USBSS-DRD controller is compliant with XHCI specification, so it works with standard XHCI Linux driver. Signed-off-by: Pawel Laszczak <pawell@cadence.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat
-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/Makefile2
-rw-r--r--drivers/usb/cdns3/Kconfig46
-rw-r--r--drivers/usb/cdns3/Makefile16
-rw-r--r--drivers/usb/cdns3/cdns3-pci-wrap.c203
-rw-r--r--drivers/usb/cdns3/core.c653
-rw-r--r--drivers/usb/cdns3/core.h98
-rw-r--r--drivers/usb/cdns3/debug.h161
-rw-r--r--drivers/usb/cdns3/drd.c381
-rw-r--r--drivers/usb/cdns3/drd.h167
-rw-r--r--drivers/usb/cdns3/ep0.c888
-rw-r--r--drivers/usb/cdns3/gadget-export.h28
-rw-r--r--drivers/usb/cdns3/gadget.c2416
-rw-r--r--drivers/usb/cdns3/gadget.h1325
-rw-r--r--drivers/usb/cdns3/host-export.h28
-rw-r--r--drivers/usb/cdns3/host.c74
-rw-r--r--drivers/usb/cdns3/trace.c11
-rw-r--r--drivers/usb/cdns3/trace.h493
18 files changed, 6992 insertions, 0 deletions
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 6e59d370ef81..2f4a70b5a225 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -114,6 +114,8 @@ source "drivers/usb/usbip/Kconfig"
114 114
115endif 115endif
116 116
117source "drivers/usb/cdns3/Kconfig"
118
117source "drivers/usb/mtu3/Kconfig" 119source "drivers/usb/mtu3/Kconfig"
118 120
119source "drivers/usb/musb/Kconfig" 121source "drivers/usb/musb/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index ecc2de1ffaae..09fc9f2448ce 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -13,6 +13,8 @@ obj-$(CONFIG_USB_DWC3) += dwc3/
13obj-$(CONFIG_USB_DWC2) += dwc2/ 13obj-$(CONFIG_USB_DWC2) += dwc2/
14obj-$(CONFIG_USB_ISP1760) += isp1760/ 14obj-$(CONFIG_USB_ISP1760) += isp1760/
15 15
16obj-$(CONFIG_USB_CDNS3) += cdns3/
17
16obj-$(CONFIG_USB_MON) += mon/ 18obj-$(CONFIG_USB_MON) += mon/
17obj-$(CONFIG_USB_MTU3) += mtu3/ 19obj-$(CONFIG_USB_MTU3) += mtu3/
18 20
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
new file mode 100644
index 000000000000..d0331613a355
--- /dev/null
+++ b/drivers/usb/cdns3/Kconfig
@@ -0,0 +1,46 @@
1config USB_CDNS3
2 tristate "Cadence USB3 Dual-Role Controller"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
5 select USB_ROLE_SWITCH
6 help
7 Say Y here if your system has a Cadence USB3 dual-role controller.
8 It supports: dual-role switch, Host-only, and Peripheral-only.
9
10 If you choose to build this driver is a dynamically linked
11 as module, the module will be called cdns3.ko.
12
13if USB_CDNS3
14
15config USB_CDNS3_GADGET
16 bool "Cadence USB3 device controller"
17 depends on USB_GADGET=y || USB_GADGET=USB_CDNS3
18 help
19 Say Y here to enable device controller functionality of the
20 Cadence USBSS-DEV driver.
21
22 This controller supports FF, HS and SS mode. It doesn't support
23 LS and SSP mode.
24
25config USB_CDNS3_HOST
26 bool "Cadence USB3 host controller"
27 depends on USB=y || USB=USB_CDNS3
28 help
29 Say Y here to enable host controller functionality of the
30 Cadence driver.
31
32 Host controller is compliant with XHCI so it will use
33 standard XHCI driver.
34
35config USB_CDNS3_PCI_WRAP
36 tristate "Cadence USB3 support on PCIe-based platforms"
37 depends on USB_PCI && ACPI
38 default USB_CDNS3
39 help
40 If you're using the USBSS Core IP with a PCIe, please say
41 'Y' or 'M' here.
42
43 If you choose to build this driver as module it will
44 be dynamically linked and module will be called cdns3-pci.ko
45
46endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
new file mode 100644
index 000000000000..a703547350bb
--- /dev/null
+++ b/drivers/usb/cdns3/Makefile
@@ -0,0 +1,16 @@
1# SPDX-License-Identifier: GPL-2.0
2# define_trace.h needs to know how to find our header
3CFLAGS_trace.o := -I$(src)
4
5cdns3-y := core.o drd.o
6
7obj-$(CONFIG_USB_CDNS3) += cdns3.o
8cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o ep0.o
9
10ifneq ($(CONFIG_USB_CDNS3_GADGET),)
11cdns3-$(CONFIG_TRACING) += trace.o
12endif
13
14cdns3-$(CONFIG_USB_CDNS3_HOST) += host.o
15
16obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
diff --git a/drivers/usb/cdns3/cdns3-pci-wrap.c b/drivers/usb/cdns3/cdns3-pci-wrap.c
new file mode 100644
index 000000000000..c41ddb61b857
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-pci-wrap.c
@@ -0,0 +1,203 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS PCI Glue driver
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/slab.h>
16
17struct cdns3_wrap {
18 struct platform_device *plat_dev;
19 struct resource dev_res[6];
20 int devfn;
21};
22
23#define RES_IRQ_HOST_ID 0
24#define RES_IRQ_PERIPHERAL_ID 1
25#define RES_IRQ_OTG_ID 2
26#define RES_HOST_ID 3
27#define RES_DEV_ID 4
28#define RES_DRD_ID 5
29
30#define PCI_BAR_HOST 0
31#define PCI_BAR_DEV 2
32#define PCI_BAR_OTG 0
33
34#define PCI_DEV_FN_HOST_DEVICE 0
35#define PCI_DEV_FN_OTG 1
36
37#define PCI_DRIVER_NAME "cdns3-pci-usbss"
38#define PLAT_DRIVER_NAME "cdns-usb3"
39
40#define CDNS_VENDOR_ID 0x17cd
41#define CDNS_DEVICE_ID 0x0100
42
43static struct pci_dev *cdns3_get_second_fun(struct pci_dev *pdev)
44{
45 struct pci_dev *func;
46
47 /*
48 * Gets the second function.
49 * It's little tricky, but this platform has two function.
50 * The fist keeps resources for Host/Device while the second
51 * keeps resources for DRD/OTG.
52 */
53 func = pci_get_device(pdev->vendor, pdev->device, NULL);
54 if (unlikely(!func))
55 return NULL;
56
57 if (func->devfn == pdev->devfn) {
58 func = pci_get_device(pdev->vendor, pdev->device, func);
59 if (unlikely(!func))
60 return NULL;
61 }
62
63 return func;
64}
65
66static int cdns3_pci_probe(struct pci_dev *pdev,
67 const struct pci_device_id *id)
68{
69 struct platform_device_info plat_info;
70 struct cdns3_wrap *wrap;
71 struct resource *res;
72 struct pci_dev *func;
73 int err;
74
75 /*
76 * for GADGET/HOST PCI (devfn) function number is 0,
77 * for OTG PCI (devfn) function number is 1
78 */
79 if (!id || (pdev->devfn != PCI_DEV_FN_HOST_DEVICE &&
80 pdev->devfn != PCI_DEV_FN_OTG))
81 return -EINVAL;
82
83 func = cdns3_get_second_fun(pdev);
84 if (unlikely(!func))
85 return -EINVAL;
86
87 err = pcim_enable_device(pdev);
88 if (err) {
89 dev_err(&pdev->dev, "Enabling PCI device has failed %d\n", err);
90 return err;
91 }
92
93 pci_set_master(pdev);
94
95 if (pci_is_enabled(func)) {
96 wrap = pci_get_drvdata(func);
97 } else {
98 wrap = kzalloc(sizeof(*wrap), GFP_KERNEL);
99 if (!wrap) {
100 pci_disable_device(pdev);
101 return -ENOMEM;
102 }
103 }
104
105 res = wrap->dev_res;
106
107 if (pdev->devfn == PCI_DEV_FN_HOST_DEVICE) {
108 /* function 0: host(BAR_0) + device(BAR_1).*/
109 dev_dbg(&pdev->dev, "Initialize Device resources\n");
110 res[RES_DEV_ID].start = pci_resource_start(pdev, PCI_BAR_DEV);
111 res[RES_DEV_ID].end = pci_resource_end(pdev, PCI_BAR_DEV);
112 res[RES_DEV_ID].name = "dev";
113 res[RES_DEV_ID].flags = IORESOURCE_MEM;
114 dev_dbg(&pdev->dev, "USBSS-DEV physical base addr: %pa\n",
115 &res[RES_DEV_ID].start);
116
117 res[RES_HOST_ID].start = pci_resource_start(pdev, PCI_BAR_HOST);
118 res[RES_HOST_ID].end = pci_resource_end(pdev, PCI_BAR_HOST);
119 res[RES_HOST_ID].name = "xhci";
120 res[RES_HOST_ID].flags = IORESOURCE_MEM;
121 dev_dbg(&pdev->dev, "USBSS-XHCI physical base addr: %pa\n",
122 &res[RES_HOST_ID].start);
123
124 /* Interrupt for XHCI */
125 wrap->dev_res[RES_IRQ_HOST_ID].start = pdev->irq;
126 wrap->dev_res[RES_IRQ_HOST_ID].name = "host";
127 wrap->dev_res[RES_IRQ_HOST_ID].flags = IORESOURCE_IRQ;
128
129 /* Interrupt device. It's the same as for HOST. */
130 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].start = pdev->irq;
131 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].name = "peripheral";
132 wrap->dev_res[RES_IRQ_PERIPHERAL_ID].flags = IORESOURCE_IRQ;
133 } else {
134 res[RES_DRD_ID].start = pci_resource_start(pdev, PCI_BAR_OTG);
135 res[RES_DRD_ID].end = pci_resource_end(pdev, PCI_BAR_OTG);
136 res[RES_DRD_ID].name = "otg";
137 res[RES_DRD_ID].flags = IORESOURCE_MEM;
138 dev_dbg(&pdev->dev, "USBSS-DRD physical base addr: %pa\n",
139 &res[RES_DRD_ID].start);
140
141 /* Interrupt for OTG/DRD. */
142 wrap->dev_res[RES_IRQ_OTG_ID].start = pdev->irq;
143 wrap->dev_res[RES_IRQ_OTG_ID].name = "otg";
144 wrap->dev_res[RES_IRQ_OTG_ID].flags = IORESOURCE_IRQ;
145 }
146
147 if (pci_is_enabled(func)) {
148 /* set up platform device info */
149 memset(&plat_info, 0, sizeof(plat_info));
150 plat_info.parent = &pdev->dev;
151 plat_info.fwnode = pdev->dev.fwnode;
152 plat_info.name = PLAT_DRIVER_NAME;
153 plat_info.id = pdev->devfn;
154 wrap->devfn = pdev->devfn;
155 plat_info.res = wrap->dev_res;
156 plat_info.num_res = ARRAY_SIZE(wrap->dev_res);
157 plat_info.dma_mask = pdev->dma_mask;
158 /* register platform device */
159 wrap->plat_dev = platform_device_register_full(&plat_info);
160 if (IS_ERR(wrap->plat_dev)) {
161 pci_disable_device(pdev);
162 kfree(wrap);
163 return PTR_ERR(wrap->plat_dev);
164 }
165 }
166
167 pci_set_drvdata(pdev, wrap);
168 return err;
169}
170
171static void cdns3_pci_remove(struct pci_dev *pdev)
172{
173 struct cdns3_wrap *wrap;
174 struct pci_dev *func;
175
176 func = cdns3_get_second_fun(pdev);
177
178 wrap = (struct cdns3_wrap *)pci_get_drvdata(pdev);
179 if (wrap->devfn == pdev->devfn)
180 platform_device_unregister(wrap->plat_dev);
181
182 if (!pci_is_enabled(func))
183 kfree(wrap);
184}
185
186static const struct pci_device_id cdns3_pci_ids[] = {
187 { PCI_DEVICE(CDNS_VENDOR_ID, CDNS_DEVICE_ID), },
188 { 0, }
189};
190
191static struct pci_driver cdns3_pci_driver = {
192 .name = PCI_DRIVER_NAME,
193 .id_table = cdns3_pci_ids,
194 .probe = cdns3_pci_probe,
195 .remove = cdns3_pci_remove,
196};
197
198module_pci_driver(cdns3_pci_driver);
199MODULE_DEVICE_TABLE(pci, cdns3_pci_ids);
200
201MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>");
202MODULE_LICENSE("GPL v2");
203MODULE_DESCRIPTION("Cadence USBSS PCI wrapperr");
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
new file mode 100644
index 000000000000..300df58a190b
--- /dev/null
+++ b/drivers/usb/cdns3/core.c
@@ -0,0 +1,653 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
7 * Copyright (C) 2019 Texas Instruments
8 *
9 * Author: Peter Chen <peter.chen@nxp.com>
10 * Pawel Laszczak <pawell@cadence.com>
11 * Roger Quadros <rogerq@ti.com>
12 */
13
14#include <linux/dma-mapping.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/pm_runtime.h>
21
22#include "gadget.h"
23#include "core.h"
24#include "host-export.h"
25#include "gadget-export.h"
26#include "drd.h"
27
28static int cdns3_idle_init(struct cdns3 *cdns);
29
30static inline
31struct cdns3_role_driver *cdns3_get_current_role_driver(struct cdns3 *cdns)
32{
33 WARN_ON(!cdns->roles[cdns->role]);
34 return cdns->roles[cdns->role];
35}
36
37static int cdns3_role_start(struct cdns3 *cdns, enum usb_role role)
38{
39 int ret;
40
41 if (WARN_ON(role > USB_ROLE_DEVICE))
42 return 0;
43
44 mutex_lock(&cdns->mutex);
45 cdns->role = role;
46 mutex_unlock(&cdns->mutex);
47
48 if (!cdns->roles[role])
49 return -ENXIO;
50
51 if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE)
52 return 0;
53
54 mutex_lock(&cdns->mutex);
55 ret = cdns->roles[role]->start(cdns);
56 if (!ret)
57 cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE;
58 mutex_unlock(&cdns->mutex);
59
60 return ret;
61}
62
63static void cdns3_role_stop(struct cdns3 *cdns)
64{
65 enum usb_role role = cdns->role;
66
67 if (WARN_ON(role > USB_ROLE_DEVICE))
68 return;
69
70 if (cdns->roles[role]->state == CDNS3_ROLE_STATE_INACTIVE)
71 return;
72
73 mutex_lock(&cdns->mutex);
74 cdns->roles[role]->stop(cdns);
75 cdns->roles[role]->state = CDNS3_ROLE_STATE_INACTIVE;
76 mutex_unlock(&cdns->mutex);
77}
78
79static void cdns3_exit_roles(struct cdns3 *cdns)
80{
81 cdns3_role_stop(cdns);
82 cdns3_drd_exit(cdns);
83}
84
85static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns);
86
87/**
88 * cdns3_core_init_role - initialize role of operation
89 * @cdns: Pointer to cdns3 structure
90 *
91 * Returns 0 on success otherwise negative errno
92 */
93static int cdns3_core_init_role(struct cdns3 *cdns)
94{
95 struct device *dev = cdns->dev;
96 enum usb_dr_mode best_dr_mode;
97 enum usb_dr_mode dr_mode;
98 int ret = 0;
99
100 dr_mode = usb_get_dr_mode(dev);
101 cdns->role = USB_ROLE_NONE;
102
103 /*
104 * If driver can't read mode by means of usb_get_dr_mode function then
105 * chooses mode according with Kernel configuration. This setting
106 * can be restricted later depending on strap pin configuration.
107 */
108 if (dr_mode == USB_DR_MODE_UNKNOWN) {
109 if (IS_ENABLED(CONFIG_USB_CDNS3_HOST) &&
110 IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
111 dr_mode = USB_DR_MODE_OTG;
112 else if (IS_ENABLED(CONFIG_USB_CDNS3_HOST))
113 dr_mode = USB_DR_MODE_HOST;
114 else if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
115 dr_mode = USB_DR_MODE_PERIPHERAL;
116 }
117
118 /*
119 * At this point cdns->dr_mode contains strap configuration.
120 * Driver try update this setting considering kernel configuration
121 */
122 best_dr_mode = cdns->dr_mode;
123
124 ret = cdns3_idle_init(cdns);
125 if (ret)
126 return ret;
127
128 if (dr_mode == USB_DR_MODE_OTG) {
129 best_dr_mode = cdns->dr_mode;
130 } else if (cdns->dr_mode == USB_DR_MODE_OTG) {
131 best_dr_mode = dr_mode;
132 } else if (cdns->dr_mode != dr_mode) {
133 dev_err(dev, "Incorrect DRD configuration\n");
134 return -EINVAL;
135 }
136
137 dr_mode = best_dr_mode;
138
139 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
140 ret = cdns3_host_init(cdns);
141 if (ret) {
142 dev_err(dev, "Host initialization failed with %d\n",
143 ret);
144 goto err;
145 }
146 }
147
148 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
149 ret = cdns3_gadget_init(cdns);
150 if (ret) {
151 dev_err(dev, "Device initialization failed with %d\n",
152 ret);
153 goto err;
154 }
155 }
156
157 cdns->dr_mode = dr_mode;
158
159 ret = cdns3_drd_update_mode(cdns);
160 if (ret)
161 goto err;
162
163 if (cdns->dr_mode != USB_DR_MODE_OTG) {
164 ret = cdns3_hw_role_switch(cdns);
165 if (ret)
166 goto err;
167 }
168
169 return ret;
170err:
171 cdns3_exit_roles(cdns);
172 return ret;
173}
174
175/**
176 * cdsn3_hw_role_state_machine - role switch state machine based on hw events.
177 * @cdns: Pointer to controller structure.
178 *
179 * Returns next role to be entered based on hw events.
180 */
181static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns)
182{
183 enum usb_role role;
184 int id, vbus;
185
186 if (cdns->dr_mode != USB_DR_MODE_OTG)
187 goto not_otg;
188
189 id = cdns3_get_id(cdns);
190 vbus = cdns3_get_vbus(cdns);
191
192 /*
193 * Role change state machine
194 * Inputs: ID, VBUS
195 * Previous state: cdns->role
196 * Next state: role
197 */
198 role = cdns->role;
199
200 switch (role) {
201 case USB_ROLE_NONE:
202 /*
203 * Driver treats USB_ROLE_NONE synonymous to IDLE state from
204 * controller specification.
205 */
206 if (!id)
207 role = USB_ROLE_HOST;
208 else if (vbus)
209 role = USB_ROLE_DEVICE;
210 break;
211 case USB_ROLE_HOST: /* from HOST, we can only change to NONE */
212 if (id)
213 role = USB_ROLE_NONE;
214 break;
215 case USB_ROLE_DEVICE: /* from GADGET, we can only change to NONE*/
216 if (!vbus)
217 role = USB_ROLE_NONE;
218 break;
219 }
220
221 dev_dbg(cdns->dev, "role %d -> %d\n", cdns->role, role);
222
223 return role;
224
225not_otg:
226 if (cdns3_is_host(cdns))
227 role = USB_ROLE_HOST;
228 if (cdns3_is_device(cdns))
229 role = USB_ROLE_DEVICE;
230
231 return role;
232}
233
234static int cdns3_idle_role_start(struct cdns3 *cdns)
235{
236 return 0;
237}
238
239static void cdns3_idle_role_stop(struct cdns3 *cdns)
240{
241 /* Program Lane swap and bring PHY out of RESET */
242 phy_reset(cdns->usb3_phy);
243}
244
245static int cdns3_idle_init(struct cdns3 *cdns)
246{
247 struct cdns3_role_driver *rdrv;
248
249 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
250 if (!rdrv)
251 return -ENOMEM;
252
253 rdrv->start = cdns3_idle_role_start;
254 rdrv->stop = cdns3_idle_role_stop;
255 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
256 rdrv->suspend = NULL;
257 rdrv->resume = NULL;
258 rdrv->name = "idle";
259
260 cdns->roles[USB_ROLE_NONE] = rdrv;
261
262 return 0;
263}
264
265/**
266 * cdns3_hw_role_switch - switch roles based on HW state
267 * @cdns3: controller
268 */
269int cdns3_hw_role_switch(struct cdns3 *cdns)
270{
271 enum usb_role real_role, current_role;
272 int ret = 0;
273
274 /* Do nothing if role based on syfs. */
275 if (cdns->role_override)
276 return 0;
277
278 pm_runtime_get_sync(cdns->dev);
279
280 current_role = cdns->role;
281 real_role = cdsn3_hw_role_state_machine(cdns);
282
283 /* Do nothing if nothing changed */
284 if (current_role == real_role)
285 goto exit;
286
287 cdns3_role_stop(cdns);
288
289 dev_dbg(cdns->dev, "Switching role %d -> %d", current_role, real_role);
290
291 ret = cdns3_role_start(cdns, real_role);
292 if (ret) {
293 /* Back to current role */
294 dev_err(cdns->dev, "set %d has failed, back to %d\n",
295 real_role, current_role);
296 ret = cdns3_role_start(cdns, current_role);
297 if (ret)
298 dev_err(cdns->dev, "back to %d failed too\n",
299 current_role);
300 }
301exit:
302 pm_runtime_put_sync(cdns->dev);
303 return ret;
304}
305
306/**
307 * cdsn3_role_get - get current role of controller.
308 *
309 * @dev: Pointer to device structure
310 *
311 * Returns role
312 */
313static enum usb_role cdns3_role_get(struct device *dev)
314{
315 struct cdns3 *cdns = dev_get_drvdata(dev);
316
317 return cdns->role;
318}
319
320/**
321 * cdns3_role_set - set current role of controller.
322 *
323 * @dev: pointer to device object
324 * @role - the previous role
325 * Handles below events:
326 * - Role switch for dual-role devices
327 * - USB_ROLE_GADGET <--> USB_ROLE_NONE for peripheral-only devices
328 */
329static int cdns3_role_set(struct device *dev, enum usb_role role)
330{
331 struct cdns3 *cdns = dev_get_drvdata(dev);
332 int ret = 0;
333
334 pm_runtime_get_sync(cdns->dev);
335
336 /*
337 * FIXME: switch role framework should be extended to meet
338 * requirements. Driver assumes that role can be controlled
339 * by SW or HW. Temporary workaround is to use USB_ROLE_NONE to
340 * switch from SW to HW control.
341 *
342 * For dr_mode == USB_DR_MODE_OTG:
343 * if user sets USB_ROLE_HOST or USB_ROLE_DEVICE then driver
344 * sets role_override flag and forces that role.
345 * if user sets USB_ROLE_NONE, driver clears role_override and lets
346 * HW state machine take over.
347 *
348 * For dr_mode != USB_DR_MODE_OTG:
349 * Assumptions:
350 * 1. Restricted user control between NONE and dr_mode.
351 * 2. Driver doesn't need to rely on role_override flag.
352 * 3. Driver needs to ensure that HW state machine is never called
353 * if dr_mode != USB_DR_MODE_OTG.
354 */
355 if (role == USB_ROLE_NONE)
356 cdns->role_override = 0;
357 else
358 cdns->role_override = 1;
359
360 /*
361 * HW state might have changed so driver need to trigger
362 * HW state machine if dr_mode == USB_DR_MODE_OTG.
363 */
364 if (!cdns->role_override && cdns->dr_mode == USB_DR_MODE_OTG) {
365 cdns3_hw_role_switch(cdns);
366 goto pm_put;
367 }
368
369 if (cdns->role == role)
370 goto pm_put;
371
372 if (cdns->dr_mode == USB_DR_MODE_HOST) {
373 switch (role) {
374 case USB_ROLE_NONE:
375 case USB_ROLE_HOST:
376 break;
377 default:
378 ret = -EPERM;
379 goto pm_put;
380 }
381 }
382
383 if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) {
384 switch (role) {
385 case USB_ROLE_NONE:
386 case USB_ROLE_DEVICE:
387 break;
388 default:
389 ret = -EPERM;
390 goto pm_put;
391 }
392 }
393
394 cdns3_role_stop(cdns);
395 ret = cdns3_role_start(cdns, role);
396 if (ret) {
397 dev_err(cdns->dev, "set role %d has failed\n", role);
398 ret = -EPERM;
399 }
400
401pm_put:
402 pm_runtime_put_sync(cdns->dev);
403 return ret;
404}
405
406static const struct usb_role_switch_desc cdns3_switch_desc = {
407 .set = cdns3_role_set,
408 .get = cdns3_role_get,
409 .allow_userspace_control = true,
410};
411
412/**
413 * cdns3_probe - probe for cdns3 core device
414 * @pdev: Pointer to cdns3 core platform device
415 *
416 * Returns 0 on success otherwise negative errno
417 */
418static int cdns3_probe(struct platform_device *pdev)
419{
420 struct device *dev = &pdev->dev;
421 struct resource *res;
422 struct cdns3 *cdns;
423 void __iomem *regs;
424 int ret;
425
426 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
427 if (ret) {
428 dev_err(dev, "error setting dma mask: %d\n", ret);
429 return -ENODEV;
430 }
431
432 cdns = devm_kzalloc(dev, sizeof(*cdns), GFP_KERNEL);
433 if (!cdns)
434 return -ENOMEM;
435
436 cdns->dev = dev;
437
438 platform_set_drvdata(pdev, cdns);
439
440 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "host");
441 if (!res) {
442 dev_err(dev, "missing host IRQ\n");
443 return -ENODEV;
444 }
445
446 cdns->xhci_res[0] = *res;
447
448 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "xhci");
449 if (!res) {
450 dev_err(dev, "couldn't get xhci resource\n");
451 return -ENXIO;
452 }
453
454 cdns->xhci_res[1] = *res;
455
456 cdns->dev_irq = platform_get_irq_byname(pdev, "peripheral");
457 if (cdns->dev_irq == -EPROBE_DEFER)
458 return cdns->dev_irq;
459
460 if (cdns->dev_irq < 0)
461 dev_err(dev, "couldn't get peripheral irq\n");
462
463 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dev");
464 regs = devm_ioremap_resource(dev, res);
465 if (IS_ERR(regs)) {
466 dev_err(dev, "couldn't iomap dev resource\n");
467 return PTR_ERR(regs);
468 }
469 cdns->dev_regs = regs;
470
471 cdns->otg_irq = platform_get_irq_byname(pdev, "otg");
472 if (cdns->otg_irq == -EPROBE_DEFER)
473 return cdns->otg_irq;
474
475 if (cdns->otg_irq < 0) {
476 dev_err(dev, "couldn't get otg irq\n");
477 return cdns->otg_irq;
478 }
479
480 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otg");
481 if (!res) {
482 dev_err(dev, "couldn't get otg resource\n");
483 return -ENXIO;
484 }
485
486 cdns->otg_res = *res;
487
488 mutex_init(&cdns->mutex);
489
490 cdns->usb2_phy = devm_phy_optional_get(dev, "cdns3,usb2-phy");
491 if (IS_ERR(cdns->usb2_phy))
492 return PTR_ERR(cdns->usb2_phy);
493
494 ret = phy_init(cdns->usb2_phy);
495 if (ret)
496 return ret;
497
498 cdns->usb3_phy = devm_phy_optional_get(dev, "cdns3,usb3-phy");
499 if (IS_ERR(cdns->usb3_phy))
500 return PTR_ERR(cdns->usb3_phy);
501
502 ret = phy_init(cdns->usb3_phy);
503 if (ret)
504 goto err1;
505
506 ret = phy_power_on(cdns->usb2_phy);
507 if (ret)
508 goto err2;
509
510 ret = phy_power_on(cdns->usb3_phy);
511 if (ret)
512 goto err3;
513
514 cdns->role_sw = usb_role_switch_register(dev, &cdns3_switch_desc);
515 if (IS_ERR(cdns->role_sw)) {
516 ret = PTR_ERR(cdns->role_sw);
517 dev_warn(dev, "Unable to register Role Switch\n");
518 goto err4;
519 }
520
521 ret = cdns3_drd_init(cdns);
522 if (ret)
523 goto err5;
524
525 ret = cdns3_core_init_role(cdns);
526 if (ret)
527 goto err5;
528
529 device_set_wakeup_capable(dev, true);
530 pm_runtime_set_active(dev);
531 pm_runtime_enable(dev);
532
533 /*
534 * The controller needs less time between bus and controller suspend,
535 * and we also needs a small delay to avoid frequently entering low
536 * power mode.
537 */
538 pm_runtime_set_autosuspend_delay(dev, 20);
539 pm_runtime_mark_last_busy(dev);
540 pm_runtime_use_autosuspend(dev);
541 dev_dbg(dev, "Cadence USB3 core: probe succeed\n");
542
543 return 0;
544err5:
545 cdns3_drd_exit(cdns);
546 usb_role_switch_unregister(cdns->role_sw);
547err4:
548 phy_power_off(cdns->usb3_phy);
549
550err3:
551 phy_power_off(cdns->usb2_phy);
552err2:
553 phy_exit(cdns->usb3_phy);
554err1:
555 phy_exit(cdns->usb2_phy);
556
557 return ret;
558}
559
560/**
561 * cdns3_remove - unbind drd driver and clean up
562 * @pdev: Pointer to Linux platform device
563 *
564 * Returns 0 on success otherwise negative errno
565 */
566static int cdns3_remove(struct platform_device *pdev)
567{
568 struct cdns3 *cdns = platform_get_drvdata(pdev);
569
570 pm_runtime_get_sync(&pdev->dev);
571 pm_runtime_disable(&pdev->dev);
572 pm_runtime_put_noidle(&pdev->dev);
573 cdns3_exit_roles(cdns);
574 usb_role_switch_unregister(cdns->role_sw);
575 phy_power_off(cdns->usb2_phy);
576 phy_power_off(cdns->usb3_phy);
577 phy_exit(cdns->usb2_phy);
578 phy_exit(cdns->usb3_phy);
579 return 0;
580}
581
582#ifdef CONFIG_PM_SLEEP
583
584static int cdns3_suspend(struct device *dev)
585{
586 struct cdns3 *cdns = dev_get_drvdata(dev);
587 unsigned long flags;
588
589 if (cdns->role == USB_ROLE_HOST)
590 return 0;
591
592 if (pm_runtime_status_suspended(dev))
593 pm_runtime_resume(dev);
594
595 if (cdns->roles[cdns->role]->suspend) {
596 spin_lock_irqsave(&cdns->gadget_dev->lock, flags);
597 cdns->roles[cdns->role]->suspend(cdns, false);
598 spin_unlock_irqrestore(&cdns->gadget_dev->lock, flags);
599 }
600
601 return 0;
602}
603
604static int cdns3_resume(struct device *dev)
605{
606 struct cdns3 *cdns = dev_get_drvdata(dev);
607 unsigned long flags;
608
609 if (cdns->role == USB_ROLE_HOST)
610 return 0;
611
612 if (cdns->roles[cdns->role]->resume) {
613 spin_lock_irqsave(&cdns->gadget_dev->lock, flags);
614 cdns->roles[cdns->role]->resume(cdns, false);
615 spin_unlock_irqrestore(&cdns->gadget_dev->lock, flags);
616 }
617
618 pm_runtime_disable(dev);
619 pm_runtime_set_active(dev);
620 pm_runtime_enable(dev);
621
622 return 0;
623}
624#endif
625
626static const struct dev_pm_ops cdns3_pm_ops = {
627 SET_SYSTEM_SLEEP_PM_OPS(cdns3_suspend, cdns3_resume)
628};
629
630#ifdef CONFIG_OF
631static const struct of_device_id of_cdns3_match[] = {
632 { .compatible = "cdns,usb3" },
633 { },
634};
635MODULE_DEVICE_TABLE(of, of_cdns3_match);
636#endif
637
638static struct platform_driver cdns3_driver = {
639 .probe = cdns3_probe,
640 .remove = cdns3_remove,
641 .driver = {
642 .name = "cdns-usb3",
643 .of_match_table = of_match_ptr(of_cdns3_match),
644 .pm = &cdns3_pm_ops,
645 },
646};
647
648module_platform_driver(cdns3_driver);
649
650MODULE_ALIAS("platform:cdns3");
651MODULE_AUTHOR("Pawel Laszczak <pawell@cadence.com>");
652MODULE_LICENSE("GPL v2");
653MODULE_DESCRIPTION("Cadence USB3 DRD Controller Driver");
diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
new file mode 100644
index 000000000000..969eb94de204
--- /dev/null
+++ b/drivers/usb/cdns3/core.h
@@ -0,0 +1,98 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Header File.
4 *
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 * Pawel Laszczak <pawell@cadence.com>
10 */
11#include <linux/usb/otg.h>
12#include <linux/usb/role.h>
13
14#ifndef __LINUX_CDNS3_CORE_H
15#define __LINUX_CDNS3_CORE_H
16
17struct cdns3;
18
19/**
20 * struct cdns3_role_driver - host/gadget role driver
21 * @start: start this role
22 * @stop: stop this role
23 * @suspend: suspend callback for this role
24 * @resume: resume callback for this role
25 * @irq: irq handler for this role
26 * @name: role name string (host/gadget)
27 * @state: current state
28 */
29struct cdns3_role_driver {
30 int (*start)(struct cdns3 *cdns);
31 void (*stop)(struct cdns3 *cdns);
32 int (*suspend)(struct cdns3 *cdns, bool do_wakeup);
33 int (*resume)(struct cdns3 *cdns, bool hibernated);
34 const char *name;
35#define CDNS3_ROLE_STATE_INACTIVE 0
36#define CDNS3_ROLE_STATE_ACTIVE 1
37 int state;
38};
39
40#define CDNS3_XHCI_RESOURCES_NUM 2
41/**
42 * struct cdns3 - Representation of Cadence USB3 DRD controller.
43 * @dev: pointer to Cadence device struct
44 * @xhci_regs: pointer to base of xhci registers
45 * @xhci_res: the resource for xhci
46 * @dev_regs: pointer to base of dev registers
47 * @otg_res: the resource for otg
48 * @otg_v0_regs: pointer to base of v0 otg registers
49 * @otg_v1_regs: pointer to base of v1 otg registers
50 * @otg_regs: pointer to base of otg registers
51 * @otg_irq: irq number for otg controller
52 * @dev_irq: irq number for device controller
53 * @roles: array of supported roles for this controller
54 * @role: current role
55 * @host_dev: the child host device pointer for cdns3 core
56 * @gadget_dev: the child gadget device pointer for cdns3 core
57 * @usb2_phy: pointer to USB2 PHY
58 * @usb3_phy: pointer to USB3 PHY
59 * @mutex: the mutex for concurrent code at driver
60 * @dr_mode: supported mode of operation it can be only Host, only Device
61 * or OTG mode that allow to switch between Device and Host mode.
62 * This field based on firmware setting, kernel configuration
63 * and hardware configuration.
64 * @role_sw: pointer to role switch object.
65 * @role_override: set 1 if role rely on SW.
66 */
67struct cdns3 {
68 struct device *dev;
69 void __iomem *xhci_regs;
70 struct resource xhci_res[CDNS3_XHCI_RESOURCES_NUM];
71 struct cdns3_usb_regs __iomem *dev_regs;
72
73 struct resource otg_res;
74 struct cdns3_otg_legacy_regs *otg_v0_regs;
75 struct cdns3_otg_regs *otg_v1_regs;
76 struct cdns3_otg_common_regs *otg_regs;
77#define CDNS3_CONTROLLER_V0 0
78#define CDNS3_CONTROLLER_V1 1
79 u32 version;
80
81 int otg_irq;
82 int dev_irq;
83 struct cdns3_role_driver *roles[USB_ROLE_DEVICE + 1];
84 enum usb_role role;
85 struct platform_device *host_dev;
86 struct cdns3_device *gadget_dev;
87 struct phy *usb2_phy;
88 struct phy *usb3_phy;
89 /* mutext used in workqueue*/
90 struct mutex mutex;
91 enum usb_dr_mode dr_mode;
92 struct usb_role_switch *role_sw;
93 int role_override;
94};
95
96int cdns3_hw_role_switch(struct cdns3 *cdns);
97
98#endif /* __LINUX_CDNS3_CORE_H */
diff --git a/drivers/usb/cdns3/debug.h b/drivers/usb/cdns3/debug.h
new file mode 100644
index 000000000000..2c9afbfe988b
--- /dev/null
+++ b/drivers/usb/cdns3/debug.h
@@ -0,0 +1,161 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver.
4 * Debug header file.
5 *
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 */
10#ifndef __LINUX_CDNS3_DEBUG
11#define __LINUX_CDNS3_DEBUG
12
13#include "core.h"
14
15static inline char *cdns3_decode_usb_irq(char *str,
16 enum usb_device_speed speed,
17 u32 usb_ists)
18{
19 int ret;
20
21 ret = sprintf(str, "IRQ %08x = ", usb_ists);
22
23 if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
24 ret += sprintf(str + ret, "Connection %s\n",
25 usb_speed_string(speed));
26 }
27 if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI)
28 ret += sprintf(str + ret, "Disconnection ");
29 if (usb_ists & USB_ISTS_L2ENTI)
30 ret += sprintf(str + ret, "suspended ");
31 if (usb_ists & USB_ISTS_L1ENTI)
32 ret += sprintf(str + ret, "L1 enter ");
33 if (usb_ists & USB_ISTS_L1EXTI)
34 ret += sprintf(str + ret, "L1 exit ");
35 if (usb_ists & USB_ISTS_L2ENTI)
36 ret += sprintf(str + ret, "L2 enter ");
37 if (usb_ists & USB_ISTS_L2EXTI)
38 ret += sprintf(str + ret, "L2 exit ");
39 if (usb_ists & USB_ISTS_U3EXTI)
40 ret += sprintf(str + ret, "U3 exit ");
41 if (usb_ists & USB_ISTS_UWRESI)
42 ret += sprintf(str + ret, "Warm Reset ");
43 if (usb_ists & USB_ISTS_UHRESI)
44 ret += sprintf(str + ret, "Hot Reset ");
45 if (usb_ists & USB_ISTS_U2RESI)
46 ret += sprintf(str + ret, "Reset");
47
48 return str;
49}
50
51static inline char *cdns3_decode_ep_irq(char *str,
52 u32 ep_sts,
53 const char *ep_name)
54{
55 int ret;
56
57 ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts);
58
59 if (ep_sts & EP_STS_SETUP)
60 ret += sprintf(str + ret, "SETUP ");
61 if (ep_sts & EP_STS_IOC)
62 ret += sprintf(str + ret, "IOC ");
63 if (ep_sts & EP_STS_ISP)
64 ret += sprintf(str + ret, "ISP ");
65 if (ep_sts & EP_STS_DESCMIS)
66 ret += sprintf(str + ret, "DESCMIS ");
67 if (ep_sts & EP_STS_STREAMR)
68 ret += sprintf(str + ret, "STREAMR ");
69 if (ep_sts & EP_STS_MD_EXIT)
70 ret += sprintf(str + ret, "MD_EXIT ");
71 if (ep_sts & EP_STS_TRBERR)
72 ret += sprintf(str + ret, "TRBERR ");
73 if (ep_sts & EP_STS_NRDY)
74 ret += sprintf(str + ret, "NRDY ");
75 if (ep_sts & EP_STS_PRIME)
76 ret += sprintf(str + ret, "PRIME ");
77 if (ep_sts & EP_STS_SIDERR)
78 ret += sprintf(str + ret, "SIDERRT ");
79 if (ep_sts & EP_STS_OUTSMM)
80 ret += sprintf(str + ret, "OUTSMM ");
81 if (ep_sts & EP_STS_ISOERR)
82 ret += sprintf(str + ret, "ISOERR ");
83 if (ep_sts & EP_STS_IOT)
84 ret += sprintf(str + ret, "IOT ");
85
86 return str;
87}
88
89static inline char *cdns3_decode_epx_irq(char *str,
90 char *ep_name,
91 u32 ep_sts)
92{
93 return cdns3_decode_ep_irq(str, ep_sts, ep_name);
94}
95
96static inline char *cdns3_decode_ep0_irq(char *str,
97 int dir,
98 u32 ep_sts)
99{
100 return cdns3_decode_ep_irq(str, ep_sts,
101 dir ? "ep0IN" : "ep0OUT");
102}
103
104/**
105 * Debug a transfer ring.
106 *
107 * Prints out all TRBs in the endpoint ring, even those after the Link TRB.
108 *.
109 */
110static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep,
111 struct cdns3_trb *ring, char *str)
112{
113 dma_addr_t addr = priv_ep->trb_pool_dma;
114 struct cdns3_trb *trb;
115 int trb_per_sector;
116 int ret = 0;
117 int i;
118
119 trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type);
120
121 trb = &priv_ep->trb_pool[priv_ep->dequeue];
122 ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name);
123
124 ret += sprintf(str + ret,
125 "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n",
126 priv_ep->dequeue, trb,
127 (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
128
129 trb = &priv_ep->trb_pool[priv_ep->enqueue];
130 ret += sprintf(str + ret,
131 "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n",
132 priv_ep->enqueue, trb,
133 (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
134
135 ret += sprintf(str + ret,
136 "\t\tfree trbs: %d, CCS=%d, PCS=%d\n",
137 priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs);
138
139 if (trb_per_sector > TRBS_PER_SEGMENT)
140 trb_per_sector = TRBS_PER_SEGMENT;
141
142 if (trb_per_sector > TRBS_PER_SEGMENT) {
143 sprintf(str + ret, "\t\tTo big transfer ring %d\n",
144 trb_per_sector);
145 return str;
146 }
147
148 for (i = 0; i < trb_per_sector; ++i) {
149 trb = &ring[i];
150 ret += sprintf(str + ret,
151 "\t\t@%pad %08x %08x %08x\n", &addr,
152 le32_to_cpu(trb->buffer),
153 le32_to_cpu(trb->length),
154 le32_to_cpu(trb->control));
155 addr += sizeof(*trb);
156 }
157
158 return str;
159}
160
161#endif /*__LINUX_CDNS3_DEBUG*/
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
new file mode 100644
index 000000000000..16ad485f0b69
--- /dev/null
+++ b/drivers/usb/cdns3/drd.c
@@ -0,0 +1,381 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2019 Texas Instruments
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 * Roger Quadros <rogerq@ti.com>
10 *
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/delay.h>
16#include <linux/iopoll.h>
17#include <linux/usb/otg.h>
18
19#include "gadget.h"
20#include "drd.h"
21#include "core.h"
22
23/**
24 * cdns3_set_mode - change mode of OTG Core
25 * @cdns: pointer to context structure
26 * @mode: selected mode from cdns_role
27 *
28 * Returns 0 on success otherwise negative errno
29 */
30int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode)
31{
32 int ret = 0;
33 u32 reg;
34
35 switch (mode) {
36 case USB_DR_MODE_PERIPHERAL:
37 break;
38 case USB_DR_MODE_HOST:
39 break;
40 case USB_DR_MODE_OTG:
41 dev_dbg(cdns->dev, "Set controller to OTG mode\n");
42 if (cdns->version == CDNS3_CONTROLLER_V1) {
43 reg = readl(&cdns->otg_v1_regs->override);
44 reg |= OVERRIDE_IDPULLUP;
45 writel(reg, &cdns->otg_v1_regs->override);
46 } else {
47 reg = readl(&cdns->otg_v0_regs->ctrl1);
48 reg |= OVERRIDE_IDPULLUP_V0;
49 writel(reg, &cdns->otg_v0_regs->ctrl1);
50 }
51
52 /*
53 * Hardware specification says: "ID_VALUE must be valid within
54 * 50ms after idpullup is set to '1" so driver must wait
55 * 50ms before reading this pin.
56 */
57 usleep_range(50000, 60000);
58 break;
59 default:
60 dev_err(cdns->dev, "Unsupported mode of operation %d\n", mode);
61 return -EINVAL;
62 }
63
64 return ret;
65}
66
67int cdns3_get_id(struct cdns3 *cdns)
68{
69 int id;
70
71 id = readl(&cdns->otg_regs->sts) & OTGSTS_ID_VALUE;
72 dev_dbg(cdns->dev, "OTG ID: %d", id);
73
74 return id;
75}
76
77int cdns3_get_vbus(struct cdns3 *cdns)
78{
79 int vbus;
80
81 vbus = !!(readl(&cdns->otg_regs->sts) & OTGSTS_VBUS_VALID);
82 dev_dbg(cdns->dev, "OTG VBUS: %d", vbus);
83
84 return vbus;
85}
86
87int cdns3_is_host(struct cdns3 *cdns)
88{
89 if (cdns->dr_mode == USB_DR_MODE_HOST)
90 return 1;
91 else if (!cdns3_get_id(cdns))
92 return 1;
93
94 return 0;
95}
96
97int cdns3_is_device(struct cdns3 *cdns)
98{
99 if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL)
100 return 1;
101 else if (cdns->dr_mode == USB_DR_MODE_OTG)
102 if (cdns3_get_id(cdns))
103 return 1;
104
105 return 0;
106}
107
108/**
109 * cdns3_otg_disable_irq - Disable all OTG interrupts
110 * @cdns: Pointer to controller context structure
111 */
112static void cdns3_otg_disable_irq(struct cdns3 *cdns)
113{
114 writel(0, &cdns->otg_regs->ien);
115}
116
117/**
118 * cdns3_otg_enable_irq - enable id and sess_valid interrupts
119 * @cdns: Pointer to controller context structure
120 */
121static void cdns3_otg_enable_irq(struct cdns3 *cdns)
122{
123 writel(OTGIEN_ID_CHANGE_INT | OTGIEN_VBUSVALID_RISE_INT |
124 OTGIEN_VBUSVALID_FALL_INT, &cdns->otg_regs->ien);
125}
126
127/**
128 * cdns3_drd_switch_host - start/stop host
129 * @cdns: Pointer to controller context structure
130 * @on: 1 for start, 0 for stop
131 *
132 * Returns 0 on success otherwise negative errno
133 */
134int cdns3_drd_switch_host(struct cdns3 *cdns, int on)
135{
136 int ret, val;
137 u32 reg = OTGCMD_OTG_DIS;
138
139 /* switch OTG core */
140 if (on) {
141 writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd);
142
143 dev_dbg(cdns->dev, "Waiting till Host mode is turned on\n");
144 ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
145 val & OTGSTS_XHCI_READY,
146 1, 100000);
147 if (ret) {
148 dev_err(cdns->dev, "timeout waiting for xhci_ready\n");
149 return ret;
150 }
151 } else {
152 writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
153 OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
154 &cdns->otg_regs->cmd);
155 /* Waiting till H_IDLE state.*/
156 readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
157 !(val & OTGSTATE_HOST_STATE_MASK),
158 1, 2000000);
159 }
160
161 return 0;
162}
163
164/**
165 * cdns3_drd_switch_gadget - start/stop gadget
166 * @cdns: Pointer to controller context structure
167 * @on: 1 for start, 0 for stop
168 *
169 * Returns 0 on success otherwise negative errno
170 */
171int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on)
172{
173 int ret, val;
174 u32 reg = OTGCMD_OTG_DIS;
175
176 /* switch OTG core */
177 if (on) {
178 writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd);
179
180 dev_dbg(cdns->dev, "Waiting till Device mode is turned on\n");
181
182 ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
183 val & OTGSTS_DEV_READY,
184 1, 100000);
185 if (ret) {
186 dev_err(cdns->dev, "timeout waiting for dev_ready\n");
187 return ret;
188 }
189 } else {
190 /*
191 * driver should wait at least 10us after disabling Device
192 * before turning-off Device (DEV_BUS_DROP)
193 */
194 usleep_range(20, 30);
195 writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
196 OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
197 &cdns->otg_regs->cmd);
198 /* Waiting till DEV_IDLE state.*/
199 readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
200 !(val & OTGSTATE_DEV_STATE_MASK),
201 1, 2000000);
202 }
203
204 return 0;
205}
206
207/**
208 * cdns3_init_otg_mode - initialize drd controller
209 * @cdns: Pointer to controller context structure
210 *
211 * Returns 0 on success otherwise negative errno
212 */
213static int cdns3_init_otg_mode(struct cdns3 *cdns)
214{
215 int ret = 0;
216
217 cdns3_otg_disable_irq(cdns);
218 /* clear all interrupts */
219 writel(~0, &cdns->otg_regs->ivect);
220
221 ret = cdns3_set_mode(cdns, USB_DR_MODE_OTG);
222 if (ret)
223 return ret;
224
225 cdns3_otg_enable_irq(cdns);
226 return ret;
227}
228
229/**
230 * cdns3_drd_update_mode - initialize mode of operation
231 * @cdns: Pointer to controller context structure
232 *
233 * Returns 0 on success otherwise negative errno
234 */
235int cdns3_drd_update_mode(struct cdns3 *cdns)
236{
237 int ret = 0;
238
239 switch (cdns->dr_mode) {
240 case USB_DR_MODE_PERIPHERAL:
241 ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
242 break;
243 case USB_DR_MODE_HOST:
244 ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
245 break;
246 case USB_DR_MODE_OTG:
247 ret = cdns3_init_otg_mode(cdns);
248 break;
249 default:
250 dev_err(cdns->dev, "Unsupported mode of operation %d\n",
251 cdns->dr_mode);
252 return -EINVAL;
253 }
254
255 return ret;
256}
257
258static irqreturn_t cdns3_drd_thread_irq(int irq, void *data)
259{
260 struct cdns3 *cdns = data;
261
262 cdns3_hw_role_switch(cdns);
263
264 return IRQ_HANDLED;
265}
266
267/**
268 * cdns3_drd_irq - interrupt handler for OTG events
269 *
270 * @irq: irq number for cdns3 core device
271 * @data: structure of cdns3
272 *
273 * Returns IRQ_HANDLED or IRQ_NONE
274 */
275static irqreturn_t cdns3_drd_irq(int irq, void *data)
276{
277 irqreturn_t ret = IRQ_NONE;
278 struct cdns3 *cdns = data;
279 u32 reg;
280
281 if (cdns->dr_mode != USB_DR_MODE_OTG)
282 return ret;
283
284 reg = readl(&cdns->otg_regs->ivect);
285
286 if (!reg)
287 return ret;
288
289 if (reg & OTGIEN_ID_CHANGE_INT) {
290 dev_dbg(cdns->dev, "OTG IRQ: new ID: %d\n",
291 cdns3_get_id(cdns));
292
293 ret = IRQ_WAKE_THREAD;
294 }
295
296 if (reg & (OTGIEN_VBUSVALID_RISE_INT | OTGIEN_VBUSVALID_FALL_INT)) {
297 dev_dbg(cdns->dev, "OTG IRQ: new VBUS: %d\n",
298 cdns3_get_vbus(cdns));
299
300 ret = IRQ_WAKE_THREAD;
301 }
302
303 writel(~0, &cdns->otg_regs->ivect);
304 return ret;
305}
306
307int cdns3_drd_init(struct cdns3 *cdns)
308{
309 void __iomem *regs;
310 int ret = 0;
311 u32 state;
312
313 regs = devm_ioremap_resource(cdns->dev, &cdns->otg_res);
314 if (IS_ERR(regs))
315 return PTR_ERR(regs);
316
317 /* Detection of DRD version. Controller has been released
318 * in two versions. Both are similar, but they have same changes
319 * in register maps.
320 * The first register in old version is command register and it's read
321 * only, so driver should read 0 from it. On the other hand, in v1
322 * the first register contains device ID number which is not set to 0.
323 * Driver uses this fact to detect the proper version of
324 * controller.
325 */
326 cdns->otg_v0_regs = regs;
327 if (!readl(&cdns->otg_v0_regs->cmd)) {
328 cdns->version = CDNS3_CONTROLLER_V0;
329 cdns->otg_v1_regs = NULL;
330 cdns->otg_regs = regs;
331 writel(1, &cdns->otg_v0_regs->simulate);
332 dev_info(cdns->dev, "DRD version v0 (%08x)\n",
333 readl(&cdns->otg_v0_regs->version));
334 } else {
335 cdns->otg_v0_regs = NULL;
336 cdns->otg_v1_regs = regs;
337 cdns->otg_regs = (void *)&cdns->otg_v1_regs->cmd;
338 cdns->version = CDNS3_CONTROLLER_V1;
339 writel(1, &cdns->otg_v1_regs->simulate);
340 dev_info(cdns->dev, "DRD version v1 (ID: %08x, rev: %08x)\n",
341 readl(&cdns->otg_v1_regs->did),
342 readl(&cdns->otg_v1_regs->rid));
343 }
344
345 state = OTGSTS_STRAP(readl(&cdns->otg_regs->sts));
346
347 /* Update dr_mode according to STRAP configuration. */
348 cdns->dr_mode = USB_DR_MODE_OTG;
349 if (state == OTGSTS_STRAP_HOST) {
350 dev_dbg(cdns->dev, "Controller strapped to HOST\n");
351 cdns->dr_mode = USB_DR_MODE_HOST;
352 } else if (state == OTGSTS_STRAP_GADGET) {
353 dev_dbg(cdns->dev, "Controller strapped to PERIPHERAL\n");
354 cdns->dr_mode = USB_DR_MODE_PERIPHERAL;
355 }
356
357 ret = devm_request_threaded_irq(cdns->dev, cdns->otg_irq,
358 cdns3_drd_irq,
359 cdns3_drd_thread_irq,
360 IRQF_SHARED,
361 dev_name(cdns->dev), cdns);
362
363 if (ret) {
364 dev_err(cdns->dev, "couldn't get otg_irq\n");
365 return ret;
366 }
367
368 state = readl(&cdns->otg_regs->sts);
369 if (OTGSTS_OTG_NRDY(state) != 0) {
370 dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n");
371 return -ENODEV;
372 }
373
374 return ret;
375}
376
377int cdns3_drd_exit(struct cdns3 *cdns)
378{
379 cdns3_otg_disable_irq(cdns);
380 return 0;
381}
diff --git a/drivers/usb/cdns3/drd.h b/drivers/usb/cdns3/drd.h
new file mode 100644
index 000000000000..04e01c4d2377
--- /dev/null
+++ b/drivers/usb/cdns3/drd.h
@@ -0,0 +1,167 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USB3 DRD header file.
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9#ifndef __LINUX_CDNS3_DRD
10#define __LINUX_CDNS3_DRD
11
12#include <linux/usb/otg.h>
13#include <linux/phy/phy.h>
14#include "core.h"
15
16/* DRD register interface for version v1. */
17struct cdns3_otg_regs {
18 __le32 did;
19 __le32 rid;
20 __le32 capabilities;
21 __le32 reserved1;
22 __le32 cmd;
23 __le32 sts;
24 __le32 state;
25 __le32 reserved2;
26 __le32 ien;
27 __le32 ivect;
28 __le32 refclk;
29 __le32 tmr;
30 __le32 reserved3[4];
31 __le32 simulate;
32 __le32 override;
33 __le32 susp_ctrl;
34 __le32 reserved4;
35 __le32 anasts;
36 __le32 adp_ramp_time;
37 __le32 ctrl1;
38 __le32 ctrl2;
39};
40
41/* DRD register interface for version v0. */
42struct cdns3_otg_legacy_regs {
43 __le32 cmd;
44 __le32 sts;
45 __le32 state;
46 __le32 refclk;
47 __le32 ien;
48 __le32 ivect;
49 __le32 reserved1[3];
50 __le32 tmr;
51 __le32 reserved2[2];
52 __le32 version;
53 __le32 capabilities;
54 __le32 reserved3[2];
55 __le32 simulate;
56 __le32 reserved4[5];
57 __le32 ctrl1;
58};
59
60/*
61 * Common registers interface for both version of DRD.
62 */
63struct cdns3_otg_common_regs {
64 __le32 cmd;
65 __le32 sts;
66 __le32 state;
67 __le32 different1;
68 __le32 ien;
69 __le32 ivect;
70};
71
72/* CDNS_RID - bitmasks */
73#define CDNS_RID(p) ((p) & GENMASK(15, 0))
74
75/* CDNS_VID - bitmasks */
76#define CDNS_DID(p) ((p) & GENMASK(31, 0))
77
78/* OTGCMD - bitmasks */
79/* "Request the bus for Device mode. */
80#define OTGCMD_DEV_BUS_REQ BIT(0)
81/* Request the bus for Host mode */
82#define OTGCMD_HOST_BUS_REQ BIT(1)
83/* Enable OTG mode. */
84#define OTGCMD_OTG_EN BIT(2)
85/* Disable OTG mode */
86#define OTGCMD_OTG_DIS BIT(3)
87/*"Configure OTG as A-Device. */
88#define OTGCMD_A_DEV_EN BIT(4)
89/*"Configure OTG as A-Device. */
90#define OTGCMD_A_DEV_DIS BIT(5)
91/* Drop the bus for Device mod e. */
92#define OTGCMD_DEV_BUS_DROP BIT(8)
93/* Drop the bus for Host mode*/
94#define OTGCMD_HOST_BUS_DROP BIT(9)
95/* Power Down USBSS-DEV. */
96#define OTGCMD_DEV_POWER_OFF BIT(11)
97/* Power Down CDNSXHCI. */
98#define OTGCMD_HOST_POWER_OFF BIT(12)
99
100/* OTGIEN - bitmasks */
101/* ID change interrupt enable */
102#define OTGIEN_ID_CHANGE_INT BIT(0)
103/* Vbusvalid fall detected interrupt enable.*/
104#define OTGIEN_VBUSVALID_RISE_INT BIT(4)
105/* Vbusvalid fall detected interrupt enable */
106#define OTGIEN_VBUSVALID_FALL_INT BIT(5)
107
108/* OTGSTS - bitmasks */
109/*
110 * Current value of the ID pin. It is only valid when idpullup in
111 * OTGCTRL1_TYPE register is set to '1'.
112 */
113#define OTGSTS_ID_VALUE BIT(0)
114/* Current value of the vbus_valid */
115#define OTGSTS_VBUS_VALID BIT(1)
116/* Current value of the b_sess_vld */
117#define OTGSTS_SESSION_VALID BIT(2)
118/*Device mode is active*/
119#define OTGSTS_DEV_ACTIVE BIT(3)
120/* Host mode is active. */
121#define OTGSTS_HOST_ACTIVE BIT(4)
122/* OTG Controller not ready. */
123#define OTGSTS_OTG_NRDY_MASK BIT(11)
124#define OTGSTS_OTG_NRDY(p) ((p) & OTGSTS_OTG_NRDY_MASK)
125/*
126 * Value of the strap pins.
127 * 000 - no default configuration
128 * 010 - Controller initiall configured as Host
129 * 100 - Controller initially configured as Device
130 */
131#define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12)
132#define OTGSTS_STRAP_NO_DEFAULT_CFG 0x00
133#define OTGSTS_STRAP_HOST_OTG 0x01
134#define OTGSTS_STRAP_HOST 0x02
135#define OTGSTS_STRAP_GADGET 0x04
136/* Host mode is turned on. */
137#define OTGSTS_XHCI_READY BIT(26)
138/* "Device mode is turned on .*/
139#define OTGSTS_DEV_READY BIT(27)
140
141/* OTGSTATE- bitmasks */
142#define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0)
143#define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3)
144#define OTGSTATE_HOST_STATE_IDLE 0x0
145#define OTGSTATE_HOST_STATE_VBUS_FALL 0x7
146#define OTGSTATE_HOST_STATE(p) (((p) & OTGSTATE_HOST_STATE_MASK) >> 3)
147
148/* OTGREFCLK - bitmasks */
149#define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31)
150
151/* OVERRIDE - bitmasks */
152#define OVERRIDE_IDPULLUP BIT(0)
153/* Only for CDNS3_CONTROLLER_V0 version */
154#define OVERRIDE_IDPULLUP_V0 BIT(24)
155
156int cdns3_is_host(struct cdns3 *cdns);
157int cdns3_is_device(struct cdns3 *cdns);
158int cdns3_get_id(struct cdns3 *cdns);
159int cdns3_get_vbus(struct cdns3 *cdns);
160int cdns3_drd_init(struct cdns3 *cdns);
161int cdns3_drd_exit(struct cdns3 *cdns);
162int cdns3_drd_update_mode(struct cdns3 *cdns);
163int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on);
164int cdns3_drd_switch_host(struct cdns3 *cdns, int on);
165int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode);
166
167#endif /* __LINUX_CDNS3_DRD */
diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
new file mode 100644
index 000000000000..e94f55d4729c
--- /dev/null
+++ b/drivers/usb/cdns3/ep0.c
@@ -0,0 +1,888 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - gadget side.
4 *
5 * Copyright (C) 2018 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Pawel Jez <pjez@cadence.com>,
9 * Pawel Laszczak <pawell@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12
13#include <linux/usb/composite.h>
14#include <linux/iopoll.h>
15
16#include "gadget.h"
17#include "trace.h"
18
19static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = {
20 .bLength = USB_DT_ENDPOINT_SIZE,
21 .bDescriptorType = USB_DT_ENDPOINT,
22 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
23};
24
25/**
26 * cdns3_ep0_run_transfer - Do transfer on default endpoint hardware
27 * @priv_dev: extended gadget object
28 * @dma_addr: physical address where data is/will be stored
29 * @length: data length
30 * @erdy: set it to 1 when ERDY packet should be sent -
31 * exit from flow control state
32 */
33static void cdns3_ep0_run_transfer(struct cdns3_device *priv_dev,
34 dma_addr_t dma_addr,
35 unsigned int length, int erdy, int zlp)
36{
37 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
38 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
39
40 priv_ep->trb_pool[0].buffer = TRB_BUFFER(dma_addr);
41 priv_ep->trb_pool[0].length = TRB_LEN(length);
42
43 if (zlp) {
44 priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_TYPE(TRB_NORMAL);
45 priv_ep->trb_pool[1].buffer = TRB_BUFFER(dma_addr);
46 priv_ep->trb_pool[1].length = TRB_LEN(0);
47 priv_ep->trb_pool[1].control = TRB_CYCLE | TRB_IOC |
48 TRB_TYPE(TRB_NORMAL);
49 } else {
50 priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_IOC |
51 TRB_TYPE(TRB_NORMAL);
52 priv_ep->trb_pool[1].control = 0;
53 }
54
55 trace_cdns3_prepare_trb(priv_ep, priv_ep->trb_pool);
56
57 cdns3_select_ep(priv_dev, priv_dev->ep0_data_dir);
58
59 writel(EP_STS_TRBERR, &regs->ep_sts);
60 writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), &regs->ep_traddr);
61 trace_cdns3_doorbell_ep0(priv_dev->ep0_data_dir ? "ep0in" : "ep0out",
62 readl(&regs->ep_traddr));
63
64 /* TRB should be prepared before starting transfer. */
65 writel(EP_CMD_DRDY, &regs->ep_cmd);
66
67 /* Resume controller before arming transfer. */
68 __cdns3_gadget_wakeup(priv_dev);
69
70 if (erdy)
71 writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd);
72}
73
74/**
75 * cdns3_ep0_delegate_req - Returns status of handling setup packet
76 * Setup is handled by gadget driver
77 * @priv_dev: extended gadget object
78 * @ctrl_req: pointer to received setup packet
79 *
80 * Returns zero on success or negative value on failure
81 */
82static int cdns3_ep0_delegate_req(struct cdns3_device *priv_dev,
83 struct usb_ctrlrequest *ctrl_req)
84{
85 int ret;
86
87 spin_unlock(&priv_dev->lock);
88 priv_dev->setup_pending = 1;
89 ret = priv_dev->gadget_driver->setup(&priv_dev->gadget, ctrl_req);
90 priv_dev->setup_pending = 0;
91 spin_lock(&priv_dev->lock);
92 return ret;
93}
94
95static void cdns3_prepare_setup_packet(struct cdns3_device *priv_dev)
96{
97 priv_dev->ep0_data_dir = 0;
98 priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
99 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
100 sizeof(struct usb_ctrlrequest), 0, 0);
101}
102
103static void cdns3_ep0_complete_setup(struct cdns3_device *priv_dev,
104 u8 send_stall, u8 send_erdy)
105{
106 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
107 struct usb_request *request;
108
109 request = cdns3_next_request(&priv_ep->pending_req_list);
110 if (request)
111 list_del_init(&request->list);
112
113 if (send_stall) {
114 trace_cdns3_halt(priv_ep, send_stall, 0);
115 /* set_stall on ep0 */
116 cdns3_select_ep(priv_dev, 0x00);
117 writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd);
118 } else {
119 cdns3_prepare_setup_packet(priv_dev);
120 }
121
122 priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
123 writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL,
124 &priv_dev->regs->ep_cmd);
125
126 cdns3_allow_enable_l1(priv_dev, 1);
127}
128
129/**
130 * cdns3_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request
131 * @priv_dev: extended gadget object
132 * @ctrl_req: pointer to received setup packet
133 *
134 * Returns 0 if success, USB_GADGET_DELAYED_STATUS on deferred status stage,
135 * error code on error
136 */
137static int cdns3_req_ep0_set_configuration(struct cdns3_device *priv_dev,
138 struct usb_ctrlrequest *ctrl_req)
139{
140 enum usb_device_state device_state = priv_dev->gadget.state;
141 struct cdns3_endpoint *priv_ep;
142 u32 config = le16_to_cpu(ctrl_req->wValue);
143 int result = 0;
144 int i;
145
146 switch (device_state) {
147 case USB_STATE_ADDRESS:
148 /* Configure non-control EPs */
149 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
150 priv_ep = priv_dev->eps[i];
151 if (!priv_ep)
152 continue;
153
154 if (priv_ep->flags & EP_CLAIMED)
155 cdns3_ep_config(priv_ep);
156 }
157
158 result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
159
160 if (result)
161 return result;
162
163 if (config) {
164 cdns3_set_hw_configuration(priv_dev);
165 } else {
166 cdns3_hw_reset_eps_config(priv_dev);
167 usb_gadget_set_state(&priv_dev->gadget,
168 USB_STATE_ADDRESS);
169 }
170 break;
171 case USB_STATE_CONFIGURED:
172 result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
173
174 if (!config && !result) {
175 cdns3_hw_reset_eps_config(priv_dev);
176 usb_gadget_set_state(&priv_dev->gadget,
177 USB_STATE_ADDRESS);
178 }
179 break;
180 default:
181 result = -EINVAL;
182 }
183
184 return result;
185}
186
187/**
188 * cdns3_req_ep0_set_address - Handling of SET_ADDRESS standard USB request
189 * @priv_dev: extended gadget object
190 * @ctrl_req: pointer to received setup packet
191 *
192 * Returns 0 if success, error code on error
193 */
194static int cdns3_req_ep0_set_address(struct cdns3_device *priv_dev,
195 struct usb_ctrlrequest *ctrl_req)
196{
197 enum usb_device_state device_state = priv_dev->gadget.state;
198 u32 reg;
199 u32 addr;
200
201 addr = le16_to_cpu(ctrl_req->wValue);
202
203 if (addr > USB_DEVICE_MAX_ADDRESS) {
204 dev_err(priv_dev->dev,
205 "Device address (%d) cannot be greater than %d\n",
206 addr, USB_DEVICE_MAX_ADDRESS);
207 return -EINVAL;
208 }
209
210 if (device_state == USB_STATE_CONFIGURED) {
211 dev_err(priv_dev->dev,
212 "can't set_address from configured state\n");
213 return -EINVAL;
214 }
215
216 reg = readl(&priv_dev->regs->usb_cmd);
217
218 writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR,
219 &priv_dev->regs->usb_cmd);
220
221 usb_gadget_set_state(&priv_dev->gadget,
222 (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT));
223
224 return 0;
225}
226
227/**
228 * cdns3_req_ep0_get_status - Handling of GET_STATUS standard USB request
229 * @priv_dev: extended gadget object
230 * @ctrl_req: pointer to received setup packet
231 *
232 * Returns 0 if success, error code on error
233 */
234static int cdns3_req_ep0_get_status(struct cdns3_device *priv_dev,
235 struct usb_ctrlrequest *ctrl)
236{
237 __le16 *response_pkt;
238 u16 usb_status = 0;
239 u32 recip;
240
241 recip = ctrl->bRequestType & USB_RECIP_MASK;
242
243 switch (recip) {
244 case USB_RECIP_DEVICE:
245 /* self powered */
246 if (priv_dev->is_selfpowered)
247 usb_status = BIT(USB_DEVICE_SELF_POWERED);
248
249 if (priv_dev->wake_up_flag)
250 usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP);
251
252 if (priv_dev->gadget.speed != USB_SPEED_SUPER)
253 break;
254
255 if (priv_dev->u1_allowed)
256 usb_status |= BIT(USB_DEV_STAT_U1_ENABLED);
257
258 if (priv_dev->u2_allowed)
259 usb_status |= BIT(USB_DEV_STAT_U2_ENABLED);
260
261 break;
262 case USB_RECIP_INTERFACE:
263 return cdns3_ep0_delegate_req(priv_dev, ctrl);
264 case USB_RECIP_ENDPOINT:
265 /* check if endpoint is stalled */
266 cdns3_select_ep(priv_dev, ctrl->wIndex);
267 if (EP_STS_STALL(readl(&priv_dev->regs->ep_sts)))
268 usb_status = BIT(USB_ENDPOINT_HALT);
269 break;
270 default:
271 return -EINVAL;
272 }
273
274 response_pkt = (__le16 *)priv_dev->setup_buf;
275 *response_pkt = cpu_to_le16(usb_status);
276
277 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
278 sizeof(*response_pkt), 1, 0);
279 return 0;
280}
281
282static int cdns3_ep0_feature_handle_device(struct cdns3_device *priv_dev,
283 struct usb_ctrlrequest *ctrl,
284 int set)
285{
286 enum usb_device_state state;
287 enum usb_device_speed speed;
288 int ret = 0;
289 u32 wValue;
290 u32 wIndex;
291 u16 tmode;
292
293 wValue = le16_to_cpu(ctrl->wValue);
294 wIndex = le16_to_cpu(ctrl->wIndex);
295 state = priv_dev->gadget.state;
296 speed = priv_dev->gadget.speed;
297
298 switch (ctrl->wValue) {
299 case USB_DEVICE_REMOTE_WAKEUP:
300 priv_dev->wake_up_flag = !!set;
301 break;
302 case USB_DEVICE_U1_ENABLE:
303 if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
304 return -EINVAL;
305
306 priv_dev->u1_allowed = !!set;
307 break;
308 case USB_DEVICE_U2_ENABLE:
309 if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
310 return -EINVAL;
311
312 priv_dev->u2_allowed = !!set;
313 break;
314 case USB_DEVICE_LTM_ENABLE:
315 ret = -EINVAL;
316 break;
317 case USB_DEVICE_TEST_MODE:
318 if (state != USB_STATE_CONFIGURED || speed > USB_SPEED_HIGH)
319 return -EINVAL;
320
321 tmode = le16_to_cpu(ctrl->wIndex);
322
323 if (!set || (tmode & 0xff) != 0)
324 return -EINVAL;
325
326 switch (tmode >> 8) {
327 case TEST_J:
328 case TEST_K:
329 case TEST_SE0_NAK:
330 case TEST_PACKET:
331 cdns3_ep0_complete_setup(priv_dev, 0, 1);
332 /**
333 * Little delay to give the controller some time
334 * for sending status stage.
335 * This time should be less then 3ms.
336 */
337 usleep_range(1000, 2000);
338 cdns3_set_register_bit(&priv_dev->regs->usb_cmd,
339 USB_CMD_STMODE |
340 USB_STS_TMODE_SEL(tmode - 1));
341 break;
342 default:
343 ret = -EINVAL;
344 }
345 break;
346 default:
347 ret = -EINVAL;
348 }
349
350 return ret;
351}
352
353static int cdns3_ep0_feature_handle_intf(struct cdns3_device *priv_dev,
354 struct usb_ctrlrequest *ctrl,
355 int set)
356{
357 u32 wValue;
358 int ret = 0;
359
360 wValue = le16_to_cpu(ctrl->wValue);
361
362 switch (wValue) {
363 case USB_INTRF_FUNC_SUSPEND:
364 break;
365 default:
366 ret = -EINVAL;
367 }
368
369 return ret;
370}
371
372static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
373 struct usb_ctrlrequest *ctrl,
374 int set)
375{
376 struct cdns3_endpoint *priv_ep;
377 int ret = 0;
378 u8 index;
379
380 if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT)
381 return -EINVAL;
382
383 if (!(ctrl->wIndex & ~USB_DIR_IN))
384 return 0;
385
386 index = cdns3_ep_addr_to_index(ctrl->wIndex);
387 priv_ep = priv_dev->eps[index];
388
389 cdns3_select_ep(priv_dev, ctrl->wIndex);
390
391 if (set)
392 __cdns3_gadget_ep_set_halt(priv_ep);
393 else if (!(priv_ep->flags & EP_WEDGE))
394 ret = __cdns3_gadget_ep_clear_halt(priv_ep);
395
396 cdns3_select_ep(priv_dev, 0x00);
397
398 return ret;
399}
400
401/**
402 * cdns3_req_ep0_handle_feature -
403 * Handling of GET/SET_FEATURE standard USB request
404 *
405 * @priv_dev: extended gadget object
406 * @ctrl_req: pointer to received setup packet
407 * @set: must be set to 1 for SET_FEATURE request
408 *
409 * Returns 0 if success, error code on error
410 */
411static int cdns3_req_ep0_handle_feature(struct cdns3_device *priv_dev,
412 struct usb_ctrlrequest *ctrl,
413 int set)
414{
415 int ret = 0;
416 u32 recip;
417
418 recip = ctrl->bRequestType & USB_RECIP_MASK;
419
420 switch (recip) {
421 case USB_RECIP_DEVICE:
422 ret = cdns3_ep0_feature_handle_device(priv_dev, ctrl, set);
423 break;
424 case USB_RECIP_INTERFACE:
425 ret = cdns3_ep0_feature_handle_intf(priv_dev, ctrl, set);
426 break;
427 case USB_RECIP_ENDPOINT:
428 ret = cdns3_ep0_feature_handle_endpoint(priv_dev, ctrl, set);
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 return ret;
435}
436
437/**
438 * cdns3_req_ep0_set_sel - Handling of SET_SEL standard USB request
439 * @priv_dev: extended gadget object
440 * @ctrl_req: pointer to received setup packet
441 *
442 * Returns 0 if success, error code on error
443 */
444static int cdns3_req_ep0_set_sel(struct cdns3_device *priv_dev,
445 struct usb_ctrlrequest *ctrl_req)
446{
447 if (priv_dev->gadget.state < USB_STATE_ADDRESS)
448 return -EINVAL;
449
450 if (ctrl_req->wLength != 6) {
451 dev_err(priv_dev->dev, "Set SEL should be 6 bytes, got %d\n",
452 ctrl_req->wLength);
453 return -EINVAL;
454 }
455
456 cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 6, 1, 0);
457 return 0;
458}
459
460/**
461 * cdns3_req_ep0_set_isoch_delay -
462 * Handling of GET_ISOCH_DELAY standard USB request
463 * @priv_dev: extended gadget object
464 * @ctrl_req: pointer to received setup packet
465 *
466 * Returns 0 if success, error code on error
467 */
468static int cdns3_req_ep0_set_isoch_delay(struct cdns3_device *priv_dev,
469 struct usb_ctrlrequest *ctrl_req)
470{
471 if (ctrl_req->wIndex || ctrl_req->wLength)
472 return -EINVAL;
473
474 priv_dev->isoch_delay = ctrl_req->wValue;
475
476 return 0;
477}
478
479/**
480 * cdns3_ep0_standard_request - Handling standard USB requests
481 * @priv_dev: extended gadget object
482 * @ctrl_req: pointer to received setup packet
483 *
484 * Returns 0 if success, error code on error
485 */
486static int cdns3_ep0_standard_request(struct cdns3_device *priv_dev,
487 struct usb_ctrlrequest *ctrl_req)
488{
489 int ret;
490
491 switch (ctrl_req->bRequest) {
492 case USB_REQ_SET_ADDRESS:
493 ret = cdns3_req_ep0_set_address(priv_dev, ctrl_req);
494 break;
495 case USB_REQ_SET_CONFIGURATION:
496 ret = cdns3_req_ep0_set_configuration(priv_dev, ctrl_req);
497 break;
498 case USB_REQ_GET_STATUS:
499 ret = cdns3_req_ep0_get_status(priv_dev, ctrl_req);
500 break;
501 case USB_REQ_CLEAR_FEATURE:
502 ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 0);
503 break;
504 case USB_REQ_SET_FEATURE:
505 ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 1);
506 break;
507 case USB_REQ_SET_SEL:
508 ret = cdns3_req_ep0_set_sel(priv_dev, ctrl_req);
509 break;
510 case USB_REQ_SET_ISOCH_DELAY:
511 ret = cdns3_req_ep0_set_isoch_delay(priv_dev, ctrl_req);
512 break;
513 default:
514 ret = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
515 break;
516 }
517
518 return ret;
519}
520
521static void __pending_setup_status_handler(struct cdns3_device *priv_dev)
522{
523 struct usb_request *request = priv_dev->pending_status_request;
524
525 if (priv_dev->status_completion_no_call && request &&
526 request->complete) {
527 request->complete(&priv_dev->eps[0]->endpoint, request);
528 priv_dev->status_completion_no_call = 0;
529 }
530}
531
532void cdns3_pending_setup_status_handler(struct work_struct *work)
533{
534 struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
535 pending_status_wq);
536 unsigned long flags;
537
538 spin_lock_irqsave(&priv_dev->lock, flags);
539 __pending_setup_status_handler(priv_dev);
540 spin_unlock_irqrestore(&priv_dev->lock, flags);
541}
542
543/**
544 * cdns3_ep0_setup_phase - Handling setup USB requests
545 * @priv_dev: extended gadget object
546 */
547static void cdns3_ep0_setup_phase(struct cdns3_device *priv_dev)
548{
549 struct usb_ctrlrequest *ctrl = priv_dev->setup_buf;
550 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
551 int result;
552
553 priv_dev->ep0_data_dir = ctrl->bRequestType & USB_DIR_IN;
554
555 trace_cdns3_ctrl_req(ctrl);
556
557 if (!list_empty(&priv_ep->pending_req_list)) {
558 struct usb_request *request;
559
560 request = cdns3_next_request(&priv_ep->pending_req_list);
561 priv_ep->dir = priv_dev->ep0_data_dir;
562 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
563 -ECONNRESET);
564 }
565
566 if (le16_to_cpu(ctrl->wLength))
567 priv_dev->ep0_stage = CDNS3_DATA_STAGE;
568 else
569 priv_dev->ep0_stage = CDNS3_STATUS_STAGE;
570
571 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
572 result = cdns3_ep0_standard_request(priv_dev, ctrl);
573 else
574 result = cdns3_ep0_delegate_req(priv_dev, ctrl);
575
576 if (result == USB_GADGET_DELAYED_STATUS)
577 return;
578
579 if (result < 0)
580 cdns3_ep0_complete_setup(priv_dev, 1, 1);
581 else if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE)
582 cdns3_ep0_complete_setup(priv_dev, 0, 1);
583}
584
585static void cdns3_transfer_completed(struct cdns3_device *priv_dev)
586{
587 struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
588
589 if (!list_empty(&priv_ep->pending_req_list)) {
590 struct usb_request *request;
591
592 trace_cdns3_complete_trb(priv_ep, priv_ep->trb_pool);
593 request = cdns3_next_request(&priv_ep->pending_req_list);
594
595 request->actual =
596 TRB_LEN(le32_to_cpu(priv_ep->trb_pool->length));
597
598 priv_ep->dir = priv_dev->ep0_data_dir;
599 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 0);
600 }
601
602 cdns3_ep0_complete_setup(priv_dev, 0, 0);
603}
604
605/**
606 * cdns3_check_new_setup - Check if controller receive new SETUP packet.
607 * @priv_dev: extended gadget object
608 *
609 * The SETUP packet can be kept in on-chip memory or in system memory.
610 */
611static bool cdns3_check_new_setup(struct cdns3_device *priv_dev)
612{
613 u32 ep_sts_reg;
614
615 cdns3_select_ep(priv_dev, 0 | USB_DIR_OUT);
616 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
617
618 return !!(ep_sts_reg & (EP_STS_SETUP | EP_STS_STPWAIT));
619}
620
621/**
622 * cdns3_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0
623 * @priv_dev: extended gadget object
624 * @dir: USB_DIR_IN for IN direction, USB_DIR_OUT for OUT direction
625 */
626void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir)
627{
628 u32 ep_sts_reg;
629
630 cdns3_select_ep(priv_dev, dir);
631
632 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
633 writel(ep_sts_reg, &priv_dev->regs->ep_sts);
634
635 trace_cdns3_ep0_irq(priv_dev, ep_sts_reg);
636
637 __pending_setup_status_handler(priv_dev);
638
639 if (ep_sts_reg & EP_STS_SETUP)
640 priv_dev->wait_for_setup = 1;
641
642 if (priv_dev->wait_for_setup && ep_sts_reg & EP_STS_IOC) {
643 priv_dev->wait_for_setup = 0;
644 cdns3_allow_enable_l1(priv_dev, 0);
645 cdns3_ep0_setup_phase(priv_dev);
646 } else if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
647 priv_dev->ep0_data_dir = dir;
648 cdns3_transfer_completed(priv_dev);
649 }
650
651 if (ep_sts_reg & EP_STS_DESCMIS) {
652 if (dir == 0 && !priv_dev->setup_pending)
653 cdns3_prepare_setup_packet(priv_dev);
654 }
655}
656
657/**
658 * cdns3_gadget_ep0_enable
659 * Function shouldn't be called by gadget driver,
660 * endpoint 0 is allways active
661 */
662static int cdns3_gadget_ep0_enable(struct usb_ep *ep,
663 const struct usb_endpoint_descriptor *desc)
664{
665 return -EINVAL;
666}
667
668/**
669 * cdns3_gadget_ep0_disable
670 * Function shouldn't be called by gadget driver,
671 * endpoint 0 is allways active
672 */
673static int cdns3_gadget_ep0_disable(struct usb_ep *ep)
674{
675 return -EINVAL;
676}
677
678/**
679 * cdns3_gadget_ep0_set_halt
680 * @ep: pointer to endpoint zero object
681 * @value: 1 for set stall, 0 for clear stall
682 *
683 * Returns 0
684 */
685static int cdns3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
686{
687 /* TODO */
688 return 0;
689}
690
691/**
692 * cdns3_gadget_ep0_queue Transfer data on endpoint zero
693 * @ep: pointer to endpoint zero object
694 * @request: pointer to request object
695 * @gfp_flags: gfp flags
696 *
697 * Returns 0 on success, error code elsewhere
698 */
699static int cdns3_gadget_ep0_queue(struct usb_ep *ep,
700 struct usb_request *request,
701 gfp_t gfp_flags)
702{
703 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
704 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
705 unsigned long flags;
706 int erdy_sent = 0;
707 int ret = 0;
708 u8 zlp = 0;
709
710 trace_cdns3_ep0_queue(priv_dev, request);
711
712 /* cancel the request if controller receive new SETUP packet. */
713 if (cdns3_check_new_setup(priv_dev))
714 return -ECONNRESET;
715
716 /* send STATUS stage. Should be called only for SET_CONFIGURATION */
717 if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) {
718 spin_lock_irqsave(&priv_dev->lock, flags);
719 cdns3_select_ep(priv_dev, 0x00);
720
721 erdy_sent = !priv_dev->hw_configured_flag;
722 cdns3_set_hw_configuration(priv_dev);
723
724 if (!erdy_sent)
725 cdns3_ep0_complete_setup(priv_dev, 0, 1);
726
727 cdns3_allow_enable_l1(priv_dev, 1);
728
729 request->actual = 0;
730 priv_dev->status_completion_no_call = true;
731 priv_dev->pending_status_request = request;
732 spin_unlock_irqrestore(&priv_dev->lock, flags);
733
734 /*
735 * Since there is no completion interrupt for status stage,
736 * it needs to call ->completion in software after
737 * ep0_queue is back.
738 */
739 queue_work(system_freezable_wq, &priv_dev->pending_status_wq);
740 return 0;
741 }
742
743 spin_lock_irqsave(&priv_dev->lock, flags);
744 if (!list_empty(&priv_ep->pending_req_list)) {
745 dev_err(priv_dev->dev,
746 "can't handle multiple requests for ep0\n");
747 spin_unlock_irqrestore(&priv_dev->lock, flags);
748 return -EBUSY;
749 }
750
751 ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request,
752 priv_dev->ep0_data_dir);
753 if (ret) {
754 spin_unlock_irqrestore(&priv_dev->lock, flags);
755 dev_err(priv_dev->dev, "failed to map request\n");
756 return -EINVAL;
757 }
758
759 request->status = -EINPROGRESS;
760 list_add_tail(&request->list, &priv_ep->pending_req_list);
761
762 if (request->zero && request->length &&
763 (request->length % ep->maxpacket == 0))
764 zlp = 1;
765
766 cdns3_ep0_run_transfer(priv_dev, request->dma, request->length, 1, zlp);
767
768 spin_unlock_irqrestore(&priv_dev->lock, flags);
769
770 return ret;
771}
772
773/**
774 * cdns3_gadget_ep_set_wedge Set wedge on selected endpoint
775 * @ep: endpoint object
776 *
777 * Returns 0
778 */
779int cdns3_gadget_ep_set_wedge(struct usb_ep *ep)
780{
781 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
782 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
783
784 dev_dbg(priv_dev->dev, "Wedge for %s\n", ep->name);
785 cdns3_gadget_ep_set_halt(ep, 1);
786 priv_ep->flags |= EP_WEDGE;
787
788 return 0;
789}
790
791const struct usb_ep_ops cdns3_gadget_ep0_ops = {
792 .enable = cdns3_gadget_ep0_enable,
793 .disable = cdns3_gadget_ep0_disable,
794 .alloc_request = cdns3_gadget_ep_alloc_request,
795 .free_request = cdns3_gadget_ep_free_request,
796 .queue = cdns3_gadget_ep0_queue,
797 .dequeue = cdns3_gadget_ep_dequeue,
798 .set_halt = cdns3_gadget_ep0_set_halt,
799 .set_wedge = cdns3_gadget_ep_set_wedge,
800};
801
802/**
803 * cdns3_ep0_config - Configures default endpoint
804 * @priv_dev: extended gadget object
805 *
806 * Functions sets parameters: maximal packet size and enables interrupts
807 */
808void cdns3_ep0_config(struct cdns3_device *priv_dev)
809{
810 struct cdns3_usb_regs __iomem *regs;
811 struct cdns3_endpoint *priv_ep;
812 u32 max_packet_size = 64;
813
814 regs = priv_dev->regs;
815
816 if (priv_dev->gadget.speed == USB_SPEED_SUPER)
817 max_packet_size = 512;
818
819 priv_ep = priv_dev->eps[0];
820
821 if (!list_empty(&priv_ep->pending_req_list)) {
822 struct usb_request *request;
823
824 request = cdns3_next_request(&priv_ep->pending_req_list);
825 list_del_init(&request->list);
826 }
827
828 priv_dev->u1_allowed = 0;
829 priv_dev->u2_allowed = 0;
830
831 priv_dev->gadget.ep0->maxpacket = max_packet_size;
832 cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(max_packet_size);
833
834 /* init ep out */
835 cdns3_select_ep(priv_dev, USB_DIR_OUT);
836
837 if (priv_dev->dev_ver >= DEV_VER_V3) {
838 cdns3_set_register_bit(&priv_dev->regs->dtrans,
839 BIT(0) | BIT(16));
840 cdns3_set_register_bit(&priv_dev->regs->tdl_from_trb,
841 BIT(0) | BIT(16));
842 }
843
844 writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
845 &regs->ep_cfg);
846
847 writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN,
848 &regs->ep_sts_en);
849
850 /* init ep in */
851 cdns3_select_ep(priv_dev, USB_DIR_IN);
852
853 writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
854 &regs->ep_cfg);
855
856 writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, &regs->ep_sts_en);
857
858 cdns3_set_register_bit(&regs->usb_conf, USB_CONF_U1DS | USB_CONF_U2DS);
859}
860
861/**
862 * cdns3_init_ep0 Initializes software endpoint 0 of gadget
863 * @priv_dev: extended gadget object
864 * @ep_priv: extended endpoint object
865 *
866 * Returns 0 on success else error code.
867 */
868int cdns3_init_ep0(struct cdns3_device *priv_dev,
869 struct cdns3_endpoint *priv_ep)
870{
871 sprintf(priv_ep->name, "ep0");
872
873 /* fill linux fields */
874 priv_ep->endpoint.ops = &cdns3_gadget_ep0_ops;
875 priv_ep->endpoint.maxburst = 1;
876 usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
877 CDNS3_EP0_MAX_PACKET_LIMIT);
878 priv_ep->endpoint.address = 0;
879 priv_ep->endpoint.caps.type_control = 1;
880 priv_ep->endpoint.caps.dir_in = 1;
881 priv_ep->endpoint.caps.dir_out = 1;
882 priv_ep->endpoint.name = priv_ep->name;
883 priv_ep->endpoint.desc = &cdns3_gadget_ep0_desc;
884 priv_dev->gadget.ep0 = &priv_ep->endpoint;
885 priv_ep->type = USB_ENDPOINT_XFER_CONTROL;
886
887 return cdns3_allocate_trb_pool(priv_ep);
888}
diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h
new file mode 100644
index 000000000000..577469eee961
--- /dev/null
+++ b/drivers/usb/cdns3/gadget-export.h
@@ -0,0 +1,28 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver - Gadget Export APIs.
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 */
10#ifndef __LINUX_CDNS3_GADGET_EXPORT
11#define __LINUX_CDNS3_GADGET_EXPORT
12
13#ifdef CONFIG_USB_CDNS3_GADGET
14
15int cdns3_gadget_init(struct cdns3 *cdns);
16void cdns3_gadget_exit(struct cdns3 *cdns);
17#else
18
19static inline int cdns3_gadget_init(struct cdns3 *cdns)
20{
21 return -ENXIO;
22}
23
24static inline void cdns3_gadget_exit(struct cdns3 *cdns) { }
25
26#endif
27
28#endif /* __LINUX_CDNS3_GADGET_EXPORT */
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
new file mode 100644
index 000000000000..49ba253d81be
--- /dev/null
+++ b/drivers/usb/cdns3/gadget.c
@@ -0,0 +1,2416 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - gadget side.
4 *
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Pawel Jez <pjez@cadence.com>,
9 * Pawel Laszczak <pawell@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12
13/*
14 * Work around 1:
15 * At some situations, the controller may get stale data address in TRB
16 * at below sequences:
17 * 1. Controller read TRB includes data address
18 * 2. Software updates TRBs includes data address and Cycle bit
19 * 3. Controller read TRB which includes Cycle bit
20 * 4. DMA run with stale data address
21 *
22 * To fix this problem, driver needs to make the first TRB in TD as invalid.
23 * After preparing all TRBs driver needs to check the position of DMA and
24 * if the DMA point to the first just added TRB and doorbell is 1,
25 * then driver must defer making this TRB as valid. This TRB will be make
26 * as valid during adding next TRB only if DMA is stopped or at TRBERR
27 * interrupt.
28 *
29 * Issue has been fixed in DEV_VER_V3 version of controller.
30 *
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/usb/gadget.h>
35#include <linux/module.h>
36#include <linux/iopoll.h>
37
38#include "core.h"
39#include "gadget-export.h"
40#include "gadget.h"
41#include "trace.h"
42#include "drd.h"
43
44static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
45 struct usb_request *request,
46 gfp_t gfp_flags);
47
48/**
49 * cdns3_set_register_bit - set bit in given register.
50 * @ptr: address of device controller register to be read and changed
51 * @mask: bits requested to set
52 */
53void cdns3_set_register_bit(void __iomem *ptr, u32 mask)
54{
55 mask = readl(ptr) | mask;
56 writel(mask, ptr);
57}
58
59/**
60 * cdns3_ep_addr_to_index - Macro converts endpoint address to
61 * index of endpoint object in cdns3_device.eps[] container
62 * @ep_addr: endpoint address for which endpoint object is required
63 *
64 */
65u8 cdns3_ep_addr_to_index(u8 ep_addr)
66{
67 return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0));
68}
69
70static int cdns3_get_dma_pos(struct cdns3_device *priv_dev,
71 struct cdns3_endpoint *priv_ep)
72{
73 int dma_index;
74
75 dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma;
76
77 return dma_index / TRB_SIZE;
78}
79
80/**
81 * cdns3_next_request - returns next request from list
82 * @list: list containing requests
83 *
84 * Returns request or NULL if no requests in list
85 */
86struct usb_request *cdns3_next_request(struct list_head *list)
87{
88 return list_first_entry_or_null(list, struct usb_request, list);
89}
90
91/**
92 * cdns3_next_align_buf - returns next buffer from list
93 * @list: list containing buffers
94 *
95 * Returns buffer or NULL if no buffers in list
96 */
97struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list)
98{
99 return list_first_entry_or_null(list, struct cdns3_aligned_buf, list);
100}
101
102/**
103 * select_ep - selects endpoint
104 * @priv_dev: extended gadget object
105 * @ep: endpoint address
106 */
107void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep)
108{
109 if (priv_dev->selected_ep == ep)
110 return;
111
112 priv_dev->selected_ep = ep;
113 writel(ep, &priv_dev->regs->ep_sel);
114}
115
116dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
117 struct cdns3_trb *trb)
118{
119 u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
120
121 return priv_ep->trb_pool_dma + offset;
122}
123
124int cdns3_ring_size(struct cdns3_endpoint *priv_ep)
125{
126 switch (priv_ep->type) {
127 case USB_ENDPOINT_XFER_ISOC:
128 return TRB_ISO_RING_SIZE;
129 case USB_ENDPOINT_XFER_CONTROL:
130 return TRB_CTRL_RING_SIZE;
131 default:
132 return TRB_RING_SIZE;
133 }
134}
135
136/**
137 * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint
138 * @priv_ep: endpoint object
139 *
140 * Function will return 0 on success or -ENOMEM on allocation error
141 */
142int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep)
143{
144 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
145 int ring_size = cdns3_ring_size(priv_ep);
146 struct cdns3_trb *link_trb;
147
148 if (!priv_ep->trb_pool) {
149 priv_ep->trb_pool = dma_alloc_coherent(priv_dev->sysdev,
150 ring_size,
151 &priv_ep->trb_pool_dma,
152 GFP_DMA32 | GFP_ATOMIC);
153 if (!priv_ep->trb_pool)
154 return -ENOMEM;
155 } else {
156 memset(priv_ep->trb_pool, 0, ring_size);
157 }
158
159 if (!priv_ep->num)
160 return 0;
161
162 priv_ep->num_trbs = ring_size / TRB_SIZE;
163 /* Initialize the last TRB as Link TRB. */
164 link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1));
165 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma);
166 link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE;
167
168 return 0;
169}
170
171static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep)
172{
173 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
174
175 if (priv_ep->trb_pool) {
176 dma_free_coherent(priv_dev->sysdev,
177 cdns3_ring_size(priv_ep),
178 priv_ep->trb_pool, priv_ep->trb_pool_dma);
179 priv_ep->trb_pool = NULL;
180 }
181}
182
183/**
184 * cdns3_ep_stall_flush - Stalls and flushes selected endpoint
185 * @priv_ep: endpoint object
186 *
187 * Endpoint must be selected before call to this function
188 */
189static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep)
190{
191 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
192 int val;
193
194 trace_cdns3_halt(priv_ep, 1, 1);
195
196 writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
197 &priv_dev->regs->ep_cmd);
198
199 /* wait for DFLUSH cleared */
200 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
201 !(val & EP_CMD_DFLUSH), 1, 1000);
202 priv_ep->flags |= EP_STALLED;
203 priv_ep->flags &= ~EP_STALL_PENDING;
204}
205
206/**
207 * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller.
208 * @priv_dev: extended gadget object
209 */
210void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev)
211{
212 writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
213
214 cdns3_allow_enable_l1(priv_dev, 0);
215 priv_dev->hw_configured_flag = 0;
216 priv_dev->onchip_used_size = 0;
217 priv_dev->out_mem_is_allocated = 0;
218 priv_dev->wait_for_setup = 0;
219}
220
221/**
222 * cdns3_ep_inc_trb - increment a trb index.
223 * @index: Pointer to the TRB index to increment.
224 * @cs: Cycle state
225 * @trb_in_seg: number of TRBs in segment
226 *
227 * The index should never point to the link TRB. After incrementing,
228 * if it is point to the link TRB, wrap around to the beginning and revert
229 * cycle state bit The
230 * link TRB is always at the last TRB entry.
231 */
232static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg)
233{
234 (*index)++;
235 if (*index == (trb_in_seg - 1)) {
236 *index = 0;
237 *cs ^= 1;
238 }
239}
240
241/**
242 * cdns3_ep_inc_enq - increment endpoint's enqueue pointer
243 * @priv_ep: The endpoint whose enqueue pointer we're incrementing
244 */
245static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep)
246{
247 priv_ep->free_trbs--;
248 cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs);
249}
250
251/**
252 * cdns3_ep_inc_deq - increment endpoint's dequeue pointer
253 * @priv_ep: The endpoint whose dequeue pointer we're incrementing
254 */
255static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep)
256{
257 priv_ep->free_trbs++;
258 cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs);
259}
260
261void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req)
262{
263 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
264 int current_trb = priv_req->start_trb;
265
266 while (current_trb != priv_req->end_trb) {
267 cdns3_ep_inc_deq(priv_ep);
268 current_trb = priv_ep->dequeue;
269 }
270
271 cdns3_ep_inc_deq(priv_ep);
272}
273
274/**
275 * cdns3_allow_enable_l1 - enable/disable permits to transition to L1.
276 * @priv_dev: Extended gadget object
277 * @enable: Enable/disable permit to transition to L1.
278 *
279 * If bit USB_CONF_L1EN is set and device receive Extended Token packet,
280 * then controller answer with ACK handshake.
281 * If bit USB_CONF_L1DS is set and device receive Extended Token packet,
282 * then controller answer with NYET handshake.
283 */
284void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable)
285{
286 if (enable)
287 writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
288 else
289 writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
290}
291
292enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev)
293{
294 u32 reg;
295
296 reg = readl(&priv_dev->regs->usb_sts);
297
298 if (DEV_SUPERSPEED(reg))
299 return USB_SPEED_SUPER;
300 else if (DEV_HIGHSPEED(reg))
301 return USB_SPEED_HIGH;
302 else if (DEV_FULLSPEED(reg))
303 return USB_SPEED_FULL;
304 else if (DEV_LOWSPEED(reg))
305 return USB_SPEED_LOW;
306 return USB_SPEED_UNKNOWN;
307}
308
309/**
310 * cdns3_start_all_request - add to ring all request not started
311 * @priv_dev: Extended gadget object
312 * @priv_ep: The endpoint for whom request will be started.
313 *
314 * Returns return ENOMEM if transfer ring i not enough TRBs to start
315 * all requests.
316 */
317static int cdns3_start_all_request(struct cdns3_device *priv_dev,
318 struct cdns3_endpoint *priv_ep)
319{
320 struct cdns3_request *priv_req;
321 struct usb_request *request;
322 int ret = 0;
323
324 while (!list_empty(&priv_ep->deferred_req_list)) {
325 request = cdns3_next_request(&priv_ep->deferred_req_list);
326 priv_req = to_cdns3_request(request);
327
328 ret = cdns3_ep_run_transfer(priv_ep, request);
329 if (ret)
330 return ret;
331
332 list_del(&request->list);
333 list_add_tail(&request->list,
334 &priv_ep->pending_req_list);
335 }
336
337 priv_ep->flags &= ~EP_RING_FULL;
338 return ret;
339}
340
341/**
342 * cdns3_gadget_giveback - call struct usb_request's ->complete callback
343 * @priv_ep: The endpoint to whom the request belongs to
344 * @priv_req: The request we're giving back
345 * @status: completion code for the request
346 *
347 * Must be called with controller's lock held and interrupts disabled. This
348 * function will unmap @req and call its ->complete() callback to notify upper
349 * layers that it has completed.
350 */
351void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
352 struct cdns3_request *priv_req,
353 int status)
354{
355 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
356 struct usb_request *request = &priv_req->request;
357
358 list_del_init(&request->list);
359
360 if (request->status == -EINPROGRESS)
361 request->status = status;
362
363 usb_gadget_unmap_request_by_dev(priv_dev->sysdev, request,
364 priv_ep->dir);
365
366 if ((priv_req->flags & REQUEST_UNALIGNED) &&
367 priv_ep->dir == USB_DIR_OUT && !request->status)
368 memcpy(request->buf, priv_req->aligned_buf->buf,
369 request->length);
370
371 priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED);
372 trace_cdns3_gadget_giveback(priv_req);
373
374 if (request->complete) {
375 spin_unlock(&priv_dev->lock);
376 usb_gadget_giveback_request(&priv_ep->endpoint,
377 request);
378 spin_lock(&priv_dev->lock);
379 }
380
381 if (request->buf == priv_dev->zlp_buf)
382 cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
383}
384
385void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep)
386{
387 /* Work around for stale data address in TRB*/
388 if (priv_ep->wa1_set) {
389 trace_cdns3_wa1(priv_ep, "restore cycle bit");
390
391 priv_ep->wa1_set = 0;
392 priv_ep->wa1_trb_index = 0xFFFF;
393 if (priv_ep->wa1_cycle_bit) {
394 priv_ep->wa1_trb->control =
395 priv_ep->wa1_trb->control | 0x1;
396 } else {
397 priv_ep->wa1_trb->control =
398 priv_ep->wa1_trb->control & ~0x1;
399 }
400 }
401}
402
403static void cdns3_free_aligned_request_buf(struct work_struct *work)
404{
405 struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
406 aligned_buf_wq);
407 struct cdns3_aligned_buf *buf, *tmp;
408 unsigned long flags;
409
410 spin_lock_irqsave(&priv_dev->lock, flags);
411
412 list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) {
413 if (!buf->in_use) {
414 list_del(&buf->list);
415
416 /*
417 * Re-enable interrupts to free DMA capable memory.
418 * Driver can't free this memory with disabled
419 * interrupts.
420 */
421 spin_unlock_irqrestore(&priv_dev->lock, flags);
422 dma_free_coherent(priv_dev->sysdev, buf->size,
423 buf->buf, buf->dma);
424 kfree(buf);
425 spin_lock_irqsave(&priv_dev->lock, flags);
426 }
427 }
428
429 spin_unlock_irqrestore(&priv_dev->lock, flags);
430}
431
432static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req)
433{
434 struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
435 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
436 struct cdns3_aligned_buf *buf;
437
438 /* check if buffer is aligned to 8. */
439 if (!((uintptr_t)priv_req->request.buf & 0x7))
440 return 0;
441
442 buf = priv_req->aligned_buf;
443
444 if (!buf || priv_req->request.length > buf->size) {
445 buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
446 if (!buf)
447 return -ENOMEM;
448
449 buf->size = priv_req->request.length;
450
451 buf->buf = dma_alloc_coherent(priv_dev->sysdev,
452 buf->size,
453 &buf->dma,
454 GFP_ATOMIC);
455 if (!buf->buf) {
456 kfree(buf);
457 return -ENOMEM;
458 }
459
460 if (priv_req->aligned_buf) {
461 trace_cdns3_free_aligned_request(priv_req);
462 priv_req->aligned_buf->in_use = 0;
463 queue_work(system_freezable_wq,
464 &priv_dev->aligned_buf_wq);
465 }
466
467 buf->in_use = 1;
468 priv_req->aligned_buf = buf;
469
470 list_add_tail(&buf->list,
471 &priv_dev->aligned_buf_list);
472 }
473
474 if (priv_ep->dir == USB_DIR_IN) {
475 memcpy(buf->buf, priv_req->request.buf,
476 priv_req->request.length);
477 }
478
479 priv_req->flags |= REQUEST_UNALIGNED;
480 trace_cdns3_prepare_aligned_request(priv_req);
481
482 return 0;
483}
484
485static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep,
486 struct cdns3_trb *trb)
487{
488 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
489
490 if (!priv_ep->wa1_set) {
491 u32 doorbell;
492
493 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
494
495 if (doorbell) {
496 priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0;
497 priv_ep->wa1_set = 1;
498 priv_ep->wa1_trb = trb;
499 priv_ep->wa1_trb_index = priv_ep->enqueue;
500 trace_cdns3_wa1(priv_ep, "set guard");
501 return 0;
502 }
503 }
504 return 1;
505}
506
507static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev,
508 struct cdns3_endpoint *priv_ep)
509{
510 int dma_index;
511 u32 doorbell;
512
513 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
514 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
515
516 if (!doorbell || dma_index != priv_ep->wa1_trb_index)
517 cdns3_wa1_restore_cycle_bit(priv_ep);
518}
519
520/**
521 * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
522 * @priv_ep: endpoint object
523 *
524 * Returns zero on success or negative value on failure
525 */
526int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
527 struct usb_request *request)
528{
529 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
530 struct cdns3_request *priv_req;
531 struct cdns3_trb *trb;
532 dma_addr_t trb_dma;
533 u32 togle_pcs = 1;
534 int sg_iter = 0;
535 int num_trb;
536 int address;
537 u32 control;
538 int pcs;
539
540 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC)
541 num_trb = priv_ep->interval;
542 else
543 num_trb = request->num_sgs ? request->num_sgs : 1;
544
545 if (num_trb > priv_ep->free_trbs) {
546 priv_ep->flags |= EP_RING_FULL;
547 return -ENOBUFS;
548 }
549
550 priv_req = to_cdns3_request(request);
551 address = priv_ep->endpoint.desc->bEndpointAddress;
552
553 priv_ep->flags |= EP_PENDING_REQUEST;
554
555 /* must allocate buffer aligned to 8 */
556 if (priv_req->flags & REQUEST_UNALIGNED)
557 trb_dma = priv_req->aligned_buf->dma;
558 else
559 trb_dma = request->dma;
560
561 trb = priv_ep->trb_pool + priv_ep->enqueue;
562 priv_req->start_trb = priv_ep->enqueue;
563 priv_req->trb = trb;
564
565 cdns3_select_ep(priv_ep->cdns3_dev, address);
566
567 /* prepare ring */
568 if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) {
569 struct cdns3_trb *link_trb;
570 int doorbell, dma_index;
571 u32 ch_bit = 0;
572
573 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
574 dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
575
576 /* Driver can't update LINK TRB if it is current processed. */
577 if (doorbell && dma_index == priv_ep->num_trbs - 1) {
578 priv_ep->flags |= EP_DEFERRED_DRDY;
579 return -ENOBUFS;
580 }
581
582 /*updating C bt in Link TRB before starting DMA*/
583 link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1);
584 /*
585 * For TRs size equal 2 enabling TRB_CHAIN for epXin causes
586 * that DMA stuck at the LINK TRB.
587 * On the other hand, removing TRB_CHAIN for longer TRs for
588 * epXout cause that DMA stuck after handling LINK TRB.
589 * To eliminate this strange behavioral driver set TRB_CHAIN
590 * bit only for TR size > 2.
591 */
592 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC ||
593 TRBS_PER_SEGMENT > 2)
594 ch_bit = TRB_CHAIN;
595
596 link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) |
597 TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit;
598 }
599
600 if (priv_dev->dev_ver <= DEV_VER_V2)
601 togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
602
603 /* set incorrect Cycle Bit for first trb*/
604 control = priv_ep->pcs ? 0 : TRB_CYCLE;
605
606 do {
607 u32 length;
608 u16 td_size = 0;
609
610 /* fill TRB */
611 control |= TRB_TYPE(TRB_NORMAL);
612 trb->buffer = TRB_BUFFER(request->num_sgs == 0
613 ? trb_dma : request->sg[sg_iter].dma_address);
614
615 if (likely(!request->num_sgs))
616 length = request->length;
617 else
618 length = request->sg[sg_iter].length;
619
620 if (likely(priv_dev->dev_ver >= DEV_VER_V2))
621 td_size = DIV_ROUND_UP(length,
622 priv_ep->endpoint.maxpacket);
623
624 trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) |
625 TRB_LEN(length);
626 if (priv_dev->gadget.speed == USB_SPEED_SUPER)
627 trb->length |= TRB_TDL_SS_SIZE(td_size);
628 else
629 control |= TRB_TDL_HS_SIZE(td_size);
630
631 pcs = priv_ep->pcs ? TRB_CYCLE : 0;
632
633 /*
634 * first trb should be prepared as last to avoid processing
635 * transfer to early
636 */
637 if (sg_iter != 0)
638 control |= pcs;
639
640 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) {
641 control |= TRB_IOC | TRB_ISP;
642 } else {
643 /* for last element in TD or in SG list */
644 if (sg_iter == (num_trb - 1) && sg_iter != 0)
645 control |= pcs | TRB_IOC | TRB_ISP;
646 }
647
648 if (sg_iter)
649 trb->control = control;
650 else
651 priv_req->trb->control = control;
652
653 control = 0;
654 ++sg_iter;
655 priv_req->end_trb = priv_ep->enqueue;
656 cdns3_ep_inc_enq(priv_ep);
657 trb = priv_ep->trb_pool + priv_ep->enqueue;
658 } while (sg_iter < num_trb);
659
660 trb = priv_req->trb;
661
662 priv_req->flags |= REQUEST_PENDING;
663
664 if (sg_iter == 1)
665 trb->control |= TRB_IOC | TRB_ISP;
666
667 /*
668 * Memory barrier - cycle bit must be set before other filds in trb.
669 */
670 wmb();
671
672 /* give the TD to the consumer*/
673 if (togle_pcs)
674 trb->control = trb->control ^ 1;
675
676 if (priv_dev->dev_ver <= DEV_VER_V2)
677 cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
678
679 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
680
681 /*
682 * Memory barrier - Cycle Bit must be set before trb->length and
683 * trb->buffer fields.
684 */
685 wmb();
686
687 /*
688 * For DMULT mode we can set address to transfer ring only once after
689 * enabling endpoint.
690 */
691 if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) {
692 /*
693 * Until SW is not ready to handle the OUT transfer the ISO OUT
694 * Endpoint should be disabled (EP_CFG.ENABLE = 0).
695 * EP_CFG_ENABLE must be set before updating ep_traddr.
696 */
697 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir &&
698 !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) {
699 priv_ep->flags |= EP_QUIRK_ISO_OUT_EN;
700 cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
701 EP_CFG_ENABLE);
702 }
703
704 writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
705 priv_req->start_trb * TRB_SIZE),
706 &priv_dev->regs->ep_traddr);
707
708 priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR;
709 }
710
711 if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) {
712 trace_cdns3_ring(priv_ep);
713 /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
714 writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
715 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
716 trace_cdns3_doorbell_epx(priv_ep->name,
717 readl(&priv_dev->regs->ep_traddr));
718 }
719
720 /* WORKAROUND for transition to L0 */
721 __cdns3_gadget_wakeup(priv_dev);
722
723 return 0;
724}
725
726void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
727{
728 struct cdns3_endpoint *priv_ep;
729 struct usb_ep *ep;
730 int val;
731
732 if (priv_dev->hw_configured_flag)
733 return;
734
735 writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
736 writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd);
737
738 cdns3_set_register_bit(&priv_dev->regs->usb_conf,
739 USB_CONF_U1EN | USB_CONF_U2EN);
740
741 /* wait until configuration set */
742 readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val,
743 val & USB_STS_CFGSTS_MASK, 1, 100);
744
745 priv_dev->hw_configured_flag = 1;
746
747 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
748 if (ep->enabled) {
749 priv_ep = ep_to_cdns3_ep(ep);
750 cdns3_start_all_request(priv_dev, priv_ep);
751 }
752 }
753}
754
755/**
756 * cdns3_request_handled - check whether request has been handled by DMA
757 *
758 * @priv_ep: extended endpoint object.
759 * @priv_req: request object for checking
760 *
761 * Endpoint must be selected before invoking this function.
762 *
763 * Returns false if request has not been handled by DMA, else returns true.
764 *
765 * SR - start ring
766 * ER - end ring
767 * DQ = priv_ep->dequeue - dequeue position
768 * EQ = priv_ep->enqueue - enqueue position
769 * ST = priv_req->start_trb - index of first TRB in transfer ring
770 * ET = priv_req->end_trb - index of last TRB in transfer ring
771 * CI = current_index - index of processed TRB by DMA.
772 *
773 * As first step, function checks if cycle bit for priv_req->start_trb is
774 * correct.
775 *
776 * some rules:
777 * 1. priv_ep->dequeue never exceed current_index.
778 * 2 priv_ep->enqueue never exceed priv_ep->dequeue
779 * 3. exception: priv_ep->enqueue == priv_ep->dequeue
780 * and priv_ep->free_trbs is zero.
781 * This case indicate that TR is full.
782 *
783 * Then We can split recognition into two parts:
784 * Case 1 - priv_ep->dequeue < current_index
785 * SR ... EQ ... DQ ... CI ... ER
786 * SR ... DQ ... CI ... EQ ... ER
787 *
788 * Request has been handled by DMA if ST and ET is between DQ and CI.
789 *
790 * Case 2 - priv_ep->dequeue > current_index
791 * This situation take place when CI go through the LINK TRB at the end of
792 * transfer ring.
793 * SR ... CI ... EQ ... DQ ... ER
794 *
795 * Request has been handled by DMA if ET is less then CI or
796 * ET is greater or equal DQ.
797 */
798static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep,
799 struct cdns3_request *priv_req)
800{
801 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
802 struct cdns3_trb *trb = priv_req->trb;
803 int current_index = 0;
804 int handled = 0;
805 int doorbell;
806
807 current_index = cdns3_get_dma_pos(priv_dev, priv_ep);
808 doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
809
810 trb = &priv_ep->trb_pool[priv_req->start_trb];
811
812 if ((trb->control & TRB_CYCLE) != priv_ep->ccs)
813 goto finish;
814
815 if (doorbell == 1 && current_index == priv_ep->dequeue)
816 goto finish;
817
818 /* The corner case for TRBS_PER_SEGMENT equal 2). */
819 if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
820 handled = 1;
821 goto finish;
822 }
823
824 if (priv_ep->enqueue == priv_ep->dequeue &&
825 priv_ep->free_trbs == 0) {
826 handled = 1;
827 } else if (priv_ep->dequeue < current_index) {
828 if ((current_index == (priv_ep->num_trbs - 1)) &&
829 !priv_ep->dequeue)
830 goto finish;
831
832 if (priv_req->end_trb >= priv_ep->dequeue &&
833 priv_req->end_trb < current_index)
834 handled = 1;
835 } else if (priv_ep->dequeue > current_index) {
836 if (priv_req->end_trb < current_index ||
837 priv_req->end_trb >= priv_ep->dequeue)
838 handled = 1;
839 }
840
841finish:
842 trace_cdns3_request_handled(priv_req, current_index, handled);
843
844 return handled;
845}
846
847static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
848 struct cdns3_endpoint *priv_ep)
849{
850 struct cdns3_request *priv_req;
851 struct usb_request *request;
852 struct cdns3_trb *trb;
853
854 while (!list_empty(&priv_ep->pending_req_list)) {
855 request = cdns3_next_request(&priv_ep->pending_req_list);
856 priv_req = to_cdns3_request(request);
857
858 /* Re-select endpoint. It could be changed by other CPU during
859 * handling usb_gadget_giveback_request.
860 */
861 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
862
863 if (!cdns3_request_handled(priv_ep, priv_req))
864 goto prepare_next_td;
865
866 trb = priv_ep->trb_pool + priv_ep->dequeue;
867 trace_cdns3_complete_trb(priv_ep, trb);
868
869 if (trb != priv_req->trb)
870 dev_warn(priv_dev->dev,
871 "request_trb=0x%p, queue_trb=0x%p\n",
872 priv_req->trb, trb);
873
874 request->actual = TRB_LEN(le32_to_cpu(trb->length));
875 cdns3_move_deq_to_next_trb(priv_req);
876 cdns3_gadget_giveback(priv_ep, priv_req, 0);
877
878 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC &&
879 TRBS_PER_SEGMENT == 2)
880 break;
881 }
882 priv_ep->flags &= ~EP_PENDING_REQUEST;
883
884prepare_next_td:
885 if (!(priv_ep->flags & EP_STALLED) &&
886 !(priv_ep->flags & EP_STALL_PENDING))
887 cdns3_start_all_request(priv_dev, priv_ep);
888}
889
890void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm)
891{
892 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
893
894 cdns3_wa1_restore_cycle_bit(priv_ep);
895
896 if (rearm) {
897 trace_cdns3_ring(priv_ep);
898
899 /* Cycle Bit must be updated before arming DMA. */
900 wmb();
901 writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
902
903 __cdns3_gadget_wakeup(priv_dev);
904
905 trace_cdns3_doorbell_epx(priv_ep->name,
906 readl(&priv_dev->regs->ep_traddr));
907 }
908}
909
910/**
911 * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint
912 * @priv_ep: endpoint object
913 *
914 * Returns 0
915 */
916static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep)
917{
918 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
919 u32 ep_sts_reg;
920
921 cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
922
923 trace_cdns3_epx_irq(priv_dev, priv_ep);
924
925 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
926 writel(ep_sts_reg, &priv_dev->regs->ep_sts);
927
928 if (ep_sts_reg & EP_STS_TRBERR) {
929 if (priv_ep->flags & EP_STALL_PENDING &&
930 !(ep_sts_reg & EP_STS_DESCMIS &&
931 priv_dev->dev_ver < DEV_VER_V2)) {
932 cdns3_ep_stall_flush(priv_ep);
933 }
934
935 /*
936 * For isochronous transfer driver completes request on
937 * IOC or on TRBERR. IOC appears only when device receive
938 * OUT data packet. If host disable stream or lost some packet
939 * then the only way to finish all queued transfer is to do it
940 * on TRBERR event.
941 */
942 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC &&
943 !priv_ep->wa1_set) {
944 if (!priv_ep->dir) {
945 u32 ep_cfg = readl(&priv_dev->regs->ep_cfg);
946
947 ep_cfg &= ~EP_CFG_ENABLE;
948 writel(ep_cfg, &priv_dev->regs->ep_cfg);
949 priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN;
950 }
951 cdns3_transfer_completed(priv_dev, priv_ep);
952 } else if (!(priv_ep->flags & EP_STALLED) &&
953 !(priv_ep->flags & EP_STALL_PENDING)) {
954 if (priv_ep->flags & EP_DEFERRED_DRDY) {
955 priv_ep->flags &= ~EP_DEFERRED_DRDY;
956 cdns3_start_all_request(priv_dev, priv_ep);
957 } else {
958 cdns3_rearm_transfer(priv_ep,
959 priv_ep->wa1_set);
960 }
961 }
962 }
963
964 if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP))
965 cdns3_transfer_completed(priv_dev, priv_ep);
966
967 return 0;
968}
969
970static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev)
971{
972 if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) {
973 spin_unlock(&priv_dev->lock);
974 priv_dev->gadget_driver->disconnect(&priv_dev->gadget);
975 spin_lock(&priv_dev->lock);
976 }
977}
978
979/**
980 * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device
981 * @priv_dev: extended gadget object
982 * @usb_ists: bitmap representation of device's reported interrupts
983 * (usb_ists register value)
984 */
985static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
986 u32 usb_ists)
987{
988 int speed = 0;
989
990 trace_cdns3_usb_irq(priv_dev, usb_ists);
991 if (usb_ists & USB_ISTS_L1ENTI) {
992 /*
993 * WORKAROUND: CDNS3 controller has issue with hardware resuming
994 * from L1. To fix it, if any DMA transfer is pending driver
995 * must starts driving resume signal immediately.
996 */
997 if (readl(&priv_dev->regs->drbl))
998 __cdns3_gadget_wakeup(priv_dev);
999 }
1000
1001 /* Connection detected */
1002 if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
1003 speed = cdns3_get_speed(priv_dev);
1004 priv_dev->gadget.speed = speed;
1005 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED);
1006 cdns3_ep0_config(priv_dev);
1007 }
1008
1009 /* Disconnection detected */
1010 if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
1011 cdns3_disconnect_gadget(priv_dev);
1012 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
1013 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
1014 cdns3_hw_reset_eps_config(priv_dev);
1015 }
1016
1017 if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) {
1018 if (priv_dev->gadget_driver &&
1019 priv_dev->gadget_driver->suspend) {
1020 spin_unlock(&priv_dev->lock);
1021 priv_dev->gadget_driver->suspend(&priv_dev->gadget);
1022 spin_lock(&priv_dev->lock);
1023 }
1024 }
1025
1026 if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) {
1027 if (priv_dev->gadget_driver &&
1028 priv_dev->gadget_driver->resume) {
1029 spin_unlock(&priv_dev->lock);
1030 priv_dev->gadget_driver->resume(&priv_dev->gadget);
1031 spin_lock(&priv_dev->lock);
1032 }
1033 }
1034
1035 /* reset*/
1036 if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) {
1037 if (priv_dev->gadget_driver) {
1038 spin_unlock(&priv_dev->lock);
1039 usb_gadget_udc_reset(&priv_dev->gadget,
1040 priv_dev->gadget_driver);
1041 spin_lock(&priv_dev->lock);
1042
1043 /*read again to check the actual speed*/
1044 speed = cdns3_get_speed(priv_dev);
1045 priv_dev->gadget.speed = speed;
1046 cdns3_hw_reset_eps_config(priv_dev);
1047 cdns3_ep0_config(priv_dev);
1048 }
1049 }
1050}
1051
1052/**
1053 * cdns3_device_irq_handler- interrupt handler for device part of controller
1054 *
1055 * @irq: irq number for cdns3 core device
1056 * @data: structure of cdns3
1057 *
1058 * Returns IRQ_HANDLED or IRQ_NONE
1059 */
1060static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
1061{
1062 struct cdns3_device *priv_dev;
1063 struct cdns3 *cdns = data;
1064 irqreturn_t ret = IRQ_NONE;
1065 u32 reg;
1066
1067 priv_dev = cdns->gadget_dev;
1068
1069 /* check USB device interrupt */
1070 reg = readl(&priv_dev->regs->usb_ists);
1071 if (reg) {
1072 /* After masking interrupts the new interrupts won't be
1073 * reported in usb_ists/ep_ists. In order to not lose some
1074 * of them driver disables only detected interrupts.
1075 * They will be enabled ASAP after clearing source of
1076 * interrupt. This an unusual behavior only applies to
1077 * usb_ists register.
1078 */
1079 reg = ~reg & readl(&priv_dev->regs->usb_ien);
1080 /* mask deferred interrupt. */
1081 writel(reg, &priv_dev->regs->usb_ien);
1082 ret = IRQ_WAKE_THREAD;
1083 }
1084
1085 /* check endpoint interrupt */
1086 reg = readl(&priv_dev->regs->ep_ists);
1087 if (reg) {
1088 writel(0, &priv_dev->regs->ep_ien);
1089 ret = IRQ_WAKE_THREAD;
1090 }
1091
1092 return ret;
1093}
1094
1095/**
1096 * cdns3_device_thread_irq_handler- interrupt handler for device part
1097 * of controller
1098 *
1099 * @irq: irq number for cdns3 core device
1100 * @data: structure of cdns3
1101 *
1102 * Returns IRQ_HANDLED or IRQ_NONE
1103 */
1104static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data)
1105{
1106 struct cdns3_device *priv_dev;
1107 struct cdns3 *cdns = data;
1108 irqreturn_t ret = IRQ_NONE;
1109 unsigned long flags;
1110 int bit;
1111 u32 reg;
1112
1113 priv_dev = cdns->gadget_dev;
1114 spin_lock_irqsave(&priv_dev->lock, flags);
1115
1116 reg = readl(&priv_dev->regs->usb_ists);
1117 if (reg) {
1118 writel(reg, &priv_dev->regs->usb_ists);
1119 writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
1120 cdns3_check_usb_interrupt_proceed(priv_dev, reg);
1121 ret = IRQ_HANDLED;
1122 }
1123
1124 reg = readl(&priv_dev->regs->ep_ists);
1125
1126 /* handle default endpoint OUT */
1127 if (reg & EP_ISTS_EP_OUT0) {
1128 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT);
1129 ret = IRQ_HANDLED;
1130 }
1131
1132 /* handle default endpoint IN */
1133 if (reg & EP_ISTS_EP_IN0) {
1134 cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN);
1135 ret = IRQ_HANDLED;
1136 }
1137
1138 /* check if interrupt from non default endpoint, if no exit */
1139 reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0);
1140 if (!reg)
1141 goto irqend;
1142
1143 for_each_set_bit(bit, (unsigned long *)&reg,
1144 sizeof(u32) * BITS_PER_BYTE) {
1145 cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]);
1146 ret = IRQ_HANDLED;
1147 }
1148
1149irqend:
1150 writel(~0, &priv_dev->regs->ep_ien);
1151 spin_unlock_irqrestore(&priv_dev->lock, flags);
1152
1153 return ret;
1154}
1155
1156/**
1157 * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP
1158 *
1159 * The real reservation will occur during write to EP_CFG register,
1160 * this function is used to check if the 'size' reservation is allowed.
1161 *
1162 * @priv_dev: extended gadget object
1163 * @size: the size (KB) for EP would like to allocate
1164 * @is_in: endpoint direction
1165 *
1166 * Return 0 if the required size can met or negative value on failure
1167 */
1168static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev,
1169 int size, int is_in)
1170{
1171 int remained;
1172
1173 /* 2KB are reserved for EP0*/
1174 remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2;
1175
1176 if (is_in) {
1177 if (remained < size)
1178 return -EPERM;
1179
1180 priv_dev->onchip_used_size += size;
1181 } else {
1182 int required;
1183
1184 /**
1185 * ALL OUT EPs are shared the same chunk onchip memory, so
1186 * driver checks if it already has assigned enough buffers
1187 */
1188 if (priv_dev->out_mem_is_allocated >= size)
1189 return 0;
1190
1191 required = size - priv_dev->out_mem_is_allocated;
1192
1193 if (required > remained)
1194 return -EPERM;
1195
1196 priv_dev->out_mem_is_allocated += required;
1197 priv_dev->onchip_used_size += required;
1198 }
1199
1200 return 0;
1201}
1202
1203void cdns3_configure_dmult(struct cdns3_device *priv_dev,
1204 struct cdns3_endpoint *priv_ep)
1205{
1206 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
1207
1208 /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
1209 if (priv_dev->dev_ver <= DEV_VER_V2)
1210 writel(USB_CONF_DMULT, &regs->usb_conf);
1211
1212 if (priv_dev->dev_ver == DEV_VER_V2)
1213 writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2);
1214
1215 if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) {
1216 u32 mask;
1217
1218 if (priv_ep->dir)
1219 mask = BIT(priv_ep->num + 16);
1220 else
1221 mask = BIT(priv_ep->num);
1222
1223 if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
1224 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1225 cdns3_set_register_bit(&regs->tdl_beh, mask);
1226 cdns3_set_register_bit(&regs->tdl_beh2, mask);
1227 cdns3_set_register_bit(&regs->dma_adv_td, mask);
1228 }
1229
1230 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1231 cdns3_set_register_bit(&regs->tdl_from_trb, mask);
1232
1233 cdns3_set_register_bit(&regs->dtrans, mask);
1234 }
1235}
1236
1237/**
1238 * cdns3_ep_config Configure hardware endpoint
1239 * @priv_ep: extended endpoint object
1240 */
1241void cdns3_ep_config(struct cdns3_endpoint *priv_ep)
1242{
1243 bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC);
1244 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1245 u32 bEndpointAddress = priv_ep->num | priv_ep->dir;
1246 u32 max_packet_size = 0;
1247 u8 maxburst = 0;
1248 u32 ep_cfg = 0;
1249 u8 buffering;
1250 u8 mult = 0;
1251 int ret;
1252
1253 buffering = CDNS3_EP_BUF_SIZE - 1;
1254
1255 cdns3_configure_dmult(priv_dev, priv_ep);
1256
1257 switch (priv_ep->type) {
1258 case USB_ENDPOINT_XFER_INT:
1259 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT);
1260
1261 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1262 priv_dev->dev_ver > DEV_VER_V2)
1263 ep_cfg |= EP_CFG_TDL_CHK;
1264 break;
1265 case USB_ENDPOINT_XFER_BULK:
1266 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK);
1267
1268 if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
1269 priv_dev->dev_ver > DEV_VER_V2)
1270 ep_cfg |= EP_CFG_TDL_CHK;
1271 break;
1272 default:
1273 ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
1274 mult = CDNS3_EP_ISO_HS_MULT - 1;
1275 buffering = mult + 1;
1276 }
1277
1278 switch (priv_dev->gadget.speed) {
1279 case USB_SPEED_FULL:
1280 max_packet_size = is_iso_ep ? 1023 : 64;
1281 break;
1282 case USB_SPEED_HIGH:
1283 max_packet_size = is_iso_ep ? 1024 : 512;
1284 break;
1285 case USB_SPEED_SUPER:
1286 /* It's limitation that driver assumes in driver. */
1287 mult = 0;
1288 max_packet_size = 1024;
1289 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1290 maxburst = CDNS3_EP_ISO_SS_BURST - 1;
1291 buffering = (mult + 1) *
1292 (maxburst + 1);
1293
1294 if (priv_ep->interval > 1)
1295 buffering++;
1296 } else {
1297 maxburst = CDNS3_EP_BUF_SIZE - 1;
1298 }
1299 break;
1300 default:
1301 /* all other speed are not supported */
1302 return;
1303 }
1304
1305 if (max_packet_size == 1024)
1306 priv_ep->trb_burst_size = 128;
1307 else if (max_packet_size >= 512)
1308 priv_ep->trb_burst_size = 64;
1309 else
1310 priv_ep->trb_burst_size = 16;
1311
1312 ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
1313 !!priv_ep->dir);
1314 if (ret) {
1315 dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n");
1316 return;
1317 }
1318
1319 ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) |
1320 EP_CFG_MULT(mult) |
1321 EP_CFG_BUFFERING(buffering) |
1322 EP_CFG_MAXBURST(maxburst);
1323
1324 cdns3_select_ep(priv_dev, bEndpointAddress);
1325 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1326
1327 dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n",
1328 priv_ep->name, ep_cfg);
1329}
1330
1331/* Find correct direction for HW endpoint according to description */
1332static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc,
1333 struct cdns3_endpoint *priv_ep)
1334{
1335 return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) ||
1336 (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc));
1337}
1338
1339static struct
1340cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev,
1341 struct usb_endpoint_descriptor *desc)
1342{
1343 struct usb_ep *ep;
1344 struct cdns3_endpoint *priv_ep;
1345
1346 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
1347 unsigned long num;
1348 int ret;
1349 /* ep name pattern likes epXin or epXout */
1350 char c[2] = {ep->name[2], '\0'};
1351
1352 ret = kstrtoul(c, 10, &num);
1353 if (ret)
1354 return ERR_PTR(ret);
1355
1356 priv_ep = ep_to_cdns3_ep(ep);
1357 if (cdns3_ep_dir_is_correct(desc, priv_ep)) {
1358 if (!(priv_ep->flags & EP_CLAIMED)) {
1359 priv_ep->num = num;
1360 return priv_ep;
1361 }
1362 }
1363 }
1364
1365 return ERR_PTR(-ENOENT);
1366}
1367
1368/*
1369 * Cadence IP has one limitation that all endpoints must be configured
1370 * (Type & MaxPacketSize) before setting configuration through hardware
1371 * register, it means we can't change endpoints configuration after
1372 * set_configuration.
1373 *
1374 * This function set EP_CLAIMED flag which is added when the gadget driver
1375 * uses usb_ep_autoconfig to configure specific endpoint;
1376 * When the udc driver receives set_configurion request,
1377 * it goes through all claimed endpoints, and configure all endpoints
1378 * accordingly.
1379 *
1380 * At usb_ep_ops.enable/disable, we only enable and disable endpoint through
1381 * ep_cfg register which can be changed after set_configuration, and do
1382 * some software operation accordingly.
1383 */
1384static struct
1385usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget,
1386 struct usb_endpoint_descriptor *desc,
1387 struct usb_ss_ep_comp_descriptor *comp_desc)
1388{
1389 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1390 struct cdns3_endpoint *priv_ep;
1391 unsigned long flags;
1392
1393 priv_ep = cdns3_find_available_ep(priv_dev, desc);
1394 if (IS_ERR(priv_ep)) {
1395 dev_err(priv_dev->dev, "no available ep\n");
1396 return NULL;
1397 }
1398
1399 dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name);
1400
1401 spin_lock_irqsave(&priv_dev->lock, flags);
1402 priv_ep->endpoint.desc = desc;
1403 priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
1404 priv_ep->type = usb_endpoint_type(desc);
1405 priv_ep->flags |= EP_CLAIMED;
1406 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1407
1408 spin_unlock_irqrestore(&priv_dev->lock, flags);
1409 return &priv_ep->endpoint;
1410}
1411
1412/**
1413 * cdns3_gadget_ep_alloc_request Allocates request
1414 * @ep: endpoint object associated with request
1415 * @gfp_flags: gfp flags
1416 *
1417 * Returns allocated request address, NULL on allocation error
1418 */
1419struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1420 gfp_t gfp_flags)
1421{
1422 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1423 struct cdns3_request *priv_req;
1424
1425 priv_req = kzalloc(sizeof(*priv_req), gfp_flags);
1426 if (!priv_req)
1427 return NULL;
1428
1429 priv_req->priv_ep = priv_ep;
1430
1431 trace_cdns3_alloc_request(priv_req);
1432 return &priv_req->request;
1433}
1434
1435/**
1436 * cdns3_gadget_ep_free_request Free memory occupied by request
1437 * @ep: endpoint object associated with request
1438 * @request: request to free memory
1439 */
1440void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1441 struct usb_request *request)
1442{
1443 struct cdns3_request *priv_req = to_cdns3_request(request);
1444
1445 if (priv_req->aligned_buf)
1446 priv_req->aligned_buf->in_use = 0;
1447
1448 trace_cdns3_free_request(priv_req);
1449 kfree(priv_req);
1450}
1451
1452/**
1453 * cdns3_gadget_ep_enable Enable endpoint
1454 * @ep: endpoint object
1455 * @desc: endpoint descriptor
1456 *
1457 * Returns 0 on success, error code elsewhere
1458 */
1459static int cdns3_gadget_ep_enable(struct usb_ep *ep,
1460 const struct usb_endpoint_descriptor *desc)
1461{
1462 struct cdns3_endpoint *priv_ep;
1463 struct cdns3_device *priv_dev;
1464 u32 reg = EP_STS_EN_TRBERREN;
1465 u32 bEndpointAddress;
1466 unsigned long flags;
1467 int enable = 1;
1468 int ret;
1469 int val;
1470
1471 priv_ep = ep_to_cdns3_ep(ep);
1472 priv_dev = priv_ep->cdns3_dev;
1473
1474 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1475 dev_dbg(priv_dev->dev, "usbss: invalid parameters\n");
1476 return -EINVAL;
1477 }
1478
1479 if (!desc->wMaxPacketSize) {
1480 dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n");
1481 return -EINVAL;
1482 }
1483
1484 if (dev_WARN_ONCE(priv_dev->dev, priv_ep->flags & EP_ENABLED,
1485 "%s is already enabled\n", priv_ep->name))
1486 return 0;
1487
1488 spin_lock_irqsave(&priv_dev->lock, flags);
1489
1490 priv_ep->endpoint.desc = desc;
1491 priv_ep->type = usb_endpoint_type(desc);
1492 priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
1493
1494 if (priv_ep->interval > ISO_MAX_INTERVAL &&
1495 priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
1496 dev_err(priv_dev->dev, "Driver is limited to %d period\n",
1497 ISO_MAX_INTERVAL);
1498
1499 ret = -EINVAL;
1500 goto exit;
1501 }
1502
1503 ret = cdns3_allocate_trb_pool(priv_ep);
1504
1505 if (ret)
1506 goto exit;
1507
1508 bEndpointAddress = priv_ep->num | priv_ep->dir;
1509 cdns3_select_ep(priv_dev, bEndpointAddress);
1510
1511 trace_cdns3_gadget_ep_enable(priv_ep);
1512
1513 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1514
1515 ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1516 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1517 1, 1000);
1518
1519 if (unlikely(ret)) {
1520 cdns3_free_trb_pool(priv_ep);
1521 ret = -EINVAL;
1522 goto exit;
1523 }
1524
1525 /* enable interrupt for selected endpoint */
1526 cdns3_set_register_bit(&priv_dev->regs->ep_ien,
1527 BIT(cdns3_ep_addr_to_index(bEndpointAddress)));
1528
1529 writel(reg, &priv_dev->regs->ep_sts_en);
1530
1531 /*
1532 * For some versions of controller at some point during ISO OUT traffic
1533 * DMA reads Transfer Ring for the EP which has never got doorbell.
1534 * This issue was detected only on simulation, but to avoid this issue
1535 * driver add protection against it. To fix it driver enable ISO OUT
1536 * endpoint before setting DRBL. This special treatment of ISO OUT
1537 * endpoints are recommended by controller specification.
1538 */
1539 if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
1540 enable = 0;
1541
1542 if (enable)
1543 cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE);
1544
1545 ep->desc = desc;
1546 priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING |
1547 EP_QUIRK_ISO_OUT_EN);
1548 priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR;
1549 priv_ep->wa1_set = 0;
1550 priv_ep->enqueue = 0;
1551 priv_ep->dequeue = 0;
1552 reg = readl(&priv_dev->regs->ep_sts);
1553 priv_ep->pcs = !!EP_STS_CCS(reg);
1554 priv_ep->ccs = !!EP_STS_CCS(reg);
1555 /* one TRB is reserved for link TRB used in DMULT mode*/
1556 priv_ep->free_trbs = priv_ep->num_trbs - 1;
1557exit:
1558 spin_unlock_irqrestore(&priv_dev->lock, flags);
1559
1560 return ret;
1561}
1562
1563/**
1564 * cdns3_gadget_ep_disable Disable endpoint
1565 * @ep: endpoint object
1566 *
1567 * Returns 0 on success, error code elsewhere
1568 */
1569static int cdns3_gadget_ep_disable(struct usb_ep *ep)
1570{
1571 struct cdns3_endpoint *priv_ep;
1572 struct cdns3_device *priv_dev;
1573 struct usb_request *request;
1574 unsigned long flags;
1575 int ret = 0;
1576 u32 ep_cfg;
1577 int val;
1578
1579 if (!ep) {
1580 pr_err("usbss: invalid parameters\n");
1581 return -EINVAL;
1582 }
1583
1584 priv_ep = ep_to_cdns3_ep(ep);
1585 priv_dev = priv_ep->cdns3_dev;
1586
1587 if (dev_WARN_ONCE(priv_dev->dev, !(priv_ep->flags & EP_ENABLED),
1588 "%s is already disabled\n", priv_ep->name))
1589 return 0;
1590
1591 spin_lock_irqsave(&priv_dev->lock, flags);
1592
1593 trace_cdns3_gadget_ep_disable(priv_ep);
1594
1595 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
1596
1597 ep_cfg = readl(&priv_dev->regs->ep_cfg);
1598 ep_cfg &= ~EP_CFG_ENABLE;
1599 writel(ep_cfg, &priv_dev->regs->ep_cfg);
1600
1601 /**
1602 * Driver needs some time before resetting endpoint.
1603 * It need waits for clearing DBUSY bit or for timeout expired.
1604 * 10us is enough time for controller to stop transfer.
1605 */
1606 readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val,
1607 !(val & EP_STS_DBUSY), 1, 10);
1608 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1609
1610 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1611 !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
1612 1, 1000);
1613 if (unlikely(ret))
1614 dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n",
1615 priv_ep->name);
1616
1617 while (!list_empty(&priv_ep->pending_req_list)) {
1618 request = cdns3_next_request(&priv_ep->pending_req_list);
1619
1620 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1621 -ESHUTDOWN);
1622 }
1623
1624 while (!list_empty(&priv_ep->deferred_req_list)) {
1625 request = cdns3_next_request(&priv_ep->deferred_req_list);
1626
1627 cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
1628 -ESHUTDOWN);
1629 }
1630
1631 ep->desc = NULL;
1632 priv_ep->flags &= ~EP_ENABLED;
1633
1634 spin_unlock_irqrestore(&priv_dev->lock, flags);
1635
1636 return ret;
1637}
1638
1639/**
1640 * cdns3_gadget_ep_queue Transfer data on endpoint
1641 * @ep: endpoint object
1642 * @request: request object
1643 * @gfp_flags: gfp flags
1644 *
1645 * Returns 0 on success, error code elsewhere
1646 */
1647static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
1648 struct usb_request *request,
1649 gfp_t gfp_flags)
1650{
1651 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1652 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1653 struct cdns3_request *priv_req;
1654 int ret = 0;
1655
1656 request->actual = 0;
1657 request->status = -EINPROGRESS;
1658 priv_req = to_cdns3_request(request);
1659 trace_cdns3_ep_queue(priv_req);
1660
1661 ret = cdns3_prepare_aligned_request_buf(priv_req);
1662 if (ret < 0)
1663 return ret;
1664
1665 ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request,
1666 usb_endpoint_dir_in(ep->desc));
1667 if (ret)
1668 return ret;
1669
1670 list_add_tail(&request->list, &priv_ep->deferred_req_list);
1671
1672 /*
1673 * If hardware endpoint configuration has not been set yet then
1674 * just queue request in deferred list. Transfer will be started in
1675 * cdns3_set_hw_configuration.
1676 */
1677 if (priv_dev->hw_configured_flag && !(priv_ep->flags & EP_STALLED) &&
1678 !(priv_ep->flags & EP_STALL_PENDING))
1679 cdns3_start_all_request(priv_dev, priv_ep);
1680
1681 return 0;
1682}
1683
1684static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1685 gfp_t gfp_flags)
1686{
1687 struct usb_request *zlp_request;
1688 struct cdns3_endpoint *priv_ep;
1689 struct cdns3_device *priv_dev;
1690 unsigned long flags;
1691 int ret;
1692
1693 if (!request || !ep)
1694 return -EINVAL;
1695
1696 priv_ep = ep_to_cdns3_ep(ep);
1697 priv_dev = priv_ep->cdns3_dev;
1698
1699 spin_lock_irqsave(&priv_dev->lock, flags);
1700
1701 ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags);
1702
1703 if (ret == 0 && request->zero && request->length &&
1704 (request->length % ep->maxpacket == 0)) {
1705 struct cdns3_request *priv_req;
1706
1707 zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1708 zlp_request->buf = priv_dev->zlp_buf;
1709 zlp_request->length = 0;
1710
1711 priv_req = to_cdns3_request(zlp_request);
1712 priv_req->flags |= REQUEST_ZLP;
1713
1714 dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n",
1715 priv_ep->name);
1716 ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags);
1717 }
1718
1719 spin_unlock_irqrestore(&priv_dev->lock, flags);
1720 return ret;
1721}
1722
1723/**
1724 * cdns3_gadget_ep_dequeue Remove request from transfer queue
1725 * @ep: endpoint object associated with request
1726 * @request: request object
1727 *
1728 * Returns 0 on success, error code elsewhere
1729 */
1730int cdns3_gadget_ep_dequeue(struct usb_ep *ep,
1731 struct usb_request *request)
1732{
1733 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1734 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1735 struct usb_request *req, *req_temp;
1736 struct cdns3_request *priv_req;
1737 struct cdns3_trb *link_trb;
1738 unsigned long flags;
1739 int ret = 0;
1740
1741 if (!ep || !request || !ep->desc)
1742 return -EINVAL;
1743
1744 spin_lock_irqsave(&priv_dev->lock, flags);
1745
1746 priv_req = to_cdns3_request(request);
1747
1748 trace_cdns3_ep_dequeue(priv_req);
1749
1750 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
1751
1752 list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list,
1753 list) {
1754 if (request == req)
1755 goto found;
1756 }
1757
1758 list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list,
1759 list) {
1760 if (request == req)
1761 goto found;
1762 }
1763
1764 goto not_found;
1765
1766found:
1767
1768 if (priv_ep->wa1_trb == priv_req->trb)
1769 cdns3_wa1_restore_cycle_bit(priv_ep);
1770
1771 link_trb = priv_req->trb;
1772 cdns3_move_deq_to_next_trb(priv_req);
1773 cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET);
1774
1775 /* Update ring */
1776 request = cdns3_next_request(&priv_ep->deferred_req_list);
1777 if (request) {
1778 priv_req = to_cdns3_request(request);
1779
1780 link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
1781 (priv_req->start_trb * TRB_SIZE));
1782 link_trb->control = (link_trb->control & TRB_CYCLE) |
1783 TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE;
1784 } else {
1785 priv_ep->flags |= EP_UPDATE_EP_TRBADDR;
1786 }
1787
1788not_found:
1789 spin_unlock_irqrestore(&priv_dev->lock, flags);
1790 return ret;
1791}
1792
1793/**
1794 * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint
1795 * Should be called after acquiring spin_lock and selecting ep
1796 * @ep: endpoint object to set stall on.
1797 */
1798void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep)
1799{
1800 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1801
1802 trace_cdns3_halt(priv_ep, 1, 0);
1803
1804 if (!(priv_ep->flags & EP_STALLED)) {
1805 u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
1806
1807 if (!(ep_sts_reg & EP_STS_DBUSY))
1808 cdns3_ep_stall_flush(priv_ep);
1809 else
1810 priv_ep->flags |= EP_STALL_PENDING;
1811 }
1812}
1813
1814/**
1815 * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint
1816 * Should be called after acquiring spin_lock and selecting ep
1817 * @ep: endpoint object to clear stall on
1818 */
1819int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
1820{
1821 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1822 struct usb_request *request;
1823 int ret = 0;
1824 int val;
1825
1826 trace_cdns3_halt(priv_ep, 0, 0);
1827
1828 writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
1829
1830 /* wait for EPRST cleared */
1831 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
1832 !(val & EP_CMD_EPRST), 1, 100);
1833 if (ret)
1834 return -EINVAL;
1835
1836 priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
1837
1838 request = cdns3_next_request(&priv_ep->pending_req_list);
1839
1840 if (request)
1841 cdns3_rearm_transfer(priv_ep, 1);
1842
1843 cdns3_start_all_request(priv_dev, priv_ep);
1844 return ret;
1845}
1846
1847/**
1848 * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint
1849 * @ep: endpoint object to set/clear stall on
1850 * @value: 1 for set stall, 0 for clear stall
1851 *
1852 * Returns 0 on success, error code elsewhere
1853 */
1854int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1855{
1856 struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
1857 struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
1858 unsigned long flags;
1859 int ret = 0;
1860
1861 if (!(priv_ep->flags & EP_ENABLED))
1862 return -EPERM;
1863
1864 spin_lock_irqsave(&priv_dev->lock, flags);
1865
1866 cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
1867
1868 if (!value) {
1869 priv_ep->flags &= ~EP_WEDGE;
1870 ret = __cdns3_gadget_ep_clear_halt(priv_ep);
1871 } else {
1872 __cdns3_gadget_ep_set_halt(priv_ep);
1873 }
1874
1875 spin_unlock_irqrestore(&priv_dev->lock, flags);
1876
1877 return ret;
1878}
1879
1880extern const struct usb_ep_ops cdns3_gadget_ep0_ops;
1881
1882static const struct usb_ep_ops cdns3_gadget_ep_ops = {
1883 .enable = cdns3_gadget_ep_enable,
1884 .disable = cdns3_gadget_ep_disable,
1885 .alloc_request = cdns3_gadget_ep_alloc_request,
1886 .free_request = cdns3_gadget_ep_free_request,
1887 .queue = cdns3_gadget_ep_queue,
1888 .dequeue = cdns3_gadget_ep_dequeue,
1889 .set_halt = cdns3_gadget_ep_set_halt,
1890 .set_wedge = cdns3_gadget_ep_set_wedge,
1891};
1892
1893/**
1894 * cdns3_gadget_get_frame Returns number of actual ITP frame
1895 * @gadget: gadget object
1896 *
1897 * Returns number of actual ITP frame
1898 */
1899static int cdns3_gadget_get_frame(struct usb_gadget *gadget)
1900{
1901 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1902
1903 return readl(&priv_dev->regs->usb_itpn);
1904}
1905
1906int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
1907{
1908 enum usb_device_speed speed;
1909
1910 speed = cdns3_get_speed(priv_dev);
1911
1912 if (speed >= USB_SPEED_SUPER)
1913 return 0;
1914
1915 /* Start driving resume signaling to indicate remote wakeup. */
1916 writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
1917
1918 return 0;
1919}
1920
1921static int cdns3_gadget_wakeup(struct usb_gadget *gadget)
1922{
1923 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1924 unsigned long flags;
1925 int ret = 0;
1926
1927 spin_lock_irqsave(&priv_dev->lock, flags);
1928 ret = __cdns3_gadget_wakeup(priv_dev);
1929 spin_unlock_irqrestore(&priv_dev->lock, flags);
1930 return ret;
1931}
1932
1933static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget,
1934 int is_selfpowered)
1935{
1936 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1937 unsigned long flags;
1938
1939 spin_lock_irqsave(&priv_dev->lock, flags);
1940 priv_dev->is_selfpowered = !!is_selfpowered;
1941 spin_unlock_irqrestore(&priv_dev->lock, flags);
1942 return 0;
1943}
1944
1945static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
1946{
1947 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
1948
1949 if (is_on)
1950 writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
1951 else
1952 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
1953
1954 return 0;
1955}
1956
1957static void cdns3_gadget_config(struct cdns3_device *priv_dev)
1958{
1959 struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
1960 u32 reg;
1961
1962 cdns3_ep0_config(priv_dev);
1963
1964 /* enable interrupts for endpoint 0 (in and out) */
1965 writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, &regs->ep_ien);
1966
1967 /*
1968 * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
1969 * revision of controller.
1970 */
1971 if (priv_dev->dev_ver == DEV_VER_TI_V1) {
1972 reg = readl(&regs->dbg_link1);
1973
1974 reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
1975 reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
1976 DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
1977 writel(reg, &regs->dbg_link1);
1978 }
1979
1980 /*
1981 * By default some platforms has set protected access to memory.
1982 * This cause problem with cache, so driver restore non-secure
1983 * access to memory.
1984 */
1985 reg = readl(&regs->dma_axi_ctrl);
1986 reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
1987 DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
1988 writel(reg, &regs->dma_axi_ctrl);
1989
1990 /* enable generic interrupt*/
1991 writel(USB_IEN_INIT, &regs->usb_ien);
1992 writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf);
1993
1994 cdns3_configure_dmult(priv_dev, NULL);
1995
1996 cdns3_gadget_pullup(&priv_dev->gadget, 1);
1997}
1998
1999/**
2000 * cdns3_gadget_udc_start Gadget start
2001 * @gadget: gadget object
2002 * @driver: driver which operates on this gadget
2003 *
2004 * Returns 0 on success, error code elsewhere
2005 */
2006static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
2007 struct usb_gadget_driver *driver)
2008{
2009 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2010 unsigned long flags;
2011
2012 spin_lock_irqsave(&priv_dev->lock, flags);
2013 priv_dev->gadget_driver = driver;
2014 cdns3_gadget_config(priv_dev);
2015 spin_unlock_irqrestore(&priv_dev->lock, flags);
2016 return 0;
2017}
2018
2019/**
2020 * cdns3_gadget_udc_stop Stops gadget
2021 * @gadget: gadget object
2022 *
2023 * Returns 0
2024 */
2025static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
2026{
2027 struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
2028 struct cdns3_endpoint *priv_ep;
2029 u32 bEndpointAddress;
2030 struct usb_ep *ep;
2031 int ret = 0;
2032 int val;
2033
2034 priv_dev->gadget_driver = NULL;
2035
2036 priv_dev->onchip_used_size = 0;
2037 priv_dev->out_mem_is_allocated = 0;
2038 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2039
2040 list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
2041 priv_ep = ep_to_cdns3_ep(ep);
2042 bEndpointAddress = priv_ep->num | priv_ep->dir;
2043 cdns3_select_ep(priv_dev, bEndpointAddress);
2044 writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
2045 readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
2046 !(val & EP_CMD_EPRST), 1, 100);
2047 }
2048
2049 /* disable interrupt for device */
2050 writel(0, &priv_dev->regs->usb_ien);
2051 writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
2052
2053 return ret;
2054}
2055
2056static const struct usb_gadget_ops cdns3_gadget_ops = {
2057 .get_frame = cdns3_gadget_get_frame,
2058 .wakeup = cdns3_gadget_wakeup,
2059 .set_selfpowered = cdns3_gadget_set_selfpowered,
2060 .pullup = cdns3_gadget_pullup,
2061 .udc_start = cdns3_gadget_udc_start,
2062 .udc_stop = cdns3_gadget_udc_stop,
2063 .match_ep = cdns3_gadget_match_ep,
2064};
2065
2066static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
2067{
2068 int i;
2069
2070 /* ep0 OUT point to ep0 IN. */
2071 priv_dev->eps[16] = NULL;
2072
2073 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
2074 if (priv_dev->eps[i]) {
2075 cdns3_free_trb_pool(priv_dev->eps[i]);
2076 devm_kfree(priv_dev->dev, priv_dev->eps[i]);
2077 }
2078}
2079
2080/**
2081 * cdns3_init_eps Initializes software endpoints of gadget
2082 * @cdns3: extended gadget object
2083 *
2084 * Returns 0 on success, error code elsewhere
2085 */
2086static int cdns3_init_eps(struct cdns3_device *priv_dev)
2087{
2088 u32 ep_enabled_reg, iso_ep_reg;
2089 struct cdns3_endpoint *priv_ep;
2090 int ep_dir, ep_number;
2091 u32 ep_mask;
2092 int ret = 0;
2093 int i;
2094
2095 /* Read it from USB_CAP3 to USB_CAP5 */
2096 ep_enabled_reg = readl(&priv_dev->regs->usb_cap3);
2097 iso_ep_reg = readl(&priv_dev->regs->usb_cap4);
2098
2099 dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n");
2100
2101 for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
2102 ep_dir = i >> 4; /* i div 16 */
2103 ep_number = i & 0xF; /* i % 16 */
2104 ep_mask = BIT(i);
2105
2106 if (!(ep_enabled_reg & ep_mask))
2107 continue;
2108
2109 if (ep_dir && !ep_number) {
2110 priv_dev->eps[i] = priv_dev->eps[0];
2111 continue;
2112 }
2113
2114 priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep),
2115 GFP_KERNEL);
2116 if (!priv_ep) {
2117 ret = -ENOMEM;
2118 goto err;
2119 }
2120
2121 /* set parent of endpoint object */
2122 priv_ep->cdns3_dev = priv_dev;
2123 priv_dev->eps[i] = priv_ep;
2124 priv_ep->num = ep_number;
2125 priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT;
2126
2127 if (!ep_number) {
2128 ret = cdns3_init_ep0(priv_dev, priv_ep);
2129 if (ret) {
2130 dev_err(priv_dev->dev, "Failed to init ep0\n");
2131 goto err;
2132 }
2133 } else {
2134 snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s",
2135 ep_number, !!ep_dir ? "in" : "out");
2136 priv_ep->endpoint.name = priv_ep->name;
2137
2138 usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
2139 CDNS3_EP_MAX_PACKET_LIMIT);
2140 priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS;
2141 priv_ep->endpoint.ops = &cdns3_gadget_ep_ops;
2142 if (ep_dir)
2143 priv_ep->endpoint.caps.dir_in = 1;
2144 else
2145 priv_ep->endpoint.caps.dir_out = 1;
2146
2147 if (iso_ep_reg & ep_mask)
2148 priv_ep->endpoint.caps.type_iso = 1;
2149
2150 priv_ep->endpoint.caps.type_bulk = 1;
2151 priv_ep->endpoint.caps.type_int = 1;
2152
2153 list_add_tail(&priv_ep->endpoint.ep_list,
2154 &priv_dev->gadget.ep_list);
2155 }
2156
2157 priv_ep->flags = 0;
2158
2159 dev_info(priv_dev->dev, "Initialized %s support: %s %s\n",
2160 priv_ep->name,
2161 priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "",
2162 priv_ep->endpoint.caps.type_iso ? "ISO" : "");
2163
2164 INIT_LIST_HEAD(&priv_ep->pending_req_list);
2165 INIT_LIST_HEAD(&priv_ep->deferred_req_list);
2166 }
2167
2168 return 0;
2169err:
2170 cdns3_free_all_eps(priv_dev);
2171 return -ENOMEM;
2172}
2173
2174void cdns3_gadget_exit(struct cdns3 *cdns)
2175{
2176 struct cdns3_device *priv_dev;
2177
2178 priv_dev = cdns->gadget_dev;
2179
2180 devm_free_irq(cdns->dev, cdns->dev_irq, cdns);
2181
2182 pm_runtime_mark_last_busy(cdns->dev);
2183 pm_runtime_put_autosuspend(cdns->dev);
2184
2185 usb_del_gadget_udc(&priv_dev->gadget);
2186
2187 cdns3_free_all_eps(priv_dev);
2188
2189 while (!list_empty(&priv_dev->aligned_buf_list)) {
2190 struct cdns3_aligned_buf *buf;
2191
2192 buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list);
2193 dma_free_coherent(priv_dev->sysdev, buf->size,
2194 buf->buf,
2195 buf->dma);
2196
2197 list_del(&buf->list);
2198 kfree(buf);
2199 }
2200
2201 dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
2202 priv_dev->setup_dma);
2203
2204 kfree(priv_dev->zlp_buf);
2205 kfree(priv_dev);
2206 cdns->gadget_dev = NULL;
2207 cdns3_drd_switch_gadget(cdns, 0);
2208}
2209
2210static int cdns3_gadget_start(struct cdns3 *cdns)
2211{
2212 struct cdns3_device *priv_dev;
2213 u32 max_speed;
2214 int ret;
2215
2216 priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
2217 if (!priv_dev)
2218 return -ENOMEM;
2219
2220 cdns->gadget_dev = priv_dev;
2221 priv_dev->sysdev = cdns->dev;
2222 priv_dev->dev = cdns->dev;
2223 priv_dev->regs = cdns->dev_regs;
2224
2225 device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size",
2226 &priv_dev->onchip_buffers);
2227
2228 if (priv_dev->onchip_buffers <= 0) {
2229 u32 reg = readl(&priv_dev->regs->usb_cap2);
2230
2231 priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
2232 }
2233
2234 if (!priv_dev->onchip_buffers)
2235 priv_dev->onchip_buffers = 256;
2236
2237 max_speed = usb_get_maximum_speed(cdns->dev);
2238
2239 /* Check the maximum_speed parameter */
2240 switch (max_speed) {
2241 case USB_SPEED_FULL:
2242 writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
2243 break;
2244 case USB_SPEED_HIGH:
2245 writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
2246 break;
2247 case USB_SPEED_SUPER:
2248 break;
2249 default:
2250 dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
2251 max_speed);
2252 /* fall through */
2253 case USB_SPEED_UNKNOWN:
2254 /* default to superspeed */
2255 max_speed = USB_SPEED_SUPER;
2256 break;
2257 }
2258
2259 /* fill gadget fields */
2260 priv_dev->gadget.max_speed = max_speed;
2261 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2262 priv_dev->gadget.ops = &cdns3_gadget_ops;
2263 priv_dev->gadget.name = "usb-ss-gadget";
2264 priv_dev->gadget.sg_supported = 1;
2265 priv_dev->gadget.quirk_avoids_skb_reserve = 1;
2266
2267 spin_lock_init(&priv_dev->lock);
2268 INIT_WORK(&priv_dev->pending_status_wq,
2269 cdns3_pending_setup_status_handler);
2270
2271 INIT_WORK(&priv_dev->aligned_buf_wq,
2272 cdns3_free_aligned_request_buf);
2273
2274 /* initialize endpoint container */
2275 INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
2276 INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
2277
2278 ret = cdns3_init_eps(priv_dev);
2279 if (ret) {
2280 dev_err(priv_dev->dev, "Failed to create endpoints\n");
2281 goto err1;
2282 }
2283
2284 /* allocate memory for setup packet buffer */
2285 priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8,
2286 &priv_dev->setup_dma, GFP_DMA);
2287 if (!priv_dev->setup_buf) {
2288 ret = -ENOMEM;
2289 goto err2;
2290 }
2291
2292 priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
2293
2294 dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
2295 readl(&priv_dev->regs->usb_cap6));
2296 dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
2297 readl(&priv_dev->regs->usb_cap1));
2298 dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n",
2299 readl(&priv_dev->regs->usb_cap2));
2300
2301 priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
2302
2303 priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
2304 if (!priv_dev->zlp_buf) {
2305 ret = -ENOMEM;
2306 goto err3;
2307 }
2308
2309 /* add USB gadget device */
2310 ret = usb_add_gadget_udc(priv_dev->dev, &priv_dev->gadget);
2311 if (ret < 0) {
2312 dev_err(priv_dev->dev,
2313 "Failed to register USB device controller\n");
2314 goto err4;
2315 }
2316
2317 return 0;
2318err4:
2319 kfree(priv_dev->zlp_buf);
2320err3:
2321 dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
2322 priv_dev->setup_dma);
2323err2:
2324 cdns3_free_all_eps(priv_dev);
2325err1:
2326 cdns->gadget_dev = NULL;
2327 return ret;
2328}
2329
2330static int __cdns3_gadget_init(struct cdns3 *cdns)
2331{
2332 struct cdns3_device *priv_dev;
2333 int ret = 0;
2334
2335 cdns3_drd_switch_gadget(cdns, 1);
2336 pm_runtime_get_sync(cdns->dev);
2337
2338 ret = cdns3_gadget_start(cdns);
2339 if (ret)
2340 return ret;
2341
2342 priv_dev = cdns->gadget_dev;
2343
2344 /*
2345 * Because interrupt line can be shared with other components in
2346 * driver it can't use IRQF_ONESHOT flag here.
2347 */
2348 ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq,
2349 cdns3_device_irq_handler,
2350 cdns3_device_thread_irq_handler,
2351 IRQF_SHARED, dev_name(cdns->dev), cdns);
2352
2353 if (ret)
2354 goto err0;
2355
2356 return 0;
2357err0:
2358 cdns3_gadget_exit(cdns);
2359 return ret;
2360}
2361
2362static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup)
2363{
2364 struct cdns3_device *priv_dev = cdns->gadget_dev;
2365
2366 cdns3_disconnect_gadget(priv_dev);
2367
2368 priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
2369 usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
2370 cdns3_hw_reset_eps_config(priv_dev);
2371
2372 /* disable interrupt for device */
2373 writel(0, &priv_dev->regs->usb_ien);
2374
2375 cdns3_gadget_pullup(&priv_dev->gadget, 0);
2376
2377 return 0;
2378}
2379
2380static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated)
2381{
2382 struct cdns3_device *priv_dev = cdns->gadget_dev;
2383
2384 if (!priv_dev->gadget_driver)
2385 return 0;
2386
2387 cdns3_gadget_config(priv_dev);
2388
2389 return 0;
2390}
2391
2392/**
2393 * cdns3_gadget_init - initialize device structure
2394 *
2395 * cdns: cdns3 instance
2396 *
2397 * This function initializes the gadget.
2398 */
2399int cdns3_gadget_init(struct cdns3 *cdns)
2400{
2401 struct cdns3_role_driver *rdrv;
2402
2403 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
2404 if (!rdrv)
2405 return -ENOMEM;
2406
2407 rdrv->start = __cdns3_gadget_init;
2408 rdrv->stop = cdns3_gadget_exit;
2409 rdrv->suspend = cdns3_gadget_suspend;
2410 rdrv->resume = cdns3_gadget_resume;
2411 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
2412 rdrv->name = "gadget";
2413 cdns->roles[USB_ROLE_DEVICE] = rdrv;
2414
2415 return 0;
2416}
diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h
new file mode 100644
index 000000000000..a4652d2e9bf9
--- /dev/null
+++ b/drivers/usb/cdns3/gadget.h
@@ -0,0 +1,1325 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * USBSS device controller driver header file
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 * Pawel Jez <pjez@cadence.com>
10 * Peter Chen <peter.chen@nxp.com>
11 */
12#ifndef __LINUX_CDNS3_GADGET
13#define __LINUX_CDNS3_GADGET
14#include <linux/usb/gadget.h>
15
16/*
17 * USBSS-DEV register interface.
18 * This corresponds to the USBSS Device Controller Interface
19 */
20
21/**
22 * struct cdns3_usb_regs - device controller registers.
23 * @usb_conf: Global Configuration.
24 * @usb_sts: Global Status.
25 * @usb_cmd: Global Command.
26 * @usb_itpn: ITP/SOF number.
27 * @usb_lpm: Global Command.
28 * @usb_ien: USB Interrupt Enable.
29 * @usb_ists: USB Interrupt Status.
30 * @ep_sel: Endpoint Select.
31 * @ep_traddr: Endpoint Transfer Ring Address.
32 * @ep_cfg: Endpoint Configuration.
33 * @ep_cmd: Endpoint Command.
34 * @ep_sts: Endpoint Status.
35 * @ep_sts_sid: Endpoint Status.
36 * @ep_sts_en: Endpoint Status Enable.
37 * @drbl: Doorbell.
38 * @ep_ien: EP Interrupt Enable.
39 * @ep_ists: EP Interrupt Status.
40 * @usb_pwr: Global Power Configuration.
41 * @usb_conf2: Global Configuration 2.
42 * @usb_cap1: Capability 1.
43 * @usb_cap2: Capability 2.
44 * @usb_cap3: Capability 3.
45 * @usb_cap4: Capability 4.
46 * @usb_cap5: Capability 5.
47 * @usb_cap6: Capability 6.
48 * @usb_cpkt1: Custom Packet 1.
49 * @usb_cpkt2: Custom Packet 2.
50 * @usb_cpkt3: Custom Packet 3.
51 * @ep_dma_ext_addr: Upper address for DMA operations.
52 * @buf_addr: Address for On-chip Buffer operations.
53 * @buf_data: Data for On-chip Buffer operations.
54 * @buf_ctrl: On-chip Buffer Access Control.
55 * @dtrans: DMA Transfer Mode.
56 * @tdl_from_trb: Source of TD Configuration.
57 * @tdl_beh: TDL Behavior Configuration.
58 * @ep_tdl: Endpoint TDL.
59 * @tdl_beh2: TDL Behavior 2 Configuration.
60 * @dma_adv_td: DMA Advance TD Configuration.
61 * @reserved1: Reserved.
62 * @cfg_regs: Configuration.
63 * @reserved2: Reserved.
64 * @dma_axi_ctrl: AXI Control.
65 * @dma_axi_id: AXI ID register.
66 * @dma_axi_cap: AXI Capability.
67 * @dma_axi_ctrl0: AXI Control 0.
68 * @dma_axi_ctrl1: AXI Control 1.
69 */
70struct cdns3_usb_regs {
71 __le32 usb_conf;
72 __le32 usb_sts;
73 __le32 usb_cmd;
74 __le32 usb_itpn;
75 __le32 usb_lpm;
76 __le32 usb_ien;
77 __le32 usb_ists;
78 __le32 ep_sel;
79 __le32 ep_traddr;
80 __le32 ep_cfg;
81 __le32 ep_cmd;
82 __le32 ep_sts;
83 __le32 ep_sts_sid;
84 __le32 ep_sts_en;
85 __le32 drbl;
86 __le32 ep_ien;
87 __le32 ep_ists;
88 __le32 usb_pwr;
89 __le32 usb_conf2;
90 __le32 usb_cap1;
91 __le32 usb_cap2;
92 __le32 usb_cap3;
93 __le32 usb_cap4;
94 __le32 usb_cap5;
95 __le32 usb_cap6;
96 __le32 usb_cpkt1;
97 __le32 usb_cpkt2;
98 __le32 usb_cpkt3;
99 __le32 ep_dma_ext_addr;
100 __le32 buf_addr;
101 __le32 buf_data;
102 __le32 buf_ctrl;
103 __le32 dtrans;
104 __le32 tdl_from_trb;
105 __le32 tdl_beh;
106 __le32 ep_tdl;
107 __le32 tdl_beh2;
108 __le32 dma_adv_td;
109 __le32 reserved1[26];
110 __le32 cfg_reg1;
111 __le32 dbg_link1;
112 __le32 dbg_link2;
113 __le32 cfg_regs[74];
114 __le32 reserved2[51];
115 __le32 dma_axi_ctrl;
116 __le32 dma_axi_id;
117 __le32 dma_axi_cap;
118 __le32 dma_axi_ctrl0;
119 __le32 dma_axi_ctrl1;
120};
121
122/* USB_CONF - bitmasks */
123/* Reset USB device configuration. */
124#define USB_CONF_CFGRST BIT(0)
125/* Set Configuration. */
126#define USB_CONF_CFGSET BIT(1)
127/* Disconnect USB device in SuperSpeed. */
128#define USB_CONF_USB3DIS BIT(3)
129/* Disconnect USB device in HS/FS */
130#define USB_CONF_USB2DIS BIT(4)
131/* Little Endian access - default */
132#define USB_CONF_LENDIAN BIT(5)
133/*
134 * Big Endian access. Driver assume that byte order for
135 * SFRs access always is as Little Endian so this bit
136 * is not used.
137 */
138#define USB_CONF_BENDIAN BIT(6)
139/* Device software reset. */
140#define USB_CONF_SWRST BIT(7)
141/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
142#define USB_CONF_DSING BIT(8)
143/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
144#define USB_CONF_DMULT BIT(9)
145/* DMA clock turn-off enable. */
146#define USB_CONF_DMAOFFEN BIT(10)
147/* DMA clock turn-off disable. */
148#define USB_CONF_DMAOFFDS BIT(11)
149/* Clear Force Full Speed. */
150#define USB_CONF_CFORCE_FS BIT(12)
151/* Set Force Full Speed. */
152#define USB_CONF_SFORCE_FS BIT(13)
153/* Device enable. */
154#define USB_CONF_DEVEN BIT(14)
155/* Device disable. */
156#define USB_CONF_DEVDS BIT(15)
157/* L1 LPM state entry enable (used in HS/FS mode). */
158#define USB_CONF_L1EN BIT(16)
159/* L1 LPM state entry disable (used in HS/FS mode). */
160#define USB_CONF_L1DS BIT(17)
161/* USB 2.0 clock gate disable. */
162#define USB_CONF_CLK2OFFEN BIT(18)
163/* USB 2.0 clock gate enable. */
164#define USB_CONF_CLK2OFFDS BIT(19)
165/* L0 LPM state entry request (used in HS/FS mode). */
166#define USB_CONF_LGO_L0 BIT(20)
167/* USB 3.0 clock gate disable. */
168#define USB_CONF_CLK3OFFEN BIT(21)
169/* USB 3.0 clock gate enable. */
170#define USB_CONF_CLK3OFFDS BIT(22)
171/* Bit 23 is reserved*/
172/* U1 state entry enable (used in SS mode). */
173#define USB_CONF_U1EN BIT(24)
174/* U1 state entry disable (used in SS mode). */
175#define USB_CONF_U1DS BIT(25)
176/* U2 state entry enable (used in SS mode). */
177#define USB_CONF_U2EN BIT(26)
178/* U2 state entry disable (used in SS mode). */
179#define USB_CONF_U2DS BIT(27)
180/* U0 state entry request (used in SS mode). */
181#define USB_CONF_LGO_U0 BIT(28)
182/* U1 state entry request (used in SS mode). */
183#define USB_CONF_LGO_U1 BIT(29)
184/* U2 state entry request (used in SS mode). */
185#define USB_CONF_LGO_U2 BIT(30)
186/* SS.Inactive state entry request (used in SS mode) */
187#define USB_CONF_LGO_SSINACT BIT(31)
188
189/* USB_STS - bitmasks */
190/*
191 * Configuration status.
192 * 1 - device is in the configured state.
193 * 0 - device is not configured.
194 */
195#define USB_STS_CFGSTS_MASK BIT(0)
196#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
197/*
198 * On-chip memory overflow.
199 * 0 - On-chip memory status OK.
200 * 1 - On-chip memory overflow.
201 */
202#define USB_STS_OV_MASK BIT(1)
203#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
204/*
205 * SuperSpeed connection status.
206 * 0 - USB in SuperSpeed mode disconnected.
207 * 1 - USB in SuperSpeed mode connected.
208 */
209#define USB_STS_USB3CONS_MASK BIT(2)
210#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
211/*
212 * DMA transfer configuration status.
213 * 0 - single request.
214 * 1 - multiple TRB chain
215 * Supported only for controller version < DEV_VER_V3
216 */
217#define USB_STS_DTRANS_MASK BIT(3)
218#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
219/*
220 * Device speed.
221 * 0 - Undefined (value after reset).
222 * 1 - Low speed
223 * 2 - Full speed
224 * 3 - High speed
225 * 4 - Super speed
226 */
227#define USB_STS_USBSPEED_MASK GENMASK(6, 4)
228#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
229#define USB_STS_LS (0x1 << 4)
230#define USB_STS_FS (0x2 << 4)
231#define USB_STS_HS (0x3 << 4)
232#define USB_STS_SS (0x4 << 4)
233#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
234#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
235#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
236#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
237#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
238/*
239 * Endianness for SFR access.
240 * 0 - Little Endian order (default after hardware reset).
241 * 1 - Big Endian order
242 */
243#define USB_STS_ENDIAN_MASK BIT(7)
244#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
245/*
246 * HS/FS clock turn-off status.
247 * 0 - hsfs clock is always on.
248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
249 * (default after hardware reset).
250 */
251#define USB_STS_CLK2OFF_MASK BIT(8)
252#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
253/*
254 * PCLK clock turn-off status.
255 * 0 - pclk clock is always on.
256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
257 * (default after hardware reset).
258 */
259#define USB_STS_CLK3OFF_MASK BIT(9)
260#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
261/*
262 * Controller in reset state.
263 * 0 - Internal reset is active.
264 * 1 - Internal reset is not active and controller is fully operational.
265 */
266#define USB_STS_IN_RST_MASK BIT(10)
267#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
268/*
269 * Status of the "TDL calculation basing on TRB" feature.
270 * 0 - disabled
271 * 1 - enabled
272 * Supported only for DEV_VER_V2 controller version.
273 */
274#define USB_STS_TDL_TRB_ENABLED BIT(11)
275/*
276 * Device enable Status.
277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
278 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
279 */
280#define USB_STS_DEVS_MASK BIT(14)
281#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
282/*
283 * Address status.
284 * 0 - USB device is default state.
285 * 1 - USB device is at least in address state.
286 */
287#define USB_STS_ADDRESSED_MASK BIT(15)
288#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
289/*
290 * L1 LPM state enable status (used in HS/FS mode).
291 * 0 - Entering to L1 LPM state disabled.
292 * 1 - Entering to L1 LPM state enabled.
293 */
294#define USB_STS_L1ENS_MASK BIT(16)
295#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
296/*
297 * Internal VBUS connection status (used both in HS/FS and SS mode).
298 * 0 - internal VBUS is not detected.
299 * 1 - internal VBUS is detected.
300 */
301#define USB_STS_VBUSS_MASK BIT(17)
302#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
303/*
304 * HS/FS LPM state (used in FS/HS mode).
305 * 0 - L0 State
306 * 1 - L1 State
307 * 2 - L2 State
308 * 3 - L3 State
309 */
310#define USB_STS_LPMST_MASK GENMASK(19, 18)
311#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
312#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
313#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
314#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
315/*
316 * Disable HS status (used in FS/HS mode).
317 * 0 - the disconnect bit for HS/FS mode is set .
318 * 1 - the disconnect bit for HS/FS mode is not set.
319 */
320#define USB_STS_USB2CONS_MASK BIT(20)
321#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
322/*
323 * HS/FS mode connection status (used in FS/HS mode).
324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
325 * 1 - High Speed operations in USB2.0 (FS/HS).
326 */
327#define USB_STS_DISABLE_HS_MASK BIT(21)
328#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
329/*
330 * U1 state enable status (used in SS mode).
331 * 0 - Entering to U1 state disabled.
332 * 1 - Entering to U1 state enabled.
333 */
334#define USB_STS_U1ENS_MASK BIT(24)
335#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
336/*
337 * U2 state enable status (used in SS mode).
338 * 0 - Entering to U2 state disabled.
339 * 1 - Entering to U2 state enabled.
340 */
341#define USB_STS_U2ENS_MASK BIT(25)
342#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
343/*
344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
345 * SuperSpeed link state
346 */
347#define USB_STS_LST_MASK GENMASK(29, 26)
348#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
349#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
350#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
351#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
352#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
353#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
354#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
355#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
356#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
357#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
358#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
359#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
360/*
361 * DMA clock turn-off status.
362 * 0 - DMA clock is always on (default after hardware reset).
363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
364 */
365#define USB_STS_DMAOFF_MASK BIT(30)
366#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
367/*
368 * SFR Endian status.
369 * 0 - Little Endian order (default after hardware reset).
370 * 1 - Big Endian order.
371 */
372#define USB_STS_ENDIAN2_MASK BIT(31)
373#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
374
375/* USB_CMD - bitmasks */
376/* Set Function Address */
377#define USB_CMD_SET_ADDR BIT(0)
378/*
379 * Function Address This field is saved to the device only when the field
380 * SET_ADDR is set '1 ' during write to USB_CMD register.
381 * Software is responsible for entering the address of the device during
382 * SET_ADDRESS request service. This field should be set immediately after
383 * the SETUP packet is decoded, and prior to confirmation of the status phase
384 */
385#define USB_CMD_FADDR_MASK GENMASK(7, 1)
386#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
387/* Send Function Wake Device Notification TP (used only in SS mode). */
388#define USB_CMD_SDNFW BIT(8)
389/* Set Test Mode (used only in HS/FS mode). */
390#define USB_CMD_STMODE BIT(9)
391/* Test mode selector (used only in HS/FS mode) */
392#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
393#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
394/*
395 * Send Latency Tolerance Message Device Notification TP (used only
396 * in SS mode).
397 */
398#define USB_CMD_SDNLTM BIT(12)
399/* Send Custom Transaction Packet (used only in SS mode) */
400#define USB_CMD_SPKT BIT(13)
401/*Device Notification 'Function Wake' - Interface value (only in SS mode. */
402#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
403#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
404/*
405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
406 * (used only in SS mode).
407 */
408#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
409#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
410
411/* USB_ITPN - bitmasks */
412/*
413 * ITP(SS) / SOF (HS/FS) number
414 * In SS mode this field represent number of last ITP received from host.
415 * In HS/FS mode this field represent number of last SOF received from host.
416 */
417#define USB_ITPN_MASK GENMASK(13, 0)
418#define USB_ITPN(p) ((p) & USB_ITPN_MASK)
419
420/* USB_LPM - bitmasks */
421/* Host Initiated Resume Duration. */
422#define USB_LPM_HIRD_MASK GENMASK(3, 0)
423#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
424/* Remote Wakeup Enable (bRemoteWake). */
425#define USB_LPM_BRW BIT(4)
426
427/* USB_IEN - bitmasks */
428/* SS connection interrupt enable */
429#define USB_IEN_CONIEN BIT(0)
430/* SS disconnection interrupt enable. */
431#define USB_IEN_DISIEN BIT(1)
432/* USB SS warm reset interrupt enable. */
433#define USB_IEN_UWRESIEN BIT(2)
434/* USB SS hot reset interrupt enable */
435#define USB_IEN_UHRESIEN BIT(3)
436/* SS link U3 state enter interrupt enable (suspend).*/
437#define USB_IEN_U3ENTIEN BIT(4)
438/* SS link U3 state exit interrupt enable (wakeup). */
439#define USB_IEN_U3EXTIEN BIT(5)
440/* SS link U2 state enter interrupt enable.*/
441#define USB_IEN_U2ENTIEN BIT(6)
442/* SS link U2 state exit interrupt enable.*/
443#define USB_IEN_U2EXTIEN BIT(7)
444/* SS link U1 state enter interrupt enable.*/
445#define USB_IEN_U1ENTIEN BIT(8)
446/* SS link U1 state exit interrupt enable.*/
447#define USB_IEN_U1EXTIEN BIT(9)
448/* ITP/SOF packet detected interrupt enable.*/
449#define USB_IEN_ITPIEN BIT(10)
450/* Wakeup interrupt enable.*/
451#define USB_IEN_WAKEIEN BIT(11)
452/* Send Custom Packet interrupt enable.*/
453#define USB_IEN_SPKTIEN BIT(12)
454/* HS/FS mode connection interrupt enable.*/
455#define USB_IEN_CON2IEN BIT(16)
456/* HS/FS mode disconnection interrupt enable.*/
457#define USB_IEN_DIS2IEN BIT(17)
458/* USB reset (HS/FS mode) interrupt enable.*/
459#define USB_IEN_U2RESIEN BIT(18)
460/* LPM L2 state enter interrupt enable.*/
461#define USB_IEN_L2ENTIEN BIT(20)
462/* LPM L2 state exit interrupt enable.*/
463#define USB_IEN_L2EXTIEN BIT(21)
464/* LPM L1 state enter interrupt enable.*/
465#define USB_IEN_L1ENTIEN BIT(24)
466/* LPM L1 state exit interrupt enable.*/
467#define USB_IEN_L1EXTIEN BIT(25)
468/* Configuration reset interrupt enable.*/
469#define USB_IEN_CFGRESIEN BIT(26)
470/* Start of the USB SS warm reset interrupt enable.*/
471#define USB_IEN_UWRESSIEN BIT(28)
472/* End of the USB SS warm reset interrupt enable.*/
473#define USB_IEN_UWRESEIEN BIT(29)
474
475#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
476 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
477 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
478 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
479
480/* USB_ISTS - bitmasks */
481/* SS Connection detected. */
482#define USB_ISTS_CONI BIT(0)
483/* SS Disconnection detected. */
484#define USB_ISTS_DISI BIT(1)
485/* UUSB warm reset detectede. */
486#define USB_ISTS_UWRESI BIT(2)
487/* USB hot reset detected. */
488#define USB_ISTS_UHRESI BIT(3)
489/* U3 link state enter detected (suspend).*/
490#define USB_ISTS_U3ENTI BIT(4)
491/* U3 link state exit detected (wakeup). */
492#define USB_ISTS_U3EXTI BIT(5)
493/* U2 link state enter detected.*/
494#define USB_ISTS_U2ENTI BIT(6)
495/* U2 link state exit detected.*/
496#define USB_ISTS_U2EXTI BIT(7)
497/* U1 link state enter detected.*/
498#define USB_ISTS_U1ENTI BIT(8)
499/* U1 link state exit detected.*/
500#define USB_ISTS_U1EXTI BIT(9)
501/* ITP/SOF packet detected.*/
502#define USB_ISTS_ITPI BIT(10)
503/* Wakeup detected.*/
504#define USB_ISTS_WAKEI BIT(11)
505/* Send Custom Packet detected.*/
506#define USB_ISTS_SPKTI BIT(12)
507/* HS/FS mode connection detected.*/
508#define USB_ISTS_CON2I BIT(16)
509/* HS/FS mode disconnection detected.*/
510#define USB_ISTS_DIS2I BIT(17)
511/* USB reset (HS/FS mode) detected.*/
512#define USB_ISTS_U2RESI BIT(18)
513/* LPM L2 state enter detected.*/
514#define USB_ISTS_L2ENTI BIT(20)
515/* LPM L2 state exit detected.*/
516#define USB_ISTS_L2EXTI BIT(21)
517/* LPM L1 state enter detected.*/
518#define USB_ISTS_L1ENTI BIT(24)
519/* LPM L1 state exit detected.*/
520#define USB_ISTS_L1EXTI BIT(25)
521/* USB configuration reset detected.*/
522#define USB_ISTS_CFGRESI BIT(26)
523/* Start of the USB warm reset detected.*/
524#define USB_ISTS_UWRESSI BIT(28)
525/* End of the USB warm reset detected.*/
526#define USB_ISTS_UWRESEI BIT(29)
527
528/* USB_SEL - bitmasks */
529#define EP_SEL_EPNO_MASK GENMASK(3, 0)
530/* Endpoint number. */
531#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
532/* Endpoint direction bit - 0 - OUT, 1 - IN. */
533#define EP_SEL_DIR BIT(7)
534
535#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
536#define select_ep_out (EP_SEL_EPNO(p))
537
538/* EP_TRADDR - bitmasks */
539/* Transfer Ring address. */
540#define EP_TRADDR_TRADDR(p) ((p))
541
542/* EP_CFG - bitmasks */
543/* Endpoint enable */
544#define EP_CFG_ENABLE BIT(0)
545/*
546 * Endpoint type.
547 * 1 - isochronous
548 * 2 - bulk
549 * 3 - interrupt
550 */
551#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
552#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
553/* Stream support enable (only in SS mode). */
554#define EP_CFG_STREAM_EN BIT(3)
555/* TDL check (only in SS mode for BULK EP). */
556#define EP_CFG_TDL_CHK BIT(4)
557/* SID check (only in SS mode for BULK OUT EP). */
558#define EP_CFG_SID_CHK BIT(5)
559/* DMA transfer endianness. */
560#define EP_CFG_EPENDIAN BIT(7)
561/* Max burst size (used only in SS mode). */
562#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
563#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
564/* ISO max burst. */
565#define EP_CFG_MULT_MASK GENMASK(15, 14)
566#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
567/* ISO max burst. */
568#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
569#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
570/* Max number of buffered packets. */
571#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
572#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
573
574/* EP_CMD - bitmasks */
575/* Endpoint reset. */
576#define EP_CMD_EPRST BIT(0)
577/* Endpoint STALL set. */
578#define EP_CMD_SSTALL BIT(1)
579/* Endpoint STALL clear. */
580#define EP_CMD_CSTALL BIT(2)
581/* Send ERDY TP. */
582#define EP_CMD_ERDY BIT(3)
583/* Request complete. */
584#define EP_CMD_REQ_CMPL BIT(5)
585/* Transfer descriptor ready. */
586#define EP_CMD_DRDY BIT(6)
587/* Data flush. */
588#define EP_CMD_DFLUSH BIT(7)
589/*
590 * Transfer Descriptor Length write (used only for Bulk Stream capable
591 * endpoints in SS mode).
592 * Bit Removed from DEV_VER_V3 controller version.
593 */
594#define EP_CMD_STDL BIT(8)
595/*
596 * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
597 * Bits Removed from DEV_VER_V3 controller version.
598 */
599#define EP_CMD_TDL_MASK GENMASK(15, 9)
600#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
601#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
602
603/* ERDY Stream ID value (used in SS mode). */
604#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
605#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
606
607/* EP_STS - bitmasks */
608/* Setup transfer complete. */
609#define EP_STS_SETUP BIT(0)
610/* Endpoint STALL status. */
611#define EP_STS_STALL(p) ((p) & BIT(1))
612/* Interrupt On Complete. */
613#define EP_STS_IOC BIT(2)
614/* Interrupt on Short Packet. */
615#define EP_STS_ISP BIT(3)
616/* Transfer descriptor missing. */
617#define EP_STS_DESCMIS BIT(4)
618/* Stream Rejected (used only in SS mode) */
619#define EP_STS_STREAMR BIT(5)
620/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
621#define EP_STS_MD_EXIT BIT(6)
622/* TRB error. */
623#define EP_STS_TRBERR BIT(7)
624/* Not ready (used only in SS mode). */
625#define EP_STS_NRDY BIT(8)
626/* DMA busy bit. */
627#define EP_STS_DBUSY BIT(9)
628/* Endpoint Buffer Empty */
629#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
630/* Current Cycle Status */
631#define EP_STS_CCS(p) ((p) & BIT(11))
632/* Prime (used only in SS mode. */
633#define EP_STS_PRIME BIT(12)
634/* Stream error (used only in SS mode). */
635#define EP_STS_SIDERR BIT(13)
636/* OUT size mismatch. */
637#define EP_STS_OUTSMM BIT(14)
638/* ISO transmission error. */
639#define EP_STS_ISOERR BIT(15)
640/* Host Packet Pending (only for SS mode). */
641#define EP_STS_HOSTPP(p) ((p) & BIT(16))
642/* Stream Protocol State Machine State (only for Bulk stream endpoints). */
643#define EP_STS_SPSMST_MASK GENMASK(18, 17)
644#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
645#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
646#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
647#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
648/* Interrupt On Transfer complete. */
649#define EP_STS_IOT BIT(19)
650/* OUT queue endpoint number. */
651#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
652#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
653/* OUT queue valid flag. */
654#define EP_STS_OUTQ_VAL_MASK BIT(28)
655#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
656/* SETUP WAIT. */
657#define EP_STS_STPWAIT BIT(31)
658
659/* EP_STS_SID - bitmasks */
660/* Stream ID (used only in SS mode). */
661#define EP_STS_SID_MASK GENMASK(15, 0)
662#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
663
664/* EP_STS_EN - bitmasks */
665/* SETUP interrupt enable. */
666#define EP_STS_EN_SETUPEN BIT(0)
667/* OUT transfer missing descriptor enable. */
668#define EP_STS_EN_DESCMISEN BIT(4)
669/* Stream Rejected enable. */
670#define EP_STS_EN_STREAMREN BIT(5)
671/* Move Data Exit enable.*/
672#define EP_STS_EN_MD_EXITEN BIT(6)
673/* TRB enable. */
674#define EP_STS_EN_TRBERREN BIT(7)
675/* NRDY enable. */
676#define EP_STS_EN_NRDYEN BIT(8)
677/* Prime enable. */
678#define EP_STS_EN_PRIMEEEN BIT(12)
679/* Stream error enable. */
680#define EP_STS_EN_SIDERREN BIT(13)
681/* OUT size mismatch enable. */
682#define EP_STS_EN_OUTSMMEN BIT(14)
683/* ISO transmission error enable. */
684#define EP_STS_EN_ISOERREN BIT(15)
685/* Interrupt on Transmission complete enable. */
686#define EP_STS_EN_IOTEN BIT(19)
687/* Setup Wait interrupt enable. */
688#define EP_STS_EN_STPWAITEN BIT(31)
689
690/* DRBL- bitmasks */
691#define DB_VALUE_BY_INDEX(index) (1 << (index))
692#define DB_VALUE_EP0_OUT BIT(0)
693#define DB_VALUE_EP0_IN BIT(16)
694
695/* EP_IEN - bitmasks */
696#define EP_IEN(index) (1 << (index))
697#define EP_IEN_EP_OUT0 BIT(0)
698#define EP_IEN_EP_IN0 BIT(16)
699
700/* EP_ISTS - bitmasks */
701#define EP_ISTS(index) (1 << (index))
702#define EP_ISTS_EP_OUT0 BIT(0)
703#define EP_ISTS_EP_IN0 BIT(16)
704
705/* USB_PWR- bitmasks */
706/*Power Shut Off capability enable*/
707#define PUSB_PWR_PSO_EN BIT(0)
708/*Power Shut Off capability disable*/
709#define PUSB_PWR_PSO_DS BIT(1)
710/*
711 * Enables turning-off Reference Clock.
712 * This bit is optional and implemented only when support for OTG is
713 * implemented (indicated by OTG_READY bit set to '1').
714 */
715#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
716/*
717 * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
718 * is completed
719 */
720#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
721/* This bit informs if Fast Registers Access is enabled. */
722#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
723/* Fast Registers Access Enable. */
724#define PUSB_PWR_FST_REG_ACCESS BIT(31)
725
726/* USB_CONF2- bitmasks */
727/*
728 * Writing 1 disables TDL calculation basing on TRB feature in controller
729 * for DMULT mode.
730 * Bit supported only for DEV_VER_V2 version.
731 */
732#define USB_CONF2_DIS_TDL_TRB BIT(1)
733/*
734 * Writing 1 enables TDL calculation basing on TRB feature in controller
735 * for DMULT mode.
736 * Bit supported only for DEV_VER_V2 version.
737 */
738#define USB_CONF2_EN_TDL_TRB BIT(2)
739
740/* USB_CAP1- bitmasks */
741/*
742 * SFR Interface type
743 * These field reflects type of SFR interface implemented:
744 * 0x0 - OCP
745 * 0x1 - AHB,
746 * 0x2 - PLB
747 * 0x3 - AXI
748 * 0x4-0xF - reserved
749 */
750#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
751#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
752#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
753#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
754#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
755/*
756 * SFR Interface width
757 * These field reflects width of SFR interface implemented:
758 * 0x0 - 8 bit interface,
759 * 0x1 - 16 bit interface,
760 * 0x2 - 32 bit interface
761 * 0x3 - 64 bit interface
762 * 0x4-0xF - reserved
763 */
764#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
765#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
766#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
767#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
768#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
769/*
770 * DMA Interface type
771 * These field reflects type of DMA interface implemented:
772 * 0x0 - OCP
773 * 0x1 - AHB,
774 * 0x2 - PLB
775 * 0x3 - AXI
776 * 0x4-0xF - reserved
777 */
778#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
779#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
780#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
781#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
782#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
783/*
784 * DMA Interface width
785 * These field reflects width of DMA interface implemented:
786 * 0x0 - reserved,
787 * 0x1 - reserved,
788 * 0x2 - 32 bit interface
789 * 0x3 - 64 bit interface
790 * 0x4-0xF - reserved
791 */
792#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
793#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
794#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
795/*
796 * USB3 PHY Interface type
797 * These field reflects type of USB3 PHY interface implemented:
798 * 0x0 - USB PIPE,
799 * 0x1 - RMMI,
800 * 0x2-0xF - reserved
801 */
802#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
803#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
804#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
805/*
806 * USB3 PHY Interface width
807 * These field reflects width of USB3 PHY interface implemented:
808 * 0x0 - 8 bit PIPE interface,
809 * 0x1 - 16 bit PIPE interface,
810 * 0x2 - 32 bit PIPE interface,
811 * 0x3 - 64 bit PIPE interface
812 * 0x4-0xF - reserved
813 * Note: When SSIC interface is implemented this field shows the width of
814 * internal PIPE interface. The RMMI interface is always 20bit wide.
815 */
816#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
817#define DEV_U3PHY_WIDTH_8(p) \
818 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
819#define DEV_U3PHY_WIDTH_16(p) \
820 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
821#define DEV_U3PHY_WIDTH_32(p) \
822 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
823#define DEV_U3PHY_WIDTH_64(p) \
824 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
825
826/*
827 * USB2 PHY Interface enable
828 * These field informs if USB2 PHY interface is implemented:
829 * 0x0 - interface NOT implemented,
830 * 0x1 - interface implemented
831 */
832#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
833/*
834 * USB2 PHY Interface type
835 * These field reflects type of USB2 PHY interface implemented:
836 * 0x0 - UTMI,
837 * 0x1 - ULPI
838 */
839#define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
840/*
841 * USB2 PHY Interface width
842 * These field reflects width of USB2 PHY interface implemented:
843 * 0x0 - 8 bit interface,
844 * 0x1 - 16 bit interface,
845 * Note: The ULPI interface is always 8bit wide.
846 */
847#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
848/*
849 * OTG Ready
850 * 0x0 - pure device mode
851 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
852 */
853#define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
854
855/*
856 * When set, indicates that controller supports automatic internal TDL
857 * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
858 * Supported only for DEV_VER_V2 controller version.
859 */
860#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
861
862/* USB_CAP2- bitmasks */
863/*
864 * The actual size of the connected On-chip RAM memory in kB:
865 * - 0 means 256 kB (max supported mem size)
866 * - value other than 0 reflects the mem size in kB
867 */
868#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
869/*
870 * Max supported mem size
871 * These field reflects width of on-chip RAM address bus width,
872 * which determines max supported mem size:
873 * 0x0-0x7 - reserved,
874 * 0x8 - support for 4kB mem,
875 * 0x9 - support for 8kB mem,
876 * 0xA - support for 16kB mem,
877 * 0xB - support for 32kB mem,
878 * 0xC - support for 64kB mem,
879 * 0xD - support for 128kB mem,
880 * 0xE - support for 256kB mem,
881 * 0xF - reserved
882 */
883#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
884
885/* USB_CAP3- bitmasks */
886#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
887
888/* USB_CAP4- bitmasks */
889#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
890
891/* USB_CAP5- bitmasks */
892#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
893
894/* USB_CAP6- bitmasks */
895/* The USBSS-DEV Controller Internal build number. */
896#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
897/* The USBSS-DEV Controller version number. */
898#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
899
900#define DEV_VER_NXP_V1 0x00024502
901#define DEV_VER_TI_V1 0x00024509
902#define DEV_VER_V2 0x0002450C
903#define DEV_VER_V3 0x0002450d
904
905/* DBG_LINK1- bitmasks */
906/*
907 * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
908 * time required for decoding the received LFPS as an LFPS.U1_Exit.
909 */
910#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
911/*
912 * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
913 * phytxelecidle deassertion when LFPS.U1_Exit
914 */
915#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
916#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
917/*
918 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
919 * Receiver termination detection sequence:
920 * 0: it is possible that USBSS_DEV will terminate Farend receiver
921 * termination detection sequence
922 * 1: USBSS_DEV will not terminate Far-end receiver termination
923 * detection sequence
924 */
925#define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
926/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
927#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
928/*
929 * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
930 * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
931 * cleared. Writing '0' has no effect
932 */
933#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
934/*
935 * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
936 * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
937 * cleared. Writing '0' has no effect
938 */
939#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
940/*
941 * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
942 * the RXDET_BREAK_DIS field value to the device. This bit is automatically
943 * cleared. Writing '0' has no effect
944 */
945#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
946/*
947 * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
948 * the LFPS_GEN_PING field value to the device. This bit is automatically
949 * cleared. Writing '0' has no effect."
950 */
951#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
952
953/* DMA_AXI_CTRL- bitmasks */
954/* The mawprot pin configuration. */
955#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
956/* The marprot pin configuration. */
957#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
958#define DMA_AXI_CTRL_NON_SECURE 0x02
959
960#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
961
962#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
963
964/*-------------------------------------------------------------------------*/
965/*
966 * USBSS-DEV DMA interface.
967 */
968#define TRBS_PER_SEGMENT 40
969
970#define ISO_MAX_INTERVAL 10
971
972#if TRBS_PER_SEGMENT < 2
973#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
974#endif
975
976/*
977 *Only for ISOC endpoints - maximum number of TRBs is calculated as
978 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
979 * driver to save memory. Controller must prepare TRB for each ITP even
980 * if bInterval > 1. It's the reason why driver needs so many TRBs for
981 * isochronous endpoints.
982 */
983#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
984
985#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
986 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
987/**
988 * struct cdns3_trb - represent Transfer Descriptor block.
989 * @buffer: pointer to buffer data
990 * @length: length of data
991 * @control: control flags.
992 *
993 * This structure describes transfer block serviced by DMA module.
994 */
995struct cdns3_trb {
996 __le32 buffer;
997 __le32 length;
998 __le32 control;
999};
1000
1001#define TRB_SIZE (sizeof(struct cdns3_trb))
1002#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
1003#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1004#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
1005
1006/* TRB bit mask */
1007#define TRB_TYPE_BITMASK GENMASK(15, 10)
1008#define TRB_TYPE(p) ((p) << 10)
1009#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1010
1011/* TRB type IDs */
1012/* bulk, interrupt, isoc , and control data stage */
1013#define TRB_NORMAL 1
1014/* TRB for linking ring segments */
1015#define TRB_LINK 6
1016
1017/* Cycle bit - indicates TRB ownership by driver or hw*/
1018#define TRB_CYCLE BIT(0)
1019/*
1020 * When set to '1', the device will toggle its interpretation of the Cycle bit
1021 */
1022#define TRB_TOGGLE BIT(1)
1023
1024/*
1025 * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
1026 * processed while USB short packet was received. No more buffers defined by
1027 * the TD will be used. DMA will automatically advance to next TD.
1028 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1029 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1030 * is detected independent if ISP is set or not.
1031 */
1032#define TRB_SP BIT(1)
1033
1034/* Interrupt on short packet*/
1035#define TRB_ISP BIT(2)
1036/*Setting this bit enables FIFO DMA operation mode*/
1037#define TRB_FIFO_MODE BIT(3)
1038/* Set PCIe no snoop attribute */
1039#define TRB_CHAIN BIT(4)
1040/* Interrupt on completion */
1041#define TRB_IOC BIT(5)
1042
1043/* stream ID bitmasks. */
1044#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
1045#define TRB_STREAM_ID(p) ((p) << 16)
1046#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1047
1048/* Size of TD expressed in USB packets for HS/FS mode. */
1049#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
1050#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
1051
1052/* transfer_len bitmasks. */
1053#define TRB_LEN(p) ((p) & GENMASK(16, 0))
1054
1055/* Size of TD expressed in USB packets for SS mode. */
1056#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
1057#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
1058
1059/* transfer_len bitmasks - bits 31:24 */
1060#define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24))
1061#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
1062
1063/* Data buffer pointer bitmasks*/
1064#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
1065
1066/*-------------------------------------------------------------------------*/
1067/* Driver numeric constants */
1068
1069/* Such declaration should be added to ch9.h */
1070#define USB_DEVICE_MAX_ADDRESS 127
1071
1072/* Endpoint init values */
1073#define CDNS3_EP_MAX_PACKET_LIMIT 1024
1074#define CDNS3_EP_MAX_STREAMS 15
1075#define CDNS3_EP0_MAX_PACKET_LIMIT 512
1076
1077/* All endpoints including EP0 */
1078#define CDNS3_ENDPOINTS_MAX_COUNT 32
1079#define CDNS3_EP_ZLP_BUF_SIZE 1024
1080
1081#define CDNS3_EP_BUF_SIZE 2 /* KB */
1082#define CDNS3_EP_ISO_HS_MULT 3
1083#define CDNS3_EP_ISO_SS_BURST 3
1084#define CDNS3_MAX_NUM_DESCMISS_BUF 32
1085#define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */
1086/*-------------------------------------------------------------------------*/
1087/* Used structs */
1088
1089struct cdns3_device;
1090
1091/**
1092 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1093 * @endpoint: usb endpoint
1094 * @pending_req_list: list of requests queuing on transfer ring.
1095 * @deferred_req_list: list of requests waiting for queuing on transfer ring.
1096 * @trb_pool: transfer ring - array of transaction buffers
1097 * @trb_pool_dma: dma address of transfer ring
1098 * @cdns3_dev: device associated with this endpoint
1099 * @name: a human readable name e.g. ep1out
1100 * @flags: specify the current state of endpoint
1101 * @dir: endpoint direction
1102 * @num: endpoint number (1 - 15)
1103 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
1104 * @interval: interval between packets used for ISOC endpoint.
1105 * @free_trbs: number of free TRBs in transfer ring
1106 * @num_trbs: number of all TRBs in transfer ring
1107 * @pcs: producer cycle state
1108 * @ccs: consumer cycle state
1109 * @enqueue: enqueue index in transfer ring
1110 * @dequeue: dequeue index in transfer ring
1111 * @trb_burst_size: number of burst used in trb.
1112 */
1113struct cdns3_endpoint {
1114 struct usb_ep endpoint;
1115 struct list_head pending_req_list;
1116 struct list_head deferred_req_list;
1117
1118 struct cdns3_trb *trb_pool;
1119 dma_addr_t trb_pool_dma;
1120
1121 struct cdns3_device *cdns3_dev;
1122 char name[20];
1123
1124#define EP_ENABLED BIT(0)
1125#define EP_STALLED BIT(1)
1126#define EP_STALL_PENDING BIT(2)
1127#define EP_WEDGE BIT(3)
1128#define EP_TRANSFER_STARTED BIT(4)
1129#define EP_UPDATE_EP_TRBADDR BIT(5)
1130#define EP_PENDING_REQUEST BIT(6)
1131#define EP_RING_FULL BIT(7)
1132#define EP_CLAIMED BIT(8)
1133#define EP_DEFERRED_DRDY BIT(9)
1134#define EP_QUIRK_ISO_OUT_EN BIT(10)
1135 u32 flags;
1136
1137 u8 dir;
1138 u8 num;
1139 u8 type;
1140 int interval;
1141
1142 int free_trbs;
1143 int num_trbs;
1144 u8 pcs;
1145 u8 ccs;
1146 int enqueue;
1147 int dequeue;
1148 u8 trb_burst_size;
1149
1150 unsigned int wa1_set:1;
1151 struct cdns3_trb *wa1_trb;
1152 unsigned int wa1_trb_index;
1153 unsigned int wa1_cycle_bit:1;
1154};
1155
1156/**
1157 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1158 * @buf: aligned to 8 bytes data buffer. Buffer address used in
1159 * TRB shall be aligned to 8.
1160 * @dma: dma address
1161 * @size: size of buffer
1162 * @in_use: inform if this buffer is associated with usb_request
1163 * @list: used to adding instance of this object to list
1164 */
1165struct cdns3_aligned_buf {
1166 void *buf;
1167 dma_addr_t dma;
1168 u32 size;
1169 int in_use:1;
1170 struct list_head list;
1171};
1172
1173/**
1174 * struct cdns3_request - extended device side representation of usb_request
1175 * object .
1176 * @request: generic usb_request object describing single I/O request.
1177 * @priv_ep: extended representation of usb_ep object
1178 * @trb: the first TRB association with this request
1179 * @start_trb: number of the first TRB in transfer ring
1180 * @end_trb: number of the last TRB in transfer ring
1181 * @aligned_buf: object holds information about aligned buffer associated whit
1182 * this endpoint
1183 * @flags: flag specifying special usage of request
1184 */
1185struct cdns3_request {
1186 struct usb_request request;
1187 struct cdns3_endpoint *priv_ep;
1188 struct cdns3_trb *trb;
1189 int start_trb;
1190 int end_trb;
1191 struct cdns3_aligned_buf *aligned_buf;
1192#define REQUEST_PENDING BIT(0)
1193#define REQUEST_INTERNAL BIT(1)
1194#define REQUEST_INTERNAL_CH BIT(2)
1195#define REQUEST_ZLP BIT(3)
1196#define REQUEST_UNALIGNED BIT(4)
1197 u32 flags;
1198 struct list_head list;
1199};
1200
1201#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1202
1203/*Stages used during enumeration process.*/
1204#define CDNS3_SETUP_STAGE 0x0
1205#define CDNS3_DATA_STAGE 0x1
1206#define CDNS3_STATUS_STAGE 0x2
1207
1208/**
1209 * struct cdns3_device - represent USB device.
1210 * @dev: pointer to device structure associated whit this controller
1211 * @sysdev: pointer to the DMA capable device
1212 * @gadget: device side representation of the peripheral controller
1213 * @gadget_driver: pointer to the gadget driver
1214 * @dev_ver: device controller version.
1215 * @lock: for synchronizing
1216 * @regs: base address for device side registers
1217 * @setup_buf: used while processing usb control requests
1218 * @setup_dma: dma address for setup_buf
1219 * @zlp_buf - zlp buffer
1220 * @ep0_stage: ep0 stage during enumeration process.
1221 * @ep0_data_dir: direction for control transfer
1222 * @eps: array of pointers to all endpoints with exclusion ep0
1223 * @aligned_buf_list: list of aligned buffers internally allocated by driver
1224 * @aligned_buf_wq: workqueue freeing no longer used aligned buf.
1225 * @selected_ep: actually selected endpoint. It's used only to improve
1226 * performance.
1227 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1228 * @u1_allowed: allow device transition to u1 state
1229 * @u2_allowed: allow device transition to u2 state
1230 * @is_selfpowered: device is self powered
1231 * @setup_pending: setup packet is processing by gadget driver
1232 * @hw_configured_flag: hardware endpoint configuration was set.
1233 * @wake_up_flag: allow device to remote up the host
1234 * @status_completion_no_call: indicate that driver is waiting for status s
1235 * stage completion. It's used in deferred SET_CONFIGURATION request.
1236 * @onchip_buffers: number of available on-chip buffers.
1237 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1238 * @pending_status_wq: workqueue handling status stage for deferred requests.
1239 * @pending_status_request: request for which status stage was deferred
1240 */
1241struct cdns3_device {
1242 struct device *dev;
1243 struct device *sysdev;
1244
1245 struct usb_gadget gadget;
1246 struct usb_gadget_driver *gadget_driver;
1247
1248#define CDNS_REVISION_V0 0x00024501
1249#define CDNS_REVISION_V1 0x00024509
1250 u32 dev_ver;
1251
1252 /* generic spin-lock for drivers */
1253 spinlock_t lock;
1254
1255 struct cdns3_usb_regs __iomem *regs;
1256
1257 struct usb_ctrlrequest *setup_buf;
1258 dma_addr_t setup_dma;
1259 void *zlp_buf;
1260
1261 u8 ep0_stage;
1262 int ep0_data_dir;
1263
1264 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1265
1266 struct list_head aligned_buf_list;
1267 struct work_struct aligned_buf_wq;
1268
1269 u32 selected_ep;
1270 u16 isoch_delay;
1271
1272 unsigned wait_for_setup:1;
1273 unsigned u1_allowed:1;
1274 unsigned u2_allowed:1;
1275 unsigned is_selfpowered:1;
1276 unsigned setup_pending:1;
1277 int hw_configured_flag:1;
1278 int wake_up_flag:1;
1279 unsigned status_completion_no_call:1;
1280 int out_mem_is_allocated;
1281
1282 struct work_struct pending_status_wq;
1283 struct usb_request *pending_status_request;
1284
1285 /*in KB */
1286 u16 onchip_buffers;
1287 u16 onchip_used_size;
1288};
1289
1290void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1291dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1292 struct cdns3_trb *trb);
1293enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1294void cdns3_pending_setup_status_handler(struct work_struct *work);
1295void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1296void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1297void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1298void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1299struct usb_request *cdns3_next_request(struct list_head *list);
1300int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
1301 struct usb_request *request);
1302void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1303int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1304u8 cdns3_ep_addr_to_index(u8 ep_addr);
1305int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1306int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1307void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1308int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1309struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1310 gfp_t gfp_flags);
1311void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1312 struct usb_request *request);
1313int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1314void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1315 struct cdns3_request *priv_req,
1316 int status);
1317
1318int cdns3_init_ep0(struct cdns3_device *priv_dev,
1319 struct cdns3_endpoint *priv_ep);
1320void cdns3_ep0_config(struct cdns3_device *priv_dev);
1321void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
1322void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1323int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1324
1325#endif /* __LINUX_CDNS3_GADGET */
diff --git a/drivers/usb/cdns3/host-export.h b/drivers/usb/cdns3/host-export.h
new file mode 100644
index 000000000000..b498a170b7e8
--- /dev/null
+++ b/drivers/usb/cdns3/host-export.h
@@ -0,0 +1,28 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Cadence USBSS DRD Driver - Host Export APIs
4 *
5 * Copyright (C) 2017-2018 NXP
6 *
7 * Authors: Peter Chen <peter.chen@nxp.com>
8 */
9#ifndef __LINUX_CDNS3_HOST_EXPORT
10#define __LINUX_CDNS3_HOST_EXPORT
11
12#ifdef CONFIG_USB_CDNS3_HOST
13
14int cdns3_host_init(struct cdns3 *cdns);
15void cdns3_host_exit(struct cdns3 *cdns);
16
17#else
18
19static inline int cdns3_host_init(struct cdns3 *cdns)
20{
21 return -ENXIO;
22}
23
24static inline void cdns3_host_exit(struct cdns3 *cdns) { }
25
26#endif /* CONFIG_USB_CDNS3_HOST */
27
28#endif /* __LINUX_CDNS3_HOST_EXPORT */
diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c
new file mode 100644
index 000000000000..2733a8f71fcd
--- /dev/null
+++ b/drivers/usb/cdns3/host.c
@@ -0,0 +1,74 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence USBSS DRD Driver - host side
4 *
5 * Copyright (C) 2018-2019 Cadence Design Systems.
6 * Copyright (C) 2017-2018 NXP
7 *
8 * Authors: Peter Chen <peter.chen@nxp.com>
9 * Pawel Laszczak <pawell@cadence.com>
10 */
11
12#include <linux/platform_device.h>
13#include "core.h"
14#include "drd.h"
15
16static int __cdns3_host_init(struct cdns3 *cdns)
17{
18 struct platform_device *xhci;
19 int ret;
20
21 cdns3_drd_switch_host(cdns, 1);
22
23 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
24 if (!xhci) {
25 dev_err(cdns->dev, "couldn't allocate xHCI device\n");
26 return -ENOMEM;
27 }
28
29 xhci->dev.parent = cdns->dev;
30 cdns->host_dev = xhci;
31
32 ret = platform_device_add_resources(xhci, cdns->xhci_res,
33 CDNS3_XHCI_RESOURCES_NUM);
34 if (ret) {
35 dev_err(cdns->dev, "couldn't add resources to xHCI device\n");
36 goto err1;
37 }
38
39 ret = platform_device_add(xhci);
40 if (ret) {
41 dev_err(cdns->dev, "failed to register xHCI device\n");
42 goto err1;
43 }
44
45 return 0;
46err1:
47 platform_device_put(xhci);
48 return ret;
49}
50
51static void cdns3_host_exit(struct cdns3 *cdns)
52{
53 platform_device_unregister(cdns->host_dev);
54 cdns->host_dev = NULL;
55 cdns3_drd_switch_host(cdns, 0);
56}
57
58int cdns3_host_init(struct cdns3 *cdns)
59{
60 struct cdns3_role_driver *rdrv;
61
62 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
63 if (!rdrv)
64 return -ENOMEM;
65
66 rdrv->start = __cdns3_host_init;
67 rdrv->stop = cdns3_host_exit;
68 rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
69 rdrv->name = "host";
70
71 cdns->roles[USB_ROLE_HOST] = rdrv;
72
73 return 0;
74}
diff --git a/drivers/usb/cdns3/trace.c b/drivers/usb/cdns3/trace.c
new file mode 100644
index 000000000000..459fa72d9c74
--- /dev/null
+++ b/drivers/usb/cdns3/trace.c
@@ -0,0 +1,11 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * USBSS device controller driver Trace Support
4 *
5 * Copyright (C) 2018-2019 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 */
9
10#define CREATE_TRACE_POINTS
11#include "trace.h"
diff --git a/drivers/usb/cdns3/trace.h b/drivers/usb/cdns3/trace.h
new file mode 100644
index 000000000000..e92348c9b4d7
--- /dev/null
+++ b/drivers/usb/cdns3/trace.h
@@ -0,0 +1,493 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * USBSS device controller driver.
4 * Trace support header file.
5 *
6 * Copyright (C) 2018-2019 Cadence.
7 *
8 * Author: Pawel Laszczak <pawell@cadence.com>
9 */
10
11#undef TRACE_SYSTEM
12#define TRACE_SYSTEM cdns3
13
14#if !defined(__LINUX_CDNS3_TRACE) || defined(TRACE_HEADER_MULTI_READ)
15#define __LINUX_CDNS3_TRACE
16
17#include <linux/types.h>
18#include <linux/tracepoint.h>
19#include <asm/byteorder.h>
20#include <linux/usb/ch9.h>
21#include "core.h"
22#include "gadget.h"
23#include "debug.h"
24
25#define CDNS3_MSG_MAX 500
26
27TRACE_EVENT(cdns3_halt,
28 TP_PROTO(struct cdns3_endpoint *ep_priv, u8 halt, u8 flush),
29 TP_ARGS(ep_priv, halt, flush),
30 TP_STRUCT__entry(
31 __string(name, ep_priv->name)
32 __field(u8, halt)
33 __field(u8, flush)
34 ),
35 TP_fast_assign(
36 __assign_str(name, ep_priv->name);
37 __entry->halt = halt;
38 __entry->flush = flush;
39 ),
40 TP_printk("Halt %s for %s: %s", __entry->flush ? " and flush" : "",
41 __get_str(name), __entry->halt ? "set" : "cleared")
42);
43
44TRACE_EVENT(cdns3_wa1,
45 TP_PROTO(struct cdns3_endpoint *ep_priv, char *msg),
46 TP_ARGS(ep_priv, msg),
47 TP_STRUCT__entry(
48 __string(ep_name, ep_priv->name)
49 __string(msg, msg)
50 ),
51 TP_fast_assign(
52 __assign_str(ep_name, ep_priv->name);
53 __assign_str(msg, msg);
54 ),
55 TP_printk("WA1: %s %s", __get_str(ep_name), __get_str(msg))
56);
57
58TRACE_EVENT(cdns3_wa2,
59 TP_PROTO(struct cdns3_endpoint *ep_priv, char *msg),
60 TP_ARGS(ep_priv, msg),
61 TP_STRUCT__entry(
62 __string(ep_name, ep_priv->name)
63 __string(msg, msg)
64 ),
65 TP_fast_assign(
66 __assign_str(ep_name, ep_priv->name);
67 __assign_str(msg, msg);
68 ),
69 TP_printk("WA2: %s %s", __get_str(ep_name), __get_str(msg))
70);
71
72DECLARE_EVENT_CLASS(cdns3_log_doorbell,
73 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
74 TP_ARGS(ep_name, ep_trbaddr),
75 TP_STRUCT__entry(
76 __string(name, ep_name)
77 __field(u32, ep_trbaddr)
78 ),
79 TP_fast_assign(
80 __assign_str(name, ep_name);
81 __entry->ep_trbaddr = ep_trbaddr;
82 ),
83 TP_printk("%s, ep_trbaddr %08x", __get_str(name),
84 __entry->ep_trbaddr)
85);
86
87DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_ep0,
88 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
89 TP_ARGS(ep_name, ep_trbaddr)
90);
91
92DEFINE_EVENT(cdns3_log_doorbell, cdns3_doorbell_epx,
93 TP_PROTO(const char *ep_name, u32 ep_trbaddr),
94 TP_ARGS(ep_name, ep_trbaddr)
95);
96
97DECLARE_EVENT_CLASS(cdns3_log_usb_irq,
98 TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists),
99 TP_ARGS(priv_dev, usb_ists),
100 TP_STRUCT__entry(
101 __field(enum usb_device_speed, speed)
102 __field(u32, usb_ists)
103 __dynamic_array(char, str, CDNS3_MSG_MAX)
104 ),
105 TP_fast_assign(
106 __entry->speed = cdns3_get_speed(priv_dev);
107 __entry->usb_ists = usb_ists;
108 ),
109 TP_printk("%s", cdns3_decode_usb_irq(__get_str(str), __entry->speed,
110 __entry->usb_ists))
111);
112
113DEFINE_EVENT(cdns3_log_usb_irq, cdns3_usb_irq,
114 TP_PROTO(struct cdns3_device *priv_dev, u32 usb_ists),
115 TP_ARGS(priv_dev, usb_ists)
116);
117
118DECLARE_EVENT_CLASS(cdns3_log_epx_irq,
119 TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep),
120 TP_ARGS(priv_dev, priv_ep),
121 TP_STRUCT__entry(
122 __string(ep_name, priv_ep->name)
123 __field(u32, ep_sts)
124 __field(u32, ep_traddr)
125 __dynamic_array(char, str, CDNS3_MSG_MAX)
126 ),
127 TP_fast_assign(
128 __assign_str(ep_name, priv_ep->name);
129 __entry->ep_sts = readl(&priv_dev->regs->ep_sts);
130 __entry->ep_traddr = readl(&priv_dev->regs->ep_traddr);
131 ),
132 TP_printk("%s, ep_traddr: %08x",
133 cdns3_decode_epx_irq(__get_str(str),
134 __get_str(ep_name),
135 __entry->ep_sts),
136 __entry->ep_traddr)
137);
138
139DEFINE_EVENT(cdns3_log_epx_irq, cdns3_epx_irq,
140 TP_PROTO(struct cdns3_device *priv_dev, struct cdns3_endpoint *priv_ep),
141 TP_ARGS(priv_dev, priv_ep)
142);
143
144DECLARE_EVENT_CLASS(cdns3_log_ep0_irq,
145 TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts),
146 TP_ARGS(priv_dev, ep_sts),
147 TP_STRUCT__entry(
148 __field(int, ep_dir)
149 __field(u32, ep_sts)
150 __dynamic_array(char, str, CDNS3_MSG_MAX)
151 ),
152 TP_fast_assign(
153 __entry->ep_dir = priv_dev->ep0_data_dir;
154 __entry->ep_sts = ep_sts;
155 ),
156 TP_printk("%s", cdns3_decode_ep0_irq(__get_str(str),
157 __entry->ep_dir,
158 __entry->ep_sts))
159);
160
161DEFINE_EVENT(cdns3_log_ep0_irq, cdns3_ep0_irq,
162 TP_PROTO(struct cdns3_device *priv_dev, u32 ep_sts),
163 TP_ARGS(priv_dev, ep_sts)
164);
165
166DECLARE_EVENT_CLASS(cdns3_log_ctrl,
167 TP_PROTO(struct usb_ctrlrequest *ctrl),
168 TP_ARGS(ctrl),
169 TP_STRUCT__entry(
170 __field(u8, bRequestType)
171 __field(u8, bRequest)
172 __field(u16, wValue)
173 __field(u16, wIndex)
174 __field(u16, wLength)
175 __dynamic_array(char, str, CDNS3_MSG_MAX)
176 ),
177 TP_fast_assign(
178 __entry->bRequestType = ctrl->bRequestType;
179 __entry->bRequest = ctrl->bRequest;
180 __entry->wValue = le16_to_cpu(ctrl->wValue);
181 __entry->wIndex = le16_to_cpu(ctrl->wIndex);
182 __entry->wLength = le16_to_cpu(ctrl->wLength);
183 ),
184 TP_printk("%s", usb_decode_ctrl(__get_str(str), CDNS3_MSG_MAX,
185 __entry->bRequestType,
186 __entry->bRequest, __entry->wValue,
187 __entry->wIndex, __entry->wLength)
188 )
189);
190
191DEFINE_EVENT(cdns3_log_ctrl, cdns3_ctrl_req,
192 TP_PROTO(struct usb_ctrlrequest *ctrl),
193 TP_ARGS(ctrl)
194);
195
196DECLARE_EVENT_CLASS(cdns3_log_request,
197 TP_PROTO(struct cdns3_request *req),
198 TP_ARGS(req),
199 TP_STRUCT__entry(
200 __string(name, req->priv_ep->name)
201 __field(struct cdns3_request *, req)
202 __field(void *, buf)
203 __field(unsigned int, actual)
204 __field(unsigned int, length)
205 __field(int, status)
206 __field(int, zero)
207 __field(int, short_not_ok)
208 __field(int, no_interrupt)
209 __field(int, start_trb)
210 __field(int, end_trb)
211 __field(struct cdns3_trb *, start_trb_addr)
212 __field(int, flags)
213 ),
214 TP_fast_assign(
215 __assign_str(name, req->priv_ep->name);
216 __entry->req = req;
217 __entry->buf = req->request.buf;
218 __entry->actual = req->request.actual;
219 __entry->length = req->request.length;
220 __entry->status = req->request.status;
221 __entry->zero = req->request.zero;
222 __entry->short_not_ok = req->request.short_not_ok;
223 __entry->no_interrupt = req->request.no_interrupt;
224 __entry->start_trb = req->start_trb;
225 __entry->end_trb = req->end_trb;
226 __entry->start_trb_addr = req->trb;
227 __entry->flags = req->flags;
228 ),
229 TP_printk("%s: req: %p, req buff %p, length: %u/%u %s%s%s, status: %d,"
230 " trb: [start:%d, end:%d: virt addr %pa], flags:%x ",
231 __get_str(name), __entry->req, __entry->buf, __entry->actual,
232 __entry->length,
233 __entry->zero ? "Z" : "z",
234 __entry->short_not_ok ? "S" : "s",
235 __entry->no_interrupt ? "I" : "i",
236 __entry->status,
237 __entry->start_trb,
238 __entry->end_trb,
239 __entry->start_trb_addr,
240 __entry->flags
241 )
242);
243
244DEFINE_EVENT(cdns3_log_request, cdns3_alloc_request,
245 TP_PROTO(struct cdns3_request *req),
246 TP_ARGS(req)
247);
248
249DEFINE_EVENT(cdns3_log_request, cdns3_free_request,
250 TP_PROTO(struct cdns3_request *req),
251 TP_ARGS(req)
252);
253
254DEFINE_EVENT(cdns3_log_request, cdns3_ep_queue,
255 TP_PROTO(struct cdns3_request *req),
256 TP_ARGS(req)
257);
258
259DEFINE_EVENT(cdns3_log_request, cdns3_ep_dequeue,
260 TP_PROTO(struct cdns3_request *req),
261 TP_ARGS(req)
262);
263
264DEFINE_EVENT(cdns3_log_request, cdns3_gadget_giveback,
265 TP_PROTO(struct cdns3_request *req),
266 TP_ARGS(req)
267);
268
269TRACE_EVENT(cdns3_ep0_queue,
270 TP_PROTO(struct cdns3_device *dev_priv, struct usb_request *request),
271 TP_ARGS(dev_priv, request),
272 TP_STRUCT__entry(
273 __field(int, dir)
274 __field(int, length)
275 ),
276 TP_fast_assign(
277 __entry->dir = dev_priv->ep0_data_dir;
278 __entry->length = request->length;
279 ),
280 TP_printk("Queue to ep0%s length: %u", __entry->dir ? "in" : "out",
281 __entry->length)
282);
283
284DECLARE_EVENT_CLASS(cdns3_log_aligned_request,
285 TP_PROTO(struct cdns3_request *priv_req),
286 TP_ARGS(priv_req),
287 TP_STRUCT__entry(
288 __string(name, priv_req->priv_ep->name)
289 __field(struct usb_request *, req)
290 __field(void *, buf)
291 __field(dma_addr_t, dma)
292 __field(void *, aligned_buf)
293 __field(dma_addr_t, aligned_dma)
294 __field(u32, aligned_buf_size)
295 ),
296 TP_fast_assign(
297 __assign_str(name, priv_req->priv_ep->name);
298 __entry->req = &priv_req->request;
299 __entry->buf = priv_req->request.buf;
300 __entry->dma = priv_req->request.dma;
301 __entry->aligned_buf = priv_req->aligned_buf->buf;
302 __entry->aligned_dma = priv_req->aligned_buf->dma;
303 __entry->aligned_buf_size = priv_req->aligned_buf->size;
304 ),
305 TP_printk("%s: req: %p, req buf %p, dma %pad a_buf %p a_dma %pad, size %d",
306 __get_str(name), __entry->req, __entry->buf, &__entry->dma,
307 __entry->aligned_buf, &__entry->aligned_dma,
308 __entry->aligned_buf_size
309 )
310);
311
312DEFINE_EVENT(cdns3_log_aligned_request, cdns3_free_aligned_request,
313 TP_PROTO(struct cdns3_request *req),
314 TP_ARGS(req)
315);
316
317DEFINE_EVENT(cdns3_log_aligned_request, cdns3_prepare_aligned_request,
318 TP_PROTO(struct cdns3_request *req),
319 TP_ARGS(req)
320);
321
322DECLARE_EVENT_CLASS(cdns3_log_trb,
323 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
324 TP_ARGS(priv_ep, trb),
325 TP_STRUCT__entry(
326 __string(name, priv_ep->name)
327 __field(struct cdns3_trb *, trb)
328 __field(u32, buffer)
329 __field(u32, length)
330 __field(u32, control)
331 __field(u32, type)
332 ),
333 TP_fast_assign(
334 __assign_str(name, priv_ep->name);
335 __entry->trb = trb;
336 __entry->buffer = trb->buffer;
337 __entry->length = trb->length;
338 __entry->control = trb->control;
339 __entry->type = usb_endpoint_type(priv_ep->endpoint.desc);
340 ),
341 TP_printk("%s: trb %p, dma buf: 0x%08x, size: %ld, burst: %d ctrl: 0x%08x (%s%s%s%s%s%s%s)",
342 __get_str(name), __entry->trb, __entry->buffer,
343 TRB_LEN(__entry->length),
344 (u8)TRB_BURST_LEN_GET(__entry->length),
345 __entry->control,
346 __entry->control & TRB_CYCLE ? "C=1, " : "C=0, ",
347 __entry->control & TRB_TOGGLE ? "T=1, " : "T=0, ",
348 __entry->control & TRB_ISP ? "ISP, " : "",
349 __entry->control & TRB_FIFO_MODE ? "FIFO, " : "",
350 __entry->control & TRB_CHAIN ? "CHAIN, " : "",
351 __entry->control & TRB_IOC ? "IOC, " : "",
352 TRB_FIELD_TO_TYPE(__entry->control) == TRB_NORMAL ? "Normal" : "LINK"
353 )
354);
355
356DEFINE_EVENT(cdns3_log_trb, cdns3_prepare_trb,
357 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
358 TP_ARGS(priv_ep, trb)
359);
360
361DEFINE_EVENT(cdns3_log_trb, cdns3_complete_trb,
362 TP_PROTO(struct cdns3_endpoint *priv_ep, struct cdns3_trb *trb),
363 TP_ARGS(priv_ep, trb)
364);
365
366DECLARE_EVENT_CLASS(cdns3_log_ring,
367 TP_PROTO(struct cdns3_endpoint *priv_ep),
368 TP_ARGS(priv_ep),
369 TP_STRUCT__entry(
370 __dynamic_array(u8, ring, TRB_RING_SIZE)
371 __dynamic_array(u8, priv_ep, sizeof(struct cdns3_endpoint))
372 __dynamic_array(char, buffer,
373 (TRBS_PER_SEGMENT * 65) + CDNS3_MSG_MAX)
374 ),
375 TP_fast_assign(
376 memcpy(__get_dynamic_array(priv_ep), priv_ep,
377 sizeof(struct cdns3_endpoint));
378 memcpy(__get_dynamic_array(ring), priv_ep->trb_pool,
379 TRB_RING_SIZE);
380 ),
381
382 TP_printk("%s",
383 cdns3_dbg_ring((struct cdns3_endpoint *)__get_str(priv_ep),
384 (struct cdns3_trb *)__get_str(ring),
385 __get_str(buffer)))
386);
387
388DEFINE_EVENT(cdns3_log_ring, cdns3_ring,
389 TP_PROTO(struct cdns3_endpoint *priv_ep),
390 TP_ARGS(priv_ep)
391);
392
393DECLARE_EVENT_CLASS(cdns3_log_ep,
394 TP_PROTO(struct cdns3_endpoint *priv_ep),
395 TP_ARGS(priv_ep),
396 TP_STRUCT__entry(
397 __string(name, priv_ep->name)
398 __field(unsigned int, maxpacket)
399 __field(unsigned int, maxpacket_limit)
400 __field(unsigned int, max_streams)
401 __field(unsigned int, maxburst)
402 __field(unsigned int, flags)
403 __field(unsigned int, dir)
404 __field(u8, enqueue)
405 __field(u8, dequeue)
406 ),
407 TP_fast_assign(
408 __assign_str(name, priv_ep->name);
409 __entry->maxpacket = priv_ep->endpoint.maxpacket;
410 __entry->maxpacket_limit = priv_ep->endpoint.maxpacket_limit;
411 __entry->max_streams = priv_ep->endpoint.max_streams;
412 __entry->maxburst = priv_ep->endpoint.maxburst;
413 __entry->flags = priv_ep->flags;
414 __entry->dir = priv_ep->dir;
415 __entry->enqueue = priv_ep->enqueue;
416 __entry->dequeue = priv_ep->dequeue;
417 ),
418 TP_printk("%s: mps: %d/%d. streams: %d, burst: %d, enq idx: %d, "
419 "deq idx: %d, flags %s%s%s%s%s%s%s%s, dir: %s",
420 __get_str(name), __entry->maxpacket,
421 __entry->maxpacket_limit, __entry->max_streams,
422 __entry->maxburst, __entry->enqueue,
423 __entry->dequeue,
424 __entry->flags & EP_ENABLED ? "EN | " : "",
425 __entry->flags & EP_STALLED ? "STALLED | " : "",
426 __entry->flags & EP_WEDGE ? "WEDGE | " : "",
427 __entry->flags & EP_TRANSFER_STARTED ? "STARTED | " : "",
428 __entry->flags & EP_UPDATE_EP_TRBADDR ? "UPD TRB | " : "",
429 __entry->flags & EP_PENDING_REQUEST ? "REQ PEN | " : "",
430 __entry->flags & EP_RING_FULL ? "RING FULL |" : "",
431 __entry->flags & EP_CLAIMED ? "CLAIMED " : "",
432 __entry->dir ? "IN" : "OUT"
433 )
434);
435
436DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_enable,
437 TP_PROTO(struct cdns3_endpoint *priv_ep),
438 TP_ARGS(priv_ep)
439);
440
441DEFINE_EVENT(cdns3_log_ep, cdns3_gadget_ep_disable,
442 TP_PROTO(struct cdns3_endpoint *priv_ep),
443 TP_ARGS(priv_ep)
444);
445
446DECLARE_EVENT_CLASS(cdns3_log_request_handled,
447 TP_PROTO(struct cdns3_request *priv_req, int current_index,
448 int handled),
449 TP_ARGS(priv_req, current_index, handled),
450 TP_STRUCT__entry(
451 __field(struct cdns3_request *, priv_req)
452 __field(unsigned int, dma_position)
453 __field(unsigned int, handled)
454 __field(unsigned int, dequeue_idx)
455 __field(unsigned int, enqueue_idx)
456 __field(unsigned int, start_trb)
457 __field(unsigned int, end_trb)
458 ),
459 TP_fast_assign(
460 __entry->priv_req = priv_req;
461 __entry->dma_position = current_index;
462 __entry->handled = handled;
463 __entry->dequeue_idx = priv_req->priv_ep->dequeue;
464 __entry->enqueue_idx = priv_req->priv_ep->enqueue;
465 __entry->start_trb = priv_req->start_trb;
466 __entry->end_trb = priv_req->end_trb;
467 ),
468 TP_printk("Req: %p %s, DMA pos: %d, ep deq: %d, ep enq: %d,"
469 " start trb: %d, end trb: %d",
470 __entry->priv_req,
471 __entry->handled ? "handled" : "not handled",
472 __entry->dma_position, __entry->dequeue_idx,
473 __entry->enqueue_idx, __entry->start_trb,
474 __entry->end_trb
475 )
476);
477
478DEFINE_EVENT(cdns3_log_request_handled, cdns3_request_handled,
479 TP_PROTO(struct cdns3_request *priv_req, int current_index,
480 int handled),
481 TP_ARGS(priv_req, current_index, handled)
482);
483#endif /* __LINUX_CDNS3_TRACE */
484
485/* this part must be outside header guard */
486
487#undef TRACE_INCLUDE_PATH
488#define TRACE_INCLUDE_PATH .
489
490#undef TRACE_INCLUDE_FILE
491#define TRACE_INCLUDE_FILE trace
492
493#include <trace/define_trace.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 11:03:09 -0400