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authorLinus Walleij <linus.walleij@linaro.org>2018-03-22 06:16:18 -0400
committerStephen Boyd <sboyd@kernel.org>2018-03-23 12:36:11 -0400
commit726fef09b8018e58f1930fc7bc0a46e8d12ed8c1 (patch)
tree74189d547433f11a7a5284ba10440416f531e612
parent7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff)
clk: ux500: Drop AB8540/9540 support
The AB8540 was an evolved version of the AB8500, but it was never mass produced or put into products, only reference designs exist. The upstream support was never completed and it is unlikely that this will happen so drop the support for now to simplify maintenance of the AB8500. Cc: Loic Pallardy <loic.pallardy@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat
-rw-r--r--drivers/clk/ux500/Makefile2
-rw-r--r--drivers/clk/ux500/abx500-clk.c16
-rw-r--r--drivers/clk/ux500/u8540_clk.c597
-rw-r--r--drivers/clk/ux500/u9540_clk.c18
4 files changed, 0 insertions, 633 deletions
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index fedc083dc8be..53fd29002401 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -10,8 +10,6 @@ obj-y += clk-sysctrl.o
10 10
11# Clock definitions 11# Clock definitions
12obj-y += u8500_of_clk.o 12obj-y += u8500_of_clk.o
13obj-y += u9540_clk.o
14obj-y += u8540_clk.o
15 13
16# ABX500 clock driver 14# ABX500 clock driver
17obj-y += abx500-clk.o 15obj-y += abx500-clk.o
diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c
index 2257d12ba988..5a86cd8fe5de 100644
--- a/drivers/clk/ux500/abx500-clk.c
+++ b/drivers/clk/ux500/abx500-clk.c
@@ -88,18 +88,6 @@ static int ab8500_reg_clks(struct device *dev)
88 return 0; 88 return 0;
89} 89}
90 90
91/* Clock definitions for ab8540 */
92static int ab8540_reg_clks(struct device *dev)
93{
94 return 0;
95}
96
97/* Clock definitions for ab9540 */
98static int ab9540_reg_clks(struct device *dev)
99{
100 return 0;
101}
102
103static int abx500_clk_probe(struct platform_device *pdev) 91static int abx500_clk_probe(struct platform_device *pdev)
104{ 92{
105 struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent); 93 struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
@@ -107,10 +95,6 @@ static int abx500_clk_probe(struct platform_device *pdev)
107 95
108 if (is_ab8500(parent) || is_ab8505(parent)) { 96 if (is_ab8500(parent) || is_ab8505(parent)) {
109 ret = ab8500_reg_clks(&pdev->dev); 97 ret = ab8500_reg_clks(&pdev->dev);
110 } else if (is_ab8540(parent)) {
111 ret = ab8540_reg_clks(&pdev->dev);
112 } else if (is_ab9540(parent)) {
113 ret = ab9540_reg_clks(&pdev->dev);
114 } else { 98 } else {
115 dev_err(&pdev->dev, "non supported plf id\n"); 99 dev_err(&pdev->dev, "non supported plf id\n");
116 return -ENODEV; 100 return -ENODEV;
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
deleted file mode 100644
index 133859f0e2bf..000000000000
--- a/drivers/clk/ux500/u8540_clk.c
+++ /dev/null
@@ -1,597 +0,0 @@
1/*
2 * Clock definitions for u8540 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/mfd/dbx500-prcmu.h>
15#include "clk.h"
16
17/* CLKRST4 is missing making it hard to index things */
18enum clkrst_index {
19 CLKRST1_INDEX = 0,
20 CLKRST2_INDEX,
21 CLKRST3_INDEX,
22 CLKRST5_INDEX,
23 CLKRST6_INDEX,
24 CLKRST_MAX,
25};
26
27static void u8540_clk_init(struct device_node *np)
28{
29 struct clk *clk;
30 u32 bases[CLKRST_MAX];
31 int i;
32
33 for (i = 0; i < ARRAY_SIZE(bases); i++) {
34 struct resource r;
35
36 if (of_address_to_resource(np, i, &r))
37 /* Not much choice but to continue */
38 pr_err("failed to get CLKRST %d base address\n",
39 i + 1);
40 bases[i] = r.start;
41 }
42
43 /* Clock sources. */
44 /* Fixed ClockGen */
45 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
46 CLK_IGNORE_UNUSED);
47 clk_register_clkdev(clk, "soc0_pll", NULL);
48
49 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
50 CLK_IGNORE_UNUSED);
51 clk_register_clkdev(clk, "soc1_pll", NULL);
52
53 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
54 CLK_IGNORE_UNUSED);
55 clk_register_clkdev(clk, "ddr_pll", NULL);
56
57 clk = clk_register_fixed_rate(NULL, "rtc32k", NULL,
58 CLK_IGNORE_UNUSED,
59 32768);
60 clk_register_clkdev(clk, "clk32k", NULL);
61 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
62
63 clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL,
64 CLK_IGNORE_UNUSED,
65 38400000);
66
67 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
68 clk_register_clkdev(clk, NULL, "UART");
69
70 /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */
71 clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1",
72 PRCMU_MSP02CLK, 0);
73 clk_register_clkdev(clk, NULL, "MSP02");
74
75 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
76 clk_register_clkdev(clk, NULL, "MSP1");
77
78 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
79 clk_register_clkdev(clk, NULL, "I2C");
80
81 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
82 clk_register_clkdev(clk, NULL, "slim");
83
84 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
85 clk_register_clkdev(clk, NULL, "PERIPH1");
86
87 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
88 clk_register_clkdev(clk, NULL, "PERIPH2");
89
90 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
91 clk_register_clkdev(clk, NULL, "PERIPH3");
92
93 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
94 clk_register_clkdev(clk, NULL, "PERIPH5");
95
96 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
97 clk_register_clkdev(clk, NULL, "PERIPH6");
98
99 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
100 clk_register_clkdev(clk, NULL, "PERIPH7");
101
102 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
103 CLK_SET_RATE_GATE);
104 clk_register_clkdev(clk, NULL, "lcd");
105 clk_register_clkdev(clk, "lcd", "mcde");
106
107 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
108 clk_register_clkdev(clk, NULL, "bml");
109
110 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
111 CLK_SET_RATE_GATE);
112
113 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
114 CLK_SET_RATE_GATE);
115
116 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
117 CLK_SET_RATE_GATE);
118 clk_register_clkdev(clk, NULL, "hdmi");
119 clk_register_clkdev(clk, "hdmi", "mcde");
120
121 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
122 clk_register_clkdev(clk, NULL, "apeat");
123
124 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, 0);
125 clk_register_clkdev(clk, NULL, "apetrace");
126
127 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
128 clk_register_clkdev(clk, NULL, "mcde");
129 clk_register_clkdev(clk, "mcde", "mcde");
130 clk_register_clkdev(clk, NULL, "dsilink.0");
131 clk_register_clkdev(clk, NULL, "dsilink.1");
132 clk_register_clkdev(clk, NULL, "dsilink.2");
133
134 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
135 clk_register_clkdev(clk, NULL, "ipi2");
136
137 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
138 clk_register_clkdev(clk, NULL, "dsialt");
139
140 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
141 clk_register_clkdev(clk, NULL, "dma40.0");
142
143 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
144 clk_register_clkdev(clk, NULL, "b2r2");
145 clk_register_clkdev(clk, NULL, "b2r2_core");
146 clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
147 clk_register_clkdev(clk, NULL, "b2r2_1_core");
148
149 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
150 CLK_SET_RATE_GATE);
151 clk_register_clkdev(clk, NULL, "tv");
152 clk_register_clkdev(clk, "tv", "mcde");
153
154 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
155 clk_register_clkdev(clk, NULL, "SSP");
156
157 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
158 clk_register_clkdev(clk, NULL, "rngclk");
159
160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
161 clk_register_clkdev(clk, NULL, "uicc");
162
163 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
164 clk_register_clkdev(clk, NULL, "mtu0");
165 clk_register_clkdev(clk, NULL, "mtu1");
166
167 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
168 PRCMU_SDMMCCLK, 100000000,
169 CLK_SET_RATE_GATE);
170 clk_register_clkdev(clk, NULL, "sdmmc");
171
172 clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL,
173 PRCMU_SDMMCHCLK, 400000000,
174 CLK_SET_RATE_GATE);
175 clk_register_clkdev(clk, NULL, "sdmmchclk");
176
177 clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, 0);
178 clk_register_clkdev(clk, NULL, "hva");
179
180 clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, 0);
181 clk_register_clkdev(clk, NULL, "g1");
182
183 clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0,
184 CLK_SET_RATE_GATE);
185 clk_register_clkdev(clk, "dsilcd", "mcde");
186
187 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
188 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
189 clk_register_clkdev(clk, "dsihs2", "mcde");
190 clk_register_clkdev(clk, "hs_clk", "dsilink.2");
191
192 clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk",
193 PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);
194 clk_register_clkdev(clk, "dsilcd_pll", "mcde");
195
196 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
197 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
198 clk_register_clkdev(clk, "dsihs0", "mcde");
199
200 clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll",
201 PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);
202 clk_register_clkdev(clk, "dsihs0", "mcde");
203 clk_register_clkdev(clk, "hs_clk", "dsilink.0");
204
205 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
206 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
207 clk_register_clkdev(clk, "dsihs1", "mcde");
208
209 clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll",
210 PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);
211 clk_register_clkdev(clk, "dsihs1", "mcde");
212 clk_register_clkdev(clk, "hs_clk", "dsilink.1");
213
214 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
215 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
216 clk_register_clkdev(clk, "lp_clk", "dsilink.0");
217 clk_register_clkdev(clk, "dsilp0", "mcde");
218
219 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
220 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
221 clk_register_clkdev(clk, "lp_clk", "dsilink.1");
222 clk_register_clkdev(clk, "dsilp1", "mcde");
223
224 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
225 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
226 clk_register_clkdev(clk, "lp_clk", "dsilink.2");
227 clk_register_clkdev(clk, "dsilp2", "mcde");
228
229 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
230 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
231 clk_register_clkdev(clk, "armss", NULL);
232
233 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
234 CLK_IGNORE_UNUSED, 1, 2);
235 clk_register_clkdev(clk, NULL, "smp_twd");
236
237 /* PRCC P-clocks */
238 /* Peripheral 1 : PRCC P-clocks */
239 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
240 BIT(0), 0);
241 clk_register_clkdev(clk, "apb_pclk", "uart0");
242
243 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
244 BIT(1), 0);
245 clk_register_clkdev(clk, "apb_pclk", "uart1");
246
247 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
248 BIT(2), 0);
249 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
250
251 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
252 BIT(3), 0);
253 clk_register_clkdev(clk, "apb_pclk", "msp0");
254 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0");
255
256 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
257 BIT(4), 0);
258 clk_register_clkdev(clk, "apb_pclk", "msp1");
259 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1");
260
261 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
262 BIT(5), 0);
263 clk_register_clkdev(clk, "apb_pclk", "sdi0");
264
265 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
266 BIT(6), 0);
267 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
268
269 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
270 BIT(7), 0);
271 clk_register_clkdev(clk, NULL, "spi3");
272
273 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
274 BIT(8), 0);
275 clk_register_clkdev(clk, "apb_pclk", "slimbus0");
276
277 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
278 BIT(9), 0);
279 clk_register_clkdev(clk, NULL, "gpio.0");
280 clk_register_clkdev(clk, NULL, "gpio.1");
281 clk_register_clkdev(clk, NULL, "gpioblock0");
282 clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0");
283
284 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
285 BIT(10), 0);
286 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
287
288 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
289 BIT(11), 0);
290 clk_register_clkdev(clk, "apb_pclk", "msp3");
291 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3");
292
293 /* Peripheral 2 : PRCC P-clocks */
294 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
295 BIT(0), 0);
296 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
297
298 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
299 BIT(1), 0);
300 clk_register_clkdev(clk, NULL, "spi2");
301
302 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
303 BIT(2), 0);
304 clk_register_clkdev(clk, NULL, "spi1");
305
306 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
307 BIT(3), 0);
308 clk_register_clkdev(clk, NULL, "pwl");
309
310 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
311 BIT(4), 0);
312 clk_register_clkdev(clk, "apb_pclk", "sdi4");
313
314 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
315 BIT(5), 0);
316 clk_register_clkdev(clk, "apb_pclk", "msp2");
317 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2");
318
319 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
320 BIT(6), 0);
321 clk_register_clkdev(clk, "apb_pclk", "sdi1");
322
323 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
324 BIT(7), 0);
325 clk_register_clkdev(clk, "apb_pclk", "sdi3");
326
327 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
328 BIT(8), 0);
329 clk_register_clkdev(clk, NULL, "spi0");
330
331 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
332 BIT(9), 0);
333 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
334
335 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
336 BIT(10), 0);
337 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
338
339 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
340 BIT(11), 0);
341 clk_register_clkdev(clk, NULL, "gpio.6");
342 clk_register_clkdev(clk, NULL, "gpio.7");
343 clk_register_clkdev(clk, NULL, "gpioblock1");
344
345 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
346 BIT(12), 0);
347 clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0");
348
349 /* Peripheral 3 : PRCC P-clocks */
350 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
351 BIT(0), 0);
352 clk_register_clkdev(clk, NULL, "fsmc");
353
354 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
355 BIT(1), 0);
356 clk_register_clkdev(clk, "apb_pclk", "ssp0");
357
358 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
359 BIT(2), 0);
360 clk_register_clkdev(clk, "apb_pclk", "ssp1");
361
362 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
363 BIT(3), 0);
364 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
365
366 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
367 BIT(4), 0);
368 clk_register_clkdev(clk, "apb_pclk", "sdi2");
369
370 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
371 BIT(5), 0);
372 clk_register_clkdev(clk, "apb_pclk", "ske");
373 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
374
375 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
376 BIT(6), 0);
377 clk_register_clkdev(clk, "apb_pclk", "uart2");
378
379 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
380 BIT(7), 0);
381 clk_register_clkdev(clk, "apb_pclk", "sdi5");
382
383 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
384 BIT(8), 0);
385 clk_register_clkdev(clk, NULL, "gpio.2");
386 clk_register_clkdev(clk, NULL, "gpio.3");
387 clk_register_clkdev(clk, NULL, "gpio.4");
388 clk_register_clkdev(clk, NULL, "gpio.5");
389 clk_register_clkdev(clk, NULL, "gpioblock2");
390
391 clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", bases[CLKRST3_INDEX],
392 BIT(9), 0);
393 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5");
394
395 clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", bases[CLKRST3_INDEX],
396 BIT(10), 0);
397 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6");
398
399 clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", bases[CLKRST3_INDEX],
400 BIT(11), 0);
401 clk_register_clkdev(clk, "apb_pclk", "uart3");
402
403 clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", bases[CLKRST3_INDEX],
404 BIT(12), 0);
405 clk_register_clkdev(clk, "apb_pclk", "uart4");
406
407 /* Peripheral 5 : PRCC P-clocks */
408 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
409 BIT(0), 0);
410 clk_register_clkdev(clk, "usb", "musb-ux500.0");
411 clk_register_clkdev(clk, "usbclk", "ab-iddet.0");
412
413 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
414 BIT(1), 0);
415 clk_register_clkdev(clk, NULL, "gpio.8");
416 clk_register_clkdev(clk, NULL, "gpioblock3");
417
418 /* Peripheral 6 : PRCC P-clocks */
419 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
420 BIT(0), 0);
421 clk_register_clkdev(clk, "apb_pclk", "rng");
422
423 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
424 BIT(1), 0);
425 clk_register_clkdev(clk, NULL, "cryp0");
426 clk_register_clkdev(clk, NULL, "cryp1");
427
428 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
429 BIT(2), 0);
430 clk_register_clkdev(clk, NULL, "hash0");
431
432 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
433 BIT(3), 0);
434 clk_register_clkdev(clk, NULL, "pka");
435
436 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
437 BIT(4), 0);
438 clk_register_clkdev(clk, NULL, "db8540-hash1");
439
440 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
441 BIT(5), 0);
442 clk_register_clkdev(clk, NULL, "cfgreg");
443
444 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
445 BIT(6), 0);
446 clk_register_clkdev(clk, "apb_pclk", "mtu0");
447
448 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
449 BIT(7), 0);
450 clk_register_clkdev(clk, "apb_pclk", "mtu1");
451
452 /*
453 * PRCC K-clocks ==> see table PRCC_PCKEN/PRCC_KCKEN
454 * This differs from the internal implementation:
455 * We don't use the PERPIH[n| clock as parent, since those _should_
456 * only be used as parents for the P-clocks.
457 * TODO: "parentjoin" with corresponding P-clocks for all K-clocks.
458 */
459
460 /* Peripheral 1 : PRCC K-clocks */
461 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
462 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
463 clk_register_clkdev(clk, NULL, "uart0");
464
465 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
466 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
467 clk_register_clkdev(clk, NULL, "uart1");
468
469 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
470 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
471 clk_register_clkdev(clk, NULL, "nmk-i2c.1");
472
473 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
474 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
475 clk_register_clkdev(clk, NULL, "msp0");
476 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0");
477
478 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
479 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
480 clk_register_clkdev(clk, NULL, "msp1");
481 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1");
482
483 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk",
484 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
485 clk_register_clkdev(clk, NULL, "sdi0");
486
487 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
488 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
489 clk_register_clkdev(clk, NULL, "nmk-i2c.2");
490
491 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
492 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
493 clk_register_clkdev(clk, NULL, "slimbus0");
494
495 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
496 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
497 clk_register_clkdev(clk, NULL, "nmk-i2c.4");
498
499 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
500 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
501 clk_register_clkdev(clk, NULL, "msp3");
502 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3");
503
504 /* Peripheral 2 : PRCC K-clocks */
505 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
506 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
507 clk_register_clkdev(clk, NULL, "nmk-i2c.3");
508
509 clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k",
510 bases[CLKRST2_INDEX], BIT(1), CLK_SET_RATE_GATE);
511 clk_register_clkdev(clk, NULL, "pwl");
512
513 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk",
514 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
515 clk_register_clkdev(clk, NULL, "sdi4");
516
517 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
518 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
519 clk_register_clkdev(clk, NULL, "msp2");
520 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2");
521
522 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk",
523 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
524 clk_register_clkdev(clk, NULL, "sdi1");
525
526 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
527 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
528 clk_register_clkdev(clk, NULL, "sdi3");
529
530 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
531 bases[CLKRST2_INDEX], BIT(6),
532 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
533 clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0");
534
535 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
536 bases[CLKRST2_INDEX], BIT(7),
537 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
538 clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0");
539
540 /* Should only be 9540, but might be added for 85xx as well */
541 clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk",
542 bases[CLKRST2_INDEX], BIT(9), CLK_SET_RATE_GATE);
543 clk_register_clkdev(clk, NULL, "msp4");
544 clk_register_clkdev(clk, "msp4", "ab85xx-codec.0");
545
546 /* Peripheral 3 : PRCC K-clocks */
547 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
548 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
549 clk_register_clkdev(clk, NULL, "ssp0");
550
551 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
552 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
553 clk_register_clkdev(clk, NULL, "ssp1");
554
555 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
556 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
557 clk_register_clkdev(clk, NULL, "nmk-i2c.0");
558
559 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk",
560 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
561 clk_register_clkdev(clk, NULL, "sdi2");
562
563 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
564 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
565 clk_register_clkdev(clk, NULL, "ske");
566 clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
567
568 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
569 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
570 clk_register_clkdev(clk, NULL, "uart2");
571
572 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
573 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
574 clk_register_clkdev(clk, NULL, "sdi5");
575
576 clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk",
577 bases[CLKRST3_INDEX], BIT(8), CLK_SET_RATE_GATE);
578 clk_register_clkdev(clk, NULL, "nmk-i2c.5");
579
580 clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk",
581 bases[CLKRST3_INDEX], BIT(9), CLK_SET_RATE_GATE);
582 clk_register_clkdev(clk, NULL, "nmk-i2c.6");
583
584 clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk",
585 bases[CLKRST3_INDEX], BIT(10), CLK_SET_RATE_GATE);
586 clk_register_clkdev(clk, NULL, "uart3");
587
588 clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk",
589 bases[CLKRST3_INDEX], BIT(11), CLK_SET_RATE_GATE);
590 clk_register_clkdev(clk, NULL, "uart4");
591
592 /* Peripheral 6 : PRCC K-clocks */
593 clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk",
594 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
595 clk_register_clkdev(clk, NULL, "rng");
596}
597CLK_OF_DECLARE(u8540_clks, "stericsson,u8540-clks", u8540_clk_init);
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
deleted file mode 100644
index 7b6bca49ce42..000000000000
--- a/drivers/clk/ux500/u9540_clk.c
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Clock definitions for u9540 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/mfd/dbx500-prcmu.h>
12#include "clk.h"
13
14static void u9540_clk_init(struct device_node *np)
15{
16 /* register clocks here */
17}
18CLK_OF_DECLARE(u9540_clks, "stericsson,u9540-clks", u9540_clk_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 16:27:22 -0400