summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2019-07-09 11:57:45 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-07-09 11:57:45 -0400
commit6e2bbb688aa6d05073dd1dd0b836d9becec195c1 (patch)
treeb267f5f593c397aa4c5eababc8d78ebc69ea3e7b
parent5ad18b2e60b75c7297a998dea702451d33a052ed (diff)
parent3d25025ce9c2f364ea4ee76f1461c8714b9c0b6d (diff)
Merge tag 'pwm/for-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding: "This set of changes contains a new driver for SiFive SoCs as well as enhancements to the core (device links are used to track dependencies between PWM providers and consumers, support for PWM controllers via ACPI, sysfs will now suspend/resume PWMs that it has claimed) and various existing drivers" * tag 'pwm/for-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (37 commits) pwm: fsl-ftm: Make sure to unlock mutex on failure pwm: fsl-ftm: Use write protection for prescaler & polarity pwm: fsl-ftm: More relaxed permissions for updating period pwm: atmel-hlcdc: Add compatible for SAM9X60 HLCDC's PWM pwm: bcm2835: Improve precision of PWM leds: pwm: Support ACPI via firmware-node framework pwm: Add support referencing PWMs from ACPI pwm: rcar: Remove suspend/resume support pwm: sysfs: Add suspend/resume support pwm: Add power management descriptions pwm: meson: Add documentation to the driver pwm: meson: Add support PWM_POLARITY_INVERSED when disabling pwm: meson: Don't cache struct pwm_state internally pwm: meson: Read the full hardware state in meson_pwm_get_state() pwm: meson: Simplify the calculation of the pre-divider and count pwm: meson: Move pwm_set_chip_data() to meson_pwm_request() pwm: meson: Add the per-channel register offsets and bits in a struct pwm: meson: Add the meson_pwm_channel data to struct meson_pwm pwm: meson: Pass struct pwm_device to meson_pwm_calc() pwm: meson: Don't duplicate the polarity internally ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt5
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-sifive.txt33
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt9
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-stm32.txt3
-rw-r--r--Documentation/pwm.txt7
-rw-r--r--drivers/leds/leds-pwm.c45
-rw-r--r--drivers/pwm/Kconfig11
-rw-r--r--drivers/pwm/Makefile1
-rw-r--r--drivers/pwm/core.c172
-rw-r--r--drivers/pwm/pwm-atmel-hlcdc.c1
-rw-r--r--drivers/pwm/pwm-bcm2835.c8
-rw-r--r--drivers/pwm/pwm-fsl-ftm.c383
-rw-r--r--drivers/pwm/pwm-jz4740.c49
-rw-r--r--drivers/pwm/pwm-meson.c386
-rw-r--r--drivers/pwm/pwm-rcar.c39
-rw-r--r--drivers/pwm/pwm-sifive.c339
-rw-r--r--drivers/pwm/pwm-stm32-lp.c25
-rw-r--r--drivers/pwm/pwm-stm32.c2
-rw-r--r--drivers/pwm/sysfs.c102
-rw-r--r--include/linux/pwm.h16
20 files changed, 1154 insertions, 482 deletions
diff --git a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
index 7d9d3f90641b..493bec80d59b 100644
--- a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt
@@ -2,10 +2,7 @@ Ingenic JZ47xx PWM Controller
2============================= 2=============================
3 3
4Required properties: 4Required properties:
5- compatible: One of: 5- compatible: Should be "ingenic,jz4740-pwm"
6 * "ingenic,jz4740-pwm"
7 * "ingenic,jz4770-pwm"
8 * "ingenic,jz4780-pwm"
9- #pwm-cells: Should be 3. See pwm.txt in this directory for a description 6- #pwm-cells: Should be 3. See pwm.txt in this directory for a description
10 of the cells format. 7 of the cells format.
11- clocks : phandle to the external clock. 8- clocks : phandle to the external clock.
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
new file mode 100644
index 000000000000..36447e3c9378
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
@@ -0,0 +1,33 @@
1SiFive PWM controller
2
3Unlike most other PWM controllers, the SiFive PWM controller currently only
4supports one period for all channels in the PWM. All PWMs need to run at
5the same period. The period also has significant restrictions on the values
6it can achieve, which the driver rounds to the nearest achievable period.
7PWM RTL that corresponds to the IP block version numbers can be found
8here:
9
10https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
11
12Required properties:
13- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
17 Please refer to sifive-blocks-ip-versioning.txt for details.
18- reg: physical base address and length of the controller's registers
19- clocks: Should contain a clock identifier for the PWM's parent clock.
20- #pwm-cells: Should be 3. See pwm.txt in this directory
21 for a description of the cell format.
22- interrupts: one interrupt per PWM channel
23
24Examples:
25
26pwm: pwm@10020000 {
27 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
28 reg = <0x0 0x10020000 0x0 0x1000>;
29 clocks = <&tlclk>;
30 interrupt-parent = <&plic>;
31 interrupts = <42 43 44 45>;
32 #pwm-cells = <3>;
33};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
index bd23302e84be..6521bc44a74e 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
@@ -11,8 +11,10 @@ Required parameters:
11 bindings defined in pwm.txt. 11 bindings defined in pwm.txt.
12 12
13Optional properties: 13Optional properties:
14- pinctrl-names: Set to "default". 14- pinctrl-names: Set to "default". An additional "sleep" state can be
15- pinctrl-0: Phandle pointing to pin configuration node for PWM. 15 defined to set pins in sleep state when in low power.
16- pinctrl-n: Phandle(s) pointing to pin configuration node for PWM,
17 respectively for "default" and "sleep" states.
16 18
17Example: 19Example:
18 timer@40002400 { 20 timer@40002400 {
@@ -21,7 +23,8 @@ Example:
21 pwm { 23 pwm {
22 compatible = "st,stm32-pwm-lp"; 24 compatible = "st,stm32-pwm-lp";
23 #pwm-cells = <3>; 25 #pwm-cells = <3>;
24 pinctrl-names = "default"; 26 pinctrl-names = "default", "sleep";
25 pinctrl-0 = <&lppwm1_pins>; 27 pinctrl-0 = <&lppwm1_pins>;
28 pinctrl-1 = <&lppwm1_sleep_pins>;
26 }; 29 };
27 }; 30 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
index 3e6d55018d7a..a8690bfa5e1f 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
@@ -8,6 +8,8 @@ Required parameters:
8- pinctrl-names: Set to "default". 8- pinctrl-names: Set to "default".
9- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. 9- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
10 For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt 10 For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
11- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
12 bindings defined in pwm.txt.
11 13
12Optional parameters: 14Optional parameters:
13- st,breakinput: One or two <index level filter> to describe break input configurations. 15- st,breakinput: One or two <index level filter> to describe break input configurations.
@@ -28,6 +30,7 @@ Example:
28 30
29 pwm { 31 pwm {
30 compatible = "st,stm32-pwm"; 32 compatible = "st,stm32-pwm";
33 #pwm-cells = <3>;
31 pinctrl-0 = <&pwm1_pins>; 34 pinctrl-0 = <&pwm1_pins>;
32 pinctrl-names = "default"; 35 pinctrl-names = "default";
33 st,breakinput = <0 1 5>; 36 st,breakinput = <0 1 5>;
diff --git a/Documentation/pwm.txt b/Documentation/pwm.txt
index 8fbf0aa3ba2d..ab62f1bb0366 100644
--- a/Documentation/pwm.txt
+++ b/Documentation/pwm.txt
@@ -65,6 +65,10 @@ period). struct pwm_args contains 2 fields (period and polarity) and should
65be used to set the initial PWM config (usually done in the probe function 65be used to set the initial PWM config (usually done in the probe function
66of the PWM user). PWM arguments are retrieved with pwm_get_args(). 66of the PWM user). PWM arguments are retrieved with pwm_get_args().
67 67
68All consumers should really be reconfiguring the PWM upon resume as
69appropriate. This is the only way to ensure that everything is resumed in
70the proper order.
71
68Using PWMs with the sysfs interface 72Using PWMs with the sysfs interface
69----------------------------------- 73-----------------------------------
70 74
@@ -141,6 +145,9 @@ The implementation of ->get_state() (a method used to retrieve initial PWM
141state) is also encouraged for the same reason: letting the PWM user know 145state) is also encouraged for the same reason: letting the PWM user know
142about the current PWM state would allow him to avoid glitches. 146about the current PWM state would allow him to avoid glitches.
143 147
148Drivers should not implement any power management. In other words,
149consumers should implement it as described in the "Using PWMs" section.
150
144Locking 151Locking
145------- 152-------
146 153
diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c
index 9328193189ba..48d068f80f11 100644
--- a/drivers/leds/leds-pwm.c
+++ b/drivers/leds/leds-pwm.c
@@ -72,7 +72,7 @@ static inline size_t sizeof_pwm_leds_priv(int num_leds)
72} 72}
73 73
74static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, 74static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv,
75 struct led_pwm *led, struct device_node *child) 75 struct led_pwm *led, struct fwnode_handle *fwnode)
76{ 76{
77 struct led_pwm_data *led_data = &priv->leds[priv->num_leds]; 77 struct led_pwm_data *led_data = &priv->leds[priv->num_leds];
78 struct pwm_args pargs; 78 struct pwm_args pargs;
@@ -85,8 +85,8 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv,
85 led_data->cdev.max_brightness = led->max_brightness; 85 led_data->cdev.max_brightness = led->max_brightness;
86 led_data->cdev.flags = LED_CORE_SUSPENDRESUME; 86 led_data->cdev.flags = LED_CORE_SUSPENDRESUME;
87 87
88 if (child) 88 if (fwnode)
89 led_data->pwm = devm_of_pwm_get(dev, child, NULL); 89 led_data->pwm = devm_fwnode_pwm_get(dev, fwnode, NULL);
90 else 90 else
91 led_data->pwm = devm_pwm_get(dev, led->name); 91 led_data->pwm = devm_pwm_get(dev, led->name);
92 if (IS_ERR(led_data->pwm)) { 92 if (IS_ERR(led_data->pwm)) {
@@ -111,7 +111,8 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv,
111 if (!led_data->period && (led->pwm_period_ns > 0)) 111 if (!led_data->period && (led->pwm_period_ns > 0))
112 led_data->period = led->pwm_period_ns; 112 led_data->period = led->pwm_period_ns;
113 113
114 ret = devm_of_led_classdev_register(dev, child, &led_data->cdev); 114 ret = devm_of_led_classdev_register(dev, to_of_node(fwnode),
115 &led_data->cdev);
115 if (ret == 0) { 116 if (ret == 0) {
116 priv->num_leds++; 117 priv->num_leds++;
117 led_pwm_set(&led_data->cdev, led_data->cdev.brightness); 118 led_pwm_set(&led_data->cdev, led_data->cdev.brightness);
@@ -123,27 +124,35 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv,
123 return ret; 124 return ret;
124} 125}
125 126
126static int led_pwm_create_of(struct device *dev, struct led_pwm_priv *priv) 127static int led_pwm_create_fwnode(struct device *dev, struct led_pwm_priv *priv)
127{ 128{
128 struct device_node *child; 129 struct fwnode_handle *fwnode;
129 struct led_pwm led; 130 struct led_pwm led;
130 int ret = 0; 131 int ret = 0;
131 132
132 memset(&led, 0, sizeof(led)); 133 memset(&led, 0, sizeof(led));
133 134
134 for_each_child_of_node(dev->of_node, child) { 135 device_for_each_child_node(dev, fwnode) {
135 led.name = of_get_property(child, "label", NULL) ? : 136 ret = fwnode_property_read_string(fwnode, "label", &led.name);
136 child->name; 137 if (ret && is_of_node(fwnode))
138 led.name = to_of_node(fwnode)->name;
137 139
138 led.default_trigger = of_get_property(child, 140 if (!led.name) {
139 "linux,default-trigger", NULL); 141 fwnode_handle_put(fwnode);
140 led.active_low = of_property_read_bool(child, "active-low"); 142 return -EINVAL;
141 of_property_read_u32(child, "max-brightness", 143 }
142 &led.max_brightness); 144
145 fwnode_property_read_string(fwnode, "linux,default-trigger",
146 &led.default_trigger);
147
148 led.active_low = fwnode_property_read_bool(fwnode,
149 "active-low");
150 fwnode_property_read_u32(fwnode, "max-brightness",
151 &led.max_brightness);
143 152
144 ret = led_pwm_add(dev, priv, &led, child); 153 ret = led_pwm_add(dev, priv, &led, fwnode);
145 if (ret) { 154 if (ret) {
146 of_node_put(child); 155 fwnode_handle_put(fwnode);
147 break; 156 break;
148 } 157 }
149 } 158 }
@@ -161,7 +170,7 @@ static int led_pwm_probe(struct platform_device *pdev)
161 if (pdata) 170 if (pdata)
162 count = pdata->num_leds; 171 count = pdata->num_leds;
163 else 172 else
164 count = of_get_child_count(pdev->dev.of_node); 173 count = device_get_child_node_count(&pdev->dev);
165 174
166 if (!count) 175 if (!count)
167 return -EINVAL; 176 return -EINVAL;
@@ -179,7 +188,7 @@ static int led_pwm_probe(struct platform_device *pdev)
179 break; 188 break;
180 } 189 }
181 } else { 190 } else {
182 ret = led_pwm_create_of(&pdev->dev, priv); 191 ret = led_pwm_create_fwnode(&pdev->dev, priv);
183 } 192 }
184 193
185 if (ret) 194 if (ret)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index dff5a93f7daa..a7e57516959e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -401,6 +401,17 @@ config PWM_SAMSUNG
401 To compile this driver as a module, choose M here: the module 401 To compile this driver as a module, choose M here: the module
402 will be called pwm-samsung. 402 will be called pwm-samsung.
403 403
404config PWM_SIFIVE
405 tristate "SiFive PWM support"
406 depends on OF
407 depends on COMMON_CLK
408 depends on RISCV || COMPILE_TEST
409 help
410 Generic PWM framework driver for SiFive SoCs.
411
412 To compile this driver as a module, choose M here: the module
413 will be called pwm-sifive.
414
404config PWM_SPEAR 415config PWM_SPEAR
405 tristate "STMicroelectronics SPEAr PWM support" 416 tristate "STMicroelectronics SPEAr PWM support"
406 depends on PLAT_SPEAR 417 depends on PLAT_SPEAR
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c368599d36c0..76b555b51887 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
39obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o 39obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
40obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o 40obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
41obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o 41obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
42obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
42obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o 43obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
43obj-$(CONFIG_PWM_STI) += pwm-sti.o 44obj-$(CONFIG_PWM_STI) += pwm-sti.o
44obj-$(CONFIG_PWM_STM32) += pwm-stm32.o 45obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index 275b5f399a1a..c3ab07ab31a9 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -6,6 +6,7 @@
6 * Copyright (C) 2011-2012 Avionic Design GmbH 6 * Copyright (C) 2011-2012 Avionic Design GmbH
7 */ 7 */
8 8
9#include <linux/acpi.h>
9#include <linux/module.h> 10#include <linux/module.h>
10#include <linux/pwm.h> 11#include <linux/pwm.h>
11#include <linux/radix-tree.h> 12#include <linux/radix-tree.h>
@@ -626,8 +627,35 @@ static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
626 return ERR_PTR(-EPROBE_DEFER); 627 return ERR_PTR(-EPROBE_DEFER);
627} 628}
628 629
630static struct device_link *pwm_device_link_add(struct device *dev,
631 struct pwm_device *pwm)
632{
633 struct device_link *dl;
634
635 if (!dev) {
636 /*
637 * No device for the PWM consumer has been provided. It may
638 * impact the PM sequence ordering: the PWM supplier may get
639 * suspended before the consumer.
640 */
641 dev_warn(pwm->chip->dev,
642 "No consumer device specified to create a link to\n");
643 return NULL;
644 }
645
646 dl = device_link_add(dev, pwm->chip->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
647 if (!dl) {
648 dev_err(dev, "failed to create device link to %s\n",
649 dev_name(pwm->chip->dev));
650 return ERR_PTR(-EINVAL);
651 }
652
653 return dl;
654}
655
629/** 656/**
630 * of_pwm_get() - request a PWM via the PWM framework 657 * of_pwm_get() - request a PWM via the PWM framework
658 * @dev: device for PWM consumer
631 * @np: device node to get the PWM from 659 * @np: device node to get the PWM from
632 * @con_id: consumer name 660 * @con_id: consumer name
633 * 661 *
@@ -645,10 +673,12 @@ static struct pwm_chip *of_node_to_pwmchip(struct device_node *np)
645 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded 673 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
646 * error code on failure. 674 * error code on failure.
647 */ 675 */
648struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id) 676struct pwm_device *of_pwm_get(struct device *dev, struct device_node *np,
677 const char *con_id)
649{ 678{
650 struct pwm_device *pwm = NULL; 679 struct pwm_device *pwm = NULL;
651 struct of_phandle_args args; 680 struct of_phandle_args args;
681 struct device_link *dl;
652 struct pwm_chip *pc; 682 struct pwm_chip *pc;
653 int index = 0; 683 int index = 0;
654 int err; 684 int err;
@@ -679,6 +709,14 @@ struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id)
679 if (IS_ERR(pwm)) 709 if (IS_ERR(pwm))
680 goto put; 710 goto put;
681 711
712 dl = pwm_device_link_add(dev, pwm);
713 if (IS_ERR(dl)) {
714 /* of_xlate ended up calling pwm_request_from_chip() */
715 pwm_free(pwm);
716 pwm = ERR_CAST(dl);
717 goto put;
718 }
719
682 /* 720 /*
683 * If a consumer name was not given, try to look it up from the 721 * If a consumer name was not given, try to look it up from the
684 * "pwm-names" property if it exists. Otherwise use the name of 722 * "pwm-names" property if it exists. Otherwise use the name of
@@ -700,6 +738,85 @@ put:
700} 738}
701EXPORT_SYMBOL_GPL(of_pwm_get); 739EXPORT_SYMBOL_GPL(of_pwm_get);
702 740
741#if IS_ENABLED(CONFIG_ACPI)
742static struct pwm_chip *device_to_pwmchip(struct device *dev)
743{
744 struct pwm_chip *chip;
745
746 mutex_lock(&pwm_lock);
747
748 list_for_each_entry(chip, &pwm_chips, list) {
749 struct acpi_device *adev = ACPI_COMPANION(chip->dev);
750
751 if ((chip->dev == dev) || (adev && &adev->dev == dev)) {
752 mutex_unlock(&pwm_lock);
753 return chip;
754 }
755 }
756
757 mutex_unlock(&pwm_lock);
758
759 return ERR_PTR(-EPROBE_DEFER);
760}
761#endif
762
763/**
764 * acpi_pwm_get() - request a PWM via parsing "pwms" property in ACPI
765 * @fwnode: firmware node to get the "pwm" property from
766 *
767 * Returns the PWM device parsed from the fwnode and index specified in the
768 * "pwms" property or a negative error-code on failure.
769 * Values parsed from the device tree are stored in the returned PWM device
770 * object.
771 *
772 * This is analogous to of_pwm_get() except con_id is not yet supported.
773 * ACPI entries must look like
774 * Package () {"pwms", Package ()
775 * { <PWM device reference>, <PWM index>, <PWM period> [, <PWM flags>]}}
776 *
777 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
778 * error code on failure.
779 */
780static struct pwm_device *acpi_pwm_get(struct fwnode_handle *fwnode)
781{
782 struct pwm_device *pwm = ERR_PTR(-ENODEV);
783#if IS_ENABLED(CONFIG_ACPI)
784 struct fwnode_reference_args args;
785 struct acpi_device *acpi;
786 struct pwm_chip *chip;
787 int ret;
788
789 memset(&args, 0, sizeof(args));
790
791 ret = __acpi_node_get_property_reference(fwnode, "pwms", 0, 3, &args);
792 if (ret < 0)
793 return ERR_PTR(ret);
794
795 acpi = to_acpi_device_node(args.fwnode);
796 if (!acpi)
797 return ERR_PTR(-EINVAL);
798
799 if (args.nargs < 2)
800 return ERR_PTR(-EPROTO);
801
802 chip = device_to_pwmchip(&acpi->dev);
803 if (IS_ERR(chip))
804 return ERR_CAST(chip);
805
806 pwm = pwm_request_from_chip(chip, args.args[0], NULL);
807 if (IS_ERR(pwm))
808 return pwm;
809
810 pwm->args.period = args.args[1];
811 pwm->args.polarity = PWM_POLARITY_NORMAL;
812
813 if (args.nargs > 2 && args.args[2] & PWM_POLARITY_INVERTED)
814 pwm->args.polarity = PWM_POLARITY_INVERSED;
815#endif
816
817 return pwm;
818}
819
703/** 820/**
704 * pwm_add_table() - register PWM device consumers 821 * pwm_add_table() - register PWM device consumers
705 * @table: array of consumers to register 822 * @table: array of consumers to register
@@ -754,6 +871,7 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id)
754 const char *dev_id = dev ? dev_name(dev) : NULL; 871 const char *dev_id = dev ? dev_name(dev) : NULL;
755 struct pwm_device *pwm; 872 struct pwm_device *pwm;
756 struct pwm_chip *chip; 873 struct pwm_chip *chip;
874 struct device_link *dl;
757 unsigned int best = 0; 875 unsigned int best = 0;
758 struct pwm_lookup *p, *chosen = NULL; 876 struct pwm_lookup *p, *chosen = NULL;
759 unsigned int match; 877 unsigned int match;
@@ -761,7 +879,11 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id)
761 879
762 /* look up via DT first */ 880 /* look up via DT first */
763 if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node) 881 if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node)
764 return of_pwm_get(dev->of_node, con_id); 882 return of_pwm_get(dev, dev->of_node, con_id);
883
884 /* then lookup via ACPI */
885 if (dev && is_acpi_node(dev->fwnode))
886 return acpi_pwm_get(dev->fwnode);
765 887
766 /* 888 /*
767 * We look up the provider in the static table typically provided by 889 * We look up the provider in the static table typically provided by
@@ -838,6 +960,12 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id)
838 if (IS_ERR(pwm)) 960 if (IS_ERR(pwm))
839 return pwm; 961 return pwm;
840 962
963 dl = pwm_device_link_add(dev, pwm);
964 if (IS_ERR(dl)) {
965 pwm_free(pwm);
966 return ERR_CAST(dl);
967 }
968
841 pwm->args.period = chosen->period; 969 pwm->args.period = chosen->period;
842 pwm->args.polarity = chosen->polarity; 970 pwm->args.polarity = chosen->polarity;
843 971
@@ -930,7 +1058,7 @@ struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np,
930 if (!ptr) 1058 if (!ptr)
931 return ERR_PTR(-ENOMEM); 1059 return ERR_PTR(-ENOMEM);
932 1060
933 pwm = of_pwm_get(np, con_id); 1061 pwm = of_pwm_get(dev, np, con_id);
934 if (!IS_ERR(pwm)) { 1062 if (!IS_ERR(pwm)) {
935 *ptr = pwm; 1063 *ptr = pwm;
936 devres_add(dev, ptr); 1064 devres_add(dev, ptr);
@@ -942,6 +1070,44 @@ struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np,
942} 1070}
943EXPORT_SYMBOL_GPL(devm_of_pwm_get); 1071EXPORT_SYMBOL_GPL(devm_of_pwm_get);
944 1072
1073/**
1074 * devm_fwnode_pwm_get() - request a resource managed PWM from firmware node
1075 * @dev: device for PWM consumer
1076 * @fwnode: firmware node to get the PWM from
1077 * @con_id: consumer name
1078 *
1079 * Returns the PWM device parsed from the firmware node. See of_pwm_get() and
1080 * acpi_pwm_get() for a detailed description.
1081 *
1082 * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded
1083 * error code on failure.
1084 */
1085struct pwm_device *devm_fwnode_pwm_get(struct device *dev,
1086 struct fwnode_handle *fwnode,
1087 const char *con_id)
1088{
1089 struct pwm_device **ptr, *pwm = ERR_PTR(-ENODEV);
1090
1091 ptr = devres_alloc(devm_pwm_release, sizeof(*ptr), GFP_KERNEL);
1092 if (!ptr)
1093 return ERR_PTR(-ENOMEM);
1094
1095 if (is_of_node(fwnode))
1096 pwm = of_pwm_get(dev, to_of_node(fwnode), con_id);
1097 else if (is_acpi_node(fwnode))
1098 pwm = acpi_pwm_get(fwnode);
1099
1100 if (!IS_ERR(pwm)) {
1101 *ptr = pwm;
1102 devres_add(dev, ptr);
1103 } else {
1104 devres_free(ptr);
1105 }
1106
1107 return pwm;
1108}
1109EXPORT_SYMBOL_GPL(devm_fwnode_pwm_get);
1110
945static int devm_pwm_match(struct device *dev, void *res, void *data) 1111static int devm_pwm_match(struct device *dev, void *res, void *data)
946{ 1112{
947 struct pwm_device **p = res; 1113 struct pwm_device **p = res;
diff --git a/drivers/pwm/pwm-atmel-hlcdc.c b/drivers/pwm/pwm-atmel-hlcdc.c
index 7186db85b15f..d13a83f430ac 100644
--- a/drivers/pwm/pwm-atmel-hlcdc.c
+++ b/drivers/pwm/pwm-atmel-hlcdc.c
@@ -235,6 +235,7 @@ static const struct of_device_id atmel_hlcdc_dt_ids[] = {
235 .compatible = "atmel,sama5d4-hlcdc", 235 .compatible = "atmel,sama5d4-hlcdc",
236 .data = &atmel_hlcdc_pwm_sama5d3_errata, 236 .data = &atmel_hlcdc_pwm_sama5d3_errata,
237 }, 237 },
238 { .compatible = "microchip,sam9x60-hlcdc", },
238 { /* sentinel */ }, 239 { /* sentinel */ },
239}; 240};
240MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids); 241MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids);
diff --git a/drivers/pwm/pwm-bcm2835.c b/drivers/pwm/pwm-bcm2835.c
index 5652f461d994..f6fe0b922e1e 100644
--- a/drivers/pwm/pwm-bcm2835.c
+++ b/drivers/pwm/pwm-bcm2835.c
@@ -70,7 +70,7 @@ static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
70 return -EINVAL; 70 return -EINVAL;
71 } 71 }
72 72
73 scaler = NSEC_PER_SEC / rate; 73 scaler = DIV_ROUND_CLOSEST(NSEC_PER_SEC, rate);
74 74
75 if (period_ns <= MIN_PERIOD) { 75 if (period_ns <= MIN_PERIOD) {
76 dev_err(pc->dev, "period %d not supported, minimum %d\n", 76 dev_err(pc->dev, "period %d not supported, minimum %d\n",
@@ -78,8 +78,10 @@ static int bcm2835_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
78 return -EINVAL; 78 return -EINVAL;
79 } 79 }
80 80
81 writel(duty_ns / scaler, pc->base + DUTY(pwm->hwpwm)); 81 writel(DIV_ROUND_CLOSEST(duty_ns, scaler),
82 writel(period_ns / scaler, pc->base + PERIOD(pwm->hwpwm)); 82 pc->base + DUTY(pwm->hwpwm));
83 writel(DIV_ROUND_CLOSEST(period_ns, scaler),
84 pc->base + PERIOD(pwm->hwpwm));
83 85
84 return 0; 86 return 0;
85} 87}
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index a39b48839df7..9d31a217111d 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -34,17 +34,19 @@ struct fsl_ftm_soc {
34 bool has_enable_bits; 34 bool has_enable_bits;
35}; 35};
36 36
37struct fsl_pwm_periodcfg {
38 enum fsl_pwm_clk clk_select;
39 unsigned int clk_ps;
40 unsigned int mod_period;
41};
42
37struct fsl_pwm_chip { 43struct fsl_pwm_chip {
38 struct pwm_chip chip; 44 struct pwm_chip chip;
39
40 struct mutex lock; 45 struct mutex lock;
41
42 unsigned int cnt_select;
43 unsigned int clk_ps;
44
45 struct regmap *regmap; 46 struct regmap *regmap;
46 47
47 int period_ns; 48 /* This value is valid iff a pwm is running */
49 struct fsl_pwm_periodcfg period;
48 50
49 struct clk *ipg_clk; 51 struct clk *ipg_clk;
50 struct clk *clk[FSL_PWM_CLK_MAX]; 52 struct clk *clk[FSL_PWM_CLK_MAX];
@@ -57,6 +59,33 @@ static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
57 return container_of(chip, struct fsl_pwm_chip, chip); 59 return container_of(chip, struct fsl_pwm_chip, chip);
58} 60}
59 61
62static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
63{
64 u32 val;
65
66 regmap_read(fpc->regmap, FTM_FMS, &val);
67 if (val & FTM_FMS_WPEN)
68 regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS,
69 FTM_MODE_WPDIS);
70}
71
72static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
73{
74 regmap_update_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN, FTM_FMS_WPEN);
75}
76
77static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
78 const struct fsl_pwm_periodcfg *b)
79{
80 if (a->clk_select != b->clk_select)
81 return false;
82 if (a->clk_ps != b->clk_ps)
83 return false;
84 if (a->mod_period != b->mod_period)
85 return false;
86 return true;
87}
88
60static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 89static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
61{ 90{
62 int ret; 91 int ret;
@@ -87,89 +116,58 @@ static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
87 clk_disable_unprepare(fpc->ipg_clk); 116 clk_disable_unprepare(fpc->ipg_clk);
88} 117}
89 118
90static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, 119static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
91 enum fsl_pwm_clk index) 120 unsigned int ticks)
92{ 121{
93 unsigned long sys_rate, cnt_rate; 122 unsigned long rate;
94 unsigned long long ratio; 123 unsigned long long exval;
95 124
96 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); 125 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
97 if (!sys_rate) 126 exval = ticks;
98 return -EINVAL; 127 exval *= 1000000000UL;
99 128 do_div(exval, rate >> fpc->period.clk_ps);
100 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); 129 return exval;
101 if (!cnt_rate)
102 return -EINVAL;
103
104 switch (index) {
105 case FSL_PWM_CLK_SYS:
106 fpc->clk_ps = 1;
107 break;
108 case FSL_PWM_CLK_FIX:
109 ratio = 2 * cnt_rate - 1;
110 do_div(ratio, sys_rate);
111 fpc->clk_ps = ratio;
112 break;
113 case FSL_PWM_CLK_EXT:
114 ratio = 4 * cnt_rate - 1;
115 do_div(ratio, sys_rate);
116 fpc->clk_ps = ratio;
117 break;
118 default:
119 return -EINVAL;
120 }
121
122 return 0;
123} 130}
124 131
125static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, 132static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
126 unsigned long period_ns) 133 unsigned int period_ns,
134 enum fsl_pwm_clk index,
135 struct fsl_pwm_periodcfg *periodcfg
136 )
127{ 137{
128 unsigned long long c, c0; 138 unsigned long long c;
139 unsigned int ps;
129 140
130 c = clk_get_rate(fpc->clk[fpc->cnt_select]); 141 c = clk_get_rate(fpc->clk[index]);
131 c = c * period_ns; 142 c = c * period_ns;
132 do_div(c, 1000000000UL); 143 do_div(c, 1000000000UL);
133 144
134 do { 145 if (c == 0)
135 c0 = c; 146 return false;
136 do_div(c0, (1 << fpc->clk_ps));
137 if (c0 <= 0xFFFF)
138 return (unsigned long)c0;
139 } while (++fpc->clk_ps < 8);
140
141 return 0;
142}
143
144static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc,
145 unsigned long period_ns,
146 enum fsl_pwm_clk index)
147{
148 int ret;
149 147
150 ret = fsl_pwm_calculate_default_ps(fpc, index); 148 for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
151 if (ret) { 149 if (c <= 0x10000) {
152 dev_err(fpc->chip.dev, 150 periodcfg->clk_select = index;
153 "failed to calculate default prescaler: %d\n", 151 periodcfg->clk_ps = ps;
154 ret); 152 periodcfg->mod_period = c - 1;
155 return 0; 153 return true;
154 }
156 } 155 }
157 156 return false;
158 return fsl_pwm_calculate_cycles(fpc, period_ns);
159} 157}
160 158
161static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 159static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
162 unsigned long period_ns) 160 unsigned int period_ns,
161 struct fsl_pwm_periodcfg *periodcfg)
163{ 162{
164 enum fsl_pwm_clk m0, m1; 163 enum fsl_pwm_clk m0, m1;
165 unsigned long fix_rate, ext_rate, cycles; 164 unsigned long fix_rate, ext_rate;
165 bool ret;
166 166
167 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, 167 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
168 FSL_PWM_CLK_SYS); 168 periodcfg);
169 if (cycles) { 169 if (ret)
170 fpc->cnt_select = FSL_PWM_CLK_SYS; 170 return true;
171 return cycles;
172 }
173 171
174 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 172 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
175 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 173 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
@@ -182,158 +180,185 @@ static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
182 m1 = FSL_PWM_CLK_FIX; 180 m1 = FSL_PWM_CLK_FIX;
183 } 181 }
184 182
185 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); 183 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
186 if (cycles) { 184 if (ret)
187 fpc->cnt_select = m0; 185 return true;
188 return cycles;
189 }
190
191 fpc->cnt_select = m1;
192 186
193 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); 187 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
194} 188}
195 189
196static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 190static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
197 unsigned long period_ns, 191 unsigned int duty_ns)
198 unsigned long duty_ns)
199{ 192{
200 unsigned long long duty; 193 unsigned long long duty;
201 u32 val;
202 194
203 regmap_read(fpc->regmap, FTM_MOD, &val); 195 unsigned int period = fpc->period.mod_period + 1;
204 duty = (unsigned long long)duty_ns * (val + 1); 196 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
197
198 duty = (unsigned long long)duty_ns * period;
205 do_div(duty, period_ns); 199 do_div(duty, period_ns);
206 200
207 return (unsigned long)duty; 201 return (unsigned int)duty;
208} 202}
209 203
210static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 204static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
211 int duty_ns, int period_ns) 205 struct pwm_device *pwm)
212{ 206{
213 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 207 u32 val;
214 u32 period, duty;
215 208
216 mutex_lock(&fpc->lock); 209 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
210 if (~val & 0xFF)
211 return true;
212 else
213 return false;
214}
215
216static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
217 struct pwm_device *pwm)
218{
219 u32 val;
217 220
221 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
222 if (~(val | BIT(pwm->hwpwm)) & 0xFF)
223 return true;
224 else
225 return false;
226}
227
228static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
229 struct pwm_device *pwm,
230 struct pwm_state *newstate)
231{
232 unsigned int duty;
233 u32 reg_polarity;
234
235 struct fsl_pwm_periodcfg periodcfg;
236 bool do_write_period = false;
237
238 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
239 dev_err(fpc->chip.dev, "failed to calculate new period\n");
240 return -EINVAL;
241 }
242
243 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
244 do_write_period = true;
218 /* 245 /*
219 * The Freescale FTM controller supports only a single period for 246 * The Freescale FTM controller supports only a single period for
220 * all PWM channels, therefore incompatible changes need to be 247 * all PWM channels, therefore verify if the newly computed period
221 * refused. 248 * is different than the current period being used. In such case
249 * we allow to change the period only if no other pwm is running.
222 */ 250 */
223 if (fpc->period_ns && fpc->period_ns != period_ns) { 251 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
224 dev_err(fpc->chip.dev, 252 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
225 "conflicting period requested for PWM %u\n", 253 dev_err(fpc->chip.dev,
226 pwm->hwpwm); 254 "Cannot change period for PWM %u, disable other PWMs first\n",
227 mutex_unlock(&fpc->lock); 255 pwm->hwpwm);
228 return -EBUSY; 256 return -EBUSY;
257 }
258 if (fpc->period.clk_select != periodcfg.clk_select) {
259 int ret;
260 enum fsl_pwm_clk oldclk = fpc->period.clk_select;
261 enum fsl_pwm_clk newclk = periodcfg.clk_select;
262
263 ret = clk_prepare_enable(fpc->clk[newclk]);
264 if (ret)
265 return ret;
266 clk_disable_unprepare(fpc->clk[oldclk]);
267 }
268 do_write_period = true;
229 } 269 }
230 270
231 if (!fpc->period_ns && duty_ns) { 271 ftm_clear_write_protection(fpc);
232 period = fsl_pwm_calculate_period(fpc, period_ns);
233 if (!period) {
234 dev_err(fpc->chip.dev, "failed to calculate period\n");
235 mutex_unlock(&fpc->lock);
236 return -EINVAL;
237 }
238 272
273 if (do_write_period) {
274 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
275 FTM_SC_CLK(periodcfg.clk_select));
239 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 276 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
240 fpc->clk_ps); 277 periodcfg.clk_ps);
241 regmap_write(fpc->regmap, FTM_MOD, period - 1); 278 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
242 279
243 fpc->period_ns = period_ns; 280 fpc->period = periodcfg;
244 } 281 }
245 282
246 mutex_unlock(&fpc->lock); 283 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
247
248 duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns);
249 284
250 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 285 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
251 FTM_CSC_MSB | FTM_CSC_ELSB); 286 FTM_CSC_MSB | FTM_CSC_ELSB);
252 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 287 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
253 288
254 return 0; 289 reg_polarity = 0;
255} 290 if (newstate->polarity == PWM_POLARITY_INVERSED)
256 291 reg_polarity = BIT(pwm->hwpwm);
257static int fsl_pwm_set_polarity(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 enum pwm_polarity polarity)
260{
261 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
262 u32 val;
263 292
264 regmap_read(fpc->regmap, FTM_POL, &val); 293 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
265 294
266 if (polarity == PWM_POLARITY_INVERSED) 295 newstate->period = fsl_pwm_ticks_to_ns(fpc,
267 val |= BIT(pwm->hwpwm); 296 fpc->period.mod_period + 1);
268 else 297 newstate->duty_cycle = fsl_pwm_ticks_to_ns(fpc, duty);
269 val &= ~BIT(pwm->hwpwm);
270 298
271 regmap_write(fpc->regmap, FTM_POL, val); 299 ftm_set_write_protection(fpc);
272 300
273 return 0; 301 return 0;
274} 302}
275 303
276static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) 304static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
277{ 305 struct pwm_state *newstate)
278 int ret;
279
280 /* select counter clock source */
281 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
282 FTM_SC_CLK(fpc->cnt_select));
283
284 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]);
285 if (ret)
286 return ret;
287
288 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
289 if (ret) {
290 clk_disable_unprepare(fpc->clk[fpc->cnt_select]);
291 return ret;
292 }
293
294 return 0;
295}
296
297static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
298{ 306{
299 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 307 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
300 int ret; 308 struct pwm_state *oldstate = &pwm->state;
301 309 int ret = 0;
302 mutex_lock(&fpc->lock);
303 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0);
304 310
305 ret = fsl_counter_clock_enable(fpc); 311 /*
306 mutex_unlock(&fpc->lock); 312 * oldstate to newstate : action
313 *
314 * disabled to disabled : ignore
315 * enabled to disabled : disable
316 * enabled to enabled : update settings
317 * disabled to enabled : update settings + enable
318 */
307 319
308 return ret; 320 mutex_lock(&fpc->lock);
309}
310 321
311static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 322 if (!newstate->enabled) {
312{ 323 if (oldstate->enabled) {
313 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 324 regmap_update_bits(fpc->regmap, FTM_OUTMASK,
314 u32 val; 325 BIT(pwm->hwpwm), BIT(pwm->hwpwm));
326 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
327 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
328 }
315 329
316 mutex_lock(&fpc->lock); 330 goto end_mutex;
317 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 331 }
318 BIT(pwm->hwpwm));
319 332
320 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 333 ret = fsl_pwm_apply_config(fpc, pwm, newstate);
321 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 334 if (ret)
335 goto end_mutex;
336
337 /* check if need to enable */
338 if (!oldstate->enabled) {
339 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
340 if (ret)
341 goto end_mutex;
342
343 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
344 if (ret) {
345 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
346 goto end_mutex;
347 }
322 348
323 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 349 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm),
324 if ((val & 0xFF) == 0xFF) 350 0);
325 fpc->period_ns = 0; 351 }
326 352
353end_mutex:
327 mutex_unlock(&fpc->lock); 354 mutex_unlock(&fpc->lock);
355 return ret;
328} 356}
329 357
330static const struct pwm_ops fsl_pwm_ops = { 358static const struct pwm_ops fsl_pwm_ops = {
331 .request = fsl_pwm_request, 359 .request = fsl_pwm_request,
332 .free = fsl_pwm_free, 360 .free = fsl_pwm_free,
333 .config = fsl_pwm_config, 361 .apply = fsl_pwm_apply,
334 .set_polarity = fsl_pwm_set_polarity,
335 .enable = fsl_pwm_enable,
336 .disable = fsl_pwm_disable,
337 .owner = THIS_MODULE, 362 .owner = THIS_MODULE,
338}; 363};
339 364
@@ -357,6 +382,8 @@ static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
357static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) 382static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
358{ 383{
359 switch (reg) { 384 switch (reg) {
385 case FTM_FMS:
386 case FTM_MODE:
360 case FTM_CNT: 387 case FTM_CNT:
361 return true; 388 return true;
362 } 389 }
@@ -474,7 +501,7 @@ static int fsl_pwm_suspend(struct device *dev)
474 continue; 501 continue;
475 502
476 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 503 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
477 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 504 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
478 } 505 }
479 506
480 return 0; 507 return 0;
@@ -496,7 +523,7 @@ static int fsl_pwm_resume(struct device *dev)
496 if (!pwm_is_enabled(pwm)) 523 if (!pwm_is_enabled(pwm))
497 continue; 524 continue;
498 525
499 clk_prepare_enable(fpc->clk[fpc->cnt_select]); 526 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
500 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 527 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
501 } 528 }
502 529
diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
index 88a51a40e695..f901e8a0d33d 100644
--- a/drivers/pwm/pwm-jz4740.c
+++ b/drivers/pwm/pwm-jz4740.c
@@ -63,7 +63,15 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
63{ 63{
64 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); 64 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
65 65
66 /* Disable PWM output. 66 /*
67 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
68 * properly return to their init level.
69 */
70 jz4740_timer_set_duty(pwm->hwpwm, 0xffff);
71 jz4740_timer_set_period(pwm->hwpwm, 0x0);
72
73 /*
74 * Disable PWM output.
67 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the 75 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
68 * counter is stopped, while in TCU1 mode the order does not matter. 76 * counter is stopped, while in TCU1 mode the order does not matter.
69 */ 77 */
@@ -74,17 +82,16 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
74 jz4740_timer_disable(pwm->hwpwm); 82 jz4740_timer_disable(pwm->hwpwm);
75} 83}
76 84
77static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 85static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
78 int duty_ns, int period_ns) 86 struct pwm_state *state)
79{ 87{
80 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); 88 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
81 unsigned long long tmp; 89 unsigned long long tmp;
82 unsigned long period, duty; 90 unsigned long period, duty;
83 unsigned int prescaler = 0; 91 unsigned int prescaler = 0;
84 uint16_t ctrl; 92 uint16_t ctrl;
85 bool is_enabled;
86 93
87 tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns; 94 tmp = (unsigned long long)clk_get_rate(jz4740->clk) * state->period;
88 do_div(tmp, 1000000000); 95 do_div(tmp, 1000000000);
89 period = tmp; 96 period = tmp;
90 97
@@ -96,16 +103,14 @@ static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96 if (prescaler == 6) 103 if (prescaler == 6)
97 return -EINVAL; 104 return -EINVAL;
98 105
99 tmp = (unsigned long long)period * duty_ns; 106 tmp = (unsigned long long)period * state->duty_cycle;
100 do_div(tmp, period_ns); 107 do_div(tmp, state->period);
101 duty = period - tmp; 108 duty = period - tmp;
102 109
103 if (duty >= period) 110 if (duty >= period)
104 duty = period - 1; 111 duty = period - 1;
105 112
106 is_enabled = jz4740_timer_is_enabled(pwm->hwpwm); 113 jz4740_pwm_disable(chip, pwm);
107 if (is_enabled)
108 jz4740_pwm_disable(chip, pwm);
109 114
110 jz4740_timer_set_count(pwm->hwpwm, 0); 115 jz4740_timer_set_count(pwm->hwpwm, 0);
111 jz4740_timer_set_duty(pwm->hwpwm, duty); 116 jz4740_timer_set_duty(pwm->hwpwm, duty);
@@ -116,18 +121,7 @@ static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
116 121
117 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); 122 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
118 123
119 if (is_enabled) 124 switch (state->polarity) {
120 jz4740_pwm_enable(chip, pwm);
121
122 return 0;
123}
124
125static int jz4740_pwm_set_polarity(struct pwm_chip *chip,
126 struct pwm_device *pwm, enum pwm_polarity polarity)
127{
128 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
129
130 switch (polarity) {
131 case PWM_POLARITY_NORMAL: 125 case PWM_POLARITY_NORMAL:
132 ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW; 126 ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
133 break; 127 break;
@@ -137,16 +131,17 @@ static int jz4740_pwm_set_polarity(struct pwm_chip *chip,
137 } 131 }
138 132
139 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); 133 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
134
135 if (state->enabled)
136 jz4740_pwm_enable(chip, pwm);
137
140 return 0; 138 return 0;
141} 139}
142 140
143static const struct pwm_ops jz4740_pwm_ops = { 141static const struct pwm_ops jz4740_pwm_ops = {
144 .request = jz4740_pwm_request, 142 .request = jz4740_pwm_request,
145 .free = jz4740_pwm_free, 143 .free = jz4740_pwm_free,
146 .config = jz4740_pwm_config, 144 .apply = jz4740_pwm_apply,
147 .set_polarity = jz4740_pwm_set_polarity,
148 .enable = jz4740_pwm_enable,
149 .disable = jz4740_pwm_disable,
150 .owner = THIS_MODULE, 145 .owner = THIS_MODULE,
151}; 146};
152 147
@@ -184,8 +179,6 @@ static int jz4740_pwm_remove(struct platform_device *pdev)
184#ifdef CONFIG_OF 179#ifdef CONFIG_OF
185static const struct of_device_id jz4740_pwm_dt_ids[] = { 180static const struct of_device_id jz4740_pwm_dt_ids[] = {
186 { .compatible = "ingenic,jz4740-pwm", }, 181 { .compatible = "ingenic,jz4740-pwm", },
187 { .compatible = "ingenic,jz4770-pwm", },
188 { .compatible = "ingenic,jz4780-pwm", },
189 {}, 182 {},
190}; 183};
191MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); 184MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index fb5a369b1a8d..3cbff5cbb789 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -1,65 +1,40 @@
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
1/* 2/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * PWM controller driver for Amlogic Meson SoCs.
3 * redistributing this file, you may do so under either license.
4 * 4 *
5 * GPL LICENSE SUMMARY 5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
6 * 16 *
7 * Copyright (c) 2016 BayLibre, SAS. 17 * The public S912 (GXM) datasheet contains some documentation for this PWM
8 * Author: Neil Armstrong <narmstrong@baylibre.com> 18 * controller starting on page 543:
9 * Copyright (C) 2014 Amlogic, Inc. 19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
10 * 20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
11 * This program is free software; you can redistribute it and/or modify 21 * datasheet contains the description for this IP block revision starting at
12 * it under the terms of version 2 of the GNU General Public License as 22 * page 1084:
13 * published by the Free Software Foundation. 23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * BSD LICENSE
26 * 24 *
27 * Copyright (c) 2016 BayLibre, SAS. 25 * Copyright (c) 2016 BayLibre, SAS.
28 * Author: Neil Armstrong <narmstrong@baylibre.com> 26 * Author: Neil Armstrong <narmstrong@baylibre.com>
29 * Copyright (C) 2014 Amlogic, Inc. 27 * Copyright (C) 2014 Amlogic, Inc.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 *
35 * * Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * * Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in
39 * the documentation and/or other materials provided with the
40 * distribution.
41 * * Neither the name of Intel Corporation nor the names of its
42 * contributors may be used to endorse or promote products derived
43 * from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
47 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
48 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
49 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 */ 28 */
57 29
30#include <linux/bitfield.h>
31#include <linux/bits.h>
58#include <linux/clk.h> 32#include <linux/clk.h>
59#include <linux/clk-provider.h> 33#include <linux/clk-provider.h>
60#include <linux/err.h> 34#include <linux/err.h>
61#include <linux/io.h> 35#include <linux/io.h>
62#include <linux/kernel.h> 36#include <linux/kernel.h>
37#include <linux/math64.h>
63#include <linux/module.h> 38#include <linux/module.h>
64#include <linux/of.h> 39#include <linux/of.h>
65#include <linux/of_device.h> 40#include <linux/of_device.h>
@@ -70,7 +45,8 @@
70 45
71#define REG_PWM_A 0x0 46#define REG_PWM_A 0x0
72#define REG_PWM_B 0x4 47#define REG_PWM_B 0x4
73#define PWM_HIGH_SHIFT 16 48#define PWM_LOW_MASK GENMASK(15, 0)
49#define PWM_HIGH_MASK GENMASK(31, 16)
74 50
75#define REG_MISC_AB 0x8 51#define REG_MISC_AB 0x8
76#define MISC_B_CLK_EN BIT(23) 52#define MISC_B_CLK_EN BIT(23)
@@ -80,13 +56,33 @@
80#define MISC_A_CLK_DIV_SHIFT 8 56#define MISC_A_CLK_DIV_SHIFT 8
81#define MISC_B_CLK_SEL_SHIFT 6 57#define MISC_B_CLK_SEL_SHIFT 6
82#define MISC_A_CLK_SEL_SHIFT 4 58#define MISC_A_CLK_SEL_SHIFT 4
83#define MISC_CLK_SEL_WIDTH 2 59#define MISC_CLK_SEL_MASK 0x3
84#define MISC_B_EN BIT(1) 60#define MISC_B_EN BIT(1)
85#define MISC_A_EN BIT(0) 61#define MISC_A_EN BIT(0)
86 62
87static const unsigned int mux_reg_shifts[] = { 63#define MESON_NUM_PWMS 2
88 MISC_A_CLK_SEL_SHIFT, 64
89 MISC_B_CLK_SEL_SHIFT 65static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u32 clk_en_mask;
70 u32 pwm_en_mask;
71} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_mask = MISC_A_CLK_EN,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_mask = MISC_B_CLK_EN,
84 .pwm_en_mask = MISC_B_EN,
85 }
90}; 86};
91 87
92struct meson_pwm_channel { 88struct meson_pwm_channel {
@@ -94,8 +90,6 @@ struct meson_pwm_channel {
94 unsigned int lo; 90 unsigned int lo;
95 u8 pre_div; 91 u8 pre_div;
96 92
97 struct pwm_state state;
98
99 struct clk *clk_parent; 93 struct clk *clk_parent;
100 struct clk_mux mux; 94 struct clk_mux mux;
101 struct clk *clk; 95 struct clk *clk;
@@ -109,8 +103,8 @@ struct meson_pwm_data {
109struct meson_pwm { 103struct meson_pwm {
110 struct pwm_chip chip; 104 struct pwm_chip chip;
111 const struct meson_pwm_data *data; 105 const struct meson_pwm_data *data;
106 struct meson_pwm_channel channels[MESON_NUM_PWMS];
112 void __iomem *base; 107 void __iomem *base;
113 u8 inverter_mask;
114 /* 108 /*
115 * Protects register (write) access to the REG_MISC_AB register 109 * Protects register (write) access to the REG_MISC_AB register
116 * that is shared between the two PWMs. 110 * that is shared between the two PWMs.
@@ -125,12 +119,16 @@ static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
125 119
126static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 120static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
127{ 121{
128 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); 122 struct meson_pwm *meson = to_meson_pwm(chip);
123 struct meson_pwm_channel *channel;
129 struct device *dev = chip->dev; 124 struct device *dev = chip->dev;
130 int err; 125 int err;
131 126
132 if (!channel) 127 channel = pwm_get_chip_data(pwm);
133 return -ENODEV; 128 if (channel)
129 return 0;
130
131 channel = &meson->channels[pwm->hwpwm];
134 132
135 if (channel->clk_parent) { 133 if (channel->clk_parent) {
136 err = clk_set_parent(channel->clk, channel->clk_parent); 134 err = clk_set_parent(channel->clk, channel->clk_parent);
@@ -149,9 +147,7 @@ static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
149 return err; 147 return err;
150 } 148 }
151 149
152 chip->ops->get_state(chip, pwm, &channel->state); 150 return pwm_set_chip_data(pwm, channel);
153
154 return 0;
155} 151}
156 152
157static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 153static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
@@ -162,20 +158,18 @@ static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
162 clk_disable_unprepare(channel->clk); 158 clk_disable_unprepare(channel->clk);
163} 159}
164 160
165static int meson_pwm_calc(struct meson_pwm *meson, 161static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
166 struct meson_pwm_channel *channel, unsigned int id, 162 struct pwm_state *state)
167 unsigned int duty, unsigned int period)
168{ 163{
169 unsigned int pre_div, cnt, duty_cnt; 164 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
165 unsigned int duty, period, pre_div, cnt, duty_cnt;
170 unsigned long fin_freq = -1; 166 unsigned long fin_freq = -1;
171 u64 fin_ps;
172 167
173 if (~(meson->inverter_mask >> id) & 0x1) 168 duty = state->duty_cycle;
174 duty = period - duty; 169 period = state->period;
175 170
176 if (period == channel->state.period && 171 if (state->polarity == PWM_POLARITY_INVERSED)
177 duty == channel->state.duty_cycle) 172 duty = period - duty;
178 return 0;
179 173
180 fin_freq = clk_get_rate(channel->clk); 174 fin_freq = clk_get_rate(channel->clk);
181 if (fin_freq == 0) { 175 if (fin_freq == 0) {
@@ -184,24 +178,19 @@ static int meson_pwm_calc(struct meson_pwm *meson,
184 } 178 }
185 179
186 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); 180 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
187 fin_ps = (u64)NSEC_PER_SEC * 1000;
188 do_div(fin_ps, fin_freq);
189
190 /* Calc pre_div with the period */
191 for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
192 cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
193 fin_ps * (pre_div + 1));
194 dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
195 fin_ps, pre_div, cnt);
196 if (cnt <= 0xffff)
197 break;
198 }
199 181
182 pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
200 if (pre_div > MISC_CLK_DIV_MASK) { 183 if (pre_div > MISC_CLK_DIV_MASK) {
201 dev_err(meson->chip.dev, "unable to get period pre_div\n"); 184 dev_err(meson->chip.dev, "unable to get period pre_div\n");
202 return -EINVAL; 185 return -EINVAL;
203 } 186 }
204 187
188 cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
189 if (cnt > 0xffff) {
190 dev_err(meson->chip.dev, "unable to get period cnt\n");
191 return -EINVAL;
192 }
193
205 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period, 194 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
206 pre_div, cnt); 195 pre_div, cnt);
207 196
@@ -215,8 +204,8 @@ static int meson_pwm_calc(struct meson_pwm *meson,
215 channel->lo = cnt; 204 channel->lo = cnt;
216 } else { 205 } else {
217 /* Then check is we can have the duty with the same pre_div */ 206 /* Then check is we can have the duty with the same pre_div */
218 duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000, 207 duty_cnt = div64_u64(fin_freq * (u64)duty,
219 fin_ps * (pre_div + 1)); 208 NSEC_PER_SEC * (pre_div + 1));
220 if (duty_cnt > 0xffff) { 209 if (duty_cnt > 0xffff) {
221 dev_err(meson->chip.dev, "unable to get duty cycle\n"); 210 dev_err(meson->chip.dev, "unable to get duty cycle\n");
222 return -EINVAL; 211 return -EINVAL;
@@ -233,73 +222,43 @@ static int meson_pwm_calc(struct meson_pwm *meson,
233 return 0; 222 return 0;
234} 223}
235 224
236static void meson_pwm_enable(struct meson_pwm *meson, 225static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
237 struct meson_pwm_channel *channel,
238 unsigned int id)
239{ 226{
240 u32 value, clk_shift, clk_enable, enable; 227 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
241 unsigned int offset; 228 struct meson_pwm_channel_data *channel_data;
242 unsigned long flags; 229 unsigned long flags;
230 u32 value;
243 231
244 switch (id) { 232 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
245 case 0:
246 clk_shift = MISC_A_CLK_DIV_SHIFT;
247 clk_enable = MISC_A_CLK_EN;
248 enable = MISC_A_EN;
249 offset = REG_PWM_A;
250 break;
251
252 case 1:
253 clk_shift = MISC_B_CLK_DIV_SHIFT;
254 clk_enable = MISC_B_CLK_EN;
255 enable = MISC_B_EN;
256 offset = REG_PWM_B;
257 break;
258
259 default:
260 return;
261 }
262 233
263 spin_lock_irqsave(&meson->lock, flags); 234 spin_lock_irqsave(&meson->lock, flags);
264 235
265 value = readl(meson->base + REG_MISC_AB); 236 value = readl(meson->base + REG_MISC_AB);
266 value &= ~(MISC_CLK_DIV_MASK << clk_shift); 237 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
267 value |= channel->pre_div << clk_shift; 238 value |= channel->pre_div << channel_data->clk_div_shift;
268 value |= clk_enable; 239 value |= channel_data->clk_en_mask;
269 writel(value, meson->base + REG_MISC_AB); 240 writel(value, meson->base + REG_MISC_AB);
270 241
271 value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo; 242 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
272 writel(value, meson->base + offset); 243 FIELD_PREP(PWM_LOW_MASK, channel->lo);
244 writel(value, meson->base + channel_data->reg_offset);
273 245
274 value = readl(meson->base + REG_MISC_AB); 246 value = readl(meson->base + REG_MISC_AB);
275 value |= enable; 247 value |= channel_data->pwm_en_mask;
276 writel(value, meson->base + REG_MISC_AB); 248 writel(value, meson->base + REG_MISC_AB);
277 249
278 spin_unlock_irqrestore(&meson->lock, flags); 250 spin_unlock_irqrestore(&meson->lock, flags);
279} 251}
280 252
281static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id) 253static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
282{ 254{
283 u32 value, enable;
284 unsigned long flags; 255 unsigned long flags;
285 256 u32 value;
286 switch (id) {
287 case 0:
288 enable = MISC_A_EN;
289 break;
290
291 case 1:
292 enable = MISC_B_EN;
293 break;
294
295 default:
296 return;
297 }
298 257
299 spin_lock_irqsave(&meson->lock, flags); 258 spin_lock_irqsave(&meson->lock, flags);
300 259
301 value = readl(meson->base + REG_MISC_AB); 260 value = readl(meson->base + REG_MISC_AB);
302 value &= ~enable; 261 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
303 writel(value, meson->base + REG_MISC_AB); 262 writel(value, meson->base + REG_MISC_AB);
304 263
305 spin_unlock_irqrestore(&meson->lock, flags); 264 spin_unlock_irqrestore(&meson->lock, flags);
@@ -316,64 +275,97 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
316 return -EINVAL; 275 return -EINVAL;
317 276
318 if (!state->enabled) { 277 if (!state->enabled) {
319 meson_pwm_disable(meson, pwm->hwpwm); 278 if (state->polarity == PWM_POLARITY_INVERSED) {
320 channel->state.enabled = false; 279 /*
321 280 * This IP block revision doesn't have an "always high"
322 return 0; 281 * setting which we can use for "inverted disabled".
323 } 282 * Instead we achieve this using the same settings
324 283 * that we use a pre_div of 0 (to get the shortest
325 if (state->period != channel->state.period || 284 * possible duration for one "count") and
326 state->duty_cycle != channel->state.duty_cycle || 285 * "period == duty_cycle". This results in a signal
327 state->polarity != channel->state.polarity) { 286 * which is LOW for one "count", while being HIGH for
328 if (state->polarity != channel->state.polarity) { 287 * the rest of the (so the signal is HIGH for slightly
329 if (state->polarity == PWM_POLARITY_NORMAL) 288 * less than 100% of the period, but this is the best
330 meson->inverter_mask |= BIT(pwm->hwpwm); 289 * we can achieve).
331 else 290 */
332 meson->inverter_mask &= ~BIT(pwm->hwpwm); 291 channel->pre_div = 0;
292 channel->hi = ~0;
293 channel->lo = 0;
294
295 meson_pwm_enable(meson, pwm);
296 } else {
297 meson_pwm_disable(meson, pwm);
333 } 298 }
334 299 } else {
335 err = meson_pwm_calc(meson, channel, pwm->hwpwm, 300 err = meson_pwm_calc(meson, pwm, state);
336 state->duty_cycle, state->period);
337 if (err < 0) 301 if (err < 0)
338 return err; 302 return err;
339 303
340 channel->state.polarity = state->polarity; 304 meson_pwm_enable(meson, pwm);
341 channel->state.period = state->period;
342 channel->state.duty_cycle = state->duty_cycle;
343 }
344
345 if (state->enabled && !channel->state.enabled) {
346 meson_pwm_enable(meson, channel, pwm->hwpwm);
347 channel->state.enabled = true;
348 } 305 }
349 306
350 return 0; 307 return 0;
351} 308}
352 309
310static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
311 struct pwm_device *pwm, u32 cnt)
312{
313 struct meson_pwm *meson = to_meson_pwm(chip);
314 struct meson_pwm_channel *channel;
315 unsigned long fin_freq;
316 u32 fin_ns;
317
318 /* to_meson_pwm() can only be used after .get_state() is called */
319 channel = &meson->channels[pwm->hwpwm];
320
321 fin_freq = clk_get_rate(channel->clk);
322 if (fin_freq == 0)
323 return 0;
324
325 fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
326
327 return cnt * fin_ns * (channel->pre_div + 1);
328}
329
353static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 330static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
354 struct pwm_state *state) 331 struct pwm_state *state)
355{ 332{
356 struct meson_pwm *meson = to_meson_pwm(chip); 333 struct meson_pwm *meson = to_meson_pwm(chip);
357 u32 value, mask; 334 struct meson_pwm_channel_data *channel_data;
335 struct meson_pwm_channel *channel;
336 u32 value, tmp;
358 337
359 if (!state) 338 if (!state)
360 return; 339 return;
361 340
362 switch (pwm->hwpwm) { 341 channel = &meson->channels[pwm->hwpwm];
363 case 0: 342 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
364 mask = MISC_A_EN;
365 break;
366 343
367 case 1: 344 value = readl(meson->base + REG_MISC_AB);
368 mask = MISC_B_EN;
369 break;
370 345
371 default: 346 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
372 return; 347 state->enabled = (value & tmp) == tmp;
373 }
374 348
375 value = readl(meson->base + REG_MISC_AB); 349 tmp = value >> channel_data->clk_div_shift;
376 state->enabled = (value & mask) != 0; 350 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
351
352 value = readl(meson->base + channel_data->reg_offset);
353
354 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
355 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
356
357 if (channel->lo == 0) {
358 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
359 state->duty_cycle = state->period;
360 } else if (channel->lo >= channel->hi) {
361 state->period = meson_pwm_cnt_to_ns(chip, pwm,
362 channel->lo + channel->hi);
363 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
364 channel->hi);
365 } else {
366 state->period = 0;
367 state->duty_cycle = 0;
368 }
377} 369}
378 370
379static const struct pwm_ops meson_pwm_ops = { 371static const struct pwm_ops meson_pwm_ops = {
@@ -433,8 +425,17 @@ static const struct meson_pwm_data pwm_axg_ao_data = {
433 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), 425 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
434}; 426};
435 427
428static const char * const pwm_g12a_ao_ab_parent_names[] = {
429 "xtal", "aoclk81", "fclk_div4", "fclk_div5"
430};
431
432static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
433 .parent_names = pwm_g12a_ao_ab_parent_names,
434 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
435};
436
436static const char * const pwm_g12a_ao_cd_parent_names[] = { 437static const char * const pwm_g12a_ao_cd_parent_names[] = {
437 "aoclk81", "xtal", 438 "xtal", "aoclk81",
438}; 439};
439 440
440static const struct meson_pwm_data pwm_g12a_ao_cd_data = { 441static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
@@ -478,7 +479,7 @@ static const struct of_device_id meson_pwm_matches[] = {
478 }, 479 },
479 { 480 {
480 .compatible = "amlogic,meson-g12a-ao-pwm-ab", 481 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
481 .data = &pwm_axg_ao_data 482 .data = &pwm_g12a_ao_ab_data
482 }, 483 },
483 { 484 {
484 .compatible = "amlogic,meson-g12a-ao-pwm-cd", 485 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
@@ -488,8 +489,7 @@ static const struct of_device_id meson_pwm_matches[] = {
488}; 489};
489MODULE_DEVICE_TABLE(of, meson_pwm_matches); 490MODULE_DEVICE_TABLE(of, meson_pwm_matches);
490 491
491static int meson_pwm_init_channels(struct meson_pwm *meson, 492static int meson_pwm_init_channels(struct meson_pwm *meson)
492 struct meson_pwm_channel *channels)
493{ 493{
494 struct device *dev = meson->chip.dev; 494 struct device *dev = meson->chip.dev;
495 struct clk_init_data init; 495 struct clk_init_data init;
@@ -498,7 +498,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
498 int err; 498 int err;
499 499
500 for (i = 0; i < meson->chip.npwm; i++) { 500 for (i = 0; i < meson->chip.npwm; i++) {
501 struct meson_pwm_channel *channel = &channels[i]; 501 struct meson_pwm_channel *channel = &meson->channels[i];
502 502
503 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); 503 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
504 504
@@ -509,8 +509,9 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
509 init.num_parents = meson->data->num_parents; 509 init.num_parents = meson->data->num_parents;
510 510
511 channel->mux.reg = meson->base + REG_MISC_AB; 511 channel->mux.reg = meson->base + REG_MISC_AB;
512 channel->mux.shift = mux_reg_shifts[i]; 512 channel->mux.shift =
513 channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1; 513 meson_pwm_per_channel_data[i].clk_sel_shift;
514 channel->mux.mask = MISC_CLK_SEL_MASK;
514 channel->mux.flags = 0; 515 channel->mux.flags = 0;
515 channel->mux.lock = &meson->lock; 516 channel->mux.lock = &meson->lock;
516 channel->mux.table = NULL; 517 channel->mux.table = NULL;
@@ -525,31 +526,16 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
525 526
526 snprintf(name, sizeof(name), "clkin%u", i); 527 snprintf(name, sizeof(name), "clkin%u", i);
527 528
528 channel->clk_parent = devm_clk_get(dev, name); 529 channel->clk_parent = devm_clk_get_optional(dev, name);
529 if (IS_ERR(channel->clk_parent)) { 530 if (IS_ERR(channel->clk_parent))
530 err = PTR_ERR(channel->clk_parent); 531 return PTR_ERR(channel->clk_parent);
531 if (err == -EPROBE_DEFER)
532 return err;
533
534 channel->clk_parent = NULL;
535 }
536 } 532 }
537 533
538 return 0; 534 return 0;
539} 535}
540 536
541static void meson_pwm_add_channels(struct meson_pwm *meson,
542 struct meson_pwm_channel *channels)
543{
544 unsigned int i;
545
546 for (i = 0; i < meson->chip.npwm; i++)
547 pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
548}
549
550static int meson_pwm_probe(struct platform_device *pdev) 537static int meson_pwm_probe(struct platform_device *pdev)
551{ 538{
552 struct meson_pwm_channel *channels;
553 struct meson_pwm *meson; 539 struct meson_pwm *meson;
554 struct resource *regs; 540 struct resource *regs;
555 int err; 541 int err;
@@ -567,19 +553,13 @@ static int meson_pwm_probe(struct platform_device *pdev)
567 meson->chip.dev = &pdev->dev; 553 meson->chip.dev = &pdev->dev;
568 meson->chip.ops = &meson_pwm_ops; 554 meson->chip.ops = &meson_pwm_ops;
569 meson->chip.base = -1; 555 meson->chip.base = -1;
570 meson->chip.npwm = 2; 556 meson->chip.npwm = MESON_NUM_PWMS;
571 meson->chip.of_xlate = of_pwm_xlate_with_flags; 557 meson->chip.of_xlate = of_pwm_xlate_with_flags;
572 meson->chip.of_pwm_n_cells = 3; 558 meson->chip.of_pwm_n_cells = 3;
573 559
574 meson->data = of_device_get_match_data(&pdev->dev); 560 meson->data = of_device_get_match_data(&pdev->dev);
575 meson->inverter_mask = BIT(meson->chip.npwm) - 1;
576 561
577 channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, 562 err = meson_pwm_init_channels(meson);
578 sizeof(*channels), GFP_KERNEL);
579 if (!channels)
580 return -ENOMEM;
581
582 err = meson_pwm_init_channels(meson, channels);
583 if (err < 0) 563 if (err < 0)
584 return err; 564 return err;
585 565
@@ -589,8 +569,6 @@ static int meson_pwm_probe(struct platform_device *pdev)
589 return err; 569 return err;
590 } 570 }
591 571
592 meson_pwm_add_channels(meson, channels);
593
594 platform_set_drvdata(pdev, meson); 572 platform_set_drvdata(pdev, meson);
595 573
596 return 0; 574 return 0;
diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index cfe7dd1b448e..5b2b8ecc354c 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -254,50 +254,11 @@ static const struct of_device_id rcar_pwm_of_table[] = {
254}; 254};
255MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); 255MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
256 256
257#ifdef CONFIG_PM_SLEEP
258static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev)
259{
260 struct rcar_pwm_chip *rcar_pwm = dev_get_drvdata(dev);
261 struct pwm_chip *chip = &rcar_pwm->chip;
262
263 return &chip->pwms[0];
264}
265
266static int rcar_pwm_suspend(struct device *dev)
267{
268 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
269
270 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
271 return 0;
272
273 pm_runtime_put(dev);
274
275 return 0;
276}
277
278static int rcar_pwm_resume(struct device *dev)
279{
280 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
281 struct pwm_state state;
282
283 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
284 return 0;
285
286 pm_runtime_get_sync(dev);
287
288 pwm_get_state(pwm, &state);
289
290 return rcar_pwm_apply(pwm->chip, pwm, &state);
291}
292#endif /* CONFIG_PM_SLEEP */
293static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume);
294
295static struct platform_driver rcar_pwm_driver = { 257static struct platform_driver rcar_pwm_driver = {
296 .probe = rcar_pwm_probe, 258 .probe = rcar_pwm_probe,
297 .remove = rcar_pwm_remove, 259 .remove = rcar_pwm_remove,
298 .driver = { 260 .driver = {
299 .name = "pwm-rcar", 261 .name = "pwm-rcar",
300 .pm = &rcar_pwm_pm_ops,
301 .of_match_table = of_match_ptr(rcar_pwm_of_table), 262 .of_match_table = of_match_ptr(rcar_pwm_of_table),
302 } 263 }
303}; 264};
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
new file mode 100644
index 000000000000..a7c107f19e66
--- /dev/null
+++ b/drivers/pwm/pwm-sifive.c
@@ -0,0 +1,339 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20#include <linux/bitfield.h>
21
22/* Register offsets */
23#define PWM_SIFIVE_PWMCFG 0x0
24#define PWM_SIFIVE_PWMCOUNT 0x8
25#define PWM_SIFIVE_PWMS 0x10
26#define PWM_SIFIVE_PWMCMP0 0x20
27
28/* PWMCFG fields */
29#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
30#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
31#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
32#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
33#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
34#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
35#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
36#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
37#define PWM_SIFIVE_PWMCFG_IP BIT(28)
38
39/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */
40#define PWM_SIFIVE_SIZE_PWMCMP 4
41#define PWM_SIFIVE_CMPWIDTH 16
42#define PWM_SIFIVE_DEFAULT_PERIOD 10000000
43
44struct pwm_sifive_ddata {
45 struct pwm_chip chip;
46 struct mutex lock; /* lock to protect user_count */
47 struct notifier_block notifier;
48 struct clk *clk;
49 void __iomem *regs;
50 unsigned int real_period;
51 unsigned int approx_period;
52 int user_count;
53};
54
55static inline
56struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
57{
58 return container_of(c, struct pwm_sifive_ddata, chip);
59}
60
61static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
62{
63 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
64
65 mutex_lock(&ddata->lock);
66 ddata->user_count++;
67 mutex_unlock(&ddata->lock);
68
69 return 0;
70}
71
72static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
73{
74 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
75
76 mutex_lock(&ddata->lock);
77 ddata->user_count--;
78 mutex_unlock(&ddata->lock);
79}
80
81static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
82 unsigned long rate)
83{
84 unsigned long long num;
85 unsigned long scale_pow;
86 int scale;
87 u32 val;
88 /*
89 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
90 * period length is using pwmscale which provides the number of bits the
91 * counter is shifted before being feed to the comparators. A period
92 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
93 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
94 */
95 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
96 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
97
98 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
99 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
100 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
101
102 /* As scale <= 15 the shift operation cannot overflow. */
103 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
104 ddata->real_period = div64_ul(num, rate);
105 dev_dbg(ddata->chip.dev,
106 "New real_period = %u ns\n", ddata->real_period);
107}
108
109static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
110 struct pwm_state *state)
111{
112 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
113 u32 duty, val;
114
115 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP0 +
116 pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
117
118 state->enabled = duty > 0;
119
120 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
121 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
122 state->enabled = false;
123
124 state->period = ddata->real_period;
125 state->duty_cycle =
126 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
127 state->polarity = PWM_POLARITY_INVERSED;
128}
129
130static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
131{
132 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
133 int ret;
134
135 if (enable) {
136 ret = clk_enable(ddata->clk);
137 if (ret) {
138 dev_err(ddata->chip.dev, "Enable clk failed\n");
139 return ret;
140 }
141 }
142
143 if (!enable)
144 clk_disable(ddata->clk);
145
146 return 0;
147}
148
149static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
150 struct pwm_state *state)
151{
152 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
153 struct pwm_state cur_state;
154 unsigned int duty_cycle;
155 unsigned long long num;
156 bool enabled;
157 int ret = 0;
158 u32 frac;
159
160 if (state->polarity != PWM_POLARITY_INVERSED)
161 return -EINVAL;
162
163 ret = clk_enable(ddata->clk);
164 if (ret) {
165 dev_err(ddata->chip.dev, "Enable clk failed\n");
166 return ret;
167 }
168
169 mutex_lock(&ddata->lock);
170 cur_state = pwm->state;
171 enabled = cur_state.enabled;
172
173 duty_cycle = state->duty_cycle;
174 if (!state->enabled)
175 duty_cycle = 0;
176
177 /*
178 * The problem of output producing mixed setting as mentioned at top,
179 * occurs here. To minimize the window for this problem, we are
180 * calculating the register values first and then writing them
181 * consecutively
182 */
183 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
184 frac = DIV_ROUND_CLOSEST_ULL(num, state->period);
185 /* The hardware cannot generate a 100% duty cycle */
186 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
187
188 if (state->period != ddata->approx_period) {
189 if (ddata->user_count != 1) {
190 ret = -EBUSY;
191 goto exit;
192 }
193 ddata->approx_period = state->period;
194 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
195 }
196
197 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP0 +
198 pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP);
199
200 if (state->enabled != enabled)
201 pwm_sifive_enable(chip, state->enabled);
202
203exit:
204 clk_disable(ddata->clk);
205 mutex_unlock(&ddata->lock);
206 return ret;
207}
208
209static const struct pwm_ops pwm_sifive_ops = {
210 .request = pwm_sifive_request,
211 .free = pwm_sifive_free,
212 .get_state = pwm_sifive_get_state,
213 .apply = pwm_sifive_apply,
214 .owner = THIS_MODULE,
215};
216
217static int pwm_sifive_clock_notifier(struct notifier_block *nb,
218 unsigned long event, void *data)
219{
220 struct clk_notifier_data *ndata = data;
221 struct pwm_sifive_ddata *ddata =
222 container_of(nb, struct pwm_sifive_ddata, notifier);
223
224 if (event == POST_RATE_CHANGE)
225 pwm_sifive_update_clock(ddata, ndata->new_rate);
226
227 return NOTIFY_OK;
228}
229
230static int pwm_sifive_probe(struct platform_device *pdev)
231{
232 struct device *dev = &pdev->dev;
233 struct pwm_sifive_ddata *ddata;
234 struct pwm_chip *chip;
235 struct resource *res;
236 int ret;
237
238 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
239 if (!ddata)
240 return -ENOMEM;
241
242 mutex_init(&ddata->lock);
243 chip = &ddata->chip;
244 chip->dev = dev;
245 chip->ops = &pwm_sifive_ops;
246 chip->of_xlate = of_pwm_xlate_with_flags;
247 chip->of_pwm_n_cells = 3;
248 chip->base = -1;
249 chip->npwm = 4;
250
251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252 ddata->regs = devm_ioremap_resource(dev, res);
253 if (IS_ERR(ddata->regs)) {
254 dev_err(dev, "Unable to map IO resources\n");
255 return PTR_ERR(ddata->regs);
256 }
257
258 ddata->clk = devm_clk_get(dev, NULL);
259 if (IS_ERR(ddata->clk)) {
260 if (PTR_ERR(ddata->clk) != -EPROBE_DEFER)
261 dev_err(dev, "Unable to find controller clock\n");
262 return PTR_ERR(ddata->clk);
263 }
264
265 ret = clk_prepare_enable(ddata->clk);
266 if (ret) {
267 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
268 return ret;
269 }
270
271 /* Watch for changes to underlying clock frequency */
272 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
273 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
274 if (ret) {
275 dev_err(dev, "failed to register clock notifier: %d\n", ret);
276 goto disable_clk;
277 }
278
279 ret = pwmchip_add(chip);
280 if (ret < 0) {
281 dev_err(dev, "cannot register PWM: %d\n", ret);
282 goto unregister_clk;
283 }
284
285 platform_set_drvdata(pdev, ddata);
286 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
287
288 return 0;
289
290unregister_clk:
291 clk_notifier_unregister(ddata->clk, &ddata->notifier);
292disable_clk:
293 clk_disable_unprepare(ddata->clk);
294
295 return ret;
296}
297
298static int pwm_sifive_remove(struct platform_device *dev)
299{
300 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
301 bool is_enabled = false;
302 struct pwm_device *pwm;
303 int ret, ch;
304
305 for (ch = 0; ch < ddata->chip.npwm; ch++) {
306 pwm = &ddata->chip.pwms[ch];
307 if (pwm->state.enabled) {
308 is_enabled = true;
309 break;
310 }
311 }
312 if (is_enabled)
313 clk_disable(ddata->clk);
314
315 clk_disable_unprepare(ddata->clk);
316 ret = pwmchip_remove(&ddata->chip);
317 clk_notifier_unregister(ddata->clk, &ddata->notifier);
318
319 return ret;
320}
321
322static const struct of_device_id pwm_sifive_of_match[] = {
323 { .compatible = "sifive,pwm0" },
324 {},
325};
326MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
327
328static struct platform_driver pwm_sifive_driver = {
329 .probe = pwm_sifive_probe,
330 .remove = pwm_sifive_remove,
331 .driver = {
332 .name = "pwm-sifive",
333 .of_match_table = pwm_sifive_of_match,
334 },
335};
336module_platform_driver(pwm_sifive_driver);
337
338MODULE_DESCRIPTION("SiFive PWM driver");
339MODULE_LICENSE("GPL v2");
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c
index 0059b24cfdc3..2211a642066d 100644
--- a/drivers/pwm/pwm-stm32-lp.c
+++ b/drivers/pwm/pwm-stm32-lp.c
@@ -13,6 +13,7 @@
13#include <linux/mfd/stm32-lptimer.h> 13#include <linux/mfd/stm32-lptimer.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/pwm.h> 18#include <linux/pwm.h>
18 19
@@ -223,6 +224,29 @@ static int stm32_pwm_lp_remove(struct platform_device *pdev)
223 return pwmchip_remove(&priv->chip); 224 return pwmchip_remove(&priv->chip);
224} 225}
225 226
227static int __maybe_unused stm32_pwm_lp_suspend(struct device *dev)
228{
229 struct stm32_pwm_lp *priv = dev_get_drvdata(dev);
230 struct pwm_state state;
231
232 pwm_get_state(&priv->chip.pwms[0], &state);
233 if (state.enabled) {
234 dev_err(dev, "The consumer didn't stop us (%s)\n",
235 priv->chip.pwms[0].label);
236 return -EBUSY;
237 }
238
239 return pinctrl_pm_select_sleep_state(dev);
240}
241
242static int __maybe_unused stm32_pwm_lp_resume(struct device *dev)
243{
244 return pinctrl_pm_select_default_state(dev);
245}
246
247static SIMPLE_DEV_PM_OPS(stm32_pwm_lp_pm_ops, stm32_pwm_lp_suspend,
248 stm32_pwm_lp_resume);
249
226static const struct of_device_id stm32_pwm_lp_of_match[] = { 250static const struct of_device_id stm32_pwm_lp_of_match[] = {
227 { .compatible = "st,stm32-pwm-lp", }, 251 { .compatible = "st,stm32-pwm-lp", },
228 {}, 252 {},
@@ -235,6 +259,7 @@ static struct platform_driver stm32_pwm_lp_driver = {
235 .driver = { 259 .driver = {
236 .name = "stm32-pwm-lp", 260 .name = "stm32-pwm-lp",
237 .of_match_table = of_match_ptr(stm32_pwm_lp_of_match), 261 .of_match_table = of_match_ptr(stm32_pwm_lp_of_match),
262 .pm = &stm32_pwm_lp_pm_ops,
238 }, 263 },
239}; 264};
240module_platform_driver(stm32_pwm_lp_driver); 265module_platform_driver(stm32_pwm_lp_driver);
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
index 4f842550fbd1..740e2dec8313 100644
--- a/drivers/pwm/pwm-stm32.c
+++ b/drivers/pwm/pwm-stm32.c
@@ -608,6 +608,8 @@ static int stm32_pwm_probe(struct platform_device *pdev)
608 priv->regmap = ddata->regmap; 608 priv->regmap = ddata->regmap;
609 priv->clk = ddata->clk; 609 priv->clk = ddata->clk;
610 priv->max_arr = ddata->max_arr; 610 priv->max_arr = ddata->max_arr;
611 priv->chip.of_xlate = of_pwm_xlate_with_flags;
612 priv->chip.of_pwm_n_cells = 3;
611 613
612 if (!priv->regmap || !priv->clk) 614 if (!priv->regmap || !priv->clk)
613 return -EINVAL; 615 return -EINVAL;
diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c
index bf6823fe0812..2389b8669846 100644
--- a/drivers/pwm/sysfs.c
+++ b/drivers/pwm/sysfs.c
@@ -18,6 +18,7 @@ struct pwm_export {
18 struct device child; 18 struct device child;
19 struct pwm_device *pwm; 19 struct pwm_device *pwm;
20 struct mutex lock; 20 struct mutex lock;
21 struct pwm_state suspend;
21}; 22};
22 23
23static struct pwm_export *child_to_pwm_export(struct device *child) 24static struct pwm_export *child_to_pwm_export(struct device *child)
@@ -372,10 +373,111 @@ static struct attribute *pwm_chip_attrs[] = {
372}; 373};
373ATTRIBUTE_GROUPS(pwm_chip); 374ATTRIBUTE_GROUPS(pwm_chip);
374 375
376/* takes export->lock on success */
377static struct pwm_export *pwm_class_get_state(struct device *parent,
378 struct pwm_device *pwm,
379 struct pwm_state *state)
380{
381 struct device *child;
382 struct pwm_export *export;
383
384 if (!test_bit(PWMF_EXPORTED, &pwm->flags))
385 return NULL;
386
387 child = device_find_child(parent, pwm, pwm_unexport_match);
388 if (!child)
389 return NULL;
390
391 export = child_to_pwm_export(child);
392 put_device(child); /* for device_find_child() */
393
394 mutex_lock(&export->lock);
395 pwm_get_state(pwm, state);
396
397 return export;
398}
399
400static int pwm_class_apply_state(struct pwm_export *export,
401 struct pwm_device *pwm,
402 struct pwm_state *state)
403{
404 int ret = pwm_apply_state(pwm, state);
405
406 /* release lock taken in pwm_class_get_state */
407 mutex_unlock(&export->lock);
408
409 return ret;
410}
411
412static int pwm_class_resume_npwm(struct device *parent, unsigned int npwm)
413{
414 struct pwm_chip *chip = dev_get_drvdata(parent);
415 unsigned int i;
416 int ret = 0;
417
418 for (i = 0; i < npwm; i++) {
419 struct pwm_device *pwm = &chip->pwms[i];
420 struct pwm_state state;
421 struct pwm_export *export;
422
423 export = pwm_class_get_state(parent, pwm, &state);
424 if (!export)
425 continue;
426
427 state.enabled = export->suspend.enabled;
428 ret = pwm_class_apply_state(export, pwm, &state);
429 if (ret < 0)
430 break;
431 }
432
433 return ret;
434}
435
436static int __maybe_unused pwm_class_suspend(struct device *parent)
437{
438 struct pwm_chip *chip = dev_get_drvdata(parent);
439 unsigned int i;
440 int ret = 0;
441
442 for (i = 0; i < chip->npwm; i++) {
443 struct pwm_device *pwm = &chip->pwms[i];
444 struct pwm_state state;
445 struct pwm_export *export;
446
447 export = pwm_class_get_state(parent, pwm, &state);
448 if (!export)
449 continue;
450
451 export->suspend = state;
452 state.enabled = false;
453 ret = pwm_class_apply_state(export, pwm, &state);
454 if (ret < 0) {
455 /*
456 * roll back the PWM devices that were disabled by
457 * this suspend function.
458 */
459 pwm_class_resume_npwm(parent, i);
460 break;
461 }
462 }
463
464 return ret;
465}
466
467static int __maybe_unused pwm_class_resume(struct device *parent)
468{
469 struct pwm_chip *chip = dev_get_drvdata(parent);
470
471 return pwm_class_resume_npwm(parent, chip->npwm);
472}
473
474static SIMPLE_DEV_PM_OPS(pwm_class_pm_ops, pwm_class_suspend, pwm_class_resume);
475
375static struct class pwm_class = { 476static struct class pwm_class = {
376 .name = "pwm", 477 .name = "pwm",
377 .owner = THIS_MODULE, 478 .owner = THIS_MODULE,
378 .dev_groups = pwm_chip_groups, 479 .dev_groups = pwm_chip_groups,
480 .pm = &pwm_class_pm_ops,
379}; 481};
380 482
381static int pwmchip_sysfs_match(struct device *parent, const void *data) 483static int pwmchip_sysfs_match(struct device *parent, const void *data)
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index eaa5c6e3fc9f..24632a7a7d11 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -405,12 +405,16 @@ struct pwm_device *of_pwm_xlate_with_flags(struct pwm_chip *pc,
405 const struct of_phandle_args *args); 405 const struct of_phandle_args *args);
406 406
407struct pwm_device *pwm_get(struct device *dev, const char *con_id); 407struct pwm_device *pwm_get(struct device *dev, const char *con_id);
408struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id); 408struct pwm_device *of_pwm_get(struct device *dev, struct device_node *np,
409 const char *con_id);
409void pwm_put(struct pwm_device *pwm); 410void pwm_put(struct pwm_device *pwm);
410 411
411struct pwm_device *devm_pwm_get(struct device *dev, const char *con_id); 412struct pwm_device *devm_pwm_get(struct device *dev, const char *con_id);
412struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np, 413struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np,
413 const char *con_id); 414 const char *con_id);
415struct pwm_device *devm_fwnode_pwm_get(struct device *dev,
416 struct fwnode_handle *fwnode,
417 const char *con_id);
414void devm_pwm_put(struct device *dev, struct pwm_device *pwm); 418void devm_pwm_put(struct device *dev, struct pwm_device *pwm);
415#else 419#else
416static inline struct pwm_device *pwm_request(int pwm_id, const char *label) 420static inline struct pwm_device *pwm_request(int pwm_id, const char *label)
@@ -493,7 +497,8 @@ static inline struct pwm_device *pwm_get(struct device *dev,
493 return ERR_PTR(-ENODEV); 497 return ERR_PTR(-ENODEV);
494} 498}
495 499
496static inline struct pwm_device *of_pwm_get(struct device_node *np, 500static inline struct pwm_device *of_pwm_get(struct device *dev,
501 struct device_node *np,
497 const char *con_id) 502 const char *con_id)
498{ 503{
499 return ERR_PTR(-ENODEV); 504 return ERR_PTR(-ENODEV);
@@ -516,6 +521,13 @@ static inline struct pwm_device *devm_of_pwm_get(struct device *dev,
516 return ERR_PTR(-ENODEV); 521 return ERR_PTR(-ENODEV);
517} 522}
518 523
524static inline struct pwm_device *
525devm_fwnode_pwm_get(struct device *dev, struct fwnode_handle *fwnode,
526 const char *con_id)
527{
528 return ERR_PTR(-ENODEV);
529}
530
519static inline void devm_pwm_put(struct device *dev, struct pwm_device *pwm) 531static inline void devm_pwm_put(struct device *dev, struct pwm_device *pwm)
520{ 532{
521} 533}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-29 11:09:40 -0400