x86/intel: Aggregate big core graphics naming

Currently big core clients with extra graphics on have:

 - _G
 - _GT3E

Make it uniformly: _G

for i in `git grep -l "\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*_GT3E"`
do
	sed -i -e 's/\(\(INTEL_FAM6_\|VULNWL_INTEL\|INTEL_CPU_FAM6\).*\)_GT3E/\1_G/g' ${i}
done

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Cc: x86@kernel.org
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Borislav Petkov <bp@alien8.de>
Link: https://lkml.kernel.org/r/20190827195122.622802314@infradead.org

14 files changed, 38 insertions, 38 deletions

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 22ef9ccaf45c..472b45c3eeb1 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3966,11 +3966,11 @@ static __init void intel_clovertown_quirk(void)
 static const struct x86_cpu_desc isolation_ucodes[] = {
         INTEL_CPU_DESC(INTEL_FAM6_HASWELL,               3, 0x0000001f),
         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,             1, 0x0000001e),
-        INTEL_CPU_DESC(INTEL_FAM6_HASWELL_GT3E,          1, 0x00000015),
+        INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,             1, 0x00000015),
         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             2, 0x00000037),
         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             4, 0x0000000a),
         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,             4, 0x00000023),
-        INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_GT3E,        1, 0x00000014),
+        INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,           1, 0x00000014),
         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,      2, 0x00000010),
         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,      3, 0x07000009),
         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_XEON_D,      4, 0x0f000009),
@@ -4860,7 +4860,7 @@ __init int intel_pmu_init(void)
         case INTEL_FAM6_HASWELL:
         case INTEL_FAM6_HASWELL_X:
         case INTEL_FAM6_HASWELL_L:
-        case INTEL_FAM6_HASWELL_GT3E:
+        case INTEL_FAM6_HASWELL_G:
                 x86_add_quirk(intel_ht_bug);
                 x86_add_quirk(intel_pebs_isolation_quirk);
                 x86_pmu.late_ack = true;
@@ -4892,7 +4892,7 @@ __init int intel_pmu_init(void)
 
         case INTEL_FAM6_BROADWELL:
         case INTEL_FAM6_BROADWELL_XEON_D:
-        case INTEL_FAM6_BROADWELL_GT3E:
+        case INTEL_FAM6_BROADWELL_G:
         case INTEL_FAM6_BROADWELL_X:
                 x86_add_quirk(intel_pebs_isolation_quirk);
                 x86_pmu.late_ack = true;
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 9b014e813626..03d7a4042bc5 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -593,9 +593,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE,   snb_cstates),
         X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
 
-        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL,      snb_cstates),
-        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X,    snb_cstates),
-        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),
+        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL,   snb_cstates),
+        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates),
+        X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_G, snb_cstates),
 
         X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_L, hswult_cstates),
 
@@ -605,7 +605,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
 
         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL,        snb_cstates),
         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
-        X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E,   snb_cstates),
+        X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_G,      snb_cstates),
         X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X,      snb_cstates),
 
         X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_L, snb_cstates),
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 8cb9626e6277..d0195d151938 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -206,7 +206,7 @@ static int __init pt_pmu_hw_init(void)
         switch (boot_cpu_data.x86_model) {
         case INTEL_FAM6_BROADWELL:
         case INTEL_FAM6_BROADWELL_XEON_D:
-        case INTEL_FAM6_BROADWELL_GT3E:
+        case INTEL_FAM6_BROADWELL_G:
         case INTEL_FAM6_BROADWELL_X:
                 /* not setting BRANCH_EN will #GP, erratum BDM106 */
                 pt_pmu.branch_en_always_on = true;
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index 70dcfe9312b0..82e2c0ea99e4 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -723,9 +723,9 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = {
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL,                model_hsw),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_X,              model_hsx),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_L,              model_hsw),
-        X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E,           model_hsw),
+        X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_G,              model_hsw),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL,              model_hsw),
-        X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E,         model_hsw),
+        X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_G,            model_hsw),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X,            model_hsx),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D,       model_hsx),
         X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL,           model_knl),
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 8428e28c9625..5a2f237707b8 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1453,9 +1453,9 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE,      ivb_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL,        hsw_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_L,      hsw_uncore_init),
-        X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E,   hsw_uncore_init),
+        X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_G,      hsw_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL,      bdw_uncore_init),
-        X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, bdw_uncore_init),
+        X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_G,    bdw_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X,  snbep_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EX,     nhmex_uncore_init),
         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EX,    nhmex_uncore_init),
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 12265c14e60d..e11fbdb3a035 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -62,11 +62,11 @@ static bool test_intel(int idx, void *data)
         case INTEL_FAM6_HASWELL:
         case INTEL_FAM6_HASWELL_X:
         case INTEL_FAM6_HASWELL_L:
-        case INTEL_FAM6_HASWELL_GT3E:
+        case INTEL_FAM6_HASWELL_G:
 
         case INTEL_FAM6_BROADWELL:
         case INTEL_FAM6_BROADWELL_XEON_D:
-        case INTEL_FAM6_BROADWELL_GT3E:
+        case INTEL_FAM6_BROADWELL_G:
         case INTEL_FAM6_BROADWELL_X:
 
         case INTEL_FAM6_ATOM_SILVERMONT:
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 25b71d4e9224..0bc7f397b4a6 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -52,10 +52,10 @@
 #define INTEL_FAM6_HASWELL              0x3C
 #define INTEL_FAM6_HASWELL_X            0x3F
 #define INTEL_FAM6_HASWELL_L            0x45
-#define INTEL_FAM6_HASWELL_GT3E         0x46
+#define INTEL_FAM6_HASWELL_G            0x46
 
 #define INTEL_FAM6_BROADWELL            0x3D
-#define INTEL_FAM6_BROADWELL_GT3E       0x47
+#define INTEL_FAM6_BROADWELL_G          0x47
 #define INTEL_FAM6_BROADWELL_X          0x4F
 #define INTEL_FAM6_BROADWELL_XEON_D     0x56
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index adf001d30b47..c297e6d6b915 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -595,10 +595,10 @@ static const struct x86_cpu_id deadline_match[] = {
 
         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL,          0x22),
         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L,        0x20),
-        DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E,     0x17),
+        DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G,        0x17),
 
         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL,        0x25),
-        DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E,   0x17),
+        DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G,      0x17),
 
         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L,        0xb2),
         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE,          0xb2),
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index f435780fe45e..0b569f10d4a0 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1186,9 +1186,9 @@ static void override_cache_bits(struct cpuinfo_x86 *c)
         case INTEL_FAM6_IVYBRIDGE:
         case INTEL_FAM6_HASWELL:
         case INTEL_FAM6_HASWELL_L:
-        case INTEL_FAM6_HASWELL_GT3E:
+        case INTEL_FAM6_HASWELL_G:
         case INTEL_FAM6_BROADWELL:
-        case INTEL_FAM6_BROADWELL_GT3E:
+        case INTEL_FAM6_BROADWELL_G:
         case INTEL_FAM6_SKYLAKE_L:
         case INTEL_FAM6_SKYLAKE:
         case INTEL_FAM6_KABYLAKE_L:
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index bafa2735f541..1d2c64bcf6ab 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -150,12 +150,12 @@ static const struct sku_microcode spectre_bad_microcodes[] = {
         { INTEL_FAM6_SKYLAKE_X,         0x03,   0x0100013e },
         { INTEL_FAM6_SKYLAKE_X,         0x04,   0x0200003c },
         { INTEL_FAM6_BROADWELL,         0x04,   0x28 },
-        { INTEL_FAM6_BROADWELL_GT3E,    0x01,   0x1b },
+        { INTEL_FAM6_BROADWELL_G,       0x01,   0x1b },
         { INTEL_FAM6_BROADWELL_XEON_D,  0x02,   0x14 },
         { INTEL_FAM6_BROADWELL_XEON_D,  0x03,   0x07000011 },
         { INTEL_FAM6_BROADWELL_X,       0x01,   0x0b000025 },
         { INTEL_FAM6_HASWELL_L,         0x01,   0x21 },
-        { INTEL_FAM6_HASWELL_GT3E,      0x01,   0x18 },
+        { INTEL_FAM6_HASWELL_G,         0x01,   0x18 },
         { INTEL_FAM6_HASWELL,           0x03,   0x23 },
         { INTEL_FAM6_HASWELL_X,         0x02,   0x3b },
         { INTEL_FAM6_HASWELL_X,         0x04,   0x10 },
diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
index 6e393aabdc13..99b9c01f8c1a 100644
--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -1876,8 +1876,8 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
         ICPU(INTEL_FAM6_HASWELL_L,              core_funcs),
-        ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
-        ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
+        ICPU(INTEL_FAM6_HASWELL_G,              core_funcs),
+        ICPU(INTEL_FAM6_BROADWELL_G,            core_funcs),
         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
         ICPU(INTEL_FAM6_SKYLAKE_L,              core_funcs),
         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index d0e4f16b8f06..c4081324a02b 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -1075,10 +1075,10 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
         INTEL_CPU_FAM6(HASWELL,                 idle_cpu_hsw),
         INTEL_CPU_FAM6(HASWELL_X,               idle_cpu_hsw),
         INTEL_CPU_FAM6(HASWELL_L,               idle_cpu_hsw),
-        INTEL_CPU_FAM6(HASWELL_GT3E,            idle_cpu_hsw),
+        INTEL_CPU_FAM6(HASWELL_G,               idle_cpu_hsw),
         INTEL_CPU_FAM6(ATOM_SILVERMONT_X,       idle_cpu_avn),
         INTEL_CPU_FAM6(BROADWELL,               idle_cpu_bdw),
-        INTEL_CPU_FAM6(BROADWELL_GT3E,          idle_cpu_bdw),
+        INTEL_CPU_FAM6(BROADWELL_G,             idle_cpu_bdw),
         INTEL_CPU_FAM6(BROADWELL_X,             idle_cpu_bdw),
         INTEL_CPU_FAM6(BROADWELL_XEON_D,        idle_cpu_bdw),
         INTEL_CPU_FAM6(SKYLAKE_L,               idle_cpu_skl),
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index ac52a6ec4931..07af068f6ab6 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -959,11 +959,11 @@ static const struct x86_cpu_id rapl_ids[] __initconst = {
 
         INTEL_CPU_FAM6(HASWELL, rapl_defaults_core),
         INTEL_CPU_FAM6(HASWELL_L, rapl_defaults_core),
-        INTEL_CPU_FAM6(HASWELL_GT3E, rapl_defaults_core),
+        INTEL_CPU_FAM6(HASWELL_G, rapl_defaults_core),
         INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server),
 
         INTEL_CPU_FAM6(BROADWELL, rapl_defaults_core),
-        INTEL_CPU_FAM6(BROADWELL_GT3E, rapl_defaults_core),
+        INTEL_CPU_FAM6(BROADWELL_G, rapl_defaults_core),
         INTEL_CPU_FAM6(BROADWELL_XEON_D, rapl_defaults_core),
         INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server),
 
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index bb1bef6bf0b9..271cf18efbab 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -3209,9 +3209,9 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
                 break;
         case INTEL_FAM6_HASWELL:        /* HSW */
         case INTEL_FAM6_HASWELL_X:      /* HSX */
-        case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
+        case INTEL_FAM6_HASWELL_G:      /* HSW */
         case INTEL_FAM6_BROADWELL:      /* BDW */
-        case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
+        case INTEL_FAM6_BROADWELL_G:    /* BDW */
         case INTEL_FAM6_BROADWELL_X:    /* BDX */
         case INTEL_FAM6_SKYLAKE_L:      /* SKL */
         case INTEL_FAM6_CANNONLAKE_L:   /* CNL */
@@ -3405,9 +3405,9 @@ int has_config_tdp(unsigned int family, unsigned int model)
         case INTEL_FAM6_IVYBRIDGE:      /* IVB */
         case INTEL_FAM6_HASWELL:        /* HSW */
         case INTEL_FAM6_HASWELL_X:      /* HSX */
-        case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
+        case INTEL_FAM6_HASWELL_G:      /* HSW */
         case INTEL_FAM6_BROADWELL:      /* BDW */
-        case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
+        case INTEL_FAM6_BROADWELL_G:    /* BDW */
         case INTEL_FAM6_BROADWELL_X:    /* BDX */
         case INTEL_FAM6_SKYLAKE_L:      /* SKL */
         case INTEL_FAM6_CANNONLAKE_L:   /* CNL */
@@ -3841,9 +3841,9 @@ void rapl_probe_intel(unsigned int family, unsigned int model)
         case INTEL_FAM6_SANDYBRIDGE:
         case INTEL_FAM6_IVYBRIDGE:
         case INTEL_FAM6_HASWELL:        /* HSW */
-        case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
+        case INTEL_FAM6_HASWELL_G:      /* HSW */
         case INTEL_FAM6_BROADWELL:      /* BDW */
-        case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
+        case INTEL_FAM6_BROADWELL_G:    /* BDW */
                 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
                 if (rapl_joules) {
                         BIC_PRESENT(BIC_Pkg_J);
@@ -4032,7 +4032,7 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model)
 
         switch (model) {
         case INTEL_FAM6_HASWELL:        /* HSW */
-        case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
+        case INTEL_FAM6_HASWELL_G:      /* HSW */
                 do_gfx_perf_limit_reasons = 1;
         case INTEL_FAM6_HASWELL_X:      /* HSX */
                 do_core_perf_limit_reasons = 1;
@@ -4251,9 +4251,9 @@ int has_snb_msrs(unsigned int family, unsigned int model)
         case INTEL_FAM6_IVYBRIDGE_X:    /* IVB Xeon */
         case INTEL_FAM6_HASWELL:        /* HSW */
         case INTEL_FAM6_HASWELL_X:      /* HSW */
-        case INTEL_FAM6_HASWELL_GT3E:   /* HSW */
+        case INTEL_FAM6_HASWELL_G:      /* HSW */
         case INTEL_FAM6_BROADWELL:      /* BDW */
-        case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
+        case INTEL_FAM6_BROADWELL_G:    /* BDW */
         case INTEL_FAM6_BROADWELL_X:    /* BDX */
         case INTEL_FAM6_SKYLAKE_L:      /* SKL */
         case INTEL_FAM6_CANNONLAKE_L:   /* CNL */