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authorZhiyong Tao <zhiyong.tao@mediatek.com>2019-03-31 23:35:35 -0400
committerLinus Walleij <linus.walleij@linaro.org>2019-04-08 05:20:28 -0400
commit5e73de3413c5e0c104588a197cbd158baa085aca (patch)
tree87b61fc40b7362c3344b6fb7ce72f68b1b3dff36
parent9f325c9837251519968821fe82cdd81b2c450a71 (diff)
pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183. The detail strength specification description of the I2C pin: When E1=0/E0=0, the strength is 0.125mA. When E1=0/E0=1, the strength is 0.25mA. When E1=1/E0=0, the strength is 0.5mA. When E1=1/E0=1, the strength is 1mA. For I2C pins, there are existing generic driving setup and the above specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving adjustment in generic driving setup. But in specific driving setup, they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific driving setup for I2C pins, the existing generic driving setup will be disabled. For some special features, we need the I2C pins specific driving setup. The specific driving setup is controlled by E1E0EN. So we need add extra vendor driving preperty instead of the generic driving property. We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific driving setup property. "XXX" means the value of E1E0EN. So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8183.c50
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c49
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h11
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-paris.c21
4 files changed, 131 insertions, 0 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
index 6262fd3678ea..2c7409ed16fa 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
@@ -472,6 +472,51 @@ static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
472 PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1), 472 PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
473}; 473};
474 474
475static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = {
476 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1),
477 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1),
478 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1),
479 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1),
480 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1),
481 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1),
482 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1),
483 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1),
484 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1),
485 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1),
486 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1),
487 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1),
488};
489
490static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = {
491 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1),
492 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1),
493 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1),
494 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1),
495 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1),
496 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1),
497 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1),
498 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1),
499 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1),
500 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1),
501 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1),
502 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1),
503};
504
505static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = {
506 PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1),
507 PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1),
508 PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1),
509 PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1),
510 PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1),
511 PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1),
512 PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1),
513 PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1),
514 PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1),
515 PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1),
516 PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1),
517 PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1),
518};
519
475static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = { 520static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
476 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range), 521 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
477 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range), 522 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
@@ -485,6 +530,9 @@ static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
485 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range), 530 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
486 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range), 531 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
487 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range), 532 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
533 [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range),
534 [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range),
535 [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range),
488}; 536};
489 537
490static const char * const mt8183_pinctrl_register_base_names[] = { 538static const char * const mt8183_pinctrl_register_base_names[] = {
@@ -517,6 +565,8 @@ static const struct mtk_pin_soc mt8183_data = {
517 .drive_get = mtk_pinconf_drive_get_rev1, 565 .drive_get = mtk_pinconf_drive_get_rev1,
518 .adv_pull_get = mtk_pinconf_adv_pull_get, 566 .adv_pull_get = mtk_pinconf_adv_pull_get,
519 .adv_pull_set = mtk_pinconf_adv_pull_set, 567 .adv_pull_set = mtk_pinconf_adv_pull_set,
568 .adv_drive_get = mtk_pinconf_adv_drive_get,
569 .adv_drive_set = mtk_pinconf_adv_drive_set,
520}; 570};
521 571
522static const struct of_device_id mt8183_pinctrl_of_match[] = { 572static const struct of_device_id mt8183_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index b1c368455d30..20e1c890e73b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -674,3 +674,52 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
674 674
675 return 0; 675 return 0;
676} 676}
677
678int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
679 const struct mtk_pin_desc *desc, u32 arg)
680{
681 int err;
682 int en = arg & 1;
683 int e0 = !!(arg & 2);
684 int e1 = !!(arg & 4);
685
686 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
687 if (err)
688 return err;
689
690 if (!en)
691 return err;
692
693 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
694 if (err)
695 return err;
696
697 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
698 if (err)
699 return err;
700
701 return err;
702}
703
704int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
705 const struct mtk_pin_desc *desc, u32 *val)
706{
707 u32 en, e0, e1;
708 int err;
709
710 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
711 if (err)
712 return err;
713
714 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
715 if (err)
716 return err;
717
718 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
719 if (err)
720 return err;
721
722 *val = (en | e0 << 1 | e1 << 2) & 0x7;
723
724 return 0;
725}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 6d24522739d9..1b7da42aa1d5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -63,6 +63,9 @@ enum {
63 PINCTRL_PIN_REG_IES, 63 PINCTRL_PIN_REG_IES,
64 PINCTRL_PIN_REG_PULLEN, 64 PINCTRL_PIN_REG_PULLEN,
65 PINCTRL_PIN_REG_PULLSEL, 65 PINCTRL_PIN_REG_PULLSEL,
66 PINCTRL_PIN_REG_DRV_EN,
67 PINCTRL_PIN_REG_DRV_E0,
68 PINCTRL_PIN_REG_DRV_E1,
66 PINCTRL_PIN_REG_MAX, 69 PINCTRL_PIN_REG_MAX,
67}; 70};
68 71
@@ -224,6 +227,10 @@ struct mtk_pin_soc {
224 int (*adv_pull_get)(struct mtk_pinctrl *hw, 227 int (*adv_pull_get)(struct mtk_pinctrl *hw,
225 const struct mtk_pin_desc *desc, bool pullup, 228 const struct mtk_pin_desc *desc, bool pullup,
226 u32 *val); 229 u32 *val);
230 int (*adv_drive_set)(struct mtk_pinctrl *hw,
231 const struct mtk_pin_desc *desc, u32 arg);
232 int (*adv_drive_get)(struct mtk_pinctrl *hw,
233 const struct mtk_pin_desc *desc, u32 *val);
227 234
228 /* Specific driver data */ 235 /* Specific driver data */
229 void *driver_data; 236 void *driver_data;
@@ -287,5 +294,9 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
287int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 294int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
288 const struct mtk_pin_desc *desc, bool pullup, 295 const struct mtk_pin_desc *desc, bool pullup,
289 u32 *val); 296 u32 *val);
297int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
298 const struct mtk_pin_desc *desc, u32 arg);
299int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
300 const struct mtk_pin_desc *desc, u32 *val);
290 301
291#endif /* __PINCTRL_MTK_COMMON_V2_H */ 302#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index b59e10852bfb..d3b34e9a7507 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -20,12 +20,14 @@
20#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) 20#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3) 21#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4) 22#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
23#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
23 24
24static const struct pinconf_generic_params mtk_custom_bindings[] = { 25static const struct pinconf_generic_params mtk_custom_bindings[] = {
25 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, 26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
26 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, 27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
27 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1}, 28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
28 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1}, 29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
29}; 31};
30 32
31#ifdef CONFIG_DEBUG_FS 33#ifdef CONFIG_DEBUG_FS
@@ -34,6 +36,7 @@ static const struct pin_config_item mtk_conf_items[] = {
34 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), 36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
35 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true), 37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true), 38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
37}; 40};
38#endif 41#endif
39 42
@@ -176,6 +179,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
176 return -ENOTSUPP; 179 return -ENOTSUPP;
177 } 180 }
178 break; 181 break;
182 case MTK_PIN_CONFIG_DRV_ADV:
183 if (hw->soc->adv_drive_get) {
184 err = hw->soc->adv_drive_get(hw, desc, &ret);
185 if (err)
186 return err;
187 } else {
188 return -ENOTSUPP;
189 }
190 break;
179 default: 191 default:
180 return -ENOTSUPP; 192 return -ENOTSUPP;
181 } 193 }
@@ -311,6 +323,15 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
311 return -ENOTSUPP; 323 return -ENOTSUPP;
312 } 324 }
313 break; 325 break;
326 case MTK_PIN_CONFIG_DRV_ADV:
327 if (hw->soc->adv_drive_set) {
328 err = hw->soc->adv_drive_set(hw, desc, arg);
329 if (err)
330 return err;
331 } else {
332 return -ENOTSUPP;
333 }
334 break;
314 default: 335 default:
315 err = -ENOTSUPP; 336 err = -ENOTSUPP;
316 } 337 }