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authorBjorn Andersson <bjorn.andersson@linaro.org>2019-07-23 10:23:38 -0400
committerGeorgi Djakov <georgi.djakov@linaro.org>2019-08-13 16:26:08 -0400
commit5e4e6c4d3ae0ccabd99ee6f8f48154fb2f59683b (patch)
tree5ab0edd95c94e964701720032115164e5941c230
parentbe06f8e7425dcf554ebc1c0f78fb286bbbfbe23a (diff)
interconnect: qcom: Add QCS404 interconnect provider driver
Add driver for the interconnect buses found in Qualcomm QCS404-based platforms. The topology consists of three NoCs that are controlled by a remote processor. This remote processor collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Diffstat
-rw-r--r--drivers/interconnect/qcom/Kconfig9
-rw-r--r--drivers/interconnect/qcom/Makefile2
-rw-r--r--drivers/interconnect/qcom/qcs404.c539
3 files changed, 550 insertions, 0 deletions
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 03fd67173494..339e8f10d4f3 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -5,6 +5,15 @@ config INTERCONNECT_QCOM
5 help 5 help
6 Support for Qualcomm's Network-on-Chip interconnect hardware. 6 Support for Qualcomm's Network-on-Chip interconnect hardware.
7 7
8config INTERCONNECT_QCOM_QCS404
9 tristate "Qualcomm QCS404 interconnect driver"
10 depends on INTERCONNECT_QCOM
11 depends on QCOM_SMD_RPM || COMPILE_TEST
12 select INTERCONNECT_QCOM_SMD_RPM
13 help
14 This is a driver for the Qualcomm Network-on-Chip on qcs404-based
15 platforms.
16
8config INTERCONNECT_QCOM_SDM845 17config INTERCONNECT_QCOM_SDM845
9 tristate "Qualcomm SDM845 interconnect driver" 18 tristate "Qualcomm SDM845 interconnect driver"
10 depends on INTERCONNECT_QCOM 19 depends on INTERCONNECT_QCOM
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index a600cf6cc272..67dafb783dec 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -1,7 +1,9 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2 2
3qnoc-qcs404-objs := qcs404.o
3qnoc-sdm845-objs := sdm845.o 4qnoc-sdm845-objs := sdm845.o
4icc-smd-rpm-objs := smd-rpm.o 5icc-smd-rpm-objs := smd-rpm.o
5 6
7obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
6obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o 8obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
7obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o 9obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c
new file mode 100644
index 000000000000..910081d6ddc0
--- /dev/null
+++ b/drivers/interconnect/qcom/qcs404.c
@@ -0,0 +1,539 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Linaro Ltd
4 */
5
6#include <dt-bindings/interconnect/qcom,qcs404.h>
7#include <linux/clk.h>
8#include <linux/device.h>
9#include <linux/interconnect-provider.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/of_platform.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16
17#include "smd-rpm.h"
18
19#define RPM_BUS_MASTER_REQ 0x73616d62
20#define RPM_BUS_SLAVE_REQ 0x766c7362
21
22enum {
23 QCS404_MASTER_AMPSS_M0 = 1,
24 QCS404_MASTER_GRAPHICS_3D,
25 QCS404_MASTER_MDP_PORT0,
26 QCS404_SNOC_BIMC_1_MAS,
27 QCS404_MASTER_TCU_0,
28 QCS404_MASTER_SPDM,
29 QCS404_MASTER_BLSP_1,
30 QCS404_MASTER_BLSP_2,
31 QCS404_MASTER_XM_USB_HS1,
32 QCS404_MASTER_CRYPTO_CORE0,
33 QCS404_MASTER_SDCC_1,
34 QCS404_MASTER_SDCC_2,
35 QCS404_SNOC_PNOC_MAS,
36 QCS404_MASTER_QPIC,
37 QCS404_MASTER_QDSS_BAM,
38 QCS404_BIMC_SNOC_MAS,
39 QCS404_PNOC_SNOC_MAS,
40 QCS404_MASTER_QDSS_ETR,
41 QCS404_MASTER_EMAC,
42 QCS404_MASTER_PCIE,
43 QCS404_MASTER_USB3,
44 QCS404_PNOC_INT_0,
45 QCS404_PNOC_INT_2,
46 QCS404_PNOC_INT_3,
47 QCS404_PNOC_SLV_0,
48 QCS404_PNOC_SLV_1,
49 QCS404_PNOC_SLV_2,
50 QCS404_PNOC_SLV_3,
51 QCS404_PNOC_SLV_4,
52 QCS404_PNOC_SLV_6,
53 QCS404_PNOC_SLV_7,
54 QCS404_PNOC_SLV_8,
55 QCS404_PNOC_SLV_9,
56 QCS404_PNOC_SLV_10,
57 QCS404_PNOC_SLV_11,
58 QCS404_SNOC_QDSS_INT,
59 QCS404_SNOC_INT_0,
60 QCS404_SNOC_INT_1,
61 QCS404_SNOC_INT_2,
62 QCS404_SLAVE_EBI_CH0,
63 QCS404_BIMC_SNOC_SLV,
64 QCS404_SLAVE_SPDM_WRAPPER,
65 QCS404_SLAVE_PDM,
66 QCS404_SLAVE_PRNG,
67 QCS404_SLAVE_TCSR,
68 QCS404_SLAVE_SNOC_CFG,
69 QCS404_SLAVE_MESSAGE_RAM,
70 QCS404_SLAVE_DISPLAY_CFG,
71 QCS404_SLAVE_GRAPHICS_3D_CFG,
72 QCS404_SLAVE_BLSP_1,
73 QCS404_SLAVE_TLMM_NORTH,
74 QCS404_SLAVE_PCIE_1,
75 QCS404_SLAVE_EMAC_CFG,
76 QCS404_SLAVE_BLSP_2,
77 QCS404_SLAVE_TLMM_EAST,
78 QCS404_SLAVE_TCU,
79 QCS404_SLAVE_PMIC_ARB,
80 QCS404_SLAVE_SDCC_1,
81 QCS404_SLAVE_SDCC_2,
82 QCS404_SLAVE_TLMM_SOUTH,
83 QCS404_SLAVE_USB_HS,
84 QCS404_SLAVE_USB3,
85 QCS404_SLAVE_CRYPTO_0_CFG,
86 QCS404_PNOC_SNOC_SLV,
87 QCS404_SLAVE_APPSS,
88 QCS404_SLAVE_WCSS,
89 QCS404_SNOC_BIMC_1_SLV,
90 QCS404_SLAVE_OCIMEM,
91 QCS404_SNOC_PNOC_SLV,
92 QCS404_SLAVE_QDSS_STM,
93 QCS404_SLAVE_CATS_128,
94 QCS404_SLAVE_OCMEM_64,
95 QCS404_SLAVE_LPASS,
96};
97
98#define to_qcom_provider(_provider) \
99 container_of(_provider, struct qcom_icc_provider, provider)
100
101static const struct clk_bulk_data bus_clocks[] = {
102 { .id = "bus" },
103 { .id = "bus_a" },
104};
105
106/**
107 * struct qcom_icc_provider - Qualcomm specific interconnect provider
108 * @provider: generic interconnect provider
109 * @bus_clks: the clk_bulk_data table of bus clocks
110 * @num_clks: the total number of clk_bulk_data entries
111 */
112struct qcom_icc_provider {
113 struct icc_provider provider;
114 struct clk_bulk_data *bus_clks;
115 int num_clks;
116};
117
118#define QCS404_MAX_LINKS 12
119
120/**
121 * struct qcom_icc_node - Qualcomm specific interconnect nodes
122 * @name: the node name used in debugfs
123 * @id: a unique node identifier
124 * @links: an array of nodes where we can go next while traversing
125 * @num_links: the total number of @links
126 * @buswidth: width of the interconnect between a node and the bus (bytes)
127 * @mas_rpm_id: RPM id for devices that are bus masters
128 * @slv_rpm_id: RPM id for devices that are bus slaves
129 * @rate: current bus clock rate in Hz
130 */
131struct qcom_icc_node {
132 unsigned char *name;
133 u16 id;
134 u16 links[QCS404_MAX_LINKS];
135 u16 num_links;
136 u16 buswidth;
137 int mas_rpm_id;
138 int slv_rpm_id;
139 u64 rate;
140};
141
142struct qcom_icc_desc {
143 struct qcom_icc_node **nodes;
144 size_t num_nodes;
145};
146
147#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
148 ...) \
149 static struct qcom_icc_node _name = { \
150 .name = #_name, \
151 .id = _id, \
152 .buswidth = _buswidth, \
153 .mas_rpm_id = _mas_rpm_id, \
154 .slv_rpm_id = _slv_rpm_id, \
155 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
156 .links = { __VA_ARGS__ }, \
157 }
158
159DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
160DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, 6, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
161DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, 8, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
162DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0);
163DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
164DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);
165DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3);
166DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3);
167DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0);
168DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
169DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0);
170DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0);
171DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2);
172DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0);
173DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT);
174DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1);
175DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0);
176DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT);
177DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
178DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
179DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
180DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
181DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9);
182DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV);
183DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM);
184DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR);
185DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG);
186DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM);
187DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG);
188DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG);
189DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2);
190DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG);
191DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB);
192DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS);
193DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3);
194DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
195DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS);
196DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2);
197DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM);
198DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0);
199DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS);
200DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0);
201DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0);
202DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0);
203DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0);
204DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0);
205DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0);
206DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
207DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
208DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0);
209DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0);
210DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0);
211DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0);
212DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0);
213DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0);
214DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0);
215DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0);
216DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0);
217DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0);
218DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0);
219DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0);
220DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0);
221DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0);
222DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS);
223DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0);
224DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0);
225DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS);
226DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0);
227DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS);
228DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0);
229DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0);
230DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0);
231DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0);
232
233static struct qcom_icc_node *qcs404_bimc_nodes[] = {
234 [MASTER_AMPSS_M0] = &mas_apps_proc,
235 [MASTER_OXILI] = &mas_oxili,
236 [MASTER_MDP_PORT0] = &mas_mdp,
237 [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
238 [MASTER_TCU_0] = &mas_tcu_0,
239 [SLAVE_EBI_CH0] = &slv_ebi,
240 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
241};
242
243static struct qcom_icc_desc qcs404_bimc = {
244 .nodes = qcs404_bimc_nodes,
245 .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
246};
247
248static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
249 [MASTER_SPDM] = &mas_spdm,
250 [MASTER_BLSP_1] = &mas_blsp_1,
251 [MASTER_BLSP_2] = &mas_blsp_2,
252 [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
253 [MASTER_CRYPT0] = &mas_crypto,
254 [MASTER_SDCC_1] = &mas_sdcc_1,
255 [MASTER_SDCC_2] = &mas_sdcc_2,
256 [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
257 [MASTER_QPIC] = &mas_qpic,
258 [PCNOC_INT_0] = &pcnoc_int_0,
259 [PCNOC_INT_2] = &pcnoc_int_2,
260 [PCNOC_INT_3] = &pcnoc_int_3,
261 [PCNOC_S_0] = &pcnoc_s_0,
262 [PCNOC_S_1] = &pcnoc_s_1,
263 [PCNOC_S_2] = &pcnoc_s_2,
264 [PCNOC_S_3] = &pcnoc_s_3,
265 [PCNOC_S_4] = &pcnoc_s_4,
266 [PCNOC_S_6] = &pcnoc_s_6,
267 [PCNOC_S_7] = &pcnoc_s_7,
268 [PCNOC_S_8] = &pcnoc_s_8,
269 [PCNOC_S_9] = &pcnoc_s_9,
270 [PCNOC_S_10] = &pcnoc_s_10,
271 [PCNOC_S_11] = &pcnoc_s_11,
272 [SLAVE_SPDM] = &slv_spdm,
273 [SLAVE_PDM] = &slv_pdm,
274 [SLAVE_PRNG] = &slv_prng,
275 [SLAVE_TCSR] = &slv_tcsr,
276 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
277 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
278 [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
279 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
280 [SLAVE_BLSP_1] = &slv_blsp_1,
281 [SLAVE_BLSP_2] = &slv_blsp_2,
282 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
283 [SLAVE_PCIE] = &slv_pcie,
284 [SLAVE_ETHERNET] = &slv_ethernet,
285 [SLAVE_TLMM_EAST] = &slv_tlmm_east,
286 [SLAVE_TCU] = &slv_tcu,
287 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
288 [SLAVE_SDCC_1] = &slv_sdcc_1,
289 [SLAVE_SDCC_2] = &slv_sdcc_2,
290 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
291 [SLAVE_USB_HS] = &slv_usb_hs,
292 [SLAVE_USB3] = &slv_usb3,
293 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
294 [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
295};
296
297static struct qcom_icc_desc qcs404_pcnoc = {
298 .nodes = qcs404_pcnoc_nodes,
299 .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
300};
301
302static struct qcom_icc_node *qcs404_snoc_nodes[] = {
303 [MASTER_QDSS_BAM] = &mas_qdss_bam,
304 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
305 [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
306 [MASTER_QDSS_ETR] = &mas_qdss_etr,
307 [MASTER_EMAC] = &mas_emac,
308 [MASTER_PCIE] = &mas_pcie,
309 [MASTER_USB3] = &mas_usb3,
310 [QDSS_INT] = &qdss_int,
311 [SNOC_INT_0] = &snoc_int_0,
312 [SNOC_INT_1] = &snoc_int_1,
313 [SNOC_INT_2] = &snoc_int_2,
314 [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
315 [SLAVE_WCSS] = &slv_wcss,
316 [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
317 [SLAVE_IMEM] = &slv_imem,
318 [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
319 [SLAVE_QDSS_STM] = &slv_qdss_stm,
320 [SLAVE_CATS_0] = &slv_cats_0,
321 [SLAVE_CATS_1] = &slv_cats_1,
322 [SLAVE_LPASS] = &slv_lpass,
323};
324
325static struct qcom_icc_desc qcs404_snoc = {
326 .nodes = qcs404_snoc_nodes,
327 .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
328};
329
330static int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
331 u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
332{
333 *agg_avg += avg_bw;
334 *agg_peak = max(*agg_peak, peak_bw);
335
336 return 0;
337}
338
339static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
340{
341 struct qcom_icc_provider *qp;
342 struct qcom_icc_node *qn;
343 struct icc_provider *provider;
344 struct icc_node *n;
345 u64 sum_bw;
346 u64 max_peak_bw;
347 u64 rate;
348 u32 agg_avg = 0;
349 u32 agg_peak = 0;
350 int ret, i;
351
352 qn = src->data;
353 provider = src->provider;
354 qp = to_qcom_provider(provider);
355
356 list_for_each_entry(n, &provider->nodes, node_list)
357 qcom_icc_aggregate(n, 0, n->avg_bw, n->peak_bw,
358 &agg_avg, &agg_peak);
359
360 sum_bw = icc_units_to_bps(agg_avg);
361 max_peak_bw = icc_units_to_bps(agg_peak);
362
363 /* send bandwidth request message to the RPM processor */
364 if (qn->mas_rpm_id != -1) {
365 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
366 RPM_BUS_MASTER_REQ,
367 qn->mas_rpm_id,
368 sum_bw);
369 if (ret) {
370 pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
371 qn->mas_rpm_id, ret);
372 return ret;
373 }
374 }
375
376 if (qn->slv_rpm_id != -1) {
377 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
378 RPM_BUS_SLAVE_REQ,
379 qn->slv_rpm_id,
380 sum_bw);
381 if (ret) {
382 pr_err("qcom_icc_rpm_smd_send slv error %d\n",
383 ret);
384 return ret;
385 }
386 }
387
388 rate = max(sum_bw, max_peak_bw);
389
390 do_div(rate, qn->buswidth);
391
392 if (qn->rate == rate)
393 return 0;
394
395 for (i = 0; i < qp->num_clks; i++) {
396 ret = clk_set_rate(qp->bus_clks[i].clk, rate);
397 if (ret) {
398 pr_err("%s clk_set_rate error: %d\n",
399 qp->bus_clks[i].id, ret);
400 return ret;
401 }
402 }
403
404 qn->rate = rate;
405
406 return 0;
407}
408
409static int qnoc_probe(struct platform_device *pdev)
410{
411 struct device *dev = &pdev->dev;
412 const struct qcom_icc_desc *desc;
413 struct icc_onecell_data *data;
414 struct icc_provider *provider;
415 struct qcom_icc_node **qnodes;
416 struct qcom_icc_provider *qp;
417 struct icc_node *node;
418 size_t num_nodes, i;
419 int ret;
420
421 /* wait for the RPM proxy */
422 if (!qcom_icc_rpm_smd_available())
423 return -EPROBE_DEFER;
424
425 desc = of_device_get_match_data(dev);
426 if (!desc)
427 return -EINVAL;
428
429 qnodes = desc->nodes;
430 num_nodes = desc->num_nodes;
431
432 qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
433 if (!qp)
434 return -ENOMEM;
435
436 data = devm_kcalloc(dev, num_nodes, sizeof(*node), GFP_KERNEL);
437 if (!data)
438 return -ENOMEM;
439
440 qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
441 GFP_KERNEL);
442 if (!qp->bus_clks)
443 return -ENOMEM;
444
445 qp->num_clks = ARRAY_SIZE(bus_clocks);
446 ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
447 if (ret)
448 return ret;
449
450 ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
451 if (ret)
452 return ret;
453
454 provider = &qp->provider;
455 INIT_LIST_HEAD(&provider->nodes);
456 provider->dev = dev;
457 provider->set = qcom_icc_set;
458 provider->aggregate = qcom_icc_aggregate;
459 provider->xlate = of_icc_xlate_onecell;
460 provider->data = data;
461
462 ret = icc_provider_add(provider);
463 if (ret) {
464 dev_err(dev, "error adding interconnect provider: %d\n", ret);
465 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
466 return ret;
467 }
468
469 for (i = 0; i < num_nodes; i++) {
470 size_t j;
471
472 node = icc_node_create(qnodes[i]->id);
473 if (IS_ERR(node)) {
474 ret = PTR_ERR(node);
475 goto err;
476 }
477
478 node->name = qnodes[i]->name;
479 node->data = qnodes[i];
480 icc_node_add(node, provider);
481
482 dev_dbg(dev, "registered node %s\n", node->name);
483
484 /* populate links */
485 for (j = 0; j < qnodes[i]->num_links; j++)
486 icc_link_create(node, qnodes[i]->links[j]);
487
488 data->nodes[i] = node;
489 }
490 data->num_nodes = num_nodes;
491
492 platform_set_drvdata(pdev, qp);
493
494 return 0;
495err:
496 list_for_each_entry(node, &provider->nodes, node_list) {
497 icc_node_del(node);
498 icc_node_destroy(node->id);
499 }
500 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
501 icc_provider_del(provider);
502
503 return ret;
504}
505
506static int qnoc_remove(struct platform_device *pdev)
507{
508 struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
509 struct icc_provider *provider = &qp->provider;
510 struct icc_node *n;
511
512 list_for_each_entry(n, &provider->nodes, node_list) {
513 icc_node_del(n);
514 icc_node_destroy(n->id);
515 }
516 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
517
518 return icc_provider_del(provider);
519}
520
521static const struct of_device_id qcs404_noc_of_match[] = {
522 { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
523 { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
524 { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
525 { },
526};
527MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
528
529static struct platform_driver qcs404_noc_driver = {
530 .probe = qnoc_probe,
531 .remove = qnoc_remove,
532 .driver = {
533 .name = "qnoc-qcs404",
534 .of_match_table = qcs404_noc_of_match,
535 },
536};
537module_platform_driver(qcs404_noc_driver);
538MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
539MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 00:55:46 -0400