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authorAlison Wang <alison.wang@nxp.com>2018-12-25 19:59:53 -0500
committerMark Brown <broonie@kernel.org>2019-01-07 13:11:25 -0500
commit5dc4ca2996840db569e43d00420c10499140274a (patch)
treeb3e4bd57d6a502628edb08692ff339c5e808f18b
parent47caf048a017ecc95cdd0802bc3b015a1559e601 (diff)
ASoC: sgtl5000: Allow SCLK pad drive strength to be changed
This patch introduces "sclk-strength" property to allow SCLK pad drive strength to be changed via device tree. When running playback test on LS1028ARDB, Tx Frame sync error interrupt will occur sometimes. Some noises also exist. After changing SCLK pad drive strength to the maximum value, the issues are gone. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/sound/sgtl5000.txt9
-rw-r--r--sound/soc/codecs/sgtl5000.c19
2 files changed, 27 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
index 9c58f724396a..9d9ff5184939 100644
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt
@@ -37,6 +37,15 @@ VDDIO 1.8V 2.5V 3.3V
372 = 3.33 mA 5.74 mA 8.03 mA 372 = 3.33 mA 5.74 mA 8.03 mA
383 = 4.99 mA 8.61 mA 12.05 mA 383 = 4.99 mA 8.61 mA 12.05 mA
39 39
40- sclk-strength: the SCLK pad strength. Possible values are:
410, 1, 2 and 3 as per the table below:
42
43VDDIO 1.8V 2.5V 3.3V
440 = Disable
451 = 1.66 mA 2.87 mA 4.02 mA
462 = 3.33 mA 5.74 mA 8.03 mA
473 = 4.99 mA 8.61 mA 12.05 mA
48
40Example: 49Example:
41 50
42sgtl5000: codec@a { 51sgtl5000: codec@a {
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index add18d6d77da..a6a4748c97f9 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -116,6 +116,13 @@ enum {
116 I2S_LRCLK_STRENGTH_HIGH, 116 I2S_LRCLK_STRENGTH_HIGH,
117}; 117};
118 118
119enum {
120 I2S_SCLK_STRENGTH_DISABLE,
121 I2S_SCLK_STRENGTH_LOW,
122 I2S_SCLK_STRENGTH_MEDIUM,
123 I2S_SCLK_STRENGTH_HIGH,
124};
125
119/* sgtl5000 private structure in codec */ 126/* sgtl5000 private structure in codec */
120struct sgtl5000_priv { 127struct sgtl5000_priv {
121 int sysclk; /* sysclk rate */ 128 int sysclk; /* sysclk rate */
@@ -129,6 +136,7 @@ struct sgtl5000_priv {
129 u8 micbias_resistor; 136 u8 micbias_resistor;
130 u8 micbias_voltage; 137 u8 micbias_voltage;
131 u8 lrclk_strength; 138 u8 lrclk_strength;
139 u8 sclk_strength;
132}; 140};
133 141
134/* 142/*
@@ -1302,7 +1310,9 @@ static int sgtl5000_probe(struct snd_soc_component *component)
1302 SGTL5000_DAC_MUTE_RIGHT | 1310 SGTL5000_DAC_MUTE_RIGHT |
1303 SGTL5000_DAC_MUTE_LEFT); 1311 SGTL5000_DAC_MUTE_LEFT);
1304 1312
1305 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f); 1313 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT |
1314 (sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT |
1315 0x1f);
1306 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg); 1316 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
1307 1317
1308 snd_soc_component_write(component, SGTL5000_CHIP_ANA_CTRL, 1318 snd_soc_component_write(component, SGTL5000_CHIP_ANA_CTRL,
@@ -1542,6 +1552,13 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
1542 sgtl5000->lrclk_strength = value; 1552 sgtl5000->lrclk_strength = value;
1543 } 1553 }
1544 1554
1555 sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW;
1556 if (!of_property_read_u32(np, "sclk-strength", &value)) {
1557 if (value > I2S_SCLK_STRENGTH_HIGH)
1558 value = I2S_SCLK_STRENGTH_LOW;
1559 sgtl5000->sclk_strength = value;
1560 }
1561
1545 /* Ensure sgtl5000 will start with sane register values */ 1562 /* Ensure sgtl5000 will start with sane register values */
1546 sgtl5000_fill_defaults(client); 1563 sgtl5000_fill_defaults(client);
1547 1564