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authorStephen Boyd <sboyd@kernel.org>2019-11-04 12:59:16 -0500
committerStephen Boyd <sboyd@kernel.org>2019-11-04 12:59:33 -0500
commit5a60b5aa96e8619baf02865e3002704fc2897731 (patch)
tree381f60a3c1399ef79f4229b1d33e98feb3abe565
parent78bdf57e9943186f4b1effb1c18555885f80b5ff (diff)
parente9323b664ce29547d996195e8a6129a351c39108 (diff)
Merge tag 'clk-v5.4-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-fixes
Pull Samsung clk driver fixes from Sylwester Nawrocki: - system suspend related fixes for the exynos542x clocks driver - probe() error paths fixes in the exynos5433 CMU driver adding proper release of memory and clk resources * tag 'clk-v5.4-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c27
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c14
2 files changed, 37 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7670cc596c74..31466cd1842f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -165,12 +165,18 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
165 GATE_BUS_CPU, 165 GATE_BUS_CPU,
166 GATE_SCLK_CPU, 166 GATE_SCLK_CPU,
167 CLKOUT_CMU_CPU, 167 CLKOUT_CMU_CPU,
168 CPLL_CON0,
169 DPLL_CON0,
168 EPLL_CON0, 170 EPLL_CON0,
169 EPLL_CON1, 171 EPLL_CON1,
170 EPLL_CON2, 172 EPLL_CON2,
171 RPLL_CON0, 173 RPLL_CON0,
172 RPLL_CON1, 174 RPLL_CON1,
173 RPLL_CON2, 175 RPLL_CON2,
176 IPLL_CON0,
177 SPLL_CON0,
178 VPLL_CON0,
179 MPLL_CON0,
174 SRC_TOP0, 180 SRC_TOP0,
175 SRC_TOP1, 181 SRC_TOP1,
176 SRC_TOP2, 182 SRC_TOP2,
@@ -1172,8 +1178,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
1172 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1178 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1173 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1179 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1174 1180
1175 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1176
1177 /* CDREX */ 1181 /* CDREX */
1178 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 1182 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
1179 GATE_BUS_CDREX0, 0, 0, 0), 1183 GATE_BUS_CDREX0, 0, 0, 0),
@@ -1248,6 +1252,15 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1248 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1252 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1249}; 1253};
1250 1254
1255static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
1256 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1257};
1258
1259static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
1260 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1261 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1262};
1263
1251static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1264static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1252 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1265 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1253}; 1266};
@@ -1320,6 +1333,14 @@ static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
1320 .pd_name = "GSC", 1333 .pd_name = "GSC",
1321}; 1334};
1322 1335
1336static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
1337 .gate_clks = exynos5x_g3d_gate_clks,
1338 .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
1339 .suspend_regs = exynos5x_g3d_suspend_regs,
1340 .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
1341 .pd_name = "G3D",
1342};
1343
1323static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { 1344static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
1324 .div_clks = exynos5x_mfc_div_clks, 1345 .div_clks = exynos5x_mfc_div_clks,
1325 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1346 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
@@ -1351,6 +1372,7 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
1351static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { 1372static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
1352 &exynos5x_disp_subcmu, 1373 &exynos5x_disp_subcmu,
1353 &exynos5x_gsc_subcmu, 1374 &exynos5x_gsc_subcmu,
1375 &exynos5x_g3d_subcmu,
1354 &exynos5x_mfc_subcmu, 1376 &exynos5x_mfc_subcmu,
1355 &exynos5x_mscl_subcmu, 1377 &exynos5x_mscl_subcmu,
1356}; 1378};
@@ -1358,6 +1380,7 @@ static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
1358static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { 1380static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
1359 &exynos5x_disp_subcmu, 1381 &exynos5x_disp_subcmu,
1360 &exynos5x_gsc_subcmu, 1382 &exynos5x_gsc_subcmu,
1383 &exynos5x_g3d_subcmu,
1361 &exynos5x_mfc_subcmu, 1384 &exynos5x_mfc_subcmu,
1362 &exynos5x_mscl_subcmu, 1385 &exynos5x_mscl_subcmu,
1363 &exynos5800_mau_subcmu, 1386 &exynos5800_mau_subcmu,
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 7824c2ba3d8e..4b1aa9382ad2 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -13,6 +13,7 @@
13#include <linux/of_device.h> 13#include <linux/of_device.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h> 15#include <linux/pm_runtime.h>
16#include <linux/slab.h>
16 17
17#include <dt-bindings/clock/exynos5433.h> 18#include <dt-bindings/clock/exynos5433.h>
18 19
@@ -5584,6 +5585,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5584 5585
5585 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs, 5586 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5586 info->nr_clk_regs); 5587 info->nr_clk_regs);
5588 if (!data->clk_save)
5589 return -ENOMEM;
5587 data->nr_clk_save = info->nr_clk_regs; 5590 data->nr_clk_save = info->nr_clk_regs;
5588 data->clk_suspend = info->suspend_regs; 5591 data->clk_suspend = info->suspend_regs;
5589 data->nr_clk_suspend = info->nr_suspend_regs; 5592 data->nr_clk_suspend = info->nr_suspend_regs;
@@ -5592,12 +5595,19 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5592 if (data->nr_pclks > 0) { 5595 if (data->nr_pclks > 0) {
5593 data->pclks = devm_kcalloc(dev, sizeof(struct clk *), 5596 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5594 data->nr_pclks, GFP_KERNEL); 5597 data->nr_pclks, GFP_KERNEL);
5595 5598 if (!data->pclks) {
5599 kfree(data->clk_save);
5600 return -ENOMEM;
5601 }
5596 for (i = 0; i < data->nr_pclks; i++) { 5602 for (i = 0; i < data->nr_pclks; i++) {
5597 struct clk *clk = of_clk_get(dev->of_node, i); 5603 struct clk *clk = of_clk_get(dev->of_node, i);
5598 5604
5599 if (IS_ERR(clk)) 5605 if (IS_ERR(clk)) {
5606 kfree(data->clk_save);
5607 while (--i >= 0)
5608 clk_put(data->pclks[i]);
5600 return PTR_ERR(clk); 5609 return PTR_ERR(clk);
5610 }
5601 data->pclks[i] = clk; 5611 data->pclks[i] = clk;
5602 } 5612 }
5603 } 5613 }