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authorArnd Bergmann <arnd@arndb.de>2019-08-09 12:33:15 -0400
committerArnd Bergmann <arnd@arndb.de>2019-08-14 09:36:21 -0400
commit59d3ae9a5bf60c037e3a6f6e6bcfbd1c048aa313 (patch)
treeff92bc0b2ad721bc221236e0ff56b15eeb4f00ba
parentf63cf88fd88b9d01063338d1f05381800660952e (diff)
ARM: remove Intel iop33x and iop13xx support
There are three families of IOP machines we support in Linux: iop32x (which includes EP80219), iop33x and iop13xx (aka IOP34x aka WP8134x). All products we support in the kernel are based on the first of these, iop32x, the other families only ever supported the Intel reference boards but no actual machine anyone could ever buy. While one could clearly make them all three work in a single kernel with some work, this takes the easy way out, removing the later two platforms entirely, under the assumption that there are no remaining users. Earlier versions of OpenWRT and Debian both had support for iop32x but not the others, and they both dropped iop32x as well in their 2015 releases. Link: https://lore.kernel.org/r/20190809163334.489360-1-arnd@arndb.de Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Wolfram Sang <wsa@the-dreams.de> # for I2C parts Acked-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/arm/Kconfig30
-rw-r--r--arch/arm/Kconfig.debug8
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/iop13xx_defconfig118
-rw-r--r--arch/arm/configs/iop33x_defconfig85
-rw-r--r--arch/arm/mach-iop13xx/Kconfig21
-rw-r--r--arch/arm/mach-iop13xx/Makefile9
-rw-r--r--arch/arm/mach-iop13xx/Makefile.boot4
-rw-r--r--arch/arm/mach-iop13xx/include/mach/adma.h608
-rw-r--r--arch/arm/mach-iop13xx/include/mach/entry-macro.S29
-rw-r--r--arch/arm/mach-iop13xx/include/mach/hardware.h22
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h508
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iq81340.h29
-rw-r--r--arch/arm/mach-iop13xx/include/mach/irqs.h195
-rw-r--r--arch/arm/mach-iop13xx/include/mach/memory.h68
-rw-r--r--arch/arm/mach-iop13xx/include/mach/time.h127
-rw-r--r--arch/arm/mach-iop13xx/include/mach/uncompress.h23
-rw-r--r--arch/arm/mach-iop13xx/io.c77
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c84
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c86
-rw-r--r--arch/arm/mach-iop13xx/irq.c227
-rw-r--r--arch/arm/mach-iop13xx/msi.c152
-rw-r--r--arch/arm/mach-iop13xx/msi.h12
-rw-r--r--arch/arm/mach-iop13xx/pci.c1115
-rw-r--r--arch/arm/mach-iop13xx/pci.h66
-rw-r--r--arch/arm/mach-iop13xx/setup.c595
-rw-r--r--arch/arm/mach-iop13xx/tpmi.c244
-rw-r--r--arch/arm/mach-iop33x/Kconfig22
-rw-r--r--arch/arm/mach-iop33x/Makefile9
-rw-r--r--arch/arm/mach-iop33x/Makefile.boot4
-rw-r--r--arch/arm/mach-iop33x/include/mach/adma.h6
-rw-r--r--arch/arm/mach-iop33x/include/mach/entry-macro.S34
-rw-r--r--arch/arm/mach-iop33x/include/mach/hardware.h44
-rw-r--r--arch/arm/mach-iop33x/include/mach/iop33x.h37
-rw-r--r--arch/arm/mach-iop33x/include/mach/iq80331.h17
-rw-r--r--arch/arm/mach-iop33x/include/mach/iq80332.h17
-rw-r--r--arch/arm/mach-iop33x/include/mach/irqs.h57
-rw-r--r--arch/arm/mach-iop33x/include/mach/time.h5
-rw-r--r--arch/arm/mach-iop33x/include/mach/uncompress.h37
-rw-r--r--arch/arm/mach-iop33x/iq80331.c148
-rw-r--r--arch/arm/mach-iop33x/iq80332.c148
-rw-r--r--arch/arm/mach-iop33x/irq.c115
-rw-r--r--arch/arm/mach-iop33x/uart.c100
-rw-r--r--arch/arm/plat-iop/Makefile14
-rw-r--r--arch/arm/plat-iop/adma.c32
-rw-r--r--arch/arm/plat-iop/i2c.c17
-rw-r--r--arch/arm/plat-iop/pmu.c6
-rw-r--r--drivers/dma/Kconfig2
-rw-r--r--drivers/gpio/Kconfig2
-rw-r--r--drivers/i2c/busses/Kconfig2
51 files changed, 9 insertions, 5419 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 2ab869c04695..a1ebe7956912 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1749,20 +1749,11 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1749S: Maintained 1749S: Maintained
1750F: arch/arm/mach-pxa/colibri-pxa270-income.c 1750F: arch/arm/mach-pxa/colibri-pxa270-income.c
1751 1751
1752ARM/INTEL IOP13XX ARM ARCHITECTURE
1753M: Lennert Buytenhek <kernel@wantstofly.org>
1754L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1755S: Maintained
1756
1757ARM/INTEL IOP32X ARM ARCHITECTURE 1752ARM/INTEL IOP32X ARM ARCHITECTURE
1758M: Lennert Buytenhek <kernel@wantstofly.org> 1753M: Lennert Buytenhek <kernel@wantstofly.org>
1759L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1754L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1760S: Maintained 1755S: Maintained
1761 1756
1762ARM/INTEL IOP33X ARM ARCHITECTURE
1763L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1764S: Orphan
1765
1766ARM/INTEL IQ81342EX MACHINE SUPPORT 1757ARM/INTEL IQ81342EX MACHINE SUPPORT
1767M: Lennert Buytenhek <kernel@wantstofly.org> 1758M: Lennert Buytenhek <kernel@wantstofly.org>
1768L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1759L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 769a853c8c6e..8c4382e5e5f3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -263,7 +263,6 @@ config PHYS_OFFSET
263 default 0x00000000 if ARCH_EBSA110 || \ 263 default 0x00000000 if ARCH_EBSA110 || \
264 ARCH_FOOTBRIDGE || \ 264 ARCH_FOOTBRIDGE || \
265 ARCH_INTEGRATOR || \ 265 ARCH_INTEGRATOR || \
266 ARCH_IOP13XX || \
267 ARCH_REALVIEW 266 ARCH_REALVIEW
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 267 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210 268 default 0x20000000 if ARCH_S5PV210
@@ -376,19 +375,6 @@ config ARCH_FOOTBRIDGE
376 Support for systems based on the DC21285 companion chip 375 Support for systems based on the DC21285 companion chip
377 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 376 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
378 377
379config ARCH_IOP13XX
380 bool "IOP13xx-based"
381 depends on MMU
382 select CPU_XSC3
383 select NEED_MACH_MEMORY_H
384 select NEED_RET_TO_USER
385 select FORCE_PCI
386 select PLAT_IOP
387 select VMSPLIT_1G
388 select SPARSE_IRQ
389 help
390 Support for Intel's IOP13XX (XScale) family of processors.
391
392config ARCH_IOP32X 378config ARCH_IOP32X
393 bool "IOP32x-based" 379 bool "IOP32x-based"
394 depends on MMU 380 depends on MMU
@@ -402,18 +388,6 @@ config ARCH_IOP32X
402 Support for Intel's 80219 and IOP32X (XScale) family of 388 Support for Intel's 80219 and IOP32X (XScale) family of
403 processors. 389 processors.
404 390
405config ARCH_IOP33X
406 bool "IOP33x-based"
407 depends on MMU
408 select CPU_XSCALE
409 select GPIO_IOP
410 select GPIOLIB
411 select NEED_RET_TO_USER
412 select FORCE_PCI
413 select PLAT_IOP
414 help
415 Support for Intel's IOP33X (XScale) family of processors.
416
417config ARCH_IXP4XX 391config ARCH_IXP4XX
418 bool "IXP4xx-based" 392 bool "IXP4xx-based"
419 depends on MMU 393 depends on MMU
@@ -706,12 +680,8 @@ source "arch/arm/mach-imx/Kconfig"
706 680
707source "arch/arm/mach-integrator/Kconfig" 681source "arch/arm/mach-integrator/Kconfig"
708 682
709source "arch/arm/mach-iop13xx/Kconfig"
710
711source "arch/arm/mach-iop32x/Kconfig" 683source "arch/arm/mach-iop32x/Kconfig"
712 684
713source "arch/arm/mach-iop33x/Kconfig"
714
715source "arch/arm/mach-ixp4xx/Kconfig" 685source "arch/arm/mach-ixp4xx/Kconfig"
716 686
717source "arch/arm/mach-keystone/Kconfig" 687source "arch/arm/mach-keystone/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 2496f1c89b88..a4447f21bb25 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1560,9 +1560,7 @@ config DEBUG_UART_PL01X
1560 1560
1561# Compatibility options for 8250 1561# Compatibility options for 8250
1562config DEBUG_UART_8250 1562config DEBUG_UART_8250
1563 def_bool ARCH_EBSA110 || \ 1563 def_bool ARCH_EBSA110 || ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC
1564 ARCH_IOP13XX || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || \
1565 ARCH_RPC
1566 1564
1567config DEBUG_UART_PHYS 1565config DEBUG_UART_PHYS
1568 hex "Physical base address of debug UART" 1566 hex "Physical base address of debug UART"
@@ -1675,7 +1673,6 @@ config DEBUG_UART_PHYS
1675 default 0xffc02000 if DEBUG_SOCFPGA_UART0 1673 default 0xffc02000 if DEBUG_SOCFPGA_UART0
1676 default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1 1674 default 0xffc02100 if DEBUG_SOCFPGA_ARRIA10_UART1
1677 default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 1675 default 0xffc03000 if DEBUG_SOCFPGA_CYCLONE5_UART1
1678 default 0xffd82340 if ARCH_IOP13XX
1679 default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 1676 default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0
1680 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 1677 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2
1681 default 0xfff36000 if DEBUG_HIGHBANK_UART 1678 default 0xfff36000 if DEBUG_HIGHBANK_UART
@@ -1685,7 +1682,6 @@ config DEBUG_UART_PHYS
1685 default 0xfffe8600 if DEBUG_BCM63XX_UART 1682 default 0xfffe8600 if DEBUG_BCM63XX_UART
1686 default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU 1683 default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU
1687 default 0xfffff200 if DEBUG_AT91_RM9200_DBGU 1684 default 0xfffff200 if DEBUG_AT91_RM9200_DBGU
1688 default 0xfffff700 if ARCH_IOP33X
1689 depends on ARCH_EP93XX || \ 1685 depends on ARCH_EP93XX || \
1690 DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ 1686 DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
1691 DEBUG_LL_UART_EFM32 || \ 1687 DEBUG_LL_UART_EFM32 || \
@@ -1797,14 +1793,12 @@ config DEBUG_UART_VIRT
1797 default 0xfedc0000 if DEBUG_EP93XX 1793 default 0xfedc0000 if DEBUG_EP93XX
1798 default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1 1794 default 0xfee003f8 if DEBUG_FOOTBRIDGE_COM1
1799 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART 1795 default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
1800 default 0xfee82340 if ARCH_IOP13XX
1801 default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN 1796 default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
1802 default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN 1797 default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
1803 default 0xfef36000 if DEBUG_HIGHBANK_UART 1798 default 0xfef36000 if DEBUG_HIGHBANK_UART
1804 default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 1799 default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
1805 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 1800 default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
1806 default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 1801 default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
1807 default 0xfefff700 if ARCH_IOP33X
1808 default 0xff003000 if DEBUG_U300_UART 1802 default 0xff003000 if DEBUG_U300_UART
1809 default 0xffd01000 if DEBUG_HIP01_UART 1803 default 0xffd01000 if DEBUG_HIP01_UART
1810 default DEBUG_UART_PHYS if !MMU 1804 default DEBUG_UART_PHYS if !MMU
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 04e3f2f5a6b4..516ff354b525 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,9 +173,7 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini
173machine-$(CONFIG_ARCH_HIGHBANK) += highbank 173machine-$(CONFIG_ARCH_HIGHBANK) += highbank
174machine-$(CONFIG_ARCH_HISI) += hisi 174machine-$(CONFIG_ARCH_HISI) += hisi
175machine-$(CONFIG_ARCH_INTEGRATOR) += integrator 175machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
176machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
177machine-$(CONFIG_ARCH_IOP32X) += iop32x 176machine-$(CONFIG_ARCH_IOP32X) += iop32x
178machine-$(CONFIG_ARCH_IOP33X) += iop33x
179machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx 177machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
180machine-$(CONFIG_ARCH_KEYSTONE) += keystone 178machine-$(CONFIG_ARCH_KEYSTONE) += keystone
181machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx 179machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
deleted file mode 100644
index 30cdb287e1b4..000000000000
--- a/arch/arm/configs/iop13xx_defconfig
+++ /dev/null
@@ -1,118 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2CONFIG_SYSVIPC=y
3CONFIG_POSIX_MQUEUE=y
4CONFIG_BSD_PROCESS_ACCT=y
5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_BLK_DEV_INITRD=y
9# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
10CONFIG_SLAB=y
11CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_IOP13XX=y
17CONFIG_MACH_IQ81340SC=y
18CONFIG_MACH_IQ81340MC=y
19CONFIG_ZBOOT_ROM_TEXT=0x0
20CONFIG_ZBOOT_ROM_BSS=0x0
21CONFIG_CMDLINE="ip=bootp root=nfs console=ttyS0,115200 nfsroot=,tcp,v3,wsize=8192,rsize=8192"
22CONFIG_FPE_NWFPE=y
23CONFIG_BINFMT_AOUT=y
24CONFIG_NET=y
25CONFIG_PACKET=y
26CONFIG_UNIX=y
27CONFIG_NET_KEY=y
28CONFIG_INET=y
29CONFIG_IP_MULTICAST=y
30CONFIG_IP_PNP=y
31CONFIG_IP_PNP_BOOTP=y
32CONFIG_IPV6=y
33# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
34# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
35# CONFIG_INET6_XFRM_MODE_BEET is not set
36# CONFIG_IPV6_SIT is not set
37CONFIG_MTD=y
38CONFIG_MTD_REDBOOT_PARTS=y
39CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
40CONFIG_MTD_REDBOOT_PARTS_READONLY=y
41CONFIG_MTD_BLOCK=y
42CONFIG_MTD_CFI=y
43CONFIG_MTD_CFI_ADV_OPTIONS=y
44CONFIG_MTD_CFI_INTELEXT=y
45CONFIG_MTD_PHYSMAP=y
46CONFIG_BLK_DEV_RAM=y
47CONFIG_BLK_DEV_RAM_COUNT=2
48CONFIG_BLK_DEV_RAM_SIZE=8192
49CONFIG_SCSI=y
50CONFIG_BLK_DEV_SD=y
51CONFIG_CHR_DEV_SG=y
52CONFIG_SCSI_CONSTANTS=y
53CONFIG_SCSI_ISCSI_ATTRS=y
54CONFIG_MD=y
55CONFIG_BLK_DEV_MD=y
56CONFIG_MD_RAID0=y
57CONFIG_MD_RAID1=y
58CONFIG_MD_RAID10=y
59CONFIG_MD_RAID456=y
60CONFIG_BLK_DEV_DM=y
61CONFIG_NETDEVICES=y
62CONFIG_E1000=y
63# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
64# CONFIG_INPUT_KEYBOARD is not set
65# CONFIG_INPUT_MOUSE is not set
66# CONFIG_SERIO is not set
67CONFIG_SERIAL_8250=y
68CONFIG_SERIAL_8250_CONSOLE=y
69CONFIG_SERIAL_8250_NR_UARTS=2
70CONFIG_HW_RANDOM=y
71CONFIG_I2C=y
72CONFIG_I2C_IOP3XX=y
73# CONFIG_VGA_CONSOLE is not set
74CONFIG_DMADEVICES=y
75CONFIG_INTEL_IOP_ADMA=y
76CONFIG_EXT2_FS=y
77CONFIG_EXT3_FS=y
78CONFIG_TMPFS=y
79CONFIG_ECRYPT_FS=y
80CONFIG_JFFS2_FS=y
81CONFIG_CRAMFS=y
82CONFIG_NFS_FS=y
83CONFIG_NFS_V3=y
84CONFIG_ROOT_NFS=y
85CONFIG_NFSD=y
86CONFIG_NFSD_V3=y
87CONFIG_SMB_FS=m
88CONFIG_CIFS=m
89CONFIG_PARTITION_ADVANCED=y
90CONFIG_NLS=y
91CONFIG_DEBUG_USER=y
92CONFIG_KEYS=y
93CONFIG_CRYPTO_NULL=y
94CONFIG_CRYPTO_LRW=y
95CONFIG_CRYPTO_PCBC=m
96CONFIG_CRYPTO_HMAC=y
97CONFIG_CRYPTO_XCBC=y
98CONFIG_CRYPTO_MD4=y
99CONFIG_CRYPTO_MICHAEL_MIC=y
100CONFIG_CRYPTO_SHA1=y
101CONFIG_CRYPTO_SHA256=y
102CONFIG_CRYPTO_SHA512=y
103CONFIG_CRYPTO_TGR192=y
104CONFIG_CRYPTO_WP512=y
105CONFIG_CRYPTO_AES=y
106CONFIG_CRYPTO_ANUBIS=y
107CONFIG_CRYPTO_ARC4=y
108CONFIG_CRYPTO_BLOWFISH=y
109CONFIG_CRYPTO_CAST5=y
110CONFIG_CRYPTO_CAST6=y
111CONFIG_CRYPTO_DES=y
112CONFIG_CRYPTO_KHAZAD=y
113CONFIG_CRYPTO_SERPENT=y
114CONFIG_CRYPTO_TEA=y
115CONFIG_CRYPTO_TWOFISH=y
116CONFIG_CRYPTO_DEFLATE=y
117CONFIG_CRC_CCITT=y
118CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
deleted file mode 100644
index 089eca43214a..000000000000
--- a/arch/arm/configs/iop33x_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
1CONFIG_SYSVIPC=y
2CONFIG_BSD_PROCESS_ACCT=y
3CONFIG_LOG_BUF_SHIFT=14
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_KALLSYMS_ALL=y
6CONFIG_SLAB=y
7CONFIG_MODULES=y
8CONFIG_MODULE_UNLOAD=y
9# CONFIG_BLK_DEV_BSG is not set
10CONFIG_ARCH_IOP33X=y
11CONFIG_ARCH_IQ80331=y
12CONFIG_MACH_IQ80332=y
13# CONFIG_ARM_THUMB is not set
14CONFIG_ZBOOT_ROM_TEXT=0x0
15CONFIG_ZBOOT_ROM_BSS=0x0
16CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc iop3xx_init_atu=y"
17CONFIG_FPE_NWFPE=y
18CONFIG_BINFMT_AOUT=y
19CONFIG_NET=y
20CONFIG_PACKET=y
21CONFIG_UNIX=y
22CONFIG_INET=y
23CONFIG_IP_MULTICAST=y
24CONFIG_IP_PNP=y
25CONFIG_IP_PNP_BOOTP=y
26CONFIG_IPV6=y
27# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
28# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
29# CONFIG_INET6_XFRM_MODE_BEET is not set
30# CONFIG_IPV6_SIT is not set
31CONFIG_MTD=y
32CONFIG_MTD_REDBOOT_PARTS=y
33CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
34CONFIG_MTD_REDBOOT_PARTS_READONLY=y
35CONFIG_MTD_BLOCK=y
36CONFIG_MTD_CFI=y
37CONFIG_MTD_CFI_ADV_OPTIONS=y
38CONFIG_MTD_CFI_INTELEXT=y
39CONFIG_MTD_PHYSMAP=y
40CONFIG_BLK_DEV_NBD=y
41CONFIG_BLK_DEV_RAM=y
42CONFIG_BLK_DEV_RAM_SIZE=8192
43CONFIG_SCSI=y
44CONFIG_BLK_DEV_SD=y
45CONFIG_CHR_DEV_SG=y
46CONFIG_MD=y
47CONFIG_BLK_DEV_MD=y
48CONFIG_MD_LINEAR=y
49CONFIG_MD_RAID0=y
50CONFIG_MD_RAID1=y
51CONFIG_MD_RAID456=y
52CONFIG_BLK_DEV_DM=y
53CONFIG_NETDEVICES=y
54CONFIG_E1000=y
55# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
56# CONFIG_INPUT_KEYBOARD is not set
57# CONFIG_INPUT_MOUSE is not set
58# CONFIG_SERIO is not set
59CONFIG_SERIAL_8250=y
60CONFIG_SERIAL_8250_CONSOLE=y
61CONFIG_HW_RANDOM=y
62CONFIG_I2C=y
63CONFIG_I2C_CHARDEV=y
64CONFIG_I2C_IOP3XX=y
65# CONFIG_VGA_CONSOLE is not set
66CONFIG_DMADEVICES=y
67CONFIG_INTEL_IOP_ADMA=y
68CONFIG_NET_DMA=y
69CONFIG_EXT2_FS=y
70CONFIG_EXT3_FS=y
71CONFIG_TMPFS=y
72CONFIG_CRAMFS=y
73CONFIG_NFS_FS=y
74CONFIG_NFS_V3=y
75CONFIG_ROOT_NFS=y
76CONFIG_NFSD=y
77CONFIG_NFSD_V3=y
78CONFIG_PARTITION_ADVANCED=y
79CONFIG_MAGIC_SYSRQ=y
80CONFIG_DEBUG_KERNEL=y
81CONFIG_DEBUG_USER=y
82CONFIG_DEBUG_LL=y
83CONFIG_DEBUG_LL_UART_8250=y
84# CONFIG_CRYPTO_ANSI_CPRNG is not set
85# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
deleted file mode 100644
index c4f04070b4c1..000000000000
--- a/arch/arm/mach-iop13xx/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0
2if ARCH_IOP13XX
3
4menu "IOP13XX Implementation Options"
5
6comment "IOP13XX Platform Support"
7
8config MACH_IQ81340SC
9 bool "Enable IQ81340SC Hardware Support"
10 help
11 Say Y here if you want to support running on the Intel IQ81340SC
12 evaluation kit.
13
14config MACH_IQ81340MC
15 bool "Enable IQ81340MC Hardware Support"
16 help
17 Say Y here if you want to support running on the Intel IQ81340MC
18 evaluation kit.
19
20endmenu
21endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
deleted file mode 100644
index 5757c8f6e371..000000000000
--- a/arch/arm/mach-iop13xx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0
2obj-$(CONFIG_ARCH_IOP13XX) += setup.o
3obj-$(CONFIG_ARCH_IOP13XX) += irq.o
4obj-$(CONFIG_ARCH_IOP13XX) += pci.o
5obj-$(CONFIG_ARCH_IOP13XX) += io.o
6obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o
7obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
8obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
9obj-$(CONFIG_PCI_MSI) += msi.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
deleted file mode 100644
index 4f29554c8401..000000000000
--- a/arch/arm/mach-iop13xx/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0-only
2 zreladdr-y += 0x00008000
3params_phys-y := 0x00000100
4initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h
deleted file mode 100644
index 51d206f5b093..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/adma.h
+++ /dev/null
@@ -1,608 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright(c) 2006, Intel Corporation.
4 */
5#ifndef _ADMA_H
6#define _ADMA_H
7#include <linux/types.h>
8#include <linux/io.h>
9#include <mach/hardware.h>
10#include <asm/hardware/iop_adma.h>
11
12#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
13#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
14#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
15#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
16#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
17#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
18#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
19#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
20#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
21#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
22#define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
23#define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
24#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
25#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
26
27struct iop13xx_adma_src {
28 u32 src_addr;
29 union {
30 u32 upper_src_addr;
31 struct {
32 unsigned int pq_upper_src_addr:24;
33 unsigned int pq_dmlt:8;
34 };
35 };
36};
37
38struct iop13xx_adma_desc_ctrl {
39 unsigned int int_en:1;
40 unsigned int xfer_dir:2;
41 unsigned int src_select:4;
42 unsigned int zero_result:1;
43 unsigned int block_fill_en:1;
44 unsigned int crc_gen_en:1;
45 unsigned int crc_xfer_dis:1;
46 unsigned int crc_seed_fetch_dis:1;
47 unsigned int status_write_back_en:1;
48 unsigned int endian_swap_en:1;
49 unsigned int reserved0:2;
50 unsigned int pq_update_xfer_en:1;
51 unsigned int dual_xor_en:1;
52 unsigned int pq_xfer_en:1;
53 unsigned int p_xfer_dis:1;
54 unsigned int reserved1:10;
55 unsigned int relax_order_en:1;
56 unsigned int no_snoop_en:1;
57};
58
59struct iop13xx_adma_byte_count {
60 unsigned int byte_count:24;
61 unsigned int host_if:3;
62 unsigned int reserved:2;
63 unsigned int zero_result_err_q:1;
64 unsigned int zero_result_err:1;
65 unsigned int tx_complete:1;
66};
67
68struct iop13xx_adma_desc_hw {
69 u32 next_desc;
70 union {
71 u32 desc_ctrl;
72 struct iop13xx_adma_desc_ctrl desc_ctrl_field;
73 };
74 union {
75 u32 crc_addr;
76 u32 block_fill_data;
77 u32 q_dest_addr;
78 };
79 union {
80 u32 byte_count;
81 struct iop13xx_adma_byte_count byte_count_field;
82 };
83 union {
84 u32 dest_addr;
85 u32 p_dest_addr;
86 };
87 union {
88 u32 upper_dest_addr;
89 u32 pq_upper_dest_addr;
90 };
91 struct iop13xx_adma_src src[1];
92};
93
94struct iop13xx_adma_desc_dual_xor {
95 u32 next_desc;
96 u32 desc_ctrl;
97 u32 reserved;
98 u32 byte_count;
99 u32 h_dest_addr;
100 u32 h_upper_dest_addr;
101 u32 src0_addr;
102 u32 upper_src0_addr;
103 u32 src1_addr;
104 u32 upper_src1_addr;
105 u32 h_src_addr;
106 u32 h_upper_src_addr;
107 u32 d_src_addr;
108 u32 d_upper_src_addr;
109 u32 d_dest_addr;
110 u32 d_upper_dest_addr;
111};
112
113struct iop13xx_adma_desc_pq_update {
114 u32 next_desc;
115 u32 desc_ctrl;
116 u32 reserved;
117 u32 byte_count;
118 u32 p_dest_addr;
119 u32 p_upper_dest_addr;
120 u32 src0_addr;
121 u32 upper_src0_addr;
122 u32 src1_addr;
123 u32 upper_src1_addr;
124 u32 p_src_addr;
125 u32 p_upper_src_addr;
126 u32 q_src_addr;
127 struct {
128 unsigned int q_upper_src_addr:24;
129 unsigned int q_dmlt:8;
130 };
131 u32 q_dest_addr;
132 u32 q_upper_dest_addr;
133};
134
135static inline int iop_adma_get_max_xor(void)
136{
137 return 16;
138}
139
140#define iop_adma_get_max_pq iop_adma_get_max_xor
141
142static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
143{
144 return __raw_readl(ADMA_ADAR(chan));
145}
146
147static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
148 u32 next_desc_addr)
149{
150 __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
151}
152
153#define ADMA_STATUS_BUSY (1 << 13)
154
155static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
156{
157 if (__raw_readl(ADMA_ACSR(chan)) &
158 ADMA_STATUS_BUSY)
159 return 1;
160 else
161 return 0;
162}
163
164static inline int
165iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
166{
167 return 1;
168}
169#define iop_desc_is_aligned(x, y) 1
170
171static inline int
172iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
173{
174 *slots_per_op = 1;
175 return 1;
176}
177
178#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
179
180static inline int
181iop_chan_memset_slot_count(size_t len, int *slots_per_op)
182{
183 *slots_per_op = 1;
184 return 1;
185}
186
187static inline int
188iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
189{
190 static const char slot_count_table[] = { 1, 2, 2, 2,
191 2, 3, 3, 3,
192 3, 4, 4, 4,
193 4, 5, 5, 5,
194 };
195 *slots_per_op = slot_count_table[src_cnt - 1];
196 return *slots_per_op;
197}
198
199#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
200#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
201#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
202#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
203#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
204#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
205#define iop_chan_pq_slot_count iop_chan_xor_slot_count
206#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count
207
208static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
209 struct iop_adma_chan *chan)
210{
211 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
212 return hw_desc->byte_count_field.byte_count;
213}
214
215static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
216 struct iop_adma_chan *chan,
217 int src_idx)
218{
219 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
220 return hw_desc->src[src_idx].src_addr;
221}
222
223static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
224 struct iop_adma_chan *chan)
225{
226 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
227 return hw_desc->desc_ctrl_field.src_select + 1;
228}
229
230static inline void
231iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
232{
233 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
234 union {
235 u32 value;
236 struct iop13xx_adma_desc_ctrl field;
237 } u_desc_ctrl;
238
239 u_desc_ctrl.value = 0;
240 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
241 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
242 hw_desc->desc_ctrl = u_desc_ctrl.value;
243 hw_desc->crc_addr = 0;
244}
245
246static inline void
247iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
248{
249 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
250 union {
251 u32 value;
252 struct iop13xx_adma_desc_ctrl field;
253 } u_desc_ctrl;
254
255 u_desc_ctrl.value = 0;
256 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
257 u_desc_ctrl.field.block_fill_en = 1;
258 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
259 hw_desc->desc_ctrl = u_desc_ctrl.value;
260 hw_desc->crc_addr = 0;
261}
262
263/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
264static inline void
265iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
266 unsigned long flags)
267{
268 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
269 union {
270 u32 value;
271 struct iop13xx_adma_desc_ctrl field;
272 } u_desc_ctrl;
273
274 u_desc_ctrl.value = 0;
275 u_desc_ctrl.field.src_select = src_cnt - 1;
276 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
277 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
278 hw_desc->desc_ctrl = u_desc_ctrl.value;
279 hw_desc->crc_addr = 0;
280
281}
282#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
283
284/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
285static inline int
286iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
287 unsigned long flags)
288{
289 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
290 union {
291 u32 value;
292 struct iop13xx_adma_desc_ctrl field;
293 } u_desc_ctrl;
294
295 u_desc_ctrl.value = 0;
296 u_desc_ctrl.field.src_select = src_cnt - 1;
297 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
298 u_desc_ctrl.field.zero_result = 1;
299 u_desc_ctrl.field.status_write_back_en = 1;
300 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
301 hw_desc->desc_ctrl = u_desc_ctrl.value;
302 hw_desc->crc_addr = 0;
303
304 return 1;
305}
306
307static inline void
308iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
309 unsigned long flags)
310{
311 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
312 union {
313 u32 value;
314 struct iop13xx_adma_desc_ctrl field;
315 } u_desc_ctrl;
316
317 u_desc_ctrl.value = 0;
318 u_desc_ctrl.field.src_select = src_cnt - 1;
319 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
320 u_desc_ctrl.field.pq_xfer_en = 1;
321 u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
322 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
323 hw_desc->desc_ctrl = u_desc_ctrl.value;
324}
325
326static inline void
327iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
328 unsigned long flags)
329{
330 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
331 union {
332 u32 value;
333 struct iop13xx_adma_desc_ctrl field;
334 } u_desc_ctrl;
335
336 u_desc_ctrl.value = 0;
337 u_desc_ctrl.field.src_select = src_cnt - 1;
338 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
339 u_desc_ctrl.field.zero_result = 1;
340 u_desc_ctrl.field.status_write_back_en = 1;
341 u_desc_ctrl.field.pq_xfer_en = 1;
342 u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
343 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
344 hw_desc->desc_ctrl = u_desc_ctrl.value;
345}
346
347static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
348 struct iop_adma_chan *chan,
349 u32 byte_count)
350{
351 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
352 hw_desc->byte_count = byte_count;
353}
354
355static inline void
356iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
357{
358 int slots_per_op = desc->slots_per_op;
359 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
360 int i = 0;
361
362 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
363 hw_desc->byte_count = len;
364 } else {
365 do {
366 iter = iop_hw_desc_slot_idx(hw_desc, i);
367 iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
368 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
369 i += slots_per_op;
370 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
371
372 if (len) {
373 iter = iop_hw_desc_slot_idx(hw_desc, i);
374 iter->byte_count = len;
375 }
376 }
377}
378
379#define iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count
380
381static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
382 struct iop_adma_chan *chan,
383 dma_addr_t addr)
384{
385 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
386 hw_desc->dest_addr = addr;
387 hw_desc->upper_dest_addr = 0;
388}
389
390static inline void
391iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr)
392{
393 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
394
395 hw_desc->dest_addr = addr[0];
396 hw_desc->q_dest_addr = addr[1];
397 hw_desc->upper_dest_addr = 0;
398}
399
400static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
401 dma_addr_t addr)
402{
403 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
404 hw_desc->src[0].src_addr = addr;
405 hw_desc->src[0].upper_src_addr = 0;
406}
407
408static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
409 int src_idx, dma_addr_t addr)
410{
411 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
412 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
413 int i = 0;
414
415 do {
416 iter = iop_hw_desc_slot_idx(hw_desc, i);
417 iter->src[src_idx].src_addr = addr;
418 iter->src[src_idx].upper_src_addr = 0;
419 slot_cnt -= slots_per_op;
420 if (slot_cnt) {
421 i += slots_per_op;
422 addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
423 }
424 } while (slot_cnt);
425}
426
427static inline void
428iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
429 dma_addr_t addr, unsigned char coef)
430{
431 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
432 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
433 struct iop13xx_adma_src *src;
434 int i = 0;
435
436 do {
437 iter = iop_hw_desc_slot_idx(hw_desc, i);
438 src = &iter->src[src_idx];
439 src->src_addr = addr;
440 src->pq_upper_src_addr = 0;
441 src->pq_dmlt = coef;
442 slot_cnt -= slots_per_op;
443 if (slot_cnt) {
444 i += slots_per_op;
445 addr += IOP_ADMA_PQ_MAX_BYTE_COUNT;
446 }
447 } while (slot_cnt);
448}
449
450static inline void
451iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
452 struct iop_adma_chan *chan)
453{
454 iop_desc_init_memcpy(desc, 1);
455 iop_desc_set_byte_count(desc, chan, 0);
456 iop_desc_set_dest_addr(desc, chan, 0);
457 iop_desc_set_memcpy_src_addr(desc, 0);
458}
459
460#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
461#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr
462
463static inline void
464iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx,
465 dma_addr_t *src)
466{
467 iop_desc_set_xor_src_addr(desc, pq_idx, src[pq_idx]);
468 iop_desc_set_xor_src_addr(desc, pq_idx+1, src[pq_idx+1]);
469}
470
471static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
472 u32 next_desc_addr)
473{
474 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
475
476 iop_paranoia(hw_desc->next_desc);
477 hw_desc->next_desc = next_desc_addr;
478}
479
480static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
481{
482 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
483 return hw_desc->next_desc;
484}
485
486static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
487{
488 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
489 hw_desc->next_desc = 0;
490}
491
492static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
493 u32 val)
494{
495 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
496 hw_desc->block_fill_data = val;
497}
498
499static inline enum sum_check_flags
500iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
501{
502 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
503 struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
504 struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
505 enum sum_check_flags flags;
506
507 BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
508
509 flags = byte_count.zero_result_err_q << SUM_CHECK_Q;
510 flags |= byte_count.zero_result_err << SUM_CHECK_P;
511
512 return flags;
513}
514
515static inline void iop_chan_append(struct iop_adma_chan *chan)
516{
517 u32 adma_accr;
518
519 adma_accr = __raw_readl(ADMA_ACCR(chan));
520 adma_accr |= 0x2;
521 __raw_writel(adma_accr, ADMA_ACCR(chan));
522}
523
524static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
525{
526 return __raw_readl(ADMA_ACSR(chan));
527}
528
529static inline void iop_chan_disable(struct iop_adma_chan *chan)
530{
531 u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
532 adma_chan_ctrl &= ~0x1;
533 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
534}
535
536static inline void iop_chan_enable(struct iop_adma_chan *chan)
537{
538 u32 adma_chan_ctrl;
539
540 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
541 adma_chan_ctrl |= 0x1;
542 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
543}
544
545static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
546{
547 u32 status = __raw_readl(ADMA_ACSR(chan));
548 status &= (1 << 12);
549 __raw_writel(status, ADMA_ACSR(chan));
550}
551
552static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
553{
554 u32 status = __raw_readl(ADMA_ACSR(chan));
555 status &= (1 << 11);
556 __raw_writel(status, ADMA_ACSR(chan));
557}
558
559static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
560{
561 u32 status = __raw_readl(ADMA_ACSR(chan));
562 status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
563 __raw_writel(status, ADMA_ACSR(chan));
564}
565
566static inline int
567iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
568{
569 return test_bit(9, &status);
570}
571
572static inline int
573iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
574{
575 return test_bit(5, &status);
576}
577
578static inline int
579iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
580{
581 return test_bit(4, &status);
582}
583
584static inline int
585iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
586{
587 return test_bit(3, &status);
588}
589
590static inline int
591iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
592{
593 return 0;
594}
595
596static inline int
597iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
598{
599 return 0;
600}
601
602static inline int
603iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
604{
605 return 0;
606}
607
608#endif /* _ADMA_H */
diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
deleted file mode 100644
index 9f4ecb8861bd..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,29 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * iop13xx low level irq macros
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6 .macro get_irqnr_preamble, base, tmp
7 mrc p15, 0, \tmp, c15, c1, 0
8 orr \tmp, \tmp, #(1 << 6)
9 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
10 .endm
11
12 /*
13 * Note: a 1-cycle window exists where iintvec will return the value
14 * of iintbase, so we explicitly check for "bad zeros"
15 */
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
18 cmp \irqnr, #0
19 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
20 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
21 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 mrc p15, 0, \tmp1, c15, c1, 0
26 ands \tmp2, \tmp1, #(1 << 6)
27 bicne \tmp1, \tmp1, #(1 << 6)
28 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
29 .endm
diff --git a/arch/arm/mach-iop13xx/include/mach/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h
deleted file mode 100644
index 8c943fa6bbd7..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_ARCH_HARDWARE_H
3#define __ASM_ARCH_HARDWARE_H
4#include <asm/types.h>
5
6#ifndef __ASSEMBLY__
7extern u16 iop13xx_dev_id(void);
8extern void iop13xx_set_atu_mmr_bases(void);
9#endif
10
11/*
12 * Generic chipset bits
13 *
14 */
15#include "iop13xx.h"
16
17/*
18 * Board specific bits
19 */
20#include "iq81340.h"
21
22#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
deleted file mode 100644
index 04bb6aca12c5..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ /dev/null
@@ -1,508 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP13XX_HW_H_
3#define _IOP13XX_HW_H_
4
5#ifndef __ASSEMBLY__
6
7enum reboot_mode;
8
9/* The ATU offsets can change based on the strapping */
10extern u32 iop13xx_atux_pmmr_offset;
11extern u32 iop13xx_atue_pmmr_offset;
12void iop13xx_init_early(void);
13void iop13xx_init_irq(void);
14void iop13xx_map_io(void);
15void iop13xx_platform_init(void);
16void iop13xx_add_tpmi_devices(void);
17void iop13xx_init_irq(void);
18void iop13xx_restart(enum reboot_mode, const char *);
19
20/* CPUID CP6 R0 Page 0 */
21static inline int iop13xx_cpu_id(void)
22{
23 int id;
24 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
25 return id;
26}
27
28/* WDTCR CP6 R7 Page 9 */
29static inline u32 read_wdtcr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtcr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
38}
39
40/* WDTSR CP6 R8 Page 9 */
41static inline u32 read_wdtsr(void)
42{
43 u32 val;
44 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
45 return val;
46}
47static inline void write_wdtsr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
50}
51
52/* RCSR - Reset Cause Status Register */
53static inline u32 read_rcsr(void)
54{
55 u32 val;
56 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
57 return val;
58}
59
60extern unsigned long get_iop_tick_rate(void);
61#endif
62
63/*
64 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
65 */
66#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
67#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
68
69/* PCI MAP
70 * bus range cpu phys cpu virt note
71 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
72 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
73 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
74 *
75 * IO MAP
76 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
77 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
78 */
79#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
80#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
81
82#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
83#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
84#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
85#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
86 IOP13XX_PCIX_LOWER_MEM_BA)
87#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
90 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
91
92#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
93#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
94#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
95 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
96#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
97 IOP13XX_PCIX_LOWER_MEM_BA)
98
99/* PCI-E ranges */
100#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
101#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
102
103#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
104#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
105#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
106#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
107 IOP13XX_PCIE_LOWER_MEM_BA)
108#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
109 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
110#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
111 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
112
113/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
114#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
115#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
116#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
119 IOP13XX_PCIE_LOWER_MEM_BA)
120
121/* PBI Ranges */
122#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
123#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
124#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
125#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
126#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
127 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
128
129/*
130 * IOP13XX chipset registers
131 */
132#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
133#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */
134#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
135#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
136 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
137#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
138 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
139#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
140 + IOP13XX_PMMR_PHYS_MEM_BASE)
141#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
142 + IOP13XX_PMMR_VIRT_MEM_BASE)
143#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
144#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
145#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
146#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
147#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
148#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
149#define IOP13XX_PMMR_SIZE 0x00080000
150
151/*=================== Defines for Platform Devices =====================*/
152#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
153#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
154#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
155#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
156
157#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
158#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
159#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
160#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
161#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
162#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
163
164/* ATU selection flags */
165/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
166#define IOP13XX_INIT_ATU_DEFAULT (0)
167#define IOP13XX_INIT_ATU_ATUX (1 << 0)
168#define IOP13XX_INIT_ATU_ATUE (1 << 1)
169#define IOP13XX_INIT_ATU_NONE (1 << 2)
170
171/* UART selection flags */
172/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
173#define IOP13XX_INIT_UART_DEFAULT (0)
174#define IOP13XX_INIT_UART_0 (1 << 0)
175#define IOP13XX_INIT_UART_1 (1 << 1)
176
177/* I2C selection flags */
178/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
179#define IOP13XX_INIT_I2C_DEFAULT (0)
180#define IOP13XX_INIT_I2C_0 (1 << 0)
181#define IOP13XX_INIT_I2C_1 (1 << 1)
182#define IOP13XX_INIT_I2C_2 (1 << 2)
183
184/* ADMA selection flags */
185/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
186#define IOP13XX_INIT_ADMA_DEFAULT (0)
187#define IOP13XX_INIT_ADMA_0 (1 << 0)
188#define IOP13XX_INIT_ADMA_1 (1 << 1)
189#define IOP13XX_INIT_ADMA_2 (1 << 2)
190
191/* Platform devices */
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_NUM_ADMA 3
196#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
197 IQ81340_NUM_I2C + \
198 IQ81340_NUM_PHYS_MAP_FLASH + \
199 IQ81340_NUM_ADMA)
200
201/*========================== PMMR offsets for key registers ============*/
202#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
203#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
204#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
205#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
206#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
207#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
208#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
209#define IOP13XX_MU_PMMR_OFFSET 0x00004000
210#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
211#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
212
213#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
214#define IOP13XX_CONTROLLER_ONLY (1 << 14)
215#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
216
217#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
218#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
219 IOP13XX_PMON_PMMR_OFFSET)
220#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
221 IOP13XX_PMON_PMMR_OFFSET)
222
223#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
224#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
225#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
226#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
227
228#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
229#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
230#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
231#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
232
233#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
234#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
235#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
236#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
237
238#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
239#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
240
241/*================================ATU===================================*/
242#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
243 iop13xx_atux_pmmr_offset + (ofs))
244
245#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x2)
247
248#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
249 iop13xx_atux_pmmr_offset + 0x4)
250#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
251 iop13xx_atux_pmmr_offset + 0x6)
252
253#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
254#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
255#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
256#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
257#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
258#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
259#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
260#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
261#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
262#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
263#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
264#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
265#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
266#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
267#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
268#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
269#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
270#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
271#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
272#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
273#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
274#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
275#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
276#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
277
278#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
279#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
280#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
281#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
282#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
283#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
284#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
285#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
286#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
287#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
288#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
289#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
290#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
291#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
292
293#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
294#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
295#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
296#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
297#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
298#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
299
300#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
301#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
302#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
303#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
304#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
305#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
306#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
307#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
308#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
309#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
310#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
311#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
312#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
313#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
314#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
315#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
316#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
317
318#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
319#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
320#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
321
322#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
323#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
324
325#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
326 iop13xx_atue_pmmr_offset + (ofs))
327
328#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
329 iop13xx_atue_pmmr_offset + 0x2)
330#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
331 iop13xx_atue_pmmr_offset + 0x4)
332#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
333 iop13xx_atue_pmmr_offset + 0x6)
334
335#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
336#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
337#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
338#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
339#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
340#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
341#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
342#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
343#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
344#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
345#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
346#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
347#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
348#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
349#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
350#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
351 iop13xx_atue_pmmr_offset + 0xe2)
352#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
353#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
354#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
355#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
356#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
357#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
358#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
359#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
360#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
361
362#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
363#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
364#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
365#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
366#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
367#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
368
369#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
370#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
371
372#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
373#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
374#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
375#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
376#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
377#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
378#define IOP13XX_ATUE_OCCAR_REG (2)
379
380#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
381#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
382#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
383#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
384#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
385#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
386#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
387
388#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
389#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
391
392#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
393#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
394
395#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
396#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
397#define IOP13XX_ATUE_STAT_PME (1 << 27)
398#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
399#define IOP13XX_ATUE_STAT_IVM (1 << 25)
400#define IOP13XX_ATUE_STAT_BIST (1 << 24)
401#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
402#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
403#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
404#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
405#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
406#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
407#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
408#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
409#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
410#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
411#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
412#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
413#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
414#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
415#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
416#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
417#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
418
419#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
420#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
421#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
422#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
423#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
424#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
425#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
426#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
427#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
428#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
429#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
430#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
431#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
432#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
433#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
434
435#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
436#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
437#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
438#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
439/*=======================================================================*/
440
441/*============================MESSAGING UNIT=============================*/
442#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
443 (ofs))
444
445#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
446#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
447#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
448#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
449#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
450#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
451#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
452#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
453#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
454#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
455#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
456#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
457#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
458#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
459#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
460#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
461
462#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
463#define IOP13XX_MU_BASE_PHYS (0xff000000)
464#define IOP13XX_MU_BASE_PCI (0xff000000)
465#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
466#define IOP13XX_MU_MIMR_CORE_SELECT (15)
467/*=======================================================================*/
468
469/*==============================ADMA UNITS===============================*/
470#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
471#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
472
473/*==============================XSI BRIDGE===============================*/
474#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
475#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
476#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
477#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
478 IOP13XX_PMMR_VIRT_TO_PHYS(\
479 IOP13XX_ATUE_OCCDR))\
480 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
481#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
482 IOP13XX_PMMR_VIRT_TO_PHYS(\
483 IOP13XX_ATUX_OCCDR))\
484 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
485/*=======================================================================*/
486
487#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
488 (ofs))
489
490#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
491#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
492#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
493#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
494#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
495#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
496
497#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
498
499/* Watchdog timer definitions */
500#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
501#define IOP_WDTCR_EN 0xe1e1e1e1
502#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
503#define IOP_WDTCR_DIS 0xf1f1f1f1
504#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
505#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
506#define IOP13XX_WDTCR_IB_RESET (1 << 0)
507
508#endif /* _IOP13XX_HW_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/iq81340.h b/arch/arm/mach-iop13xx/include/mach/iq81340.h
deleted file mode 100644
index d7ad27a95558..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/iq81340.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IQ81340_H_
3#define _IQ81340_H_
4
5#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
6#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
7
8#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
9
10#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
11
12#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
13#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
14#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
15#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
16#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
17#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
18#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
19#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
20#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
21#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
22#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
23#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
24
25#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
26#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
27
28
29#endif /* _IQ81340_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h
deleted file mode 100644
index cd6b6375c050..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/irqs.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP13XX_IRQS_H_
3#define _IOP13XX_IRQS_H_
4
5#ifndef __ASSEMBLER__
6#include <linux/types.h>
7
8/* INTPND0 CP6 R0 Page 3
9 */
10static inline u32 read_intpnd_0(void)
11{
12 u32 val;
13 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
14 return val;
15}
16
17/* INTPND1 CP6 R1 Page 3
18 */
19static inline u32 read_intpnd_1(void)
20{
21 u32 val;
22 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
23 return val;
24}
25
26/* INTPND2 CP6 R2 Page 3
27 */
28static inline u32 read_intpnd_2(void)
29{
30 u32 val;
31 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
32 return val;
33}
34
35/* INTPND3 CP6 R3 Page 3
36 */
37static inline u32 read_intpnd_3(void)
38{
39 u32 val;
40 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
41 return val;
42}
43#endif
44
45#define INTBASE 0
46#define INTSIZE_4 1
47
48/*
49 * iop34x chipset interrupts
50 */
51#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
52
53/*
54 * On IRQ or FIQ register
55 */
56#define IRQ_IOP13XX_ADMA0_EOT (0)
57#define IRQ_IOP13XX_ADMA0_EOC (1)
58#define IRQ_IOP13XX_ADMA1_EOT (2)
59#define IRQ_IOP13XX_ADMA1_EOC (3)
60#define IRQ_IOP13XX_ADMA2_EOT (4)
61#define IRQ_IOP13XX_ADMA2_EOC (5)
62#define IRQ_IOP134_WATCHDOG (6)
63#define IRQ_IOP13XX_RSVD_7 (7)
64#define IRQ_IOP13XX_TIMER0 (8)
65#define IRQ_IOP13XX_TIMER1 (9)
66#define IRQ_IOP13XX_I2C_0 (10)
67#define IRQ_IOP13XX_I2C_1 (11)
68#define IRQ_IOP13XX_MSG (12)
69#define IRQ_IOP13XX_MSGIBQ (13)
70#define IRQ_IOP13XX_ATU_IM (14)
71#define IRQ_IOP13XX_ATU_BIST (15)
72#define IRQ_IOP13XX_PPMU (16)
73#define IRQ_IOP13XX_COREPMU (17)
74#define IRQ_IOP13XX_CORECACHE (18)
75#define IRQ_IOP13XX_RSVD_19 (19)
76#define IRQ_IOP13XX_RSVD_20 (20)
77#define IRQ_IOP13XX_RSVD_21 (21)
78#define IRQ_IOP13XX_RSVD_22 (22)
79#define IRQ_IOP13XX_RSVD_23 (23)
80#define IRQ_IOP13XX_XINT0 (24)
81#define IRQ_IOP13XX_XINT1 (25)
82#define IRQ_IOP13XX_XINT2 (26)
83#define IRQ_IOP13XX_XINT3 (27)
84#define IRQ_IOP13XX_XINT4 (28)
85#define IRQ_IOP13XX_XINT5 (29)
86#define IRQ_IOP13XX_XINT6 (30)
87#define IRQ_IOP13XX_XINT7 (31)
88 /* IINTSRC1 bit */
89#define IRQ_IOP13XX_XINT8 (32) /* 0 */
90#define IRQ_IOP13XX_XINT9 (33) /* 1 */
91#define IRQ_IOP13XX_XINT10 (34) /* 2 */
92#define IRQ_IOP13XX_XINT11 (35) /* 3 */
93#define IRQ_IOP13XX_XINT12 (36) /* 4 */
94#define IRQ_IOP13XX_XINT13 (37) /* 5 */
95#define IRQ_IOP13XX_XINT14 (38) /* 6 */
96#define IRQ_IOP13XX_XINT15 (39) /* 7 */
97#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
98#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
99#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
100#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
101#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
102#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
103#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
104#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
105#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
106#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
107#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
108#define IRQ_IOP13XX_UART0 (51) /* 19 */
109#define IRQ_IOP13XX_UART1 (52) /* 20 */
110#define IRQ_IOP13XX_PBIE (53) /* 21 */
111#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
112#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
113#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
114#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
115#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
116#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
117#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
118#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
119#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
120#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
121 /* IINTSRC2 bit */
122#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
123#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
124#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
125#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
126#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
127#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
128#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
129#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
130#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
131#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
132#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
133#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
134#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
135#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
136#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
137#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
138#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
139#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
140#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
141#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
142#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
143#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
144#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
145#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
146#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
147#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
148#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
149#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
150#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
151#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
152#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
153#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
154 /* IINTSRC3 bit */
155#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
156#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
157#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
158#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
159#define IRQ_IOP13XX_IMU (100) /* 4 */
160#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
161#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
162#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
163#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
164#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
165#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
166#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
167#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
168#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
169#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
170#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
171#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
172#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */
173#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
174#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
175#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
176#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
177#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
178#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
179#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
180#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
181#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
182#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
183#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
184#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
185#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
186#define IRQ_IOP13XX_HPI (127) /* 31 */
187
188#ifdef CONFIG_PCI_MSI
189#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1)
190#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128)
191#else
192#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
193#endif
194
195#endif /* _IOP13XX_IRQ_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
deleted file mode 100644
index 32da0e09c6a3..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_ARCH_MEMORY_H
3#define __ASM_ARCH_MEMORY_H
4
5#include <mach/hardware.h>
6
7#ifndef __ASSEMBLY__
8
9#if defined(CONFIG_ARCH_IOP13XX)
10#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
11#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
12#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
13#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
14
15static inline dma_addr_t __virt_to_lbus(void __iomem *x)
16{
17 return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
18}
19
20static inline void __iomem *__lbus_to_virt(dma_addr_t x)
21{
22 return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
23}
24
25#define __is_lbus_dma(a) \
26 ((a) >= IOP13XX_PMMR_P_START && (a) < IOP13XX_PMMR_P_END)
27
28#define __is_lbus_virt(a) \
29 ((a) >= IOP13XX_PMMR_V_START && (a) < IOP13XX_PMMR_V_END)
30
31/* Device is an lbus device if it is on the platform bus of the IOP13XX */
32#define is_lbus_device(dev) \
33 (dev && strncmp(dev->bus->name, "platform", 8) == 0)
34
35#define __arch_dma_to_virt(dev, addr) \
36 ({ \
37 void * __virt; \
38 dma_addr_t __dma = addr; \
39 if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \
40 __virt = __lbus_to_virt(__dma); \
41 else \
42 __virt = (void *)__phys_to_virt(__dma); \
43 __virt; \
44 })
45
46#define __arch_virt_to_dma(dev, addr) \
47 ({ \
48 void * __virt = addr; \
49 dma_addr_t __dma; \
50 if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \
51 __dma = __virt_to_lbus(__virt); \
52 else \
53 __dma = __virt_to_phys((unsigned long)__virt); \
54 __dma; \
55 })
56
57#define __arch_pfn_to_dma(dev, pfn) \
58 ({ \
59 /* __is_lbus_virt() can never be true for RAM pages */ \
60 (dma_addr_t)__pfn_to_phys(pfn); \
61 })
62
63#define __arch_dma_to_pfn(dev, addr) __phys_to_pfn(addr)
64
65#endif /* CONFIG_ARCH_IOP13XX */
66#endif /* !ASSEMBLY */
67
68#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
deleted file mode 100644
index 2c2d7532d5c3..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/time.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP13XX_TIME_H_
3#define _IOP13XX_TIME_H_
4
5#include <mach/irqs.h>
6
7#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
8
9#define IOP_TMR_EN 0x02
10#define IOP_TMR_RELOAD 0x04
11#define IOP_TMR_PRIVILEGED 0x08
12#define IOP_TMR_RATIO_1_1 0x00
13
14#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
15#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
16#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
17#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
18#define IOP13XX_CORE_FREQ_MASK (7 << 16)
19#define IOP13XX_CORE_FREQ_600 (0 << 16)
20#define IOP13XX_CORE_FREQ_667 (1 << 16)
21#define IOP13XX_CORE_FREQ_800 (2 << 16)
22#define IOP13XX_CORE_FREQ_933 (3 << 16)
23#define IOP13XX_CORE_FREQ_1000 (4 << 16)
24#define IOP13XX_CORE_FREQ_1200 (5 << 16)
25
26void iop_init_time(unsigned long tickrate);
27
28static inline unsigned long iop13xx_core_freq(void)
29{
30 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
31 freq &= IOP13XX_CORE_FREQ_MASK;
32 switch (freq) {
33 case IOP13XX_CORE_FREQ_600:
34 return 600000000;
35 case IOP13XX_CORE_FREQ_667:
36 return 667000000;
37 case IOP13XX_CORE_FREQ_800:
38 return 800000000;
39 case IOP13XX_CORE_FREQ_933:
40 return 933000000;
41 case IOP13XX_CORE_FREQ_1000:
42 return 1000000000;
43 case IOP13XX_CORE_FREQ_1200:
44 return 1200000000;
45 default:
46 printk("%s: warning unknown frequency, defaulting to 800MHz\n",
47 __func__);
48 }
49
50 return 800000000;
51}
52
53static inline unsigned long iop13xx_xsi_bus_ratio(void)
54{
55 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
56 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
57 switch (ratio) {
58 case IOP13XX_XSI_FREQ_RATIO_2:
59 return 2;
60 case IOP13XX_XSI_FREQ_RATIO_3:
61 return 3;
62 case IOP13XX_XSI_FREQ_RATIO_4:
63 return 4;
64 default:
65 printk("%s: warning unknown ratio, defaulting to 2\n",
66 __func__);
67 }
68
69 return 2;
70}
71
72static inline u32 read_tmr0(void)
73{
74 u32 val;
75 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
76 return val;
77}
78
79static inline void write_tmr0(u32 val)
80{
81 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
82}
83
84static inline void write_tmr1(u32 val)
85{
86 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
87}
88
89static inline u32 read_tcr0(void)
90{
91 u32 val;
92 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
93 return val;
94}
95
96static inline void write_tcr0(u32 val)
97{
98 asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
99}
100
101static inline u32 read_tcr1(void)
102{
103 u32 val;
104 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
105 return val;
106}
107
108static inline void write_tcr1(u32 val)
109{
110 asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
111}
112
113static inline void write_trr0(u32 val)
114{
115 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
116}
117
118static inline void write_trr1(u32 val)
119{
120 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
121}
122
123static inline void write_tisr(u32 val)
124{
125 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
126}
127#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h
deleted file mode 100644
index c62903041d11..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#include <asm/types.h>
3#include <linux/serial_reg.h>
4#include <mach/hardware.h>
5
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
8
9static inline void putc(char c)
10{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 barrier();
13 UART_BASE[UART_TX] = c;
14}
15
16static inline void flush(void)
17{
18}
19
20/*
21 * nothing to do
22 */
23#define arch_decomp_setup()
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
deleted file mode 100644
index 253d446b1f3f..000000000000
--- a/arch/arm/mach-iop13xx/io.c
+++ /dev/null
@@ -1,77 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iop13xx custom ioremap implementation
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/io.h>
9#include <mach/hardware.h>
10
11#include "pci.h"
12
13static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
14 size_t size, unsigned int mtype, void *caller)
15{
16 void __iomem * retval;
17
18 switch (cookie) {
19 case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
20 if (unlikely(!iop13xx_atux_mem_base))
21 retval = NULL;
22 else
23 retval = (iop13xx_atux_mem_base +
24 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
25 break;
26 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
27 if (unlikely(!iop13xx_atue_mem_base))
28 retval = NULL;
29 else
30 retval = (iop13xx_atue_mem_base +
31 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
32 break;
33 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
34 retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA +
35 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
36 size, mtype, __builtin_return_address(0));
37 break;
38 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
39 retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
40 break;
41 default:
42 retval = __arm_ioremap_caller(cookie, size, mtype,
43 caller);
44 }
45
46 return retval;
47}
48
49static void __iop13xx_iounmap(volatile void __iomem *addr)
50{
51 if (iop13xx_atue_mem_base)
52 if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
53 addr < (void __iomem *) (iop13xx_atue_mem_base +
54 iop13xx_atue_mem_size))
55 goto skip;
56
57 if (iop13xx_atux_mem_base)
58 if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
59 addr < (void __iomem *) (iop13xx_atux_mem_base +
60 iop13xx_atux_mem_size))
61 goto skip;
62
63 switch ((u32) addr) {
64 case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
65 goto skip;
66 }
67 __iounmap(addr);
68
69skip:
70 return;
71}
72
73void __init iop13xx_init_early(void)
74{
75 arch_ioremap_caller = __iop13xx_ioremap_caller;
76 arch_iounmap = __iop13xx_iounmap;
77}
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
deleted file mode 100644
index b3ce5cb228cc..000000000000
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ /dev/null
@@ -1,84 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iq81340mc board support
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6#include <linux/pci.h>
7
8#include <mach/hardware.h>
9#include <asm/irq.h>
10#include <asm/mach/pci.h>
11#include <asm/mach-types.h>
12#include <asm/mach/arch.h>
13#include "pci.h"
14#include <asm/mach/time.h>
15#include <mach/time.h>
16
17extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
18
19static int __init
20iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
21{
22 switch (idsel) {
23 case 1:
24 switch (pin) {
25 case 1: return ATUX_INTB;
26 case 2: return ATUX_INTC;
27 case 3: return ATUX_INTD;
28 case 4: return ATUX_INTA;
29 default: return -1;
30 }
31 case 2:
32 switch (pin) {
33 case 1: return ATUX_INTC;
34 case 2: return ATUX_INTD;
35 case 3: return ATUX_INTC;
36 case 4: return ATUX_INTD;
37 default: return -1;
38 }
39 default: return -1;
40 }
41}
42
43static struct hw_pci iq81340mc_pci __initdata = {
44 .nr_controllers = 0,
45 .setup = iop13xx_pci_setup,
46 .map_irq = iq81340mc_pcix_map_irq,
47 .scan = iop13xx_scan_bus,
48 .preinit = iop13xx_pci_init,
49};
50
51static int __init iq81340mc_pci_init(void)
52{
53 iop13xx_atu_select(&iq81340mc_pci);
54 pci_common_init(&iq81340mc_pci);
55 iop13xx_map_pci_memory();
56
57 return 0;
58}
59
60static void __init iq81340mc_init(void)
61{
62 iop13xx_platform_init();
63 iq81340mc_pci_init();
64 iop13xx_add_tpmi_devices();
65}
66
67static void __init iq81340mc_timer_init(void)
68{
69 unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
70 printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
71 iop_init_time(bus_freq);
72}
73
74MACHINE_START(IQ81340MC, "Intel IQ81340MC")
75 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
76 .atag_offset = 0x100,
77 .init_early = iop13xx_init_early,
78 .map_io = iop13xx_map_io,
79 .init_irq = iop13xx_init_irq,
80 .init_time = iq81340mc_timer_init,
81 .init_machine = iq81340mc_init,
82 .restart = iop13xx_restart,
83 .nr_irqs = NR_IOP13XX_IRQS,
84MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
deleted file mode 100644
index 123845dcf2d3..000000000000
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ /dev/null
@@ -1,86 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iq81340sc board support
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6#include <linux/pci.h>
7
8#include <mach/hardware.h>
9#include <asm/irq.h>
10#include <asm/mach/pci.h>
11#include <asm/mach-types.h>
12#include <asm/mach/arch.h>
13#include "pci.h"
14#include <asm/mach/time.h>
15#include <mach/time.h>
16
17extern int init_atu;
18
19static int __init
20iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
21{
22 WARN_ON(idsel < 1 || idsel > 2);
23
24 switch (idsel) {
25 case 1:
26 switch (pin) {
27 case 1: return ATUX_INTB;
28 case 2: return ATUX_INTC;
29 case 3: return ATUX_INTD;
30 case 4: return ATUX_INTA;
31 default: return -1;
32 }
33 case 2:
34 switch (pin) {
35 case 1: return ATUX_INTC;
36 case 2: return ATUX_INTC;
37 case 3: return ATUX_INTC;
38 case 4: return ATUX_INTC;
39 default: return -1;
40 }
41 default: return -1;
42 }
43}
44
45static struct hw_pci iq81340sc_pci __initdata = {
46 .nr_controllers = 0,
47 .setup = iop13xx_pci_setup,
48 .scan = iop13xx_scan_bus,
49 .map_irq = iq81340sc_atux_map_irq,
50 .preinit = iop13xx_pci_init
51};
52
53static int __init iq81340sc_pci_init(void)
54{
55 iop13xx_atu_select(&iq81340sc_pci);
56 pci_common_init(&iq81340sc_pci);
57 iop13xx_map_pci_memory();
58
59 return 0;
60}
61
62static void __init iq81340sc_init(void)
63{
64 iop13xx_platform_init();
65 iq81340sc_pci_init();
66 iop13xx_add_tpmi_devices();
67}
68
69static void __init iq81340sc_timer_init(void)
70{
71 unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio();
72 printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq);
73 iop_init_time(bus_freq);
74}
75
76MACHINE_START(IQ81340SC, "Intel IQ81340SC")
77 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
78 .atag_offset = 0x100,
79 .init_early = iop13xx_init_early,
80 .map_io = iop13xx_map_io,
81 .init_irq = iop13xx_init_irq,
82 .init_time = iq81340sc_timer_init,
83 .init_machine = iq81340sc_init,
84 .restart = iop13xx_restart,
85 .nr_irqs = NR_IOP13XX_IRQS,
86MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
deleted file mode 100644
index 0e24ba7a1309..000000000000
--- a/arch/arm/mach-iop13xx/irq.c
+++ /dev/null
@@ -1,227 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iop13xx IRQ handling / support functions
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6#include <linux/init.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/sysctl.h>
10#include <linux/uaccess.h>
11#include <asm/mach/irq.h>
12#include <asm/irq.h>
13#include <mach/hardware.h>
14#include <mach/irqs.h>
15#include "msi.h"
16
17/* INTCTL0 CP6 R0 Page 4
18 */
19static u32 read_intctl_0(void)
20{
21 u32 val;
22 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
23 return val;
24}
25static void write_intctl_0(u32 val)
26{
27 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
28}
29
30/* INTCTL1 CP6 R1 Page 4
31 */
32static u32 read_intctl_1(void)
33{
34 u32 val;
35 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
36 return val;
37}
38static void write_intctl_1(u32 val)
39{
40 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
41}
42
43/* INTCTL2 CP6 R2 Page 4
44 */
45static u32 read_intctl_2(void)
46{
47 u32 val;
48 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
49 return val;
50}
51static void write_intctl_2(u32 val)
52{
53 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
54}
55
56/* INTCTL3 CP6 R3 Page 4
57 */
58static u32 read_intctl_3(void)
59{
60 u32 val;
61 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
62 return val;
63}
64static void write_intctl_3(u32 val)
65{
66 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
67}
68
69/* INTSTR0 CP6 R0 Page 5
70 */
71static void write_intstr_0(u32 val)
72{
73 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
74}
75
76/* INTSTR1 CP6 R1 Page 5
77 */
78static void write_intstr_1(u32 val)
79{
80 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
81}
82
83/* INTSTR2 CP6 R2 Page 5
84 */
85static void write_intstr_2(u32 val)
86{
87 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
88}
89
90/* INTSTR3 CP6 R3 Page 5
91 */
92static void write_intstr_3(u32 val)
93{
94 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
95}
96
97/* INTBASE CP6 R0 Page 2
98 */
99static void write_intbase(u32 val)
100{
101 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
102}
103
104/* INTSIZE CP6 R2 Page 2
105 */
106static void write_intsize(u32 val)
107{
108 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
109}
110
111/* 0 = Interrupt Masked and 1 = Interrupt not masked */
112static void
113iop13xx_irq_mask0 (struct irq_data *d)
114{
115 write_intctl_0(read_intctl_0() & ~(1 << (d->irq - 0)));
116}
117
118static void
119iop13xx_irq_mask1 (struct irq_data *d)
120{
121 write_intctl_1(read_intctl_1() & ~(1 << (d->irq - 32)));
122}
123
124static void
125iop13xx_irq_mask2 (struct irq_data *d)
126{
127 write_intctl_2(read_intctl_2() & ~(1 << (d->irq - 64)));
128}
129
130static void
131iop13xx_irq_mask3 (struct irq_data *d)
132{
133 write_intctl_3(read_intctl_3() & ~(1 << (d->irq - 96)));
134}
135
136static void
137iop13xx_irq_unmask0(struct irq_data *d)
138{
139 write_intctl_0(read_intctl_0() | (1 << (d->irq - 0)));
140}
141
142static void
143iop13xx_irq_unmask1(struct irq_data *d)
144{
145 write_intctl_1(read_intctl_1() | (1 << (d->irq - 32)));
146}
147
148static void
149iop13xx_irq_unmask2(struct irq_data *d)
150{
151 write_intctl_2(read_intctl_2() | (1 << (d->irq - 64)));
152}
153
154static void
155iop13xx_irq_unmask3(struct irq_data *d)
156{
157 write_intctl_3(read_intctl_3() | (1 << (d->irq - 96)));
158}
159
160static struct irq_chip iop13xx_irqchip1 = {
161 .name = "IOP13xx-1",
162 .irq_ack = iop13xx_irq_mask0,
163 .irq_mask = iop13xx_irq_mask0,
164 .irq_unmask = iop13xx_irq_unmask0,
165};
166
167static struct irq_chip iop13xx_irqchip2 = {
168 .name = "IOP13xx-2",
169 .irq_ack = iop13xx_irq_mask1,
170 .irq_mask = iop13xx_irq_mask1,
171 .irq_unmask = iop13xx_irq_unmask1,
172};
173
174static struct irq_chip iop13xx_irqchip3 = {
175 .name = "IOP13xx-3",
176 .irq_ack = iop13xx_irq_mask2,
177 .irq_mask = iop13xx_irq_mask2,
178 .irq_unmask = iop13xx_irq_unmask2,
179};
180
181static struct irq_chip iop13xx_irqchip4 = {
182 .name = "IOP13xx-4",
183 .irq_ack = iop13xx_irq_mask3,
184 .irq_mask = iop13xx_irq_mask3,
185 .irq_unmask = iop13xx_irq_unmask3,
186};
187
188extern void iop_init_cp6_handler(void);
189
190void __init iop13xx_init_irq(void)
191{
192 unsigned int i;
193
194 iop_init_cp6_handler();
195
196 /* disable all interrupts */
197 write_intctl_0(0);
198 write_intctl_1(0);
199 write_intctl_2(0);
200 write_intctl_3(0);
201
202 /* treat all as IRQ */
203 write_intstr_0(0);
204 write_intstr_1(0);
205 write_intstr_2(0);
206 write_intstr_3(0);
207
208 /* initialize the interrupt vector generator */
209 write_intbase(INTBASE);
210 write_intsize(INTSIZE_4);
211
212 for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
213 if (i < 32)
214 irq_set_chip(i, &iop13xx_irqchip1);
215 else if (i < 64)
216 irq_set_chip(i, &iop13xx_irqchip2);
217 else if (i < 96)
218 irq_set_chip(i, &iop13xx_irqchip3);
219 else
220 irq_set_chip(i, &iop13xx_irqchip4);
221
222 irq_set_handler(i, handle_level_irq);
223 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
224 }
225
226 iop13xx_msi_init();
227}
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
deleted file mode 100644
index f4d70cba1dd1..000000000000
--- a/arch/arm/mach-iop13xx/msi.c
+++ /dev/null
@@ -1,152 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-iop13xx/msi.c
4 *
5 * PCI MSI support for the iop13xx processor
6 *
7 * Copyright (c) 2006, Intel Corporation.
8 */
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <asm/mach/irq.h>
12#include <asm/irq.h>
13#include <mach/irqs.h>
14
15/* IMIPR0 CP6 R8 Page 1
16 */
17static u32 read_imipr_0(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
21 return val;
22}
23static void write_imipr_0(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
26}
27
28/* IMIPR1 CP6 R9 Page 1
29 */
30static u32 read_imipr_1(void)
31{
32 u32 val;
33 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
34 return val;
35}
36static void write_imipr_1(u32 val)
37{
38 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
39}
40
41/* IMIPR2 CP6 R10 Page 1
42 */
43static u32 read_imipr_2(void)
44{
45 u32 val;
46 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
47 return val;
48}
49static void write_imipr_2(u32 val)
50{
51 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
52}
53
54/* IMIPR3 CP6 R11 Page 1
55 */
56static u32 read_imipr_3(void)
57{
58 u32 val;
59 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
60 return val;
61}
62static void write_imipr_3(u32 val)
63{
64 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
65}
66
67static u32 (*read_imipr[])(void) = {
68 read_imipr_0,
69 read_imipr_1,
70 read_imipr_2,
71 read_imipr_3,
72};
73
74static void (*write_imipr[])(u32) = {
75 write_imipr_0,
76 write_imipr_1,
77 write_imipr_2,
78 write_imipr_3,
79};
80
81static void iop13xx_msi_handler(struct irq_desc *desc)
82{
83 int i, j;
84 unsigned long status;
85
86 /* read IMIPR registers and find any active interrupts,
87 * then call ISR for each active interrupt
88 */
89 for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
90 status = (read_imipr[i])();
91 if (!status)
92 continue;
93
94 do {
95 j = find_first_bit(&status, 32);
96 (write_imipr[i])(1 << j); /* write back to clear bit */
97 generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
98 status = (read_imipr[i])();
99 } while (status);
100 }
101}
102
103void __init iop13xx_msi_init(void)
104{
105 irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
106}
107
108static void iop13xx_msi_nop(struct irq_data *d)
109{
110 return;
111}
112
113static struct irq_chip iop13xx_msi_chip = {
114 .name = "PCI-MSI",
115 .irq_ack = iop13xx_msi_nop,
116 .irq_enable = pci_msi_unmask_irq,
117 .irq_disable = pci_msi_mask_irq,
118 .irq_mask = pci_msi_mask_irq,
119 .irq_unmask = pci_msi_unmask_irq,
120};
121
122int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
123{
124 int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
125 struct msi_msg msg;
126
127 if (irq < 0)
128 return irq;
129
130 if (irq >= NR_IOP13XX_IRQS) {
131 irq_free_desc(irq);
132 return -ENOSPC;
133 }
134
135 irq_set_msi_desc(irq, desc);
136
137 msg.address_hi = 0x0;
138 msg.address_lo = IOP13XX_MU_MIMR_PCI;
139
140 id = iop13xx_cpu_id();
141 msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
142
143 pci_write_msi_msg(irq, &msg);
144 irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
145
146 return 0;
147}
148
149void arch_teardown_msi_irq(unsigned int irq)
150{
151 irq_free_desc(irq);
152}
diff --git a/arch/arm/mach-iop13xx/msi.h b/arch/arm/mach-iop13xx/msi.h
deleted file mode 100644
index 766dcfaaa353..000000000000
--- a/arch/arm/mach-iop13xx/msi.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP13XX_MSI_H_
3#define _IOP13XX_MSI_H_
4#ifdef CONFIG_PCI_MSI
5void iop13xx_msi_init(void);
6#else
7static inline void iop13xx_msi_init(void)
8{
9 return;
10}
11#endif
12#endif
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
deleted file mode 100644
index 46ea06e906cc..000000000000
--- a/arch/arm/mach-iop13xx/pci.c
+++ /dev/null
@@ -1,1115 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iop13xx PCI support
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6
7#include <linux/pci.h>
8#include <linux/slab.h>
9#include <linux/delay.h>
10#include <linux/jiffies.h>
11#include <linux/export.h>
12#include <asm/irq.h>
13#include <mach/hardware.h>
14#include <linux/sizes.h>
15#include <asm/signal.h>
16#include <asm/mach/pci.h>
17#include "pci.h"
18
19#define IOP13XX_PCI_DEBUG 0
20#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
21
22u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
23u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
24static struct pci_bus *pci_bus_atux = 0;
25static struct pci_bus *pci_bus_atue = 0;
26void __iomem *iop13xx_atue_mem_base;
27void __iomem *iop13xx_atux_mem_base;
28size_t iop13xx_atue_mem_size;
29size_t iop13xx_atux_mem_size;
30
31EXPORT_SYMBOL(iop13xx_atue_mem_base);
32EXPORT_SYMBOL(iop13xx_atux_mem_base);
33EXPORT_SYMBOL(iop13xx_atue_mem_size);
34EXPORT_SYMBOL(iop13xx_atux_mem_size);
35
36int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
37static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
38 access */
39
40/* Scan the initialized busses and ioremap the requested memory range
41 */
42void iop13xx_map_pci_memory(void)
43{
44 int atu;
45 struct pci_bus *bus;
46 struct pci_dev *dev;
47 resource_size_t end = 0;
48
49 for (atu = 0; atu < 2; atu++) {
50 bus = atu ? pci_bus_atue : pci_bus_atux;
51 if (bus) {
52 list_for_each_entry(dev, &bus->devices, bus_list) {
53 int i;
54 int max = 7;
55
56 if (dev->subordinate)
57 max = DEVICE_COUNT_RESOURCE;
58
59 for (i = 0; i < max; i++) {
60 struct resource *res = &dev->resource[i];
61 if (res->flags & IORESOURCE_MEM)
62 end = max(res->end, end);
63 }
64 }
65
66 switch(atu) {
67 case 0:
68 iop13xx_atux_mem_size =
69 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
70
71 /* 16MB align the request */
72 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
73 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
74 iop13xx_atux_mem_size += SZ_16M;
75 }
76
77 if (end) {
78 iop13xx_atux_mem_base = __arm_ioremap_pfn(
79 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
80 , 0, iop13xx_atux_mem_size, MT_DEVICE);
81 if (!iop13xx_atux_mem_base) {
82 printk("%s: atux allocation "
83 "failed\n", __func__);
84 BUG();
85 }
86 } else
87 iop13xx_atux_mem_size = 0;
88 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
89 __func__, atu, iop13xx_atux_mem_size,
90 iop13xx_atux_mem_base);
91 break;
92 case 1:
93 iop13xx_atue_mem_size =
94 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
95
96 /* 16MB align the request */
97 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
98 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
99 iop13xx_atue_mem_size += SZ_16M;
100 }
101
102 if (end) {
103 iop13xx_atue_mem_base = __arm_ioremap_pfn(
104 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
105 , 0, iop13xx_atue_mem_size, MT_DEVICE);
106 if (!iop13xx_atue_mem_base) {
107 printk("%s: atue allocation "
108 "failed\n", __func__);
109 BUG();
110 }
111 } else
112 iop13xx_atue_mem_size = 0;
113 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
114 __func__, atu, iop13xx_atue_mem_size,
115 iop13xx_atue_mem_base);
116 break;
117 }
118
119 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
120 atu ? "ATUE" : "ATUX",
121 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
122 SZ_1M,
123 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
124 IOP13XX_PCIX_LOWER_MEM_RA,
125 atu ? iop13xx_atue_mem_base :
126 iop13xx_atux_mem_base);
127 end = 0;
128 }
129
130 }
131}
132
133static int iop13xx_atu_function(int atu)
134{
135 int func = 0;
136 /* the function number depends on the value of the
137 * IOP13XX_INTERFACE_SEL_PCIX reset strap
138 * see C-Spec section 3.17
139 */
140 switch(atu) {
141 case IOP13XX_INIT_ATU_ATUX:
142 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
143 func = 5;
144 else
145 func = 0;
146 break;
147 case IOP13XX_INIT_ATU_ATUE:
148 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
149 func = 0;
150 else
151 func = 5;
152 break;
153 default:
154 BUG();
155 }
156
157 return func;
158}
159
160/* iop13xx_atux_cfg_address - format a configuration address for atux
161 * @bus: Target bus to access
162 * @devfn: Combined device number and function number
163 * @where: Desired register's address offset
164 *
165 * Convert the parameters to a configuration address formatted
166 * according the PCI-X 2.0 specification
167 */
168static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
169{
170 struct pci_sys_data *sys = bus->sysdata;
171 u32 addr;
172
173 if (sys->busnr == bus->number)
174 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
175 else
176 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
177
178 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
179 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
180
181 return addr;
182}
183
184/* iop13xx_atue_cfg_address - format a configuration address for atue
185 * @bus: Target bus to access
186 * @devfn: Combined device number and function number
187 * @where: Desired register's address offset
188 *
189 * Convert the parameters to an address usable by the ATUE_OCCAR
190 */
191static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
192{
193 struct pci_sys_data *sys = bus->sysdata;
194 u32 addr;
195
196 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
197 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
198 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
199 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
200 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
201 (where & ~0x3);
202
203 if (sys->busnr != bus->number)
204 addr |= 1; /* type 1 access */
205
206 return addr;
207}
208
209/* This routine checks the status of the last configuration cycle. If an error
210 * was detected it returns >0, else it returns a 0. The errors being checked
211 * are parity, master abort, target abort (master and target). These types of
212 * errors occur during a config cycle where there is no device, like during
213 * the discovery stage.
214 */
215static int iop13xx_atux_pci_status(int clear)
216{
217 unsigned int status;
218 int err = 0;
219
220 /*
221 * Check the status registers.
222 */
223 status = __raw_readw(IOP13XX_ATUX_ATUSR);
224 if (status & IOP_PCI_STATUS_ERROR)
225 {
226 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
227 if(clear)
228 __raw_writew(status & IOP_PCI_STATUS_ERROR,
229 IOP13XX_ATUX_ATUSR);
230 err = 1;
231 }
232 status = __raw_readl(IOP13XX_ATUX_ATUISR);
233 if (status & IOP13XX_ATUX_ATUISR_ERROR)
234 {
235 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
236 if(clear)
237 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
238 IOP13XX_ATUX_ATUISR);
239 err = 1;
240 }
241 return err;
242}
243
244/* Simply write the address register and read the configuration
245 * data. Note that the data dependency on %0 encourages an abort
246 * to be detected before we return.
247 */
248static u32 iop13xx_atux_read(unsigned long addr)
249{
250 u32 val;
251
252 __asm__ __volatile__(
253 "str %1, [%2]\n\t"
254 "ldr %0, [%3]\n\t"
255 "mov %0, %0\n\t"
256 : "=r" (val)
257 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
258
259 return val;
260}
261
262/* The read routines must check the error status of the last configuration
263 * cycle. If there was an error, the routine returns all hex f's.
264 */
265static int
266iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
267 int size, u32 *value)
268{
269 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
270 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
271
272 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
273 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
274 IOP13XX_XBG_BECSR);
275 val = 0xffffffff;
276 }
277
278 *value = val;
279
280 return PCIBIOS_SUCCESSFUL;
281}
282
283static int
284iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
285 int size, u32 value)
286{
287 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
288 u32 val;
289
290 if (size != 4) {
291 val = iop13xx_atux_read(addr);
292 if (!iop13xx_atux_pci_status(1) == 0)
293 return PCIBIOS_SUCCESSFUL;
294
295 where = (where & 3) * 8;
296
297 if (size == 1)
298 val &= ~(0xff << where);
299 else
300 val &= ~(0xffff << where);
301
302 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
303 } else {
304 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
305 __raw_writel(value, IOP13XX_ATUX_OCCDR);
306 }
307
308 return PCIBIOS_SUCCESSFUL;
309}
310
311static struct pci_ops iop13xx_atux_ops = {
312 .read = iop13xx_atux_read_config,
313 .write = iop13xx_atux_write_config,
314};
315
316/* This routine checks the status of the last configuration cycle. If an error
317 * was detected it returns >0, else it returns a 0. The errors being checked
318 * are parity, master abort, target abort (master and target). These types of
319 * errors occur during a config cycle where there is no device, like during
320 * the discovery stage.
321 */
322static int iop13xx_atue_pci_status(int clear)
323{
324 unsigned int status;
325 int err = 0;
326
327 /*
328 * Check the status registers.
329 */
330
331 /* standard pci status register */
332 status = __raw_readw(IOP13XX_ATUE_ATUSR);
333 if (status & IOP_PCI_STATUS_ERROR) {
334 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
335 if(clear)
336 __raw_writew(status & IOP_PCI_STATUS_ERROR,
337 IOP13XX_ATUE_ATUSR);
338 err++;
339 }
340
341 /* check the normal status bits in the ATUISR */
342 status = __raw_readl(IOP13XX_ATUE_ATUISR);
343 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
344 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
345 if (clear)
346 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
347 IOP13XX_ATUE_ATUISR);
348 err++;
349
350 /* check the PCI-E status if the ATUISR reports an interface error */
351 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
352 /* get the unmasked errors */
353 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
354 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
355
356 if (status) {
357 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
358 __raw_readl(IOP13XX_ATUE_PIE_STS));
359 err++;
360 } else {
361 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
362 __raw_readl(IOP13XX_ATUE_PIE_STS));
363 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
364 __raw_readl(IOP13XX_ATUE_PIE_MSK));
365 BUG();
366 }
367
368 if(clear)
369 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
370 }
371 }
372
373 return err;
374}
375
376static int
377iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
378{
379 WARN_ON(idsel != 0);
380
381 switch (pin) {
382 case 1: return ATUE_INTA;
383 case 2: return ATUE_INTB;
384 case 3: return ATUE_INTC;
385 case 4: return ATUE_INTD;
386 default: return -1;
387 }
388}
389
390static u32 iop13xx_atue_read(unsigned long addr)
391{
392 u32 val;
393
394 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
395 val = __raw_readl(IOP13XX_ATUE_OCCDR);
396
397 rmb();
398
399 return val;
400}
401
402/* The read routines must check the error status of the last configuration
403 * cycle. If there was an error, the routine returns all hex f's.
404 */
405static int
406iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
407 int size, u32 *value)
408{
409 u32 val;
410 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
411
412 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
413 if (!PCI_SLOT(devfn) || (addr & 1)) {
414 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
415 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
416 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
417 IOP13XX_XBG_BECSR);
418 val = 0xffffffff;
419 }
420
421 PRINTK("addr=%#0lx, val=%#010x", addr, val);
422 } else
423 val = 0xffffffff;
424
425 *value = val;
426
427 return PCIBIOS_SUCCESSFUL;
428}
429
430static int
431iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
432 int size, u32 value)
433{
434 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
435 u32 val;
436
437 if (size != 4) {
438 val = iop13xx_atue_read(addr);
439 if (!iop13xx_atue_pci_status(1) == 0)
440 return PCIBIOS_SUCCESSFUL;
441
442 where = (where & 3) * 8;
443
444 if (size == 1)
445 val &= ~(0xff << where);
446 else
447 val &= ~(0xffff << where);
448
449 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
450 } else {
451 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
452 __raw_writel(value, IOP13XX_ATUE_OCCDR);
453 }
454
455 return PCIBIOS_SUCCESSFUL;
456}
457
458static struct pci_ops iop13xx_atue_ops = {
459 .read = iop13xx_atue_read_config,
460 .write = iop13xx_atue_write_config,
461};
462
463/* When a PCI device does not exist during config cycles, the XScale gets a
464 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
465 * bits to tell us that it was indeed a configuration cycle that caused this
466 * error especially in the case when the ATUE link is down. Instead we rely
467 * on data from the south XSI bridge to validate the abort
468 */
469int
470iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
471{
472 PRINTK("Data abort: address = 0x%08lx "
473 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
474 addr, fsr, regs->ARM_pc, regs->ARM_lr);
475
476 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
477 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
478 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
479
480 /* If it was an imprecise abort, then we need to correct the
481 * return address to be _after_ the instruction.
482 */
483 if (fsr & (1 << 10))
484 regs->ARM_pc += 4;
485
486 if (is_atue_occdr_error() || is_atux_occdr_error())
487 return 0;
488 else
489 return 1;
490}
491
492/* Scan an IOP13XX PCI bus. nr selects which ATU we use.
493 */
494int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge)
495{
496 int which_atu, ret;
497 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
498
499 switch (init_atu) {
500 case IOP13XX_INIT_ATU_ATUX:
501 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
502 break;
503 case IOP13XX_INIT_ATU_ATUE:
504 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
505 break;
506 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
507 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
508 break;
509 default:
510 which_atu = 0;
511 }
512
513 if (!which_atu) {
514 BUG();
515 return -ENODEV;
516 }
517
518 list_splice_init(&sys->resources, &bridge->windows);
519 bridge->dev.parent = NULL;
520 bridge->sysdata = sys;
521 bridge->busnr = sys->busnr;
522
523 switch (which_atu) {
524 case IOP13XX_INIT_ATU_ATUX:
525 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
526 atux_trhfa_timeout)) /* ensure not wrap */
527 while(time_before(jiffies, atux_trhfa_timeout))
528 udelay(100);
529
530 bridge->ops = &iop13xx_atux_ops;
531 ret = pci_scan_root_bus_bridge(bridge);
532 if (!ret)
533 pci_bus_atux = bridge->bus;
534 break;
535 case IOP13XX_INIT_ATU_ATUE:
536 bridge->ops = &iop13xx_atue_ops;
537 ret = pci_scan_root_bus_bridge(bridge);
538 if (!ret)
539 pci_bus_atue = bridge->bus;
540 break;
541 default:
542 ret = -EINVAL;
543 }
544
545 return ret;
546}
547
548/* This function is called from iop13xx_pci_init() after assigning valid
549 * values to iop13xx_atue_pmmr_offset. This is the location for common
550 * setup of ATUE for all IOP13XX implementations.
551 */
552void __init iop13xx_atue_setup(void)
553{
554 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
555 u32 reg_val;
556
557#ifdef CONFIG_PCI_MSI
558 /* BAR 0 (inbound msi window) */
559 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
560 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
561 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
562 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
563#endif
564
565 /* BAR 1 (1:1 mapping with Physical RAM) */
566 /* Set limit and enable */
567 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
568 IOP13XX_ATUE_IALR1);
569 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
570
571 /* Set base at the top of the reserved address space */
572 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
573 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
574
575 /* 1:1 mapping with physical ram
576 * (leave big endian byte swap disabled)
577 */
578 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
579 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
580
581 /* Outbound window 1 (PCIX/PCIE memory window) */
582 /* 32 bit Address Space */
583 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
584 /* PA[35:32] */
585 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
586 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
587 IOP13XX_ATUE_OUMBAR1);
588
589 /* Setup the I/O Bar
590 * A[35-16] in 31-12
591 */
592 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
593 IOP13XX_ATUE_OIOBAR);
594 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
595
596 /* clear startup errors */
597 iop13xx_atue_pci_status(1);
598
599 /* OIOBAR function number
600 */
601 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
602 reg_val &= ~0x7;
603 reg_val |= func;
604 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
605
606 /* OUMBAR function numbers
607 */
608 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
609 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
610 IOP13XX_ATU_OUMBAR_FUNC_NUM);
611 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
612 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
613
614 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
615 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
616 IOP13XX_ATU_OUMBAR_FUNC_NUM);
617 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
618 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
619
620 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
621 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
622 IOP13XX_ATU_OUMBAR_FUNC_NUM);
623 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
624 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
625
626 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
627 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
628 IOP13XX_ATU_OUMBAR_FUNC_NUM);
629 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
630 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
631
632 /* Enable inbound and outbound cycles
633 */
634 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
635 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
636 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
637 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
638
639 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
640 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
641 IOP13XX_ATUE_ATUCR_IVM;
642 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
643}
644
645void __init iop13xx_atue_disable(void)
646{
647 u32 reg_val;
648
649 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
650 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
651
652 /* wait for cycles to quiesce */
653 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
654 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
655 IOP13XX_ATUE_PCSR_LLRB_BUSY))
656 cpu_relax();
657
658 /* BAR 0 ( Disabled ) */
659 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
660 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
661 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
662 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
663 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
664 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
665 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
666 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
667
668 /* BAR 1 ( Disabled ) */
669 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
670 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
671 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
672 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
673 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
674 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
675 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
676 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
677
678 /* BAR 2 ( Disabled ) */
679 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
680 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
681 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
682 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
683 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
684 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
685 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
686 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
687
688 /* BAR 3 ( Disabled ) */
689 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
690 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
691 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
692
693 /* Setup the I/O Bar
694 * A[35-16] in 31-12
695 */
696 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
697 IOP13XX_ATUE_OIOBAR);
698 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
699}
700
701/* This function is called from iop13xx_pci_init() after assigning valid
702 * values to iop13xx_atux_pmmr_offset. This is the location for common
703 * setup of ATUX for all IOP13XX implementations.
704 */
705void __init iop13xx_atux_setup(void)
706{
707 u32 reg_val;
708 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
709
710 /* Take PCI-X bus out of reset if bootloader hasn't already.
711 * According to spec, we should wait for 2^25 PCI clocks to meet
712 * the PCI timing parameter Trhfa (RST# high to first access).
713 * This is rarely necessary and often ignored.
714 */
715 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
716 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
717 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
718 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
719 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
720 IOP13XX_ATUX_PCSR);
721 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
722 }
723 else
724 atux_trhfa_timeout = jiffies;
725
726#ifdef CONFIG_PCI_MSI
727 /* BAR 0 (inbound msi window) */
728 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
729 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
730 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
731 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
732#endif
733
734 /* BAR 1 (1:1 mapping with Physical RAM) */
735 /* Set limit and enable */
736 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
737 IOP13XX_ATUX_IALR1);
738 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
739
740 /* Set base at the top of the reserved address space */
741 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
742 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
743
744 /* 1:1 mapping with physical ram
745 * (leave big endian byte swap disabled)
746 */
747 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
748 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
749
750 /* Outbound window 1 (PCIX/PCIE memory window) */
751 /* 32 bit Address Space */
752 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
753 /* PA[35:32] */
754 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
755 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
756 IOP13XX_ATUX_OUMBAR1);
757
758 /* Setup the I/O Bar
759 * A[35-16] in 31-12
760 */
761 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
762 IOP13XX_ATUX_OIOBAR);
763 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
764
765 /* clear startup errors */
766 iop13xx_atux_pci_status(1);
767
768 /* OIOBAR function number
769 */
770 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
771 reg_val &= ~0x7;
772 reg_val |= func;
773 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
774
775 /* OUMBAR function numbers
776 */
777 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
778 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
779 IOP13XX_ATU_OUMBAR_FUNC_NUM);
780 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
781 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
782
783 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
784 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
785 IOP13XX_ATU_OUMBAR_FUNC_NUM);
786 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
787 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
788
789 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
790 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
791 IOP13XX_ATU_OUMBAR_FUNC_NUM);
792 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
793 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
794
795 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
796 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
797 IOP13XX_ATU_OUMBAR_FUNC_NUM);
798 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
799 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
800
801 /* Enable inbound and outbound cycles
802 */
803 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
804 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
805 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
806 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
807
808 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
809 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
810 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
811}
812
813void __init iop13xx_atux_disable(void)
814{
815 u32 reg_val;
816
817 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
818 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
819
820 /* wait for cycles to quiesce */
821 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
822 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
823 cpu_relax();
824
825 /* BAR 0 ( Disabled ) */
826 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
827 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
828 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
829 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
830 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
831 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
832 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
833 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
834
835 /* BAR 1 ( Disabled ) */
836 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
837 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
838 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
839 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
840 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
841 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
842 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
843 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
844
845 /* BAR 2 ( Disabled ) */
846 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
847 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
848 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
849 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
850 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
851 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
852 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
853 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
854
855 /* BAR 3 ( Disabled ) */
856 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
857 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
858 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
859 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
860 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
861 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
862 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
863 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
864
865 /* Setup the I/O Bar
866 * A[35-16] in 31-12
867 */
868 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
869 IOP13XX_ATUX_OIOBAR);
870 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
871}
872
873void __init iop13xx_set_atu_mmr_bases(void)
874{
875 /* Based on ESSR0, determine the ATU X/E offsets */
876 switch(__raw_readl(IOP13XX_ESSR0) &
877 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
878 /* both asserted */
879 case 0:
880 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
881 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
882 break;
883 /* IOP13XX_CONTROLLER_ONLY = deasserted
884 * IOP13XX_INTERFACE_SEL_PCIX = asserted
885 */
886 case IOP13XX_CONTROLLER_ONLY:
887 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
888 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 break;
890 /* IOP13XX_CONTROLLER_ONLY = asserted
891 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
892 */
893 case IOP13XX_INTERFACE_SEL_PCIX:
894 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
895 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
896 break;
897 /* both deasserted */
898 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
899 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
900 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
901 break;
902 default:
903 BUG();
904 }
905}
906
907void __init iop13xx_atu_select(struct hw_pci *plat_pci)
908{
909 int i;
910
911 /* set system defaults
912 * note: if "iop13xx_init_atu=" is specified this autodetect
913 * sequence will be bypassed
914 */
915 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
916 /* check for single/dual interface */
917 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
918 /* ATUE must be present check the device id
919 * to see if ATUX is present.
920 */
921 init_atu |= IOP13XX_INIT_ATU_ATUE;
922 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
923 case 0x70:
924 case 0x80:
925 case 0xc0:
926 init_atu |= IOP13XX_INIT_ATU_ATUX;
927 break;
928 }
929 } else {
930 /* ATUX must be present check the device id
931 * to see if ATUE is present.
932 */
933 init_atu |= IOP13XX_INIT_ATU_ATUX;
934 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
935 case 0x70:
936 case 0x80:
937 case 0xc0:
938 init_atu |= IOP13XX_INIT_ATU_ATUE;
939 break;
940 }
941 }
942
943 /* check central resource and root complex capability */
944 if (init_atu & IOP13XX_INIT_ATU_ATUX)
945 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
946 IOP13XX_ATUX_PCSR_CENTRAL_RES))
947 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
948
949 if (init_atu & IOP13XX_INIT_ATU_ATUE)
950 if (__raw_readl(IOP13XX_ATUE_PCSR) &
951 IOP13XX_ATUE_PCSR_END_POINT)
952 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
953 }
954
955 for (i = 0; i < 2; i++) {
956 if((init_atu & (1 << i)) == (1 << i))
957 plat_pci->nr_controllers++;
958 }
959}
960
961void __init iop13xx_pci_init(void)
962{
963 /* clear pre-existing south bridge errors */
964 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
965
966 /* Setup the Min Address for PCI memory... */
967 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
968
969 /* if Linux is given control of an ATU
970 * clear out its prior configuration,
971 * otherwise do not touch the registers
972 */
973 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
974 iop13xx_atue_disable();
975 iop13xx_atue_setup();
976 }
977
978 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
979 iop13xx_atux_disable();
980 iop13xx_atux_setup();
981 }
982
983 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
984 "imprecise external abort");
985}
986
987/* initialize the pci memory space. handle any combination of
988 * atue and atux enabled/disabled
989 */
990int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
991{
992 struct resource *res;
993 int which_atu;
994 u32 pcixsr, pcsr;
995
996 if (nr > 1)
997 return 0;
998
999 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1000 if (!res)
1001 panic("PCI: unable to alloc resources");
1002
1003
1004 /* 'nr' assumptions:
1005 * ATUX is always 0
1006 * ATUE is 1 when ATUX is also enabled
1007 * ATUE is 0 when ATUX is disabled
1008 */
1009 switch(init_atu) {
1010 case IOP13XX_INIT_ATU_ATUX:
1011 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1012 break;
1013 case IOP13XX_INIT_ATU_ATUE:
1014 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1015 break;
1016 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1017 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1018 break;
1019 default:
1020 which_atu = 0;
1021 }
1022
1023 if (!which_atu) {
1024 kfree(res);
1025 return 0;
1026 }
1027
1028 switch(which_atu) {
1029 case IOP13XX_INIT_ATU_ATUX:
1030 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1031 pcixsr &= ~0xffff;
1032 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1033 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1034 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1035 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1036 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1037
1038 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1039
1040 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1041 res->end = IOP13XX_PCIX_UPPER_MEM_RA;
1042 res->name = "IQ81340 ATUX PCI Memory Space";
1043 res->flags = IORESOURCE_MEM;
1044 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1045 break;
1046 case IOP13XX_INIT_ATU_ATUE:
1047 /* Note: the function number field in the PCSR is ro */
1048 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1049 pcsr &= ~(0xfff8 << 16);
1050 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1051 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1052
1053 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1054
1055 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1056
1057 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1058 res->end = IOP13XX_PCIE_UPPER_MEM_RA;
1059 res->name = "IQ81340 ATUE PCI Memory Space";
1060 res->flags = IORESOURCE_MEM;
1061 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1062 sys->map_irq = iop13xx_pcie_map_irq;
1063 break;
1064 default:
1065 kfree(res);
1066 return 0;
1067 }
1068
1069 request_resource(&iomem_resource, res);
1070
1071 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1072
1073 return 1;
1074}
1075
1076u16 iop13xx_dev_id(void)
1077{
1078 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1079 return __raw_readw(IOP13XX_ATUE_DID);
1080 else
1081 return __raw_readw(IOP13XX_ATUX_DID);
1082}
1083
1084static int __init iop13xx_init_atu_setup(char *str)
1085{
1086 init_atu = IOP13XX_INIT_ATU_NONE;
1087 if (str) {
1088 while (*str != '\0') {
1089 switch (*str) {
1090 case 'x':
1091 case 'X':
1092 init_atu |= IOP13XX_INIT_ATU_ATUX;
1093 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1094 break;
1095 case 'e':
1096 case 'E':
1097 init_atu |= IOP13XX_INIT_ATU_ATUE;
1098 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1099 break;
1100 case ',':
1101 case '=':
1102 break;
1103 default:
1104 PRINTK("\"iop13xx_init_atu\" malformed at "
1105 "character: \'%c\'", *str);
1106 *(str + 1) = '\0';
1107 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1108 }
1109 str++;
1110 }
1111 }
1112 return 1;
1113}
1114
1115__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
deleted file mode 100644
index 736168d8c7ac..000000000000
--- a/arch/arm/mach-iop13xx/pci.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP13XX_PCI_H_
3#define _IOP13XX_PCI_H_
4#include <linux/io.h>
5#include <mach/irqs.h>
6
7#include <linux/types.h>
8
9extern void __iomem *iop13xx_atue_mem_base;
10extern void __iomem *iop13xx_atux_mem_base;
11extern size_t iop13xx_atue_mem_size;
12extern size_t iop13xx_atux_mem_size;
13
14struct pci_sys_data;
15struct pci_host_bridge;
16struct hw_pci;
17int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
18int iop13xx_scan_bus(int nr, struct pci_host_bridge *bridge);
19void iop13xx_atu_select(struct hw_pci *plat_pci);
20void iop13xx_pci_init(void);
21void iop13xx_map_pci_memory(void);
22
23#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
24 PCI_STATUS_SIG_TARGET_ABORT | \
25 PCI_STATUS_REC_TARGET_ABORT | \
26 PCI_STATUS_REC_TARGET_ABORT | \
27 PCI_STATUS_REC_MASTER_ABORT | \
28 PCI_STATUS_SIG_SYSTEM_ERROR | \
29 PCI_STATUS_DETECTED_PARITY)
30
31#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
32 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
33 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
34 IOP13XX_ATUE_STAT_ERR_COR | \
35 IOP13XX_ATUE_STAT_ERR_UNCOR | \
36 IOP13XX_ATUE_STAT_CRS | \
37 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
39 IOP13XX_ATUE_STAT_SIG_TABORT | \
40 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
41 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
42
43#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
44 IOP13XX_ATUX_STAT_REC_SCEM | \
45 IOP13XX_ATUX_STAT_TX_SERR | \
46 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
47 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
48 IOP13XX_ATUX_STAT_REC_SERR | \
49 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
50 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
51 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
52 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
53
54/* PCI interrupts
55 */
56#define ATUX_INTA IRQ_IOP13XX_XINT0
57#define ATUX_INTB IRQ_IOP13XX_XINT1
58#define ATUX_INTC IRQ_IOP13XX_XINT2
59#define ATUX_INTD IRQ_IOP13XX_XINT3
60
61#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
62#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
63#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
64#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
65
66#endif /* _IOP13XX_PCI_H_ */
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
deleted file mode 100644
index c5c84c9ec9ee..000000000000
--- a/arch/arm/mach-iop13xx/setup.c
+++ /dev/null
@@ -1,595 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iop13xx platform Initialization
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6
7#include <linux/dma-mapping.h>
8#include <linux/serial_8250.h>
9#include <linux/io.h>
10#include <linux/reboot.h>
11#ifdef CONFIG_MTD_PHYSMAP
12#include <linux/mtd/physmap.h>
13#endif
14#include <asm/mach/map.h>
15#include <mach/hardware.h>
16#include <asm/irq.h>
17#include <asm/hardware/iop_adma.h>
18#include <mach/irqs.h>
19
20#define IOP13XX_UART_XTAL 33334000
21#define IOP13XX_SETUP_DEBUG 0
22#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
23
24/* Standard IO mapping for all IOP13XX based systems
25 */
26static struct map_desc iop13xx_std_desc[] __initdata = {
27 { /* mem mapped registers */
28 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
29 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
30 .length = IOP13XX_PMMR_SIZE,
31 .type = MT_DEVICE,
32 },
33};
34
35static struct resource iop13xx_uart0_resources[] = {
36 [0] = {
37 .start = IOP13XX_UART0_PHYS,
38 .end = IOP13XX_UART0_PHYS + 0x3f,
39 .flags = IORESOURCE_MEM,
40 },
41 [1] = {
42 .start = IRQ_IOP13XX_UART0,
43 .end = IRQ_IOP13XX_UART0,
44 .flags = IORESOURCE_IRQ
45 }
46};
47
48static struct resource iop13xx_uart1_resources[] = {
49 [0] = {
50 .start = IOP13XX_UART1_PHYS,
51 .end = IOP13XX_UART1_PHYS + 0x3f,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = IRQ_IOP13XX_UART1,
56 .end = IRQ_IOP13XX_UART1,
57 .flags = IORESOURCE_IRQ
58 }
59};
60
61static struct plat_serial8250_port iop13xx_uart0_data[] = {
62 {
63 .membase = IOP13XX_UART0_VIRT,
64 .mapbase = IOP13XX_UART0_PHYS,
65 .irq = IRQ_IOP13XX_UART0,
66 .uartclk = IOP13XX_UART_XTAL,
67 .regshift = 2,
68 .iotype = UPIO_MEM,
69 .flags = UPF_SKIP_TEST,
70 },
71 { },
72};
73
74static struct plat_serial8250_port iop13xx_uart1_data[] = {
75 {
76 .membase = IOP13XX_UART1_VIRT,
77 .mapbase = IOP13XX_UART1_PHYS,
78 .irq = IRQ_IOP13XX_UART1,
79 .uartclk = IOP13XX_UART_XTAL,
80 .regshift = 2,
81 .iotype = UPIO_MEM,
82 .flags = UPF_SKIP_TEST,
83 },
84 { },
85};
86
87/* The ids are fixed up later in iop13xx_platform_init */
88static struct platform_device iop13xx_uart0 = {
89 .name = "serial8250",
90 .id = 0,
91 .dev.platform_data = iop13xx_uart0_data,
92 .num_resources = 2,
93 .resource = iop13xx_uart0_resources,
94};
95
96static struct platform_device iop13xx_uart1 = {
97 .name = "serial8250",
98 .id = 0,
99 .dev.platform_data = iop13xx_uart1_data,
100 .num_resources = 2,
101 .resource = iop13xx_uart1_resources
102};
103
104static struct resource iop13xx_i2c_0_resources[] = {
105 [0] = {
106 .start = IOP13XX_I2C0_PHYS,
107 .end = IOP13XX_I2C0_PHYS + 0x18,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = IRQ_IOP13XX_I2C_0,
112 .end = IRQ_IOP13XX_I2C_0,
113 .flags = IORESOURCE_IRQ
114 }
115};
116
117static struct resource iop13xx_i2c_1_resources[] = {
118 [0] = {
119 .start = IOP13XX_I2C1_PHYS,
120 .end = IOP13XX_I2C1_PHYS + 0x18,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = IRQ_IOP13XX_I2C_1,
125 .end = IRQ_IOP13XX_I2C_1,
126 .flags = IORESOURCE_IRQ
127 }
128};
129
130static struct resource iop13xx_i2c_2_resources[] = {
131 [0] = {
132 .start = IOP13XX_I2C2_PHYS,
133 .end = IOP13XX_I2C2_PHYS + 0x18,
134 .flags = IORESOURCE_MEM,
135 },
136 [1] = {
137 .start = IRQ_IOP13XX_I2C_2,
138 .end = IRQ_IOP13XX_I2C_2,
139 .flags = IORESOURCE_IRQ
140 }
141};
142
143/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
144 * we just use the same device name.
145 */
146
147/* The ids are fixed up later in iop13xx_platform_init */
148static struct platform_device iop13xx_i2c_0_controller = {
149 .name = "IOP3xx-I2C",
150 .id = 0,
151 .num_resources = 2,
152 .resource = iop13xx_i2c_0_resources
153};
154
155static struct platform_device iop13xx_i2c_1_controller = {
156 .name = "IOP3xx-I2C",
157 .id = 0,
158 .num_resources = 2,
159 .resource = iop13xx_i2c_1_resources
160};
161
162static struct platform_device iop13xx_i2c_2_controller = {
163 .name = "IOP3xx-I2C",
164 .id = 0,
165 .num_resources = 2,
166 .resource = iop13xx_i2c_2_resources
167};
168
169#ifdef CONFIG_MTD_PHYSMAP
170/* PBI Flash Device
171 */
172static struct physmap_flash_data iq8134x_flash_data = {
173 .width = 2,
174};
175
176static struct resource iq8134x_flash_resource = {
177 .start = IQ81340_FLASHBASE,
178 .end = 0,
179 .flags = IORESOURCE_MEM,
180};
181
182static struct platform_device iq8134x_flash = {
183 .name = "physmap-flash",
184 .id = 0,
185 .dev = { .platform_data = &iq8134x_flash_data, },
186 .num_resources = 1,
187 .resource = &iq8134x_flash_resource,
188};
189
190static unsigned long iq8134x_probe_flash_size(void)
191{
192 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
193 int i;
194 char query[3];
195 unsigned long size = 0;
196 int width = iq8134x_flash_data.width;
197
198 if (flash_addr) {
199 /* send CFI 'query' command */
200 writew(0x98, flash_addr);
201
202 /* check for CFI compliance */
203 for (i = 0; i < 3 * width; i += width)
204 query[i / width] = readb(flash_addr + (0x10 * width) + i);
205
206 /* read the size */
207 if (memcmp(query, "QRY", 3) == 0)
208 size = 1 << readb(flash_addr + (0x27 * width));
209
210 /* send CFI 'read array' command */
211 writew(0xff, flash_addr);
212
213 iounmap(flash_addr);
214 }
215
216 return size;
217}
218#endif
219
220/* ADMA Channels */
221static struct resource iop13xx_adma_0_resources[] = {
222 [0] = {
223 .start = IOP13XX_ADMA_PHYS_BASE(0),
224 .end = IOP13XX_ADMA_UPPER_PA(0),
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = IRQ_IOP13XX_ADMA0_EOT,
229 .end = IRQ_IOP13XX_ADMA0_EOT,
230 .flags = IORESOURCE_IRQ
231 },
232 [2] = {
233 .start = IRQ_IOP13XX_ADMA0_EOC,
234 .end = IRQ_IOP13XX_ADMA0_EOC,
235 .flags = IORESOURCE_IRQ
236 },
237 [3] = {
238 .start = IRQ_IOP13XX_ADMA0_ERR,
239 .end = IRQ_IOP13XX_ADMA0_ERR,
240 .flags = IORESOURCE_IRQ
241 }
242};
243
244static struct resource iop13xx_adma_1_resources[] = {
245 [0] = {
246 .start = IOP13XX_ADMA_PHYS_BASE(1),
247 .end = IOP13XX_ADMA_UPPER_PA(1),
248 .flags = IORESOURCE_MEM,
249 },
250 [1] = {
251 .start = IRQ_IOP13XX_ADMA1_EOT,
252 .end = IRQ_IOP13XX_ADMA1_EOT,
253 .flags = IORESOURCE_IRQ
254 },
255 [2] = {
256 .start = IRQ_IOP13XX_ADMA1_EOC,
257 .end = IRQ_IOP13XX_ADMA1_EOC,
258 .flags = IORESOURCE_IRQ
259 },
260 [3] = {
261 .start = IRQ_IOP13XX_ADMA1_ERR,
262 .end = IRQ_IOP13XX_ADMA1_ERR,
263 .flags = IORESOURCE_IRQ
264 }
265};
266
267static struct resource iop13xx_adma_2_resources[] = {
268 [0] = {
269 .start = IOP13XX_ADMA_PHYS_BASE(2),
270 .end = IOP13XX_ADMA_UPPER_PA(2),
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = IRQ_IOP13XX_ADMA2_EOT,
275 .end = IRQ_IOP13XX_ADMA2_EOT,
276 .flags = IORESOURCE_IRQ
277 },
278 [2] = {
279 .start = IRQ_IOP13XX_ADMA2_EOC,
280 .end = IRQ_IOP13XX_ADMA2_EOC,
281 .flags = IORESOURCE_IRQ
282 },
283 [3] = {
284 .start = IRQ_IOP13XX_ADMA2_ERR,
285 .end = IRQ_IOP13XX_ADMA2_ERR,
286 .flags = IORESOURCE_IRQ
287 }
288};
289
290static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32);
291static struct iop_adma_platform_data iop13xx_adma_0_data = {
292 .hw_id = 0,
293 .pool_size = PAGE_SIZE,
294};
295
296static struct iop_adma_platform_data iop13xx_adma_1_data = {
297 .hw_id = 1,
298 .pool_size = PAGE_SIZE,
299};
300
301static struct iop_adma_platform_data iop13xx_adma_2_data = {
302 .hw_id = 2,
303 .pool_size = PAGE_SIZE,
304};
305
306/* The ids are fixed up later in iop13xx_platform_init */
307static struct platform_device iop13xx_adma_0_channel = {
308 .name = "iop-adma",
309 .id = 0,
310 .num_resources = 4,
311 .resource = iop13xx_adma_0_resources,
312 .dev = {
313 .dma_mask = &iop13xx_adma_dmamask,
314 .coherent_dma_mask = DMA_BIT_MASK(32),
315 .platform_data = (void *) &iop13xx_adma_0_data,
316 },
317};
318
319static struct platform_device iop13xx_adma_1_channel = {
320 .name = "iop-adma",
321 .id = 0,
322 .num_resources = 4,
323 .resource = iop13xx_adma_1_resources,
324 .dev = {
325 .dma_mask = &iop13xx_adma_dmamask,
326 .coherent_dma_mask = DMA_BIT_MASK(32),
327 .platform_data = (void *) &iop13xx_adma_1_data,
328 },
329};
330
331static struct platform_device iop13xx_adma_2_channel = {
332 .name = "iop-adma",
333 .id = 0,
334 .num_resources = 4,
335 .resource = iop13xx_adma_2_resources,
336 .dev = {
337 .dma_mask = &iop13xx_adma_dmamask,
338 .coherent_dma_mask = DMA_BIT_MASK(32),
339 .platform_data = (void *) &iop13xx_adma_2_data,
340 },
341};
342
343void __init iop13xx_map_io(void)
344{
345 /* Initialize the Static Page Table maps */
346 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
347}
348
349static int init_uart;
350static int init_i2c;
351static int init_adma;
352
353void __init iop13xx_platform_init(void)
354{
355 int i;
356 u32 uart_idx, i2c_idx, adma_idx, plat_idx;
357 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
358
359 /* set the bases so we can read the device id */
360 iop13xx_set_atu_mmr_bases();
361
362 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
363
364 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
365 switch (iop13xx_dev_id()) {
366 /* enable both uarts on iop341 */
367 case 0x3380:
368 case 0x3384:
369 case 0x3388:
370 case 0x338c:
371 init_uart |= IOP13XX_INIT_UART_0;
372 init_uart |= IOP13XX_INIT_UART_1;
373 break;
374 /* only enable uart 1 */
375 default:
376 init_uart |= IOP13XX_INIT_UART_1;
377 }
378 }
379
380 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
381 switch (iop13xx_dev_id()) {
382 /* enable all i2c units on iop341 and iop342 */
383 case 0x3380:
384 case 0x3384:
385 case 0x3388:
386 case 0x338c:
387 case 0x3382:
388 case 0x3386:
389 case 0x338a:
390 case 0x338e:
391 init_i2c |= IOP13XX_INIT_I2C_0;
392 init_i2c |= IOP13XX_INIT_I2C_1;
393 init_i2c |= IOP13XX_INIT_I2C_2;
394 break;
395 /* only enable i2c 1 and 2 */
396 default:
397 init_i2c |= IOP13XX_INIT_I2C_1;
398 init_i2c |= IOP13XX_INIT_I2C_2;
399 }
400 }
401
402 if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
403 init_adma |= IOP13XX_INIT_ADMA_0;
404 init_adma |= IOP13XX_INIT_ADMA_1;
405 init_adma |= IOP13XX_INIT_ADMA_2;
406 }
407
408 plat_idx = 0;
409 uart_idx = 0;
410 i2c_idx = 0;
411
412 /* uart 1 (if enabled) is ttyS0 */
413 if (init_uart & IOP13XX_INIT_UART_1) {
414 PRINTK("Adding uart1 to platform device list\n");
415 iop13xx_uart1.id = uart_idx++;
416 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
417 }
418 if (init_uart & IOP13XX_INIT_UART_0) {
419 PRINTK("Adding uart0 to platform device list\n");
420 iop13xx_uart0.id = uart_idx++;
421 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
422 }
423
424 for(i = 0; i < IQ81340_NUM_I2C; i++) {
425 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
426 printk("Adding i2c%d to platform device list\n", i);
427 switch(init_i2c & (1 << i)) {
428 case IOP13XX_INIT_I2C_0:
429 iop13xx_i2c_0_controller.id = i2c_idx++;
430 iop13xx_devices[plat_idx++] =
431 &iop13xx_i2c_0_controller;
432 break;
433 case IOP13XX_INIT_I2C_1:
434 iop13xx_i2c_1_controller.id = i2c_idx++;
435 iop13xx_devices[plat_idx++] =
436 &iop13xx_i2c_1_controller;
437 break;
438 case IOP13XX_INIT_I2C_2:
439 iop13xx_i2c_2_controller.id = i2c_idx++;
440 iop13xx_devices[plat_idx++] =
441 &iop13xx_i2c_2_controller;
442 break;
443 }
444 }
445
446 /* initialize adma channel ids and capabilities */
447 adma_idx = 0;
448 for (i = 0; i < IQ81340_NUM_ADMA; i++) {
449 struct iop_adma_platform_data *plat_data;
450 if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
451 printk(KERN_INFO
452 "Adding adma%d to platform device list\n", i);
453 switch (init_adma & (1 << i)) {
454 case IOP13XX_INIT_ADMA_0:
455 iop13xx_adma_0_channel.id = adma_idx++;
456 iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
457 plat_data = &iop13xx_adma_0_data;
458 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
459 dma_cap_set(DMA_XOR, plat_data->cap_mask);
460 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
461 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
462 break;
463 case IOP13XX_INIT_ADMA_1:
464 iop13xx_adma_1_channel.id = adma_idx++;
465 iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
466 plat_data = &iop13xx_adma_1_data;
467 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
468 dma_cap_set(DMA_XOR, plat_data->cap_mask);
469 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
470 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
471 break;
472 case IOP13XX_INIT_ADMA_2:
473 iop13xx_adma_2_channel.id = adma_idx++;
474 iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
475 plat_data = &iop13xx_adma_2_data;
476 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
477 dma_cap_set(DMA_XOR, plat_data->cap_mask);
478 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
479 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
480 dma_cap_set(DMA_PQ, plat_data->cap_mask);
481 dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
482 break;
483 }
484 }
485
486#ifdef CONFIG_MTD_PHYSMAP
487 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
488 iq8134x_probe_flash_size() - 1;
489 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
490 iop13xx_devices[plat_idx++] = &iq8134x_flash;
491 else
492 printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
493#endif
494
495 platform_add_devices(iop13xx_devices, plat_idx);
496}
497
498static int __init iop13xx_init_uart_setup(char *str)
499{
500 if (str) {
501 while (*str != '\0') {
502 switch(*str) {
503 case '0':
504 init_uart |= IOP13XX_INIT_UART_0;
505 break;
506 case '1':
507 init_uart |= IOP13XX_INIT_UART_1;
508 break;
509 case ',':
510 case '=':
511 break;
512 default:
513 PRINTK("\"iop13xx_init_uart\" malformed"
514 " at character: \'%c\'", *str);
515 *(str + 1) = '\0';
516 init_uart = IOP13XX_INIT_UART_DEFAULT;
517 }
518 str++;
519 }
520 }
521 return 1;
522}
523
524static int __init iop13xx_init_i2c_setup(char *str)
525{
526 if (str) {
527 while (*str != '\0') {
528 switch(*str) {
529 case '0':
530 init_i2c |= IOP13XX_INIT_I2C_0;
531 break;
532 case '1':
533 init_i2c |= IOP13XX_INIT_I2C_1;
534 break;
535 case '2':
536 init_i2c |= IOP13XX_INIT_I2C_2;
537 break;
538 case ',':
539 case '=':
540 break;
541 default:
542 PRINTK("\"iop13xx_init_i2c\" malformed"
543 " at character: \'%c\'", *str);
544 *(str + 1) = '\0';
545 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
546 }
547 str++;
548 }
549 }
550 return 1;
551}
552
553static int __init iop13xx_init_adma_setup(char *str)
554{
555 if (str) {
556 while (*str != '\0') {
557 switch (*str) {
558 case '0':
559 init_adma |= IOP13XX_INIT_ADMA_0;
560 break;
561 case '1':
562 init_adma |= IOP13XX_INIT_ADMA_1;
563 break;
564 case '2':
565 init_adma |= IOP13XX_INIT_ADMA_2;
566 break;
567 case ',':
568 case '=':
569 break;
570 default:
571 PRINTK("\"iop13xx_init_adma\" malformed"
572 " at character: \'%c\'", *str);
573 *(str + 1) = '\0';
574 init_adma = IOP13XX_INIT_ADMA_DEFAULT;
575 }
576 str++;
577 }
578 }
579 return 1;
580}
581
582__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
583__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
584__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
585
586void iop13xx_restart(enum reboot_mode mode, const char *cmd)
587{
588 /*
589 * Reset the internal bus (warning both cores are reset)
590 */
591 write_wdtcr(IOP_WDTCR_EN_ARM);
592 write_wdtcr(IOP_WDTCR_EN);
593 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
594 write_wdtcr(0x1000);
595}
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c
deleted file mode 100644
index 4f916549e381..000000000000
--- a/arch/arm/mach-iop13xx/tpmi.c
+++ /dev/null
@@ -1,244 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * iop13xx tpmi device resources
4 * Copyright (c) 2005-2006, Intel Corporation.
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/dma-mapping.h>
11#include <linux/io.h>
12#include <asm/irq.h>
13#include <linux/sizes.h>
14#include <mach/irqs.h>
15
16/* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
17#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
18#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
19#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
20#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
21#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
22#define IOP13XX_TPMI_MEM_SIZE (255)
23#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
24#define IOP13XX_TPMI_RESOURCE_MMR 0
25#define IOP13XX_TPMI_RESOURCE_MEM 1
26#define IOP13XX_TPMI_RESOURCE_CTRL 2
27#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
28#define IOP13XX_TPMI_RESOURCE_IRQ 4
29
30static struct resource iop13xx_tpmi_0_resources[] = {
31 [IOP13XX_TPMI_RESOURCE_MMR] = {
32 .start = IOP13XX_TPMI_MMR(4), /* tpmi0 starts at dev == 4 */
33 .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
34 .flags = IORESOURCE_MEM,
35 },
36 [IOP13XX_TPMI_RESOURCE_MEM] = {
37 .start = IOP13XX_TPMI_MEM(0),
38 .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
39 .flags = IORESOURCE_MEM,
40 },
41 [IOP13XX_TPMI_RESOURCE_CTRL] = {
42 .start = IOP13XX_TPMI_CTRL(0),
43 .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
44 .flags = IORESOURCE_MEM,
45 },
46 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
47 .start = IOP13XX_TPMI_IOP_CTRL(0),
48 .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
49 .flags = IORESOURCE_MEM,
50 },
51 [IOP13XX_TPMI_RESOURCE_IRQ] = {
52 .start = IRQ_IOP13XX_TPMI0_OUT,
53 .end = IRQ_IOP13XX_TPMI0_OUT,
54 .flags = IORESOURCE_IRQ
55 }
56};
57
58static struct resource iop13xx_tpmi_1_resources[] = {
59 [IOP13XX_TPMI_RESOURCE_MMR] = {
60 .start = IOP13XX_TPMI_MMR(1),
61 .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
62 .flags = IORESOURCE_MEM,
63 },
64 [IOP13XX_TPMI_RESOURCE_MEM] = {
65 .start = IOP13XX_TPMI_MEM(1),
66 .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
67 .flags = IORESOURCE_MEM,
68 },
69 [IOP13XX_TPMI_RESOURCE_CTRL] = {
70 .start = IOP13XX_TPMI_CTRL(1),
71 .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
72 .flags = IORESOURCE_MEM,
73 },
74 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
75 .start = IOP13XX_TPMI_IOP_CTRL(1),
76 .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
77 .flags = IORESOURCE_MEM,
78 },
79 [IOP13XX_TPMI_RESOURCE_IRQ] = {
80 .start = IRQ_IOP13XX_TPMI1_OUT,
81 .end = IRQ_IOP13XX_TPMI1_OUT,
82 .flags = IORESOURCE_IRQ
83 }
84};
85
86static struct resource iop13xx_tpmi_2_resources[] = {
87 [IOP13XX_TPMI_RESOURCE_MMR] = {
88 .start = IOP13XX_TPMI_MMR(2),
89 .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
90 .flags = IORESOURCE_MEM,
91 },
92 [IOP13XX_TPMI_RESOURCE_MEM] = {
93 .start = IOP13XX_TPMI_MEM(2),
94 .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
95 .flags = IORESOURCE_MEM,
96 },
97 [IOP13XX_TPMI_RESOURCE_CTRL] = {
98 .start = IOP13XX_TPMI_CTRL(2),
99 .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
100 .flags = IORESOURCE_MEM,
101 },
102 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
103 .start = IOP13XX_TPMI_IOP_CTRL(2),
104 .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
105 .flags = IORESOURCE_MEM,
106 },
107 [IOP13XX_TPMI_RESOURCE_IRQ] = {
108 .start = IRQ_IOP13XX_TPMI2_OUT,
109 .end = IRQ_IOP13XX_TPMI2_OUT,
110 .flags = IORESOURCE_IRQ
111 }
112};
113
114static struct resource iop13xx_tpmi_3_resources[] = {
115 [IOP13XX_TPMI_RESOURCE_MMR] = {
116 .start = IOP13XX_TPMI_MMR(3),
117 .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
118 .flags = IORESOURCE_MEM,
119 },
120 [IOP13XX_TPMI_RESOURCE_MEM] = {
121 .start = IOP13XX_TPMI_MEM(3),
122 .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
123 .flags = IORESOURCE_MEM,
124 },
125 [IOP13XX_TPMI_RESOURCE_CTRL] = {
126 .start = IOP13XX_TPMI_CTRL(3),
127 .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
128 .flags = IORESOURCE_MEM,
129 },
130 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
131 .start = IOP13XX_TPMI_IOP_CTRL(3),
132 .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
133 .flags = IORESOURCE_MEM,
134 },
135 [IOP13XX_TPMI_RESOURCE_IRQ] = {
136 .start = IRQ_IOP13XX_TPMI3_OUT,
137 .end = IRQ_IOP13XX_TPMI3_OUT,
138 .flags = IORESOURCE_IRQ
139 }
140};
141
142u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32);
143static struct platform_device iop13xx_tpmi_0_device = {
144 .name = "iop-tpmi",
145 .id = 0,
146 .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
147 .resource = iop13xx_tpmi_0_resources,
148 .dev = {
149 .dma_mask = &iop13xx_tpmi_mask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
151 },
152};
153
154static struct platform_device iop13xx_tpmi_1_device = {
155 .name = "iop-tpmi",
156 .id = 1,
157 .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
158 .resource = iop13xx_tpmi_1_resources,
159 .dev = {
160 .dma_mask = &iop13xx_tpmi_mask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163};
164
165static struct platform_device iop13xx_tpmi_2_device = {
166 .name = "iop-tpmi",
167 .id = 2,
168 .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
169 .resource = iop13xx_tpmi_2_resources,
170 .dev = {
171 .dma_mask = &iop13xx_tpmi_mask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
173 },
174};
175
176static struct platform_device iop13xx_tpmi_3_device = {
177 .name = "iop-tpmi",
178 .id = 3,
179 .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
180 .resource = iop13xx_tpmi_3_resources,
181 .dev = {
182 .dma_mask = &iop13xx_tpmi_mask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187__init void iop13xx_add_tpmi_devices(void)
188{
189 unsigned short device_id;
190
191 /* tpmi's not present on iop341 or iop342 */
192 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
193 /* ATUE must be present */
194 device_id = __raw_readw(IOP13XX_ATUE_DID);
195 else
196 /* ATUX must be present */
197 device_id = __raw_readw(IOP13XX_ATUX_DID);
198
199 switch (device_id) {
200 /* iop34[1|2] 0-tpmi */
201 case 0x3380:
202 case 0x3384:
203 case 0x3388:
204 case 0x338c:
205 case 0x3382:
206 case 0x3386:
207 case 0x338a:
208 case 0x338e:
209 return;
210 /* iop348 1-tpmi */
211 case 0x3310:
212 case 0x3312:
213 case 0x3314:
214 case 0x3318:
215 case 0x331a:
216 case 0x331c:
217 case 0x33c0:
218 case 0x33c2:
219 case 0x33c4:
220 case 0x33c8:
221 case 0x33ca:
222 case 0x33cc:
223 case 0x33b0:
224 case 0x33b2:
225 case 0x33b4:
226 case 0x33b8:
227 case 0x33ba:
228 case 0x33bc:
229 case 0x3320:
230 case 0x3322:
231 case 0x3324:
232 case 0x3328:
233 case 0x332a:
234 case 0x332c:
235 platform_device_register(&iop13xx_tpmi_0_device);
236 return;
237 default:
238 platform_device_register(&iop13xx_tpmi_0_device);
239 platform_device_register(&iop13xx_tpmi_1_device);
240 platform_device_register(&iop13xx_tpmi_2_device);
241 platform_device_register(&iop13xx_tpmi_3_device);
242 return;
243 }
244}
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
deleted file mode 100644
index cd6069c7c568..000000000000
--- a/arch/arm/mach-iop33x/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0-only
2if ARCH_IOP33X
3
4menu "IOP33x Implementation Options"
5
6comment "IOP33x Platform Types"
7
8config ARCH_IQ80331
9 bool "Enable support for IQ80331"
10 help
11 Say Y here if you want to run your kernel on the Intel IQ80331
12 evaluation kit for the IOP331 chipset.
13
14config MACH_IQ80332
15 bool "Enable support for IQ80332"
16 help
17 Say Y here if you want to run your kernel on the Intel IQ80332
18 evaluation kit for the IOP332 chipset.
19
20endmenu
21
22endif
diff --git a/arch/arm/mach-iop33x/Makefile b/arch/arm/mach-iop33x/Makefile
deleted file mode 100644
index 320ecde1f907..000000000000
--- a/arch/arm/mach-iop33x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Makefile for the linux kernel.
4#
5
6obj-y := irq.o uart.o
7
8obj-$(CONFIG_ARCH_IQ80331) += iq80331.o
9obj-$(CONFIG_MACH_IQ80332) += iq80332.o
diff --git a/arch/arm/mach-iop33x/Makefile.boot b/arch/arm/mach-iop33x/Makefile.boot
deleted file mode 100644
index e4dd1d26038f..000000000000
--- a/arch/arm/mach-iop33x/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
1# SPDX-License-Identifier: GPL-2.0-only
2 zreladdr-y += 0x00008000
3params_phys-y := 0x00000100
4initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop33x/include/mach/adma.h b/arch/arm/mach-iop33x/include/mach/adma.h
deleted file mode 100644
index 8aa7159ab6d8..000000000000
--- a/arch/arm/mach-iop33x/include/mach/adma.h
+++ /dev/null
@@ -1,6 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef IOP33X_ADMA_H
3#define IOP33X_ADMA_H
4#include <asm/hardware/iop3xx-adma.h>
5#endif
6
diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S
deleted file mode 100644
index 0a398fe1fba4..000000000000
--- a/arch/arm/mach-iop33x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP33x-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#include <mach/iop33x.h>
11
12 .macro get_irqnr_preamble, base, tmp
13 mrc p15, 0, \tmp, c15, c1, 0
14 orr \tmp, \tmp, #(1 << 6)
15 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
16 mrc p15, 0, \tmp, c15, c1, 0
17 mov \tmp, \tmp
18 sub pc, pc, #4 @ cp_wait
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
23 cmp \irqstat, #0
24 mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
25 adds \irqnr, \irqstat, #1
26 movne \irqnr, \irqstat, lsr #2
27 .endm
28
29 .macro arch_ret_to_user, tmp1, tmp2
30 mrc p15, 0, \tmp1, c15, c1, 0
31 ands \tmp2, \tmp1, #(1 << 6)
32 bicne \tmp1, \tmp1, #(1 << 6)
33 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
34 .endm
diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h
deleted file mode 100644
index 020bafbc36a5..000000000000
--- a/arch/arm/mach-iop33x/include/mach/hardware.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * arch/arm/mach-iop33x/include/mach/hardware.h
4 */
5
6#ifndef __HARDWARE_H
7#define __HARDWARE_H
8
9#include <asm/types.h>
10
11/*
12 * Note about PCI IO space mappings
13 *
14 * To make IO space accesses efficient, we store virtual addresses in
15 * the IO resources.
16 *
17 * The PCI IO space is located at virtual 0xfe000000 from physical
18 * 0x90000000. The PCI BARs must be programmed with physical addresses,
19 * but when we read them, we convert them to virtual addresses. See
20 * arch/arm/mach-iop3xx/iop3xx-pci.c
21 */
22
23#ifndef __ASSEMBLY__
24void iop33x_init_irq(void);
25
26extern struct platform_device iop33x_uart0_device;
27extern struct platform_device iop33x_uart1_device;
28#endif
29
30
31/*
32 * Generic chipset bits
33 *
34 */
35#include "iop33x.h"
36
37/*
38 * Board specific bits
39 */
40#include "iq80331.h"
41#include "iq80332.h"
42
43
44#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iop33x.h b/arch/arm/mach-iop33x/include/mach/iop33x.h
deleted file mode 100644
index 0c7041ed7a60..000000000000
--- a/arch/arm/mach-iop33x/include/mach/iop33x.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/mach-iop33x/include/mach/iop33x.h
4 *
5 * Intel IOP33X Chip definitions
6 *
7 * Author: Dave Jiang (dave.jiang@intel.com)
8 * Copyright (C) 2003, 2004 Intel Corp.
9 */
10
11#ifndef __IOP33X_H
12#define __IOP33X_H
13
14/*
15 * Peripherals that are shared between the iop32x and iop33x but
16 * located at different addresses.
17 */
18#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
19
20#include <asm/hardware/iop3xx.h>
21
22/* UARTs */
23#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
24#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
25#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
26#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
27
28/* ATU Parameters
29 * set up a 1:1 bus to physical ram relationship
30 * w/ pci on top of physical ram in memory map
31 */
32#define IOP33X_MAX_RAM_SIZE 0x80000000UL
33#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
34#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
35
36
37#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80331.h b/arch/arm/mach-iop33x/include/mach/iq80331.h
deleted file mode 100644
index c7e68d863e44..000000000000
--- a/arch/arm/mach-iop33x/include/mach/iq80331.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * arch/arm/mach-iop33x/include/mach/iq80331.h
4 *
5 * Intel IQ80331 evaluation board registers
6 */
7
8#ifndef __IQ80331_H
9#define __IQ80331_H
10
11#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
12#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
13#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
14#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
15
16
17#endif
diff --git a/arch/arm/mach-iop33x/include/mach/iq80332.h b/arch/arm/mach-iop33x/include/mach/iq80332.h
deleted file mode 100644
index 749b44bf7f62..000000000000
--- a/arch/arm/mach-iop33x/include/mach/iq80332.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * arch/arm/mach-iop33x/include/mach/iq80332.h
4 *
5 * Intel IQ80332 evaluation board registers
6 */
7
8#ifndef __IQ80332_H
9#define __IQ80332_H
10
11#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
12#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
13#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
14#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
15
16
17#endif
diff --git a/arch/arm/mach-iop33x/include/mach/irqs.h b/arch/arm/mach-iop33x/include/mach/irqs.h
deleted file mode 100644
index cc3dce0ad4a1..000000000000
--- a/arch/arm/mach-iop33x/include/mach/irqs.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/mach-iop33x/include/mach/irqs.h
4 *
5 * Author: Dave Jiang (dave.jiang@intel.com)
6 * Copyright: (C) 2003 Intel Corp.
7 */
8
9#ifndef __IRQS_H
10#define __IRQS_H
11
12/*
13 * IOP80331 chipset interrupts
14 */
15#define IRQ_IOP33X_DMA0_EOT 0
16#define IRQ_IOP33X_DMA0_EOC 1
17#define IRQ_IOP33X_DMA1_EOT 2
18#define IRQ_IOP33X_DMA1_EOC 3
19#define IRQ_IOP33X_AA_EOT 6
20#define IRQ_IOP33X_AA_EOC 7
21#define IRQ_IOP33X_TIMER0 8
22#define IRQ_IOP33X_TIMER1 9
23#define IRQ_IOP33X_I2C_0 10
24#define IRQ_IOP33X_I2C_1 11
25#define IRQ_IOP33X_MSG 12
26#define IRQ_IOP33X_MSGIBQ 13
27#define IRQ_IOP33X_ATU_BIST 14
28#define IRQ_IOP33X_PERFMON 15
29#define IRQ_IOP33X_CORE_PMU 16
30#define IRQ_IOP33X_XINT0 24
31#define IRQ_IOP33X_XINT1 25
32#define IRQ_IOP33X_XINT2 26
33#define IRQ_IOP33X_XINT3 27
34#define IRQ_IOP33X_XINT8 32
35#define IRQ_IOP33X_XINT9 33
36#define IRQ_IOP33X_XINT10 34
37#define IRQ_IOP33X_XINT11 35
38#define IRQ_IOP33X_XINT12 36
39#define IRQ_IOP33X_XINT13 37
40#define IRQ_IOP33X_XINT14 38
41#define IRQ_IOP33X_XINT15 39
42#define IRQ_IOP33X_UART0 51
43#define IRQ_IOP33X_UART1 52
44#define IRQ_IOP33X_PBIE 53
45#define IRQ_IOP33X_ATU_CRW 54
46#define IRQ_IOP33X_ATU_ERR 55
47#define IRQ_IOP33X_MCU_ERR 56
48#define IRQ_IOP33X_DMA0_ERR 57
49#define IRQ_IOP33X_DMA1_ERR 58
50#define IRQ_IOP33X_AA_ERR 60
51#define IRQ_IOP33X_MSG_ERR 62
52#define IRQ_IOP33X_HPI 63
53
54#define NR_IRQS 64
55
56
57#endif
diff --git a/arch/arm/mach-iop33x/include/mach/time.h b/arch/arm/mach-iop33x/include/mach/time.h
deleted file mode 100644
index 801f8fd644ad..000000000000
--- a/arch/arm/mach-iop33x/include/mach/time.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _IOP33X_TIME_H_
3#define _IOP33X_TIME_H_
4#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
5#endif
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
deleted file mode 100644
index 62b71cde1f79..000000000000
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * arch/arm/mach-iop33x/include/mach/uncompress.h
4 */
5
6#include <asm/types.h>
7#include <asm/mach-types.h>
8#include <linux/serial_reg.h>
9#include <mach/hardware.h>
10
11volatile u32 *uart_base;
12
13#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
14
15static inline void putc(char c)
16{
17 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
18 barrier();
19 uart_base[UART_TX] = c;
20}
21
22static inline void flush(void)
23{
24}
25
26static __inline__ void __arch_decomp_setup(unsigned long arch_id)
27{
28 if (machine_is_iq80331() || machine_is_iq80332())
29 uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
30 else
31 uart_base = (volatile u32 *)0xfe800000;
32}
33
34/*
35 * nothing to do
36 */
37#define arch_decomp_setup() __arch_decomp_setup(arch_id)
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
deleted file mode 100644
index ab74fbabc749..000000000000
--- a/arch/arm/mach-iop33x/iq80331.c
+++ /dev/null
@@ -1,148 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/arm/mach-iop33x/iq80331.c
4 *
5 * Board support code for the Intel IQ80331 platform.
6 *
7 * Author: Dave Jiang <dave.jiang@intel.com>
8 * Copyright (C) 2003 Intel Corp.
9 */
10
11#include <linux/mm.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/string.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/mtd/physmap.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <mach/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/pci.h>
26#include <asm/mach/time.h>
27#include <asm/mach-types.h>
28#include <asm/page.h>
29#include <asm/pgtable.h>
30#include <mach/time.h>
31
32/*
33 * IQ80331 timer tick configuration.
34 */
35static void __init iq80331_timer_init(void)
36{
37 /* D-Step parts run at a higher internal bus frequency */
38 if (*IOP3XX_ATURID >= 0xa)
39 iop_init_time(333000000);
40 else
41 iop_init_time(266000000);
42}
43
44
45/*
46 * IQ80331 PCI.
47 */
48static int __init
49iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
50{
51 int irq;
52
53 if (slot == 1 && pin == 1) {
54 /* PCI-X Slot INTA */
55 irq = IRQ_IOP33X_XINT1;
56 } else if (slot == 1 && pin == 2) {
57 /* PCI-X Slot INTB */
58 irq = IRQ_IOP33X_XINT2;
59 } else if (slot == 1 && pin == 3) {
60 /* PCI-X Slot INTC */
61 irq = IRQ_IOP33X_XINT3;
62 } else if (slot == 1 && pin == 4) {
63 /* PCI-X Slot INTD */
64 irq = IRQ_IOP33X_XINT0;
65 } else if (slot == 2) {
66 /* GigE */
67 irq = IRQ_IOP33X_XINT2;
68 } else {
69 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
70 "device PCI:%d:%d:%d\n", dev->bus->number,
71 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
72 irq = -1;
73 }
74
75 return irq;
76}
77
78static struct hw_pci iq80331_pci __initdata = {
79 .nr_controllers = 1,
80 .ops = &iop3xx_ops,
81 .setup = iop3xx_pci_setup,
82 .preinit = iop3xx_pci_preinit_cond,
83 .map_irq = iq80331_pci_map_irq,
84};
85
86static int __init iq80331_pci_init(void)
87{
88 if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
89 machine_is_iq80331())
90 pci_common_init(&iq80331_pci);
91
92 return 0;
93}
94
95subsys_initcall(iq80331_pci_init);
96
97
98/*
99 * IQ80331 machine initialisation.
100 */
101static struct physmap_flash_data iq80331_flash_data = {
102 .width = 1,
103};
104
105static struct resource iq80331_flash_resource = {
106 .start = 0xc0000000,
107 .end = 0xc07fffff,
108 .flags = IORESOURCE_MEM,
109};
110
111static struct platform_device iq80331_flash_device = {
112 .name = "physmap-flash",
113 .id = 0,
114 .dev = {
115 .platform_data = &iq80331_flash_data,
116 },
117 .num_resources = 1,
118 .resource = &iq80331_flash_resource,
119};
120
121static struct resource iq80331_gpio_res[] = {
122 DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
123};
124
125static void __init iq80331_init_machine(void)
126{
127 platform_device_register_simple("gpio-iop", 0,
128 iq80331_gpio_res,
129 ARRAY_SIZE(iq80331_gpio_res));
130 platform_device_register(&iop3xx_i2c0_device);
131 platform_device_register(&iop3xx_i2c1_device);
132 platform_device_register(&iop33x_uart0_device);
133 platform_device_register(&iop33x_uart1_device);
134 platform_device_register(&iq80331_flash_device);
135 platform_device_register(&iop3xx_dma_0_channel);
136 platform_device_register(&iop3xx_dma_1_channel);
137 platform_device_register(&iop3xx_aau_channel);
138}
139
140MACHINE_START(IQ80331, "Intel IQ80331")
141 /* Maintainer: Intel Corp. */
142 .atag_offset = 0x100,
143 .map_io = iop3xx_map_io,
144 .init_irq = iop33x_init_irq,
145 .init_time = iq80331_timer_init,
146 .init_machine = iq80331_init_machine,
147 .restart = iop3xx_restart,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
deleted file mode 100644
index 2e309b197aa4..000000000000
--- a/arch/arm/mach-iop33x/iq80332.c
+++ /dev/null
@@ -1,148 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/arm/mach-iop33x/iq80332.c
4 *
5 * Board support code for the Intel IQ80332 platform.
6 *
7 * Author: Dave Jiang <dave.jiang@intel.com>
8 * Copyright (C) 2004 Intel Corp.
9 */
10
11#include <linux/mm.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/string.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/mtd/physmap.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <mach/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/pci.h>
26#include <asm/mach/time.h>
27#include <asm/mach-types.h>
28#include <asm/page.h>
29#include <asm/pgtable.h>
30#include <mach/time.h>
31
32/*
33 * IQ80332 timer tick configuration.
34 */
35static void __init iq80332_timer_init(void)
36{
37 /* D-Step parts and the iop333 run at a higher internal bus frequency */
38 if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
39 iop_init_time(333000000);
40 else
41 iop_init_time(266000000);
42}
43
44
45/*
46 * IQ80332 PCI.
47 */
48static int __init
49iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
50{
51 int irq;
52
53 if (slot == 4 && pin == 1) {
54 /* PCI-X Slot INTA */
55 irq = IRQ_IOP33X_XINT0;
56 } else if (slot == 4 && pin == 2) {
57 /* PCI-X Slot INTB */
58 irq = IRQ_IOP33X_XINT1;
59 } else if (slot == 4 && pin == 3) {
60 /* PCI-X Slot INTC */
61 irq = IRQ_IOP33X_XINT2;
62 } else if (slot == 4 && pin == 4) {
63 /* PCI-X Slot INTD */
64 irq = IRQ_IOP33X_XINT3;
65 } else if (slot == 6) {
66 /* GigE */
67 irq = IRQ_IOP33X_XINT2;
68 } else {
69 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
70 "device PCI:%d:%d:%d\n", dev->bus->number,
71 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
72 irq = -1;
73 }
74
75 return irq;
76}
77
78static struct hw_pci iq80332_pci __initdata = {
79 .nr_controllers = 1,
80 .ops = &iop3xx_ops,
81 .setup = iop3xx_pci_setup,
82 .preinit = iop3xx_pci_preinit_cond,
83 .map_irq = iq80332_pci_map_irq,
84};
85
86static int __init iq80332_pci_init(void)
87{
88 if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) &&
89 machine_is_iq80332())
90 pci_common_init(&iq80332_pci);
91
92 return 0;
93}
94
95subsys_initcall(iq80332_pci_init);
96
97
98/*
99 * IQ80332 machine initialisation.
100 */
101static struct physmap_flash_data iq80332_flash_data = {
102 .width = 1,
103};
104
105static struct resource iq80332_flash_resource = {
106 .start = 0xc0000000,
107 .end = 0xc07fffff,
108 .flags = IORESOURCE_MEM,
109};
110
111static struct platform_device iq80332_flash_device = {
112 .name = "physmap-flash",
113 .id = 0,
114 .dev = {
115 .platform_data = &iq80332_flash_data,
116 },
117 .num_resources = 1,
118 .resource = &iq80332_flash_resource,
119};
120
121static struct resource iq80332_gpio_res[] = {
122 DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x1780), 0x10),
123};
124
125static void __init iq80332_init_machine(void)
126{
127 platform_device_register_simple("gpio-iop", 0,
128 iq80332_gpio_res,
129 ARRAY_SIZE(iq80332_gpio_res));
130 platform_device_register(&iop3xx_i2c0_device);
131 platform_device_register(&iop3xx_i2c1_device);
132 platform_device_register(&iop33x_uart0_device);
133 platform_device_register(&iop33x_uart1_device);
134 platform_device_register(&iq80332_flash_device);
135 platform_device_register(&iop3xx_dma_0_channel);
136 platform_device_register(&iop3xx_dma_1_channel);
137 platform_device_register(&iop3xx_aau_channel);
138}
139
140MACHINE_START(IQ80332, "Intel IQ80332")
141 /* Maintainer: Intel Corp. */
142 .atag_offset = 0x100,
143 .map_io = iop3xx_map_io,
144 .init_irq = iop33x_init_irq,
145 .init_time = iq80332_timer_init,
146 .init_machine = iq80332_init_machine,
147 .restart = iop3xx_restart,
148MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
deleted file mode 100644
index 03ad7d3a8f49..000000000000
--- a/arch/arm/mach-iop33x/irq.c
+++ /dev/null
@@ -1,115 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-iop33x/irq.c
4 *
5 * Generic IOP331 IRQ handling functionality
6 *
7 * Author: Dave Jiang <dave.jiang@intel.com>
8 * Copyright (C) 2003 Intel Corp.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/list.h>
14#include <asm/mach/irq.h>
15#include <asm/irq.h>
16#include <mach/hardware.h>
17#include <asm/mach-types.h>
18
19static u32 iop33x_mask0;
20static u32 iop33x_mask1;
21
22static void intctl0_write(u32 val)
23{
24 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
25}
26
27static void intctl1_write(u32 val)
28{
29 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
30}
31
32static void intstr0_write(u32 val)
33{
34 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
35}
36
37static void intstr1_write(u32 val)
38{
39 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
40}
41
42static void intbase_write(u32 val)
43{
44 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
45}
46
47static void intsize_write(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
50}
51
52static void
53iop33x_irq_mask1 (struct irq_data *d)
54{
55 iop33x_mask0 &= ~(1 << d->irq);
56 intctl0_write(iop33x_mask0);
57}
58
59static void
60iop33x_irq_mask2 (struct irq_data *d)
61{
62 iop33x_mask1 &= ~(1 << (d->irq - 32));
63 intctl1_write(iop33x_mask1);
64}
65
66static void
67iop33x_irq_unmask1(struct irq_data *d)
68{
69 iop33x_mask0 |= 1 << d->irq;
70 intctl0_write(iop33x_mask0);
71}
72
73static void
74iop33x_irq_unmask2(struct irq_data *d)
75{
76 iop33x_mask1 |= (1 << (d->irq - 32));
77 intctl1_write(iop33x_mask1);
78}
79
80struct irq_chip iop33x_irqchip1 = {
81 .name = "IOP33x-1",
82 .irq_ack = iop33x_irq_mask1,
83 .irq_mask = iop33x_irq_mask1,
84 .irq_unmask = iop33x_irq_unmask1,
85};
86
87struct irq_chip iop33x_irqchip2 = {
88 .name = "IOP33x-2",
89 .irq_ack = iop33x_irq_mask2,
90 .irq_mask = iop33x_irq_mask2,
91 .irq_unmask = iop33x_irq_unmask2,
92};
93
94void __init iop33x_init_irq(void)
95{
96 int i;
97
98 iop_init_cp6_handler();
99
100 intctl0_write(0);
101 intctl1_write(0);
102 intstr0_write(0);
103 intstr1_write(0);
104 intbase_write(0);
105 intsize_write(1);
106 if (machine_is_iq80331())
107 *IOP3XX_PCIIRSR = 0x0f;
108
109 for (i = 0; i < NR_IRQS; i++) {
110 irq_set_chip_and_handler(i,
111 (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
112 handle_level_irq);
113 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
114 }
115}
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
deleted file mode 100644
index 8fa079d2e3c3..000000000000
--- a/arch/arm/mach-iop33x/uart.c
+++ /dev/null
@@ -1,100 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-iop33x/uart.c
4 *
5 * Author: Dave Jiang (dave.jiang@intel.com)
6 * Copyright (C) 2004 Intel Corporation.
7 */
8
9#include <linux/mm.h>
10#include <linux/init.h>
11#include <linux/major.h>
12#include <linux/fs.h>
13#include <linux/platform_device.h>
14#include <linux/serial.h>
15#include <linux/tty.h>
16#include <linux/serial_8250.h>
17#include <linux/io.h>
18#include <asm/pgtable.h>
19#include <asm/page.h>
20#include <asm/mach/map.h>
21#include <asm/setup.h>
22#include <asm/memory.h>
23#include <mach/hardware.h>
24#include <asm/hardware/iop3xx.h>
25#include <asm/mach/arch.h>
26
27#define IOP33X_UART_XTAL 33334000
28
29static struct plat_serial8250_port iop33x_uart0_data[] = {
30 {
31 .membase = (char *)IOP33X_UART0_VIRT,
32 .mapbase = IOP33X_UART0_PHYS,
33 .irq = IRQ_IOP33X_UART0,
34 .uartclk = IOP33X_UART_XTAL,
35 .regshift = 2,
36 .iotype = UPIO_MEM,
37 .flags = UPF_SKIP_TEST,
38 },
39 { },
40};
41
42static struct resource iop33x_uart0_resources[] = {
43 [0] = {
44 .start = IOP33X_UART0_PHYS,
45 .end = IOP33X_UART0_PHYS + 0x3f,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = IRQ_IOP33X_UART0,
50 .end = IRQ_IOP33X_UART0,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55struct platform_device iop33x_uart0_device = {
56 .name = "serial8250",
57 .id = PLAT8250_DEV_PLATFORM,
58 .dev = {
59 .platform_data = iop33x_uart0_data,
60 },
61 .num_resources = 2,
62 .resource = iop33x_uart0_resources,
63};
64
65
66static struct resource iop33x_uart1_resources[] = {
67 [0] = {
68 .start = IOP33X_UART1_PHYS,
69 .end = IOP33X_UART1_PHYS + 0x3f,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = IRQ_IOP33X_UART1,
74 .end = IRQ_IOP33X_UART1,
75 .flags = IORESOURCE_IRQ,
76 },
77};
78
79static struct plat_serial8250_port iop33x_uart1_data[] = {
80 {
81 .membase = (char *)IOP33X_UART1_VIRT,
82 .mapbase = IOP33X_UART1_PHYS,
83 .irq = IRQ_IOP33X_UART1,
84 .uartclk = IOP33X_UART_XTAL,
85 .regshift = 2,
86 .iotype = UPIO_MEM,
87 .flags = UPF_SKIP_TEST,
88 },
89 { },
90};
91
92struct platform_device iop33x_uart1_device = {
93 .name = "serial8250",
94 .id = PLAT8250_DEV_PLATFORM1,
95 .dev = {
96 .platform_data = iop33x_uart1_data,
97 },
98 .num_resources = 2,
99 .resource = iop33x_uart1_resources,
100};
diff --git a/arch/arm/plat-iop/Makefile b/arch/arm/plat-iop/Makefile
index 4d839a3cf284..86e354b9065d 100644
--- a/arch/arm/plat-iop/Makefile
+++ b/arch/arm/plat-iop/Makefile
@@ -12,17 +12,3 @@ obj-$(CONFIG_ARCH_IOP32X) += cp6.o
12obj-$(CONFIG_ARCH_IOP32X) += adma.o 12obj-$(CONFIG_ARCH_IOP32X) += adma.o
13obj-$(CONFIG_ARCH_IOP32X) += pmu.o 13obj-$(CONFIG_ARCH_IOP32X) += pmu.o
14obj-$(CONFIG_ARCH_IOP32X) += restart.o 14obj-$(CONFIG_ARCH_IOP32X) += restart.o
15
16# IOP33X
17obj-$(CONFIG_ARCH_IOP33X) += i2c.o
18obj-$(CONFIG_ARCH_IOP33X) += pci.o
19obj-$(CONFIG_ARCH_IOP33X) += setup.o
20obj-$(CONFIG_ARCH_IOP33X) += time.o
21obj-$(CONFIG_ARCH_IOP33X) += cp6.o
22obj-$(CONFIG_ARCH_IOP33X) += adma.o
23obj-$(CONFIG_ARCH_IOP33X) += pmu.o
24obj-$(CONFIG_ARCH_IOP33X) += restart.o
25
26# IOP13XX
27obj-$(CONFIG_ARCH_IOP13XX) += cp6.o
28obj-$(CONFIG_ARCH_IOP13XX) += time.o
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
index b8e360299293..368496471e60 100644
--- a/arch/arm/plat-iop/adma.c
+++ b/arch/arm/plat-iop/adma.c
@@ -9,7 +9,6 @@
9#include <mach/adma.h> 9#include <mach/adma.h>
10#include <asm/hardware/iop_adma.h> 10#include <asm/hardware/iop_adma.h>
11 11
12#ifdef CONFIG_ARCH_IOP32X
13#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT 12#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
14#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC 13#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
15#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR 14#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
@@ -21,20 +20,7 @@
21#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT 20#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
22#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC 21#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
23#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR 22#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
24#endif 23
25#ifdef CONFIG_ARCH_IOP33X
26#define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
27#define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
28#define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
29
30#define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
31#define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
32#define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
33
34#define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
35#define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
36#define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
37#endif
38/* AAU and DMA Channels */ 24/* AAU and DMA Channels */
39static struct resource iop3xx_dma_0_resources[] = { 25static struct resource iop3xx_dma_0_resources[] = {
40 [0] = { 26 [0] = {
@@ -161,30 +147,14 @@ struct platform_device iop3xx_aau_channel = {
161 147
162static int __init iop3xx_adma_cap_init(void) 148static int __init iop3xx_adma_cap_init(void)
163{ 149{
164 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
165 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
166 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
167 #else
168 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); 150 dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
169 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); 151 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
170 #endif
171 152
172 #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
173 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); 153 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
174 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); 154 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
175 #else
176 dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
177 dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
178 #endif
179 155
180 #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
181 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
182 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
183 #else
184 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); 156 dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
185 dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
186 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); 157 dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
187 #endif
188 158
189 return 0; 159 return 0;
190} 160}
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index dfbd7c332866..8d5fe349c7cd 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -26,15 +26,6 @@
26#include <asm/hardware/iop3xx.h> 26#include <asm/hardware/iop3xx.h>
27#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
28 28
29#ifdef CONFIG_ARCH_IOP32X
30#define IRQ_IOP3XX_I2C_0 IRQ_IOP32X_I2C_0
31#define IRQ_IOP3XX_I2C_1 IRQ_IOP32X_I2C_1
32#endif
33#ifdef CONFIG_ARCH_IOP33X
34#define IRQ_IOP3XX_I2C_0 IRQ_IOP33X_I2C_0
35#define IRQ_IOP3XX_I2C_1 IRQ_IOP33X_I2C_1
36#endif
37
38/* 29/*
39 * Each of the I2C busses have corresponding GPIO lines, and the driver 30 * Each of the I2C busses have corresponding GPIO lines, and the driver
40 * need to access these directly to drive the bus low at times. 31 * need to access these directly to drive the bus low at times.
@@ -65,8 +56,8 @@ static struct resource iop3xx_i2c0_resources[] = {
65 .flags = IORESOURCE_MEM, 56 .flags = IORESOURCE_MEM,
66 }, 57 },
67 [1] = { 58 [1] = {
68 .start = IRQ_IOP3XX_I2C_0, 59 .start = IRQ_IOP32X_I2C_0,
69 .end = IRQ_IOP3XX_I2C_0, 60 .end = IRQ_IOP32X_I2C_0,
70 .flags = IORESOURCE_IRQ, 61 .flags = IORESOURCE_IRQ,
71 }, 62 },
72}; 63};
@@ -86,8 +77,8 @@ static struct resource iop3xx_i2c1_resources[] = {
86 .flags = IORESOURCE_MEM, 77 .flags = IORESOURCE_MEM,
87 }, 78 },
88 [1] = { 79 [1] = {
89 .start = IRQ_IOP3XX_I2C_1, 80 .start = IRQ_IOP32X_I2C_1,
90 .end = IRQ_IOP3XX_I2C_1, 81 .end = IRQ_IOP32X_I2C_1,
91 .flags = IORESOURCE_IRQ, 82 .flags = IORESOURCE_IRQ,
92 } 83 }
93}; 84};
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index 04c44a809b32..3834142c17f4 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -8,14 +8,8 @@
8#include <mach/irqs.h> 8#include <mach/irqs.h>
9 9
10static struct resource pmu_resource = { 10static struct resource pmu_resource = {
11#ifdef CONFIG_ARCH_IOP32X
12 .start = IRQ_IOP32X_CORE_PMU, 11 .start = IRQ_IOP32X_CORE_PMU,
13 .end = IRQ_IOP32X_CORE_PMU, 12 .end = IRQ_IOP32X_CORE_PMU,
14#endif
15#ifdef CONFIG_ARCH_IOP33X
16 .start = IRQ_IOP33X_CORE_PMU,
17 .end = IRQ_IOP33X_CORE_PMU,
18#endif
19 .flags = IORESOURCE_IRQ, 13 .flags = IORESOURCE_IRQ,
20}; 14};
21 15
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 03fa0c58cef3..cc84863bc52b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -295,7 +295,7 @@ config INTEL_IOATDMA
295 295
296config INTEL_IOP_ADMA 296config INTEL_IOP_ADMA
297 tristate "Intel IOP ADMA support" 297 tristate "Intel IOP ADMA support"
298 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX 298 depends on ARCH_IOP32X
299 select DMA_ENGINE 299 select DMA_ENGINE
300 select ASYNC_TX_ENABLE_CHANNEL_SWITCH 300 select ASYNC_TX_ENABLE_CHANNEL_SWITCH
301 help 301 help
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index bb13c266c329..6d4bc584efc4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -275,7 +275,7 @@ config GPIO_ICH
275 275
276config GPIO_IOP 276config GPIO_IOP
277 tristate "Intel IOP GPIO" 277 tristate "Intel IOP GPIO"
278 depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST 278 depends on ARCH_IOP32X || COMPILE_TEST
279 select GPIO_GENERIC 279 select GPIO_GENERIC
280 help 280 help
281 Say yes here to support the GPIO functionality of a number of Intel 281 Say yes here to support the GPIO functionality of a number of Intel
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 09367fc014c3..f8c77edf70d0 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -684,7 +684,7 @@ config I2C_IMX_LPI2C
684 684
685config I2C_IOP3XX 685config I2C_IOP3XX
686 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" 686 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
687 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX 687 depends on ARCH_IOP32X || ARCH_IXP4XX
688 help 688 help
689 Say Y here if you want to use the IIC bus controller on 689 Say Y here if you want to use the IIC bus controller on
690 the Intel IOPx3xx I/O Processors or IXP4xx Network Processors. 690 the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 00:11:00 -0400