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authorDaniel Baluta <daniel.baluta@nxp.com>2019-08-06 11:12:12 -0400
committerMark Brown <broonie@kernel.org>2019-08-07 09:26:04 -0400
commit4f7a0728b5305e2d865f543fbcffd617e03c7674 (patch)
tree7d8ac358ff46c51c304f250977c0173bae43471a
parentb84f50b0fcb497a62068926fca793d2d213c7dbd (diff)
ASoC: fsl_sai: Add support for SAI new version
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf Signed-off-by: Mihai Serban <mihai.serban@nxp.com> [initial coding in the NXP internal tree] Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> [bugfixing and cleanups] Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> [adapted to linux-next] Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--sound/soc/fsl/fsl_sai.c228
-rw-r--r--sound/soc/fsl/fsl_sai.h41
2 files changed, 156 insertions, 113 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index f2698c94c9fe..0c5452927c04 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -40,6 +40,7 @@ static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
40static irqreturn_t fsl_sai_isr(int irq, void *devid) 40static irqreturn_t fsl_sai_isr(int irq, void *devid)
41{ 41{
42 struct fsl_sai *sai = (struct fsl_sai *)devid; 42 struct fsl_sai *sai = (struct fsl_sai *)devid;
43 unsigned int ofs = sai->soc_data->reg_offset;
43 struct device *dev = &sai->pdev->dev; 44 struct device *dev = &sai->pdev->dev;
44 u32 flags, xcsr, mask; 45 u32 flags, xcsr, mask;
45 bool irq_none = true; 46 bool irq_none = true;
@@ -52,7 +53,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
52 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 53 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
53 54
54 /* Tx IRQ */ 55 /* Tx IRQ */
55 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); 56 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
56 flags = xcsr & mask; 57 flags = xcsr & mask;
57 58
58 if (flags) 59 if (flags)
@@ -82,11 +83,11 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
82 xcsr &= ~FSL_SAI_CSR_xF_MASK; 83 xcsr &= ~FSL_SAI_CSR_xF_MASK;
83 84
84 if (flags) 85 if (flags)
85 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); 86 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
86 87
87irq_rx: 88irq_rx:
88 /* Rx IRQ */ 89 /* Rx IRQ */
89 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); 90 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
90 flags = xcsr & mask; 91 flags = xcsr & mask;
91 92
92 if (flags) 93 if (flags)
@@ -116,7 +117,7 @@ irq_rx:
116 xcsr &= ~FSL_SAI_CSR_xF_MASK; 117 xcsr &= ~FSL_SAI_CSR_xF_MASK;
117 118
118 if (flags) 119 if (flags)
119 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); 120 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
120 121
121out: 122out:
122 if (irq_none) 123 if (irq_none)
@@ -140,6 +141,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
140 int clk_id, unsigned int freq, int fsl_dir) 141 int clk_id, unsigned int freq, int fsl_dir)
141{ 142{
142 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 143 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
144 unsigned int ofs = sai->soc_data->reg_offset;
143 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 145 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
144 u32 val_cr2 = 0; 146 u32 val_cr2 = 0;
145 147
@@ -160,7 +162,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
160 return -EINVAL; 162 return -EINVAL;
161 } 163 }
162 164
163 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), 165 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
164 FSL_SAI_CR2_MSEL_MASK, val_cr2); 166 FSL_SAI_CR2_MSEL_MASK, val_cr2);
165 167
166 return 0; 168 return 0;
@@ -193,6 +195,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
193 unsigned int fmt, int fsl_dir) 195 unsigned int fmt, int fsl_dir)
194{ 196{
195 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 197 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
198 unsigned int ofs = sai->soc_data->reg_offset;
196 bool tx = fsl_dir == FSL_FMT_TRANSMITTER; 199 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
197 u32 val_cr2 = 0, val_cr4 = 0; 200 u32 val_cr2 = 0, val_cr4 = 0;
198 201
@@ -287,9 +290,9 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
287 return -EINVAL; 290 return -EINVAL;
288 } 291 }
289 292
290 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), 293 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
291 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 294 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
292 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), 295 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
293 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 296 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
294 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 297 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
295 298
@@ -316,6 +319,7 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
316static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 319static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
317{ 320{
318 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 321 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
322 unsigned int ofs = sai->soc_data->reg_offset;
319 unsigned long clk_rate; 323 unsigned long clk_rate;
320 u32 savediv = 0, ratio, savesub = freq; 324 u32 savediv = 0, ratio, savesub = freq;
321 u32 id; 325 u32 id;
@@ -378,17 +382,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
378 */ 382 */
379 if ((sai->synchronous[TX] && !sai->synchronous[RX]) || 383 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
380 (!tx && !sai->synchronous[RX])) { 384 (!tx && !sai->synchronous[RX])) {
381 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, 385 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
382 FSL_SAI_CR2_MSEL_MASK, 386 FSL_SAI_CR2_MSEL_MASK,
383 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 387 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
384 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, 388 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
385 FSL_SAI_CR2_DIV_MASK, savediv - 1); 389 FSL_SAI_CR2_DIV_MASK, savediv - 1);
386 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || 390 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
387 (tx && !sai->synchronous[TX])) { 391 (tx && !sai->synchronous[TX])) {
388 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, 392 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
389 FSL_SAI_CR2_MSEL_MASK, 393 FSL_SAI_CR2_MSEL_MASK,
390 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 394 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
391 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, 395 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
392 FSL_SAI_CR2_DIV_MASK, savediv - 1); 396 FSL_SAI_CR2_DIV_MASK, savediv - 1);
393 } 397 }
394 398
@@ -403,6 +407,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
403 struct snd_soc_dai *cpu_dai) 407 struct snd_soc_dai *cpu_dai)
404{ 408{
405 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 409 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
410 unsigned int ofs = sai->soc_data->reg_offset;
406 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 411 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
407 unsigned int channels = params_channels(params); 412 unsigned int channels = params_channels(params);
408 u32 word_width = params_width(params); 413 u32 word_width = params_width(params);
@@ -455,19 +460,19 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
455 460
456 if (!sai->is_slave_mode) { 461 if (!sai->is_slave_mode) {
457 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { 462 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
458 regmap_update_bits(sai->regmap, FSL_SAI_TCR4, 463 regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
459 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 464 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
460 val_cr4); 465 val_cr4);
461 regmap_update_bits(sai->regmap, FSL_SAI_TCR5, 466 regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
462 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 467 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
463 FSL_SAI_CR5_FBT_MASK, val_cr5); 468 FSL_SAI_CR5_FBT_MASK, val_cr5);
464 regmap_write(sai->regmap, FSL_SAI_TMR, 469 regmap_write(sai->regmap, FSL_SAI_TMR,
465 ~0UL - ((1 << channels) - 1)); 470 ~0UL - ((1 << channels) - 1));
466 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { 471 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
467 regmap_update_bits(sai->regmap, FSL_SAI_RCR4, 472 regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
468 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 473 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
469 val_cr4); 474 val_cr4);
470 regmap_update_bits(sai->regmap, FSL_SAI_RCR5, 475 regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
471 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 476 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
472 FSL_SAI_CR5_FBT_MASK, val_cr5); 477 FSL_SAI_CR5_FBT_MASK, val_cr5);
473 regmap_write(sai->regmap, FSL_SAI_RMR, 478 regmap_write(sai->regmap, FSL_SAI_RMR,
@@ -475,10 +480,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
475 } 480 }
476 } 481 }
477 482
478 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), 483 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
479 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, 484 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
480 val_cr4); 485 val_cr4);
481 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), 486 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
482 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 487 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
483 FSL_SAI_CR5_FBT_MASK, val_cr5); 488 FSL_SAI_CR5_FBT_MASK, val_cr5);
484 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); 489 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
@@ -506,6 +511,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
506 struct snd_soc_dai *cpu_dai) 511 struct snd_soc_dai *cpu_dai)
507{ 512{
508 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 513 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
514 unsigned int ofs = sai->soc_data->reg_offset;
515
509 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 516 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
510 u32 xcsr, count = 100; 517 u32 xcsr, count = 100;
511 518
@@ -514,9 +521,9 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
514 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 521 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
515 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 522 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
516 */ 523 */
517 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 524 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
518 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 525 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
519 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, 526 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
520 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 527 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
521 528
522 /* 529 /*
@@ -527,43 +534,44 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
527 case SNDRV_PCM_TRIGGER_START: 534 case SNDRV_PCM_TRIGGER_START:
528 case SNDRV_PCM_TRIGGER_RESUME: 535 case SNDRV_PCM_TRIGGER_RESUME:
529 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 536 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
530 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 537 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
531 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 538 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
532 539
533 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 540 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
534 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 541 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
535 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 542 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
536 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 543 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
537 544
538 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 545 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
539 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 546 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
540 break; 547 break;
541 case SNDRV_PCM_TRIGGER_STOP: 548 case SNDRV_PCM_TRIGGER_STOP:
542 case SNDRV_PCM_TRIGGER_SUSPEND: 549 case SNDRV_PCM_TRIGGER_SUSPEND:
543 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 550 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
544 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 551 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
545 FSL_SAI_CSR_FRDE, 0); 552 FSL_SAI_CSR_FRDE, 0);
546 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), 553 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
547 FSL_SAI_CSR_xIE_MASK, 0); 554 FSL_SAI_CSR_xIE_MASK, 0);
548 555
549 /* Check if the opposite FRDE is also disabled */ 556 /* Check if the opposite FRDE is also disabled */
550 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); 557 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
551 if (!(xcsr & FSL_SAI_CSR_FRDE)) { 558 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
552 /* Disable both directions and reset their FIFOs */ 559 /* Disable both directions and reset their FIFOs */
553 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 560 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
554 FSL_SAI_CSR_TERE, 0); 561 FSL_SAI_CSR_TERE, 0);
555 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 562 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
556 FSL_SAI_CSR_TERE, 0); 563 FSL_SAI_CSR_TERE, 0);
557 564
558 /* TERE will remain set till the end of current frame */ 565 /* TERE will remain set till the end of current frame */
559 do { 566 do {
560 udelay(10); 567 udelay(10);
561 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); 568 regmap_read(sai->regmap,
569 FSL_SAI_xCSR(tx, ofs), &xcsr);
562 } while (--count && xcsr & FSL_SAI_CSR_TERE); 570 } while (--count && xcsr & FSL_SAI_CSR_TERE);
563 571
564 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 572 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
565 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 573 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
566 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 574 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
567 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 575 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
568 576
569 /* 577 /*
@@ -575,13 +583,13 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
575 */ 583 */
576 if (!sai->is_slave_mode) { 584 if (!sai->is_slave_mode) {
577 /* Software Reset for both Tx and Rx */ 585 /* Software Reset for both Tx and Rx */
578 regmap_write(sai->regmap, 586 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
579 FSL_SAI_TCSR, FSL_SAI_CSR_SR); 587 FSL_SAI_CSR_SR);
580 regmap_write(sai->regmap, 588 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
581 FSL_SAI_RCSR, FSL_SAI_CSR_SR); 589 FSL_SAI_CSR_SR);
582 /* Clear SR bit to finish the reset */ 590 /* Clear SR bit to finish the reset */
583 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 591 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
584 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 592 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
585 } 593 }
586 } 594 }
587 break; 595 break;
@@ -596,10 +604,11 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
596 struct snd_soc_dai *cpu_dai) 604 struct snd_soc_dai *cpu_dai)
597{ 605{
598 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 606 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
607 unsigned int ofs = sai->soc_data->reg_offset;
599 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 608 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
600 int ret; 609 int ret;
601 610
602 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), 611 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
603 FSL_SAI_CR3_TRCE_MASK, 612 FSL_SAI_CR3_TRCE_MASK,
604 FSL_SAI_CR3_TRCE); 613 FSL_SAI_CR3_TRCE);
605 614
@@ -613,9 +622,10 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *cpu_dai) 622 struct snd_soc_dai *cpu_dai)
614{ 623{
615 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 624 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
625 unsigned int ofs = sai->soc_data->reg_offset;
616 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 626 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
617 627
618 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), 628 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
619 FSL_SAI_CR3_TRCE_MASK, 0); 629 FSL_SAI_CR3_TRCE_MASK, 0);
620} 630}
621 631
@@ -633,18 +643,20 @@ static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
633static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 643static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
634{ 644{
635 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 645 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
646 unsigned int ofs = sai->soc_data->reg_offset;
636 647
637 /* Software Reset for both Tx and Rx */ 648 /* Software Reset for both Tx and Rx */
638 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); 649 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
639 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); 650 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
640 /* Clear SR bit to finish the reset */ 651 /* Clear SR bit to finish the reset */
641 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 652 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
642 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 653 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
643 654
644 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, 655 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
656 FSL_SAI_CR1_RFW_MASK,
645 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); 657 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
646 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, 658 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
647 FSL_SAI_MAXBURST_RX - 1); 659 FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
648 660
649 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 661 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
650 &sai->dma_params_rx); 662 &sai->dma_params_rx);
@@ -681,12 +693,12 @@ static const struct snd_soc_component_driver fsl_component = {
681 .name = "fsl-sai", 693 .name = "fsl-sai",
682}; 694};
683 695
684static struct reg_default fsl_sai_reg_defaults[] = { 696static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
685 {FSL_SAI_TCR1, 0}, 697 {FSL_SAI_TCR1(0), 0},
686 {FSL_SAI_TCR2, 0}, 698 {FSL_SAI_TCR2(0), 0},
687 {FSL_SAI_TCR3, 0}, 699 {FSL_SAI_TCR3(0), 0},
688 {FSL_SAI_TCR4, 0}, 700 {FSL_SAI_TCR4(0), 0},
689 {FSL_SAI_TCR5, 0}, 701 {FSL_SAI_TCR5(0), 0},
690 {FSL_SAI_TDR0, 0}, 702 {FSL_SAI_TDR0, 0},
691 {FSL_SAI_TDR1, 0}, 703 {FSL_SAI_TDR1, 0},
692 {FSL_SAI_TDR2, 0}, 704 {FSL_SAI_TDR2, 0},
@@ -695,24 +707,50 @@ static struct reg_default fsl_sai_reg_defaults[] = {
695 {FSL_SAI_TDR5, 0}, 707 {FSL_SAI_TDR5, 0},
696 {FSL_SAI_TDR6, 0}, 708 {FSL_SAI_TDR6, 0},
697 {FSL_SAI_TDR7, 0}, 709 {FSL_SAI_TDR7, 0},
698 {FSL_SAI_TMR, 0}, 710 {FSL_SAI_TMR, 0},
699 {FSL_SAI_RCR1, 0}, 711 {FSL_SAI_RCR1(0), 0},
700 {FSL_SAI_RCR2, 0}, 712 {FSL_SAI_RCR2(0), 0},
701 {FSL_SAI_RCR3, 0}, 713 {FSL_SAI_RCR3(0), 0},
702 {FSL_SAI_RCR4, 0}, 714 {FSL_SAI_RCR4(0), 0},
703 {FSL_SAI_RCR5, 0}, 715 {FSL_SAI_RCR5(0), 0},
704 {FSL_SAI_RMR, 0}, 716 {FSL_SAI_RMR, 0},
717};
718
719static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
720 {FSL_SAI_TCR1(8), 0},
721 {FSL_SAI_TCR2(8), 0},
722 {FSL_SAI_TCR3(8), 0},
723 {FSL_SAI_TCR4(8), 0},
724 {FSL_SAI_TCR5(8), 0},
725 {FSL_SAI_TDR0, 0},
726 {FSL_SAI_TDR1, 0},
727 {FSL_SAI_TDR2, 0},
728 {FSL_SAI_TDR3, 0},
729 {FSL_SAI_TDR4, 0},
730 {FSL_SAI_TDR5, 0},
731 {FSL_SAI_TDR6, 0},
732 {FSL_SAI_TDR7, 0},
733 {FSL_SAI_TMR, 0},
734 {FSL_SAI_RCR1(8), 0},
735 {FSL_SAI_RCR2(8), 0},
736 {FSL_SAI_RCR3(8), 0},
737 {FSL_SAI_RCR4(8), 0},
738 {FSL_SAI_RCR5(8), 0},
739 {FSL_SAI_RMR, 0},
705}; 740};
706 741
707static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 742static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
708{ 743{
744 struct fsl_sai *sai = dev_get_drvdata(dev);
745 unsigned int ofs = sai->soc_data->reg_offset;
746
747 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
748 return true;
749
750 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
751 return true;
752
709 switch (reg) { 753 switch (reg) {
710 case FSL_SAI_TCSR:
711 case FSL_SAI_TCR1:
712 case FSL_SAI_TCR2:
713 case FSL_SAI_TCR3:
714 case FSL_SAI_TCR4:
715 case FSL_SAI_TCR5:
716 case FSL_SAI_TFR0: 754 case FSL_SAI_TFR0:
717 case FSL_SAI_TFR1: 755 case FSL_SAI_TFR1:
718 case FSL_SAI_TFR2: 756 case FSL_SAI_TFR2:
@@ -722,12 +760,6 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
722 case FSL_SAI_TFR6: 760 case FSL_SAI_TFR6:
723 case FSL_SAI_TFR7: 761 case FSL_SAI_TFR7:
724 case FSL_SAI_TMR: 762 case FSL_SAI_TMR:
725 case FSL_SAI_RCSR:
726 case FSL_SAI_RCR1:
727 case FSL_SAI_RCR2:
728 case FSL_SAI_RCR3:
729 case FSL_SAI_RCR4:
730 case FSL_SAI_RCR5:
731 case FSL_SAI_RDR0: 763 case FSL_SAI_RDR0:
732 case FSL_SAI_RDR1: 764 case FSL_SAI_RDR1:
733 case FSL_SAI_RDR2: 765 case FSL_SAI_RDR2:
@@ -753,9 +785,13 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
753 785
754static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 786static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
755{ 787{
788 struct fsl_sai *sai = dev_get_drvdata(dev);
789 unsigned int ofs = sai->soc_data->reg_offset;
790
791 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
792 return true;
793
756 switch (reg) { 794 switch (reg) {
757 case FSL_SAI_TCSR:
758 case FSL_SAI_RCSR:
759 case FSL_SAI_TFR0: 795 case FSL_SAI_TFR0:
760 case FSL_SAI_TFR1: 796 case FSL_SAI_TFR1:
761 case FSL_SAI_TFR2: 797 case FSL_SAI_TFR2:
@@ -788,13 +824,16 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
788 824
789static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 825static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
790{ 826{
827 struct fsl_sai *sai = dev_get_drvdata(dev);
828 unsigned int ofs = sai->soc_data->reg_offset;
829
830 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
831 return true;
832
833 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
834 return true;
835
791 switch (reg) { 836 switch (reg) {
792 case FSL_SAI_TCSR:
793 case FSL_SAI_TCR1:
794 case FSL_SAI_TCR2:
795 case FSL_SAI_TCR3:
796 case FSL_SAI_TCR4:
797 case FSL_SAI_TCR5:
798 case FSL_SAI_TDR0: 837 case FSL_SAI_TDR0:
799 case FSL_SAI_TDR1: 838 case FSL_SAI_TDR1:
800 case FSL_SAI_TDR2: 839 case FSL_SAI_TDR2:
@@ -804,12 +843,6 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
804 case FSL_SAI_TDR6: 843 case FSL_SAI_TDR6:
805 case FSL_SAI_TDR7: 844 case FSL_SAI_TDR7:
806 case FSL_SAI_TMR: 845 case FSL_SAI_TMR:
807 case FSL_SAI_RCSR:
808 case FSL_SAI_RCR1:
809 case FSL_SAI_RCR2:
810 case FSL_SAI_RCR3:
811 case FSL_SAI_RCR4:
812 case FSL_SAI_RCR5:
813 case FSL_SAI_RMR: 846 case FSL_SAI_RMR:
814 return true; 847 return true;
815 default: 848 default:
@@ -817,15 +850,15 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
817 } 850 }
818} 851}
819 852
820static const struct regmap_config fsl_sai_regmap_config = { 853static struct regmap_config fsl_sai_regmap_config = {
821 .reg_bits = 32, 854 .reg_bits = 32,
822 .reg_stride = 4, 855 .reg_stride = 4,
823 .val_bits = 32, 856 .val_bits = 32,
824 .fast_io = true, 857 .fast_io = true,
825 858
826 .max_register = FSL_SAI_RMR, 859 .max_register = FSL_SAI_RMR,
827 .reg_defaults = fsl_sai_reg_defaults, 860 .reg_defaults = fsl_sai_reg_defaults_ofs0,
828 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), 861 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
829 .readable_reg = fsl_sai_readable_reg, 862 .readable_reg = fsl_sai_readable_reg,
830 .volatile_reg = fsl_sai_volatile_reg, 863 .volatile_reg = fsl_sai_volatile_reg,
831 .writeable_reg = fsl_sai_writeable_reg, 864 .writeable_reg = fsl_sai_writeable_reg,
@@ -857,6 +890,12 @@ static int fsl_sai_probe(struct platform_device *pdev)
857 if (IS_ERR(base)) 890 if (IS_ERR(base))
858 return PTR_ERR(base); 891 return PTR_ERR(base);
859 892
893 if (sai->soc_data->reg_offset == 8) {
894 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
895 fsl_sai_regmap_config.num_reg_defaults =
896 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
897 }
898
860 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 899 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
861 "bus", base, &fsl_sai_regmap_config); 900 "bus", base, &fsl_sai_regmap_config);
862 901
@@ -971,11 +1010,13 @@ static int fsl_sai_remove(struct platform_device *pdev)
971static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1010static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
972 .use_imx_pcm = false, 1011 .use_imx_pcm = false,
973 .fifo_depth = 32, 1012 .fifo_depth = 32,
1013 .reg_offset = 0,
974}; 1014};
975 1015
976static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1016static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
977 .use_imx_pcm = true, 1017 .use_imx_pcm = true,
978 .fifo_depth = 32, 1018 .fifo_depth = 32,
1019 .reg_offset = 0,
979}; 1020};
980 1021
981static const struct of_device_id fsl_sai_ids[] = { 1022static const struct of_device_id fsl_sai_ids[] = {
@@ -1008,6 +1049,7 @@ static int fsl_sai_runtime_suspend(struct device *dev)
1008static int fsl_sai_runtime_resume(struct device *dev) 1049static int fsl_sai_runtime_resume(struct device *dev)
1009{ 1050{
1010 struct fsl_sai *sai = dev_get_drvdata(dev); 1051 struct fsl_sai *sai = dev_get_drvdata(dev);
1052 unsigned int ofs = sai->soc_data->reg_offset;
1011 int ret; 1053 int ret;
1012 1054
1013 ret = clk_prepare_enable(sai->bus_clk); 1055 ret = clk_prepare_enable(sai->bus_clk);
@@ -1029,11 +1071,11 @@ static int fsl_sai_runtime_resume(struct device *dev)
1029 } 1071 }
1030 1072
1031 regcache_cache_only(sai->regmap, false); 1073 regcache_cache_only(sai->regmap, false);
1032 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); 1074 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1033 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); 1075 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1034 usleep_range(1000, 2000); 1076 usleep_range(1000, 2000);
1035 regmap_write(sai->regmap, FSL_SAI_TCSR, 0); 1077 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1036 regmap_write(sai->regmap, FSL_SAI_RCSR, 0); 1078 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1037 1079
1038 ret = regcache_sync(sai->regmap); 1080 ret = regcache_sync(sai->regmap);
1039 if (ret) 1081 if (ret)
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 20c5b9b1e8bc..b89b0ca26053 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -14,12 +14,12 @@
14 SNDRV_PCM_FMTBIT_S32_LE) 14 SNDRV_PCM_FMTBIT_S32_LE)
15 15
16/* SAI Register Map Register */ 16/* SAI Register Map Register */
17#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */ 17#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
18#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */ 18#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
19#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */ 19#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
20#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */ 20#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
21#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */ 21#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
22#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */ 22#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
23#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */ 23#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
24#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */ 24#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
25#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */ 25#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
@@ -37,12 +37,12 @@
37#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */ 37#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
38#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */ 38#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
39#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */ 39#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
40#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */ 40#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
41#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */ 41#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
42#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */ 42#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
43#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */ 43#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
44#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */ 44#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
45#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */ 45#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
46#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */ 46#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
47#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */ 47#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
48#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */ 48#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
@@ -61,14 +61,14 @@
61#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */ 61#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
62#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */ 62#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
63 63
64#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR) 64#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
65#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1) 65#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
66#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2) 66#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
67#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3) 67#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
68#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4) 68#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
69#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5) 69#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
70#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR) 70#define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs))
71#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR) 71#define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs))
72#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR) 72#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
73 73
74/* SAI Transmit/Receive Control Register */ 74/* SAI Transmit/Receive Control Register */
@@ -158,6 +158,7 @@
158struct fsl_sai_soc_data { 158struct fsl_sai_soc_data {
159 bool use_imx_pcm; 159 bool use_imx_pcm;
160 unsigned int fifo_depth; 160 unsigned int fifo_depth;
161 unsigned int reg_offset;
161}; 162};
162 163
163struct fsl_sai { 164struct fsl_sai {
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-26 02:26:11 -0400