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authorJC Kuo <jckuo@nvidia.com>2019-02-21 10:46:31 -0500
committerKishon Vijay Abraham I <kishon@ti.com>2019-04-17 04:42:43 -0400
commit3cffa0818dc82a90d1a3df5ea7111999cb7b8646 (patch)
tree79c88b715b697e1bc198fd48d26bd69800bb8695
parent2b8d59296cff37a73dc72a0667c148b0e57ae64f (diff)
phy: tegra: xusb: Skip single function lane programming
Tegra186 USB2 pads and USB3 pads do not have hardware mux for changing the pad function. For such "lanes", we can skip the lane mux register programming. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-rw-r--r--drivers/phy/tegra/xusb.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index 5b3b8863363e..e3bc60cfe6a1 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -313,6 +313,10 @@ static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane)
313 const struct tegra_xusb_lane_soc *soc = lane->soc; 313 const struct tegra_xusb_lane_soc *soc = lane->soc;
314 u32 value; 314 u32 value;
315 315
316 /* skip single function lanes */
317 if (soc->num_funcs < 2)
318 return;
319
316 /* choose function */ 320 /* choose function */
317 value = padctl_readl(padctl, soc->offset); 321 value = padctl_readl(padctl, soc->offset);
318 value &= ~(soc->mask << soc->shift); 322 value &= ~(soc->mask << soc->shift);