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authorBard Liao <bardliao@realtek.com>2016-11-13 22:00:10 -0500
committerMark Brown <broonie@kernel.org>2016-11-14 06:37:57 -0500
commit33ada14a26c8f174dac8765f4236ca66c64ae5be (patch)
tree349d605c737c84d2362f9d53c8317d5cc9709c5b
parent134340b33f2ddf4869519d728ad0ca4bc67154f3 (diff)
ASoC: add rt5665 codec driver
This is the initial codec driver for rt5665. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rwxr-xr-xDocumentation/devicetree/bindings/sound/rt5665.txt68
-rwxr-xr-xinclude/sound/rt5665.h47
-rw-r--r--sound/soc/codecs/Kconfig6
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5665.c4875
-rw-r--r--sound/soc/codecs/rt5665.h1990
6 files changed, 6988 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt
new file mode 100755
index 000000000000..419c89219681
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5665.txt
@@ -0,0 +1,68 @@
1RT5665/RT5666/RT5668 audio CODEC
2
3This device supports I2C only.
4
5Required properties:
6
7- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668".
8
9- reg : The I2C address of the device.
10
11- interrupts : The CODEC's interrupt output.
12
13Optional properties:
14
15- realtek,in1-differential
16- realtek,in2-differential
17- realtek,in3-differential
18- realtek,in4-differential
19 Boolean. Indicate MIC1/2/3/4 input are differential, rather than single-ended.
20
21- realtek,dmic1-data-pin
22 0: dmic1 is not used
23 1: using GPIO4 pin as dmic1 data pin
24 2: using IN2N pin as dmic2 data pin
25
26- realtek,dmic2-data-pin
27 0: dmic2 is not used
28 1: using GPIO5 pin as dmic2 data pin
29 2: using IN2P pin as dmic2 data pin
30
31- realtek,jd-src
32 0: No JD is used
33 1: using JD1 as JD source
34
35- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
36
37Pins on the device (for linking into audio routes) for RT5659/RT5658:
38
39 * DMIC L1
40 * DMIC R1
41 * DMIC L2
42 * DMIC R2
43 * IN1P
44 * IN1N
45 * IN2P
46 * IN2N
47 * IN3P
48 * IN3N
49 * IN4P
50 * IN4N
51 * HPOL
52 * HPOR
53 * LOUTL
54 * LOUTR
55 * MONOOUT
56 * PDML
57 * PDMR
58
59Example:
60
61rt5659 {
62 compatible = "realtek,rt5665";
63 reg = <0x1b>;
64 interrupt-parent = <&gpio>;
65 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
66 realtek,ldo1-en-gpios =
67 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
68};
diff --git a/include/sound/rt5665.h b/include/sound/rt5665.h
new file mode 100755
index 000000000000..963229e71dc7
--- /dev/null
+++ b/include/sound/rt5665.h
@@ -0,0 +1,47 @@
1/*
2 * linux/sound/rt5665.h -- Platform data for RT5665
3 *
4 * Copyright 2016 Realtek Microelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_RT5665_H
12#define __LINUX_SND_RT5665_H
13
14enum rt5665_dmic1_data_pin {
15 RT5665_DMIC1_NULL,
16 RT5665_DMIC1_DATA_GPIO4,
17 RT5665_DMIC1_DATA_IN2N,
18};
19
20enum rt5665_dmic2_data_pin {
21 RT5665_DMIC2_NULL,
22 RT5665_DMIC2_DATA_GPIO5,
23 RT5665_DMIC2_DATA_IN2P,
24};
25
26enum rt5665_jd_src {
27 RT5665_JD_NULL,
28 RT5665_JD1,
29};
30
31struct rt5665_platform_data {
32 bool in1_diff;
33 bool in2_diff;
34 bool in3_diff;
35 bool in4_diff;
36
37 int ldo1_en; /* GPIO for LDO1_EN */
38
39 enum rt5665_dmic1_data_pin dmic1_data_pin;
40 enum rt5665_dmic2_data_pin dmic2_data_pin;
41 enum rt5665_jd_src jd_src;
42
43 unsigned int sar_hs_type;
44};
45
46#endif
47
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c67667bb970f..f1de9720d9d3 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -114,6 +114,7 @@ config SND_SOC_ALL_CODECS
114 select SND_SOC_RT5651 if I2C 114 select SND_SOC_RT5651 if I2C
115 select SND_SOC_RT5659 if I2C 115 select SND_SOC_RT5659 if I2C
116 select SND_SOC_RT5660 if I2C 116 select SND_SOC_RT5660 if I2C
117 select SND_SOC_RT5665 if I2C
117 select SND_SOC_RT5663 if I2C 118 select SND_SOC_RT5663 if I2C
118 select SND_SOC_RT5670 if I2C 119 select SND_SOC_RT5670 if I2C
119 select SND_SOC_RT5677 if I2C && SPI_MASTER 120 select SND_SOC_RT5677 if I2C && SPI_MASTER
@@ -649,6 +650,7 @@ config SND_SOC_RL6231
649 default y if SND_SOC_RT5651=y 650 default y if SND_SOC_RT5651=y
650 default y if SND_SOC_RT5659=y 651 default y if SND_SOC_RT5659=y
651 default y if SND_SOC_RT5660=y 652 default y if SND_SOC_RT5660=y
653 default y if SND_SOC_RT5665=y
652 default y if SND_SOC_RT5663=y 654 default y if SND_SOC_RT5663=y
653 default y if SND_SOC_RT5670=y 655 default y if SND_SOC_RT5670=y
654 default y if SND_SOC_RT5677=y 656 default y if SND_SOC_RT5677=y
@@ -659,6 +661,7 @@ config SND_SOC_RL6231
659 default m if SND_SOC_RT5651=m 661 default m if SND_SOC_RT5651=m
660 default m if SND_SOC_RT5659=m 662 default m if SND_SOC_RT5659=m
661 default m if SND_SOC_RT5660=m 663 default m if SND_SOC_RT5660=m
664 default m if SND_SOC_RT5665=m
662 default m if SND_SOC_RT5663=m 665 default m if SND_SOC_RT5663=m
663 default m if SND_SOC_RT5670=m 666 default m if SND_SOC_RT5670=m
664 default m if SND_SOC_RT5677=m 667 default m if SND_SOC_RT5677=m
@@ -708,6 +711,9 @@ config SND_SOC_RT5659
708config SND_SOC_RT5660 711config SND_SOC_RT5660
709 tristate 712 tristate
710 713
714config SND_SOC_RT5665
715 tristate
716
711config SND_SOC_RT5663 717config SND_SOC_RT5663
712 tristate 718 tristate
713 719
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 958cd4912fbc..e1704e09806c 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -114,6 +114,7 @@ snd-soc-rt5645-objs := rt5645.o
114snd-soc-rt5651-objs := rt5651.o 114snd-soc-rt5651-objs := rt5651.o
115snd-soc-rt5659-objs := rt5659.o 115snd-soc-rt5659-objs := rt5659.o
116snd-soc-rt5660-objs := rt5660.o 116snd-soc-rt5660-objs := rt5660.o
117snd-soc-rt5665-objs := rt5665.o
117snd-soc-rt5663-objs := rt5663.o 118snd-soc-rt5663-objs := rt5663.o
118snd-soc-rt5670-objs := rt5670.o 119snd-soc-rt5670-objs := rt5670.o
119snd-soc-rt5677-objs := rt5677.o 120snd-soc-rt5677-objs := rt5677.o
@@ -338,6 +339,7 @@ obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
338obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 339obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
339obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o 340obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
340obj-$(CONFIG_SND_SOC_RT5660) += snd-soc-rt5660.o 341obj-$(CONFIG_SND_SOC_RT5660) += snd-soc-rt5660.o
342obj-$(CONFIG_SND_SOC_RT5665) += snd-soc-rt5665.o
341obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o 343obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o
342obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o 344obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
343obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o 345obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
diff --git a/sound/soc/codecs/rt5665.c b/sound/soc/codecs/rt5665.c
new file mode 100644
index 000000000000..34254fd47efe
--- /dev/null
+++ b/sound/soc/codecs/rt5665.c
@@ -0,0 +1,4875 @@
1/*
2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5665.h>
34
35#include "rl6231.h"
36#include "rt5665.h"
37
38#define RT5665_NUM_SUPPLIES 3
39
40static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5665_priv {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
64 int id;
65
66 int pll_src;
67 int pll_in;
68 int pll_out;
69
70 int jack_type;
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
73};
74
75static const struct reg_default rt5665_reg[] = {
76 {0x0000, 0x0000},
77 {0x0001, 0xc8c8},
78 {0x0002, 0x8080},
79 {0x0003, 0x8000},
80 {0x0004, 0xc80a},
81 {0x0005, 0x0000},
82 {0x0006, 0x0000},
83 {0x0007, 0x0000},
84 {0x000a, 0x0000},
85 {0x000b, 0x0000},
86 {0x000c, 0x0000},
87 {0x000d, 0x0000},
88 {0x000f, 0x0808},
89 {0x0010, 0x4040},
90 {0x0011, 0x0000},
91 {0x0012, 0x1404},
92 {0x0013, 0x1000},
93 {0x0014, 0xa00a},
94 {0x0015, 0x0404},
95 {0x0016, 0x0404},
96 {0x0017, 0x0011},
97 {0x0018, 0xafaf},
98 {0x0019, 0xafaf},
99 {0x001a, 0xafaf},
100 {0x001b, 0x0011},
101 {0x001c, 0x2f2f},
102 {0x001d, 0x2f2f},
103 {0x001e, 0x2f2f},
104 {0x001f, 0x0000},
105 {0x0020, 0x0000},
106 {0x0021, 0x0000},
107 {0x0022, 0x5757},
108 {0x0023, 0x0039},
109 {0x0026, 0xc0c0},
110 {0x0027, 0xc0c0},
111 {0x0028, 0xc0c0},
112 {0x0029, 0x8080},
113 {0x002a, 0xaaaa},
114 {0x002b, 0xaaaa},
115 {0x002c, 0xaba8},
116 {0x002d, 0x0000},
117 {0x002e, 0x0000},
118 {0x002f, 0x0000},
119 {0x0030, 0x0000},
120 {0x0031, 0x5000},
121 {0x0032, 0x0000},
122 {0x0033, 0x0000},
123 {0x0034, 0x0000},
124 {0x0035, 0x0000},
125 {0x003a, 0x0000},
126 {0x003b, 0x0000},
127 {0x003c, 0x00ff},
128 {0x003d, 0x0000},
129 {0x003e, 0x00ff},
130 {0x003f, 0x0000},
131 {0x0040, 0x0000},
132 {0x0041, 0x00ff},
133 {0x0042, 0x0000},
134 {0x0043, 0x00ff},
135 {0x0044, 0x0c0c},
136 {0x0049, 0xc00b},
137 {0x004a, 0x0000},
138 {0x004b, 0x031f},
139 {0x004d, 0x0000},
140 {0x004e, 0x001f},
141 {0x004f, 0x0000},
142 {0x0050, 0x001f},
143 {0x0052, 0xf000},
144 {0x0061, 0x0000},
145 {0x0062, 0x0000},
146 {0x0063, 0x003e},
147 {0x0064, 0x0000},
148 {0x0065, 0x0000},
149 {0x0066, 0x003f},
150 {0x0067, 0x0000},
151 {0x006b, 0x0000},
152 {0x006d, 0xff00},
153 {0x006e, 0x2808},
154 {0x006f, 0x000a},
155 {0x0070, 0x8000},
156 {0x0071, 0x8000},
157 {0x0072, 0x8000},
158 {0x0073, 0x7000},
159 {0x0074, 0x7770},
160 {0x0075, 0x0002},
161 {0x0076, 0x0001},
162 {0x0078, 0x00f0},
163 {0x0079, 0x0000},
164 {0x007a, 0x0000},
165 {0x007b, 0x0000},
166 {0x007c, 0x0000},
167 {0x007d, 0x0123},
168 {0x007e, 0x4500},
169 {0x007f, 0x8003},
170 {0x0080, 0x0000},
171 {0x0081, 0x0000},
172 {0x0082, 0x0000},
173 {0x0083, 0x0000},
174 {0x0084, 0x0000},
175 {0x0085, 0x0000},
176 {0x0086, 0x0008},
177 {0x0087, 0x0000},
178 {0x0088, 0x0000},
179 {0x0089, 0x0000},
180 {0x008a, 0x0000},
181 {0x008b, 0x0000},
182 {0x008c, 0x0003},
183 {0x008e, 0x0060},
184 {0x008f, 0x1000},
185 {0x0091, 0x0c26},
186 {0x0092, 0x0073},
187 {0x0093, 0x0000},
188 {0x0094, 0x0080},
189 {0x0098, 0x0000},
190 {0x0099, 0x0000},
191 {0x009a, 0x0007},
192 {0x009f, 0x0000},
193 {0x00a0, 0x0000},
194 {0x00a1, 0x0002},
195 {0x00a2, 0x0001},
196 {0x00a3, 0x0002},
197 {0x00a4, 0x0001},
198 {0x00ae, 0x2040},
199 {0x00af, 0x0000},
200 {0x00b6, 0x0000},
201 {0x00b7, 0x0000},
202 {0x00b8, 0x0000},
203 {0x00b9, 0x0000},
204 {0x00ba, 0x0002},
205 {0x00bb, 0x0000},
206 {0x00be, 0x0000},
207 {0x00c0, 0x0000},
208 {0x00c1, 0x0aaa},
209 {0x00c2, 0xaa80},
210 {0x00c3, 0x0003},
211 {0x00c4, 0x0000},
212 {0x00d0, 0x0000},
213 {0x00d1, 0x2244},
214 {0x00d3, 0x3300},
215 {0x00d4, 0x2200},
216 {0x00d9, 0x0809},
217 {0x00da, 0x0000},
218 {0x00db, 0x0008},
219 {0x00dc, 0x00c0},
220 {0x00dd, 0x6724},
221 {0x00de, 0x3131},
222 {0x00df, 0x0008},
223 {0x00e0, 0x4000},
224 {0x00e1, 0x3131},
225 {0x00e2, 0x600c},
226 {0x00ea, 0xb320},
227 {0x00eb, 0x0000},
228 {0x00ec, 0xb300},
229 {0x00ed, 0x0000},
230 {0x00ee, 0xb320},
231 {0x00ef, 0x0000},
232 {0x00f0, 0x0201},
233 {0x00f1, 0x0ddd},
234 {0x00f2, 0x0ddd},
235 {0x00f6, 0x0000},
236 {0x00f7, 0x0000},
237 {0x00f8, 0x0000},
238 {0x00fa, 0x0000},
239 {0x00fb, 0x0000},
240 {0x00fc, 0x0000},
241 {0x00fd, 0x0000},
242 {0x00fe, 0x10ec},
243 {0x00ff, 0x6451},
244 {0x0100, 0xaaaa},
245 {0x0101, 0x000a},
246 {0x010a, 0xaaaa},
247 {0x010b, 0xa0a0},
248 {0x010c, 0xaeae},
249 {0x010d, 0xaaaa},
250 {0x010e, 0xaaaa},
251 {0x010f, 0xaaaa},
252 {0x0110, 0xe002},
253 {0x0111, 0xa402},
254 {0x0112, 0xaaaa},
255 {0x0113, 0x2000},
256 {0x0117, 0x0f00},
257 {0x0125, 0x0410},
258 {0x0132, 0x0000},
259 {0x0133, 0x0000},
260 {0x0137, 0x5540},
261 {0x0138, 0x3700},
262 {0x0139, 0x79a1},
263 {0x013a, 0x2020},
264 {0x013b, 0x2020},
265 {0x013c, 0x2005},
266 {0x013f, 0x0000},
267 {0x0145, 0x0002},
268 {0x0146, 0x0000},
269 {0x0147, 0x0000},
270 {0x0148, 0x0000},
271 {0x0150, 0x0000},
272 {0x0160, 0x4eff},
273 {0x0161, 0x0080},
274 {0x0162, 0x0200},
275 {0x0163, 0x0800},
276 {0x0164, 0x0000},
277 {0x0165, 0x0000},
278 {0x0166, 0x0000},
279 {0x0167, 0x000f},
280 {0x0170, 0x4e87},
281 {0x0171, 0x0080},
282 {0x0172, 0x0200},
283 {0x0173, 0x0800},
284 {0x0174, 0x00ff},
285 {0x0175, 0x0000},
286 {0x0190, 0x413d},
287 {0x0191, 0x4139},
288 {0x0192, 0x4135},
289 {0x0193, 0x413d},
290 {0x0194, 0x0000},
291 {0x0195, 0x0000},
292 {0x0196, 0x0000},
293 {0x0197, 0x0000},
294 {0x0198, 0x0000},
295 {0x0199, 0x0000},
296 {0x01a0, 0x1e64},
297 {0x01a1, 0x06a3},
298 {0x01a2, 0x0000},
299 {0x01a3, 0x0000},
300 {0x01a4, 0x0000},
301 {0x01a5, 0x0000},
302 {0x01a6, 0x0000},
303 {0x01a7, 0x8000},
304 {0x01a8, 0x0000},
305 {0x01a9, 0x0000},
306 {0x01aa, 0x0000},
307 {0x01ab, 0x0000},
308 {0x01b5, 0x0000},
309 {0x01b6, 0x01c3},
310 {0x01b7, 0x02a0},
311 {0x01b8, 0x03e9},
312 {0x01b9, 0x1389},
313 {0x01ba, 0xc351},
314 {0x01bb, 0x0009},
315 {0x01bc, 0x0018},
316 {0x01bd, 0x002a},
317 {0x01be, 0x004c},
318 {0x01bf, 0x0097},
319 {0x01c0, 0x433d},
320 {0x01c1, 0x0000},
321 {0x01c2, 0x0000},
322 {0x01c3, 0x0000},
323 {0x01c4, 0x0000},
324 {0x01c5, 0x0000},
325 {0x01c6, 0x0000},
326 {0x01c7, 0x0000},
327 {0x01c8, 0x40af},
328 {0x01c9, 0x0702},
329 {0x01ca, 0x0000},
330 {0x01cb, 0x0000},
331 {0x01cc, 0x5757},
332 {0x01cd, 0x5757},
333 {0x01ce, 0x5757},
334 {0x01cf, 0x5757},
335 {0x01d0, 0x5757},
336 {0x01d1, 0x5757},
337 {0x01d2, 0x5757},
338 {0x01d3, 0x5757},
339 {0x01d4, 0x5757},
340 {0x01d5, 0x5757},
341 {0x01d6, 0x003c},
342 {0x01da, 0x0000},
343 {0x01db, 0x0000},
344 {0x01dc, 0x0000},
345 {0x01de, 0x7c00},
346 {0x01df, 0x0320},
347 {0x01e0, 0x06a1},
348 {0x01e1, 0x0000},
349 {0x01e2, 0x0000},
350 {0x01e3, 0x0000},
351 {0x01e4, 0x0000},
352 {0x01e6, 0x0001},
353 {0x01e7, 0x0000},
354 {0x01e8, 0x0000},
355 {0x01ea, 0xbf3f},
356 {0x01eb, 0x0000},
357 {0x01ec, 0x0000},
358 {0x01ed, 0x0000},
359 {0x01ee, 0x0000},
360 {0x01ef, 0x0000},
361 {0x01f0, 0x0000},
362 {0x01f1, 0x0000},
363 {0x01f2, 0x0000},
364 {0x01f3, 0x0000},
365 {0x01f4, 0x0000},
366 {0x0200, 0x0000},
367 {0x0201, 0x0000},
368 {0x0202, 0x0000},
369 {0x0203, 0x0000},
370 {0x0204, 0x0000},
371 {0x0205, 0x0000},
372 {0x0206, 0x0000},
373 {0x0207, 0x0000},
374 {0x0208, 0x0000},
375 {0x0210, 0x60b1},
376 {0x0211, 0xa005},
377 {0x0212, 0x024c},
378 {0x0213, 0xf7ff},
379 {0x0214, 0x024c},
380 {0x0215, 0x0102},
381 {0x0216, 0x00a3},
382 {0x0217, 0x0048},
383 {0x0218, 0xa2c0},
384 {0x0219, 0x0400},
385 {0x021a, 0x00c8},
386 {0x021b, 0x00c0},
387 {0x02ff, 0x0110},
388 {0x0300, 0x001f},
389 {0x0301, 0x032c},
390 {0x0302, 0x5f21},
391 {0x0303, 0x4000},
392 {0x0304, 0x4000},
393 {0x0305, 0x06d5},
394 {0x0306, 0x8000},
395 {0x0307, 0x0700},
396 {0x0310, 0x4560},
397 {0x0311, 0xa4a8},
398 {0x0312, 0x7418},
399 {0x0313, 0x0000},
400 {0x0314, 0x0006},
401 {0x0315, 0xffff},
402 {0x0316, 0xc400},
403 {0x0317, 0x0000},
404 {0x0330, 0x00a6},
405 {0x0331, 0x04c3},
406 {0x0332, 0x27c8},
407 {0x0333, 0xbf50},
408 {0x0334, 0x0045},
409 {0x0335, 0x0007},
410 {0x0336, 0x7418},
411 {0x0337, 0x0501},
412 {0x0338, 0x0000},
413 {0x0339, 0x0010},
414 {0x033a, 0x1010},
415 {0x03c0, 0x7e00},
416 {0x03c1, 0x8000},
417 {0x03c2, 0x8000},
418 {0x03c3, 0x8000},
419 {0x03c4, 0x8000},
420 {0x03c5, 0x8000},
421 {0x03c6, 0x8000},
422 {0x03c7, 0x8000},
423 {0x03c8, 0x8000},
424 {0x03c9, 0x8000},
425 {0x03ca, 0x8000},
426 {0x03cb, 0x8000},
427 {0x03cc, 0x8000},
428 {0x03d0, 0x0000},
429 {0x03d1, 0x0000},
430 {0x03d2, 0x0000},
431 {0x03d3, 0x0000},
432 {0x03d4, 0x2000},
433 {0x03d5, 0x2000},
434 {0x03d6, 0x0000},
435 {0x03d7, 0x0000},
436 {0x03d8, 0x2000},
437 {0x03d9, 0x2000},
438 {0x03da, 0x2000},
439 {0x03db, 0x2000},
440 {0x03dc, 0x0000},
441 {0x03dd, 0x0000},
442 {0x03de, 0x0000},
443 {0x03df, 0x2000},
444 {0x03e0, 0x0000},
445 {0x03e1, 0x0000},
446 {0x03e2, 0x0000},
447 {0x03e3, 0x0000},
448 {0x03e4, 0x0000},
449 {0x03e5, 0x0000},
450 {0x03e6, 0x0000},
451 {0x03e7, 0x0000},
452 {0x03e8, 0x0000},
453 {0x03e9, 0x0000},
454 {0x03ea, 0x0000},
455 {0x03eb, 0x0000},
456 {0x03ec, 0x0000},
457 {0x03ed, 0x0000},
458 {0x03ee, 0x0000},
459 {0x03ef, 0x0000},
460 {0x03f0, 0x0800},
461 {0x03f1, 0x0800},
462 {0x03f2, 0x0800},
463 {0x03f3, 0x0800},
464};
465
466static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
467{
468 switch (reg) {
469 case RT5665_RESET:
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
485 return true;
486 default:
487 return false;
488 }
489}
490
491static bool rt5665_readable_register(struct device *dev, unsigned int reg)
492{
493 switch (reg) {
494 case RT5665_RESET:
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
498 case RT5665_LOUT:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
507 case RT5665_IN1_IN2:
508 case RT5665_IN3_IN4:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
556 case RT5665_CAL_REC:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
571 case RT5665_PWR_VOL:
572 case RT5665_CLK_DET:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
591 case RT5665_GLB_CLK:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
594 case RT5665_ASRC_1:
595 case RT5665_ASRC_2:
596 case RT5665_ASRC_3:
597 case RT5665_ASRC_4:
598 case RT5665_ASRC_5:
599 case RT5665_ASRC_6:
600 case RT5665_ASRC_7:
601 case RT5665_ASRC_8:
602 case RT5665_ASRC_9:
603 case RT5665_ASRC_10:
604 case RT5665_DEPOP_1:
605 case RT5665_DEPOP_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
610 case RT5665_ASRC_12:
611 case RT5665_ASRC_13:
612 case RT5665_ASRC_14:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
654 case RT5665_JD1_THD:
655 case RT5665_JD2_THD:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
660 case RT5665_DUMMY_2:
661 case RT5665_DUMMY_3:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
680 case RT5665_PLL:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
884 return true;
885 default:
886 return false;
887 }
888}
889
890static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
898
899/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
908);
909
910/* Interface data select */
911static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
913};
914
915static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
917
918static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
920
921static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
923
924static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
926
927static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
929
930static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
932
933static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
935
936static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
938
939static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
941
942static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
944
945static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
947
948static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
950
951static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
953
954static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
956
957static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
959
960static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
962
963static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
965
966static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
968
969static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
971
972static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
974
975static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
977
978static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
980
981static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
983
984static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
986
987static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
989
990static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
992
993static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
995
996static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
998
999static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1004
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1010 }
1011
1012 return ret;
1013}
1014
1015static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1017{
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1020
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1026 }
1027
1028 return ret;
1029}
1030
1031/**
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1036 *
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1044 */
1045int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1047{
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1052
1053 switch (clk_src) {
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1061 break;
1062
1063 default:
1064 return -EINVAL;
1065 }
1066
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1071 }
1072
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1077 }
1078
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1083 }
1084
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1101 }
1102
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1107 }
1108
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1113 }
1114
1115 if (asrc2_mask)
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1118
1119 if (asrc3_mask)
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1122
1123 return 0;
1124}
1125EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1126
1127static int rt5665_button_detect(struct snd_soc_codec *codec)
1128{
1129 int btn_type, val;
1130
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1134
1135 return btn_type;
1136}
1137
1138static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1139 bool enable)
1140{
1141 if (enable) {
1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x000b);
1143 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1144 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1145 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1146 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1147 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1148 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1149 } else {
1150 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1151 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1152 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1153 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1154 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1155 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1156 }
1157}
1158
1159/**
1160 * rt5665_headset_detect - Detect headset.
1161 * @codec: SoC audio codec device.
1162 * @jack_insert: Jack insert or not.
1163 *
1164 * Detect whether is headset or not when jack inserted.
1165 *
1166 * Returns detect status.
1167 */
1168static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1169{
1170 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1171 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1172 unsigned int sar_hs_type, val;
1173
1174 if (jack_insert) {
1175 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1176 snd_soc_dapm_sync(dapm);
1177
1178 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1179 0x100);
1180
1181 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1182 if (val & 0x4) {
1183 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1184 0x100, 0);
1185
1186 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1187 while (val & 0x4) {
1188 usleep_range(10000, 15000);
1189 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1190 &val);
1191 }
1192 }
1193
1194 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1195 0x180, 0x180);
1196 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1197 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1198
1199 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1200 RT5665_SAR_IL_CMD_4) & 0x7ff;
1201
1202 sar_hs_type = rt5665->pdata.sar_hs_type ?
1203 rt5665->pdata.sar_hs_type : 729;
1204
1205 if (rt5665->sar_adc_value > sar_hs_type) {
1206 rt5665->jack_type = SND_JACK_HEADSET;
1207 rt5665_enable_push_button_irq(codec, true);
1208 } else {
1209 rt5665->jack_type = SND_JACK_HEADPHONE;
1210 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1211 0x2291);
1212 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1213 0x100, 0);
1214 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1215 snd_soc_dapm_sync(dapm);
1216 }
1217 } else {
1218 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1219 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1220 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1221 snd_soc_dapm_sync(dapm);
1222 if (rt5665->jack_type == SND_JACK_HEADSET)
1223 rt5665_enable_push_button_irq(codec, false);
1224 rt5665->jack_type = 0;
1225 }
1226
1227 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1228 return rt5665->jack_type;
1229}
1230
1231static irqreturn_t rt5665_irq(int irq, void *data)
1232{
1233 struct rt5665_priv *rt5665 = data;
1234
1235 mod_delayed_work(system_power_efficient_wq,
1236 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1237
1238 return IRQ_HANDLED;
1239}
1240
1241static void rt5665_jd_check_handler(struct work_struct *work)
1242{
1243 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1244 calibrate_work.work);
1245
1246 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1247 /* jack out */
1248 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1249
1250 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1251 SND_JACK_HEADSET |
1252 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1253 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1254 } else {
1255 schedule_delayed_work(&rt5665->jd_check_work, 500);
1256 }
1257}
1258
1259int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1260 struct snd_soc_jack *hs_jack)
1261{
1262 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1263
1264 switch (rt5665->pdata.jd_src) {
1265 case RT5665_JD1:
1266 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1267 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1268 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1269 0xc000, 0xc000);
1270 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1271 RT5665_PWR_JD1, RT5665_PWR_JD1);
1272 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1273 break;
1274
1275 case RT5665_JD_NULL:
1276 break;
1277
1278 default:
1279 dev_warn(codec->dev, "Wrong JD source\n");
1280 break;
1281 }
1282
1283 rt5665->hs_jack = hs_jack;
1284
1285 return 0;
1286}
1287EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
1288
1289static void rt5665_jack_detect_handler(struct work_struct *work)
1290{
1291 struct rt5665_priv *rt5665 =
1292 container_of(work, struct rt5665_priv, jack_detect_work.work);
1293 int val, btn_type;
1294
1295 while (!rt5665->codec) {
1296 pr_debug("%s codec = null\n", __func__);
1297 usleep_range(10000, 15000);
1298 }
1299
1300 while (!rt5665->codec->component.card->instantiated) {
1301 pr_debug("%s\n", __func__);
1302 usleep_range(10000, 15000);
1303 }
1304
1305 mutex_lock(&rt5665->calibrate_mutex);
1306
1307 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1308 if (!val) {
1309 /* jack in */
1310 if (rt5665->jack_type == 0) {
1311 /* jack was out, report jack type */
1312 rt5665->jack_type =
1313 rt5665_headset_detect(rt5665->codec, 1);
1314 } else {
1315 /* jack is already in, report button event */
1316 rt5665->jack_type = SND_JACK_HEADSET;
1317 btn_type = rt5665_button_detect(rt5665->codec);
1318 /**
1319 * rt5665 can report three kinds of button behavior,
1320 * one click, double click and hold. However,
1321 * currently we will report button pressed/released
1322 * event. So all the three button behaviors are
1323 * treated as button pressed.
1324 */
1325 switch (btn_type) {
1326 case 0x8000:
1327 case 0x4000:
1328 case 0x2000:
1329 rt5665->jack_type |= SND_JACK_BTN_0;
1330 break;
1331 case 0x1000:
1332 case 0x0800:
1333 case 0x0400:
1334 rt5665->jack_type |= SND_JACK_BTN_1;
1335 break;
1336 case 0x0200:
1337 case 0x0100:
1338 case 0x0080:
1339 rt5665->jack_type |= SND_JACK_BTN_2;
1340 break;
1341 case 0x0040:
1342 case 0x0020:
1343 case 0x0010:
1344 rt5665->jack_type |= SND_JACK_BTN_3;
1345 break;
1346 case 0x0000: /* unpressed */
1347 break;
1348 default:
1349 btn_type = 0;
1350 dev_err(rt5665->codec->dev,
1351 "Unexpected button code 0x%04x\n",
1352 btn_type);
1353 break;
1354 }
1355 }
1356 } else {
1357 /* jack out */
1358 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1359 }
1360
1361 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1362 SND_JACK_HEADSET |
1363 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1364 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1365
1366 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1367 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1368 schedule_delayed_work(&rt5665->jd_check_work, 0);
1369 else
1370 cancel_delayed_work_sync(&rt5665->jd_check_work);
1371
1372 mutex_unlock(&rt5665->calibrate_mutex);
1373}
1374
1375static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1376 /* Headphone Output Volume */
1377 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1378 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1379 rt5665_hp_vol_put, hp_vol_tlv),
1380
1381 /* Mono Output Volume */
1382 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1383 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1384 rt5665_mono_vol_put, mono_vol_tlv),
1385
1386 /* Output Volume */
1387 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1388 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1389
1390 /* DAC Digital Volume */
1391 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1392 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1393 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1394 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1395 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1396 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1397
1398 /* IN1/IN2/IN3/IN4 Volume */
1399 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1400 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1401 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1402 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1403 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1404 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1405 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1406 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1407 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1408 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1409
1410 /* INL/INR Volume Control */
1411 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1412 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1413
1414 /* ADC Digital Volume Control */
1415 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1416 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1417 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1418 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1419 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1420 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1421 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1422 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1423 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1424 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1425 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1426 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1427
1428 /* ADC Boost Volume Control */
1429 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1430 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1431 3, 0, adc_bst_tlv),
1432
1433 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1434 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1435 3, 0, adc_bst_tlv),
1436
1437 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1438 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1439 3, 0, adc_bst_tlv),
1440};
1441
1442/**
1443 * set_dmic_clk - Set parameter of dmic.
1444 *
1445 * @w: DAPM widget.
1446 * @kcontrol: The kcontrol of this widget.
1447 * @event: Event id.
1448 *
1449 * Choose dmic clock between 1MHz and 3MHz.
1450 * It is better for clock to approximate 3MHz.
1451 */
1452static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1453 struct snd_kcontrol *kcontrol, int event)
1454{
1455 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1456 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1457 int pd, idx = -EINVAL;
1458
1459 pd = rl6231_get_pre_div(rt5665->regmap,
1460 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1461 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1462
1463 if (idx < 0)
1464 dev_err(codec->dev, "Failed to set DMIC clock\n");
1465 else {
1466 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1467 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1468 }
1469 return idx;
1470}
1471
1472static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1473 struct snd_kcontrol *kcontrol, int event)
1474{
1475 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1476
1477 switch (event) {
1478 case SND_SOC_DAPM_PRE_PMU:
1479 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1480 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1481 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1482 break;
1483 case SND_SOC_DAPM_POST_PMD:
1484 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1485 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1486 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1487 break;
1488 default:
1489 return 0;
1490 }
1491
1492 return 0;
1493}
1494
1495static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1496 struct snd_soc_dapm_widget *sink)
1497{
1498 unsigned int val;
1499 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1500
1501 val = snd_soc_read(codec, RT5665_GLB_CLK);
1502 val &= RT5665_SCLK_SRC_MASK;
1503 if (val == RT5665_SCLK_SRC_PLL1)
1504 return 1;
1505 else
1506 return 0;
1507}
1508
1509static int is_using_asrc(struct snd_soc_dapm_widget *w,
1510 struct snd_soc_dapm_widget *sink)
1511{
1512 unsigned int reg, shift, val;
1513 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1514
1515 switch (w->shift) {
1516 case RT5665_ADC_MONO_R_ASRC_SFT:
1517 reg = RT5665_ASRC_3;
1518 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1519 break;
1520 case RT5665_ADC_MONO_L_ASRC_SFT:
1521 reg = RT5665_ASRC_3;
1522 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1523 break;
1524 case RT5665_ADC_STO1_ASRC_SFT:
1525 reg = RT5665_ASRC_3;
1526 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1527 break;
1528 case RT5665_ADC_STO2_ASRC_SFT:
1529 reg = RT5665_ASRC_3;
1530 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1531 break;
1532 case RT5665_DAC_MONO_R_ASRC_SFT:
1533 reg = RT5665_ASRC_2;
1534 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1535 break;
1536 case RT5665_DAC_MONO_L_ASRC_SFT:
1537 reg = RT5665_ASRC_2;
1538 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1539 break;
1540 case RT5665_DAC_STO1_ASRC_SFT:
1541 reg = RT5665_ASRC_2;
1542 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1543 break;
1544 case RT5665_DAC_STO2_ASRC_SFT:
1545 reg = RT5665_ASRC_2;
1546 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1547 break;
1548 default:
1549 return 0;
1550 }
1551
1552 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1553 switch (val) {
1554 case RT5665_CLK_SEL_I2S1_ASRC:
1555 case RT5665_CLK_SEL_I2S2_ASRC:
1556 case RT5665_CLK_SEL_I2S3_ASRC:
1557 /* I2S_Pre_Div1 should be 1 in asrc mode */
1558 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1559 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1560 return 1;
1561 default:
1562 return 0;
1563 }
1564
1565}
1566
1567/* Digital Mixer */
1568static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1569 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1570 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1571 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1572 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1573};
1574
1575static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1576 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1577 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1578 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1579 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1580};
1581
1582static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1583 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1584 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1585 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1586 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1587};
1588
1589static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1590 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1591 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1592 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1593 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1594};
1595
1596static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1597 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1598 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1599 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1600 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1601};
1602
1603static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1604 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1605 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1606 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1607 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1608};
1609
1610static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1611 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1612 RT5665_M_ADCMIX_L_SFT, 1, 1),
1613 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1614 RT5665_M_DAC1_L_SFT, 1, 1),
1615};
1616
1617static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1618 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1619 RT5665_M_ADCMIX_R_SFT, 1, 1),
1620 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1621 RT5665_M_DAC1_R_SFT, 1, 1),
1622};
1623
1624static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1625 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1626 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1627 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1628 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1629 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1630 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1632 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1633};
1634
1635static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1636 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1637 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1639 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1642 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1643 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1644};
1645
1646static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1647 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1648 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1650 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1652 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1653};
1654
1655static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1656 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1657 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1658 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1659 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1662};
1663
1664static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1665 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1666 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1667 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1668 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1670 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1672 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1673};
1674
1675static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1676 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1677 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1679 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1683 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1684};
1685
1686/* Analog Input Mixer */
1687static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1688 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1689 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1690 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1691 RT5665_M_INL_RM1_L_SFT, 1, 1),
1692 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1693 RT5665_M_INR_RM1_L_SFT, 1, 1),
1694 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1695 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1696 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1697 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1698 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1699 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1700 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1701 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1702};
1703
1704static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1705 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1706 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1707 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1708 RT5665_M_INR_RM1_R_SFT, 1, 1),
1709 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1710 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1711 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1712 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1713 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1714 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1715 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1716 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1717};
1718
1719static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1720 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1721 RT5665_M_INL_RM2_L_SFT, 1, 1),
1722 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1723 RT5665_M_INR_RM2_L_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1725 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1727 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1728 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1729 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1730 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1731 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1732 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1733 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1734};
1735
1736static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1737 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1738 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1740 RT5665_M_INL_RM2_R_SFT, 1, 1),
1741 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1742 RT5665_M_INR_RM2_R_SFT, 1, 1),
1743 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1744 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1745 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1746 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1747 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1748 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1749 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1750 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1751};
1752
1753static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1754 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1755 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1756 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1757 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1758 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1759 RT5665_M_BST1_MM_SFT, 1, 1),
1760 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1761 RT5665_M_BST2_MM_SFT, 1, 1),
1762 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1763 RT5665_M_BST3_MM_SFT, 1, 1),
1764};
1765
1766static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1767 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1768 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1770 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1772 RT5665_M_BST1_OM_L_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1774 RT5665_M_BST2_OM_L_SFT, 1, 1),
1775 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1776 RT5665_M_BST3_OM_L_SFT, 1, 1),
1777};
1778
1779static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1780 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1781 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1783 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1785 RT5665_M_BST2_OM_R_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1787 RT5665_M_BST3_OM_R_SFT, 1, 1),
1788 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1789 RT5665_M_BST4_OM_R_SFT, 1, 1),
1790};
1791
1792static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1793 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1794 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1796 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1797};
1798
1799static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1800 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1801 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1802 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1803 RT5665_M_OV_L_LM_SFT, 1, 1),
1804};
1805
1806static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1807 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1808 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1809 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1810 RT5665_M_OV_R_LM_SFT, 1, 1),
1811};
1812
1813/*DAC L2, DAC R2*/
1814/*MX-17 [6:4], MX-17 [2:0]*/
1815static const char * const rt5665_dac2_src[] = {
1816 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1817};
1818
1819static const SOC_ENUM_SINGLE_DECL(
1820 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1821 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1822
1823static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1824 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1825
1826static const SOC_ENUM_SINGLE_DECL(
1827 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1828 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1829
1830static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1831 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1832
1833/*DAC L3, DAC R3*/
1834/*MX-1B [6:4], MX-1B [2:0]*/
1835static const char * const rt5665_dac3_src[] = {
1836 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1837};
1838
1839static const SOC_ENUM_SINGLE_DECL(
1840 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1841 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1842
1843static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1844 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1845
1846static const SOC_ENUM_SINGLE_DECL(
1847 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1848 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1849
1850static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1851 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1852
1853/* STO1 ADC1 Source */
1854/* MX-26 [13] [5] */
1855static const char * const rt5665_sto1_adc1_src[] = {
1856 "DD Mux", "ADC"
1857};
1858
1859static const SOC_ENUM_SINGLE_DECL(
1860 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1861 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1862
1863static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1864 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1865
1866static const SOC_ENUM_SINGLE_DECL(
1867 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1868 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1869
1870static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1871 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1872
1873/* STO1 ADC Source */
1874/* MX-26 [11:10] [3:2] */
1875static const char * const rt5665_sto1_adc_src[] = {
1876 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1877};
1878
1879static const SOC_ENUM_SINGLE_DECL(
1880 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1881 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1882
1883static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1884 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1885
1886static const SOC_ENUM_SINGLE_DECL(
1887 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1888 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1889
1890static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1891 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1892
1893/* STO1 ADC2 Source */
1894/* MX-26 [12] [4] */
1895static const char * const rt5665_sto1_adc2_src[] = {
1896 "DAC MIX", "DMIC"
1897};
1898
1899static const SOC_ENUM_SINGLE_DECL(
1900 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1901 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1902
1903static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1904 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1905
1906static const SOC_ENUM_SINGLE_DECL(
1907 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1908 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1909
1910static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1911 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1912
1913/* STO1 DMIC Source */
1914/* MX-26 [8] */
1915static const char * const rt5665_sto1_dmic_src[] = {
1916 "DMIC1", "DMIC2"
1917};
1918
1919static const SOC_ENUM_SINGLE_DECL(
1920 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1921 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1922
1923static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1924 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1925
1926/* MX-26 [9] */
1927static const char * const rt5665_sto1_dd_l_src[] = {
1928 "STO2 DAC", "MONO DAC"
1929};
1930
1931static const SOC_ENUM_SINGLE_DECL(
1932 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1933 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1934
1935static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1936 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1937
1938/* MX-26 [1:0] */
1939static const char * const rt5665_sto1_dd_r_src[] = {
1940 "STO2 DAC", "MONO DAC", "AEC REF"
1941};
1942
1943static const SOC_ENUM_SINGLE_DECL(
1944 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1945 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1946
1947static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1948 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1949
1950/* MONO ADC L2 Source */
1951/* MX-27 [12] */
1952static const char * const rt5665_mono_adc_l2_src[] = {
1953 "DAC MIXL", "DMIC"
1954};
1955
1956static const SOC_ENUM_SINGLE_DECL(
1957 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1958 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1959
1960static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1961 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1962
1963
1964/* MONO ADC L1 Source */
1965/* MX-27 [13] */
1966static const char * const rt5665_mono_adc_l1_src[] = {
1967 "DD Mux", "ADC"
1968};
1969
1970static const SOC_ENUM_SINGLE_DECL(
1971 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1972 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1973
1974static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1975 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1976
1977/* MX-27 [9][1]*/
1978static const char * const rt5665_mono_dd_src[] = {
1979 "STO2 DAC", "MONO DAC"
1980};
1981
1982static const SOC_ENUM_SINGLE_DECL(
1983 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1984 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1985
1986static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1987 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1988
1989static const SOC_ENUM_SINGLE_DECL(
1990 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1991 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1992
1993static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1994 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1995
1996/* MONO ADC L Source, MONO ADC R Source*/
1997/* MX-27 [11:10], MX-27 [3:2] */
1998static const char * const rt5665_mono_adc_src[] = {
1999 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2000};
2001
2002static const SOC_ENUM_SINGLE_DECL(
2003 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2004 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2005
2006static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2007 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2008
2009static const SOC_ENUM_SINGLE_DECL(
2010 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2011 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2012
2013static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2014 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2015
2016/* MONO DMIC L Source */
2017/* MX-27 [8] */
2018static const char * const rt5665_mono_dmic_l_src[] = {
2019 "DMIC1 L", "DMIC2 L"
2020};
2021
2022static const SOC_ENUM_SINGLE_DECL(
2023 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2024 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2025
2026static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2027 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2028
2029/* MONO ADC R2 Source */
2030/* MX-27 [4] */
2031static const char * const rt5665_mono_adc_r2_src[] = {
2032 "DAC MIXR", "DMIC"
2033};
2034
2035static const SOC_ENUM_SINGLE_DECL(
2036 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2037 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2038
2039static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2040 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2041
2042/* MONO ADC R1 Source */
2043/* MX-27 [5] */
2044static const char * const rt5665_mono_adc_r1_src[] = {
2045 "DD Mux", "ADC"
2046};
2047
2048static const SOC_ENUM_SINGLE_DECL(
2049 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2050 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2051
2052static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2053 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2054
2055/* MONO DMIC R Source */
2056/* MX-27 [0] */
2057static const char * const rt5665_mono_dmic_r_src[] = {
2058 "DMIC1 R", "DMIC2 R"
2059};
2060
2061static const SOC_ENUM_SINGLE_DECL(
2062 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2063 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2064
2065static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2066 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2067
2068
2069/* STO2 ADC1 Source */
2070/* MX-28 [13] [5] */
2071static const char * const rt5665_sto2_adc1_src[] = {
2072 "DD Mux", "ADC"
2073};
2074
2075static const SOC_ENUM_SINGLE_DECL(
2076 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2077 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2078
2079static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2080 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2081
2082static const SOC_ENUM_SINGLE_DECL(
2083 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2084 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2085
2086static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2087 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2088
2089/* STO2 ADC Source */
2090/* MX-28 [11:10] [3:2] */
2091static const char * const rt5665_sto2_adc_src[] = {
2092 "ADC1 L", "ADC1 R", "ADC2 L"
2093};
2094
2095static const SOC_ENUM_SINGLE_DECL(
2096 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2097 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2098
2099static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2100 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2101
2102static const SOC_ENUM_SINGLE_DECL(
2103 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2104 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2105
2106static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2107 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2108
2109/* STO2 ADC2 Source */
2110/* MX-28 [12] [4] */
2111static const char * const rt5665_sto2_adc2_src[] = {
2112 "DAC MIX", "DMIC"
2113};
2114
2115static const SOC_ENUM_SINGLE_DECL(
2116 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2117 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2118
2119static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2120 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2121
2122static const SOC_ENUM_SINGLE_DECL(
2123 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2124 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2125
2126static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2127 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2128
2129/* STO2 DMIC Source */
2130/* MX-28 [8] */
2131static const char * const rt5665_sto2_dmic_src[] = {
2132 "DMIC1", "DMIC2"
2133};
2134
2135static const SOC_ENUM_SINGLE_DECL(
2136 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2137 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2138
2139static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2140 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2141
2142/* MX-28 [9] */
2143static const char * const rt5665_sto2_dd_l_src[] = {
2144 "STO2 DAC", "MONO DAC"
2145};
2146
2147static const SOC_ENUM_SINGLE_DECL(
2148 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2149 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2150
2151static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2152 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2153
2154/* MX-28 [1] */
2155static const char * const rt5665_sto2_dd_r_src[] = {
2156 "STO2 DAC", "MONO DAC"
2157};
2158
2159static const SOC_ENUM_SINGLE_DECL(
2160 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2161 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2162
2163static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2164 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2165
2166/* DAC R1 Source, DAC L1 Source*/
2167/* MX-29 [11:10], MX-29 [9:8]*/
2168static const char * const rt5665_dac1_src[] = {
2169 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2170};
2171
2172static const SOC_ENUM_SINGLE_DECL(
2173 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2174 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2175
2176static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2177 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2178
2179static const SOC_ENUM_SINGLE_DECL(
2180 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2181 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2182
2183static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2184 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2185
2186/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2187/* MX-2D [13:12], MX-2D [9:8]*/
2188static const char * const rt5665_dig_dac_mix_src[] = {
2189 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2190};
2191
2192static const SOC_ENUM_SINGLE_DECL(
2193 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2194 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2195
2196static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2197 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2198
2199static const SOC_ENUM_SINGLE_DECL(
2200 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2201 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2202
2203static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2204 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2205
2206/* Analog DAC L1 Source, Analog DAC R1 Source*/
2207/* MX-2D [5:4], MX-2D [1:0]*/
2208static const char * const rt5665_alg_dac1_src[] = {
2209 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2210};
2211
2212static const SOC_ENUM_SINGLE_DECL(
2213 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2214 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2215
2216static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2217 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2218
2219static const SOC_ENUM_SINGLE_DECL(
2220 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2221 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2222
2223static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2224 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2225
2226/* Analog DAC LR Source, Analog DAC R2 Source*/
2227/* MX-2E [5:4], MX-2E [0]*/
2228static const char * const rt5665_alg_dac2_src[] = {
2229 "Mono DAC Mixer", "DAC2"
2230};
2231
2232static const SOC_ENUM_SINGLE_DECL(
2233 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2234 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2235
2236static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2237 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2238
2239static const SOC_ENUM_SINGLE_DECL(
2240 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2241 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2242
2243static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2244 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2245
2246/* Interface2 ADC Data Input*/
2247/* MX-2F [14:12] */
2248static const char * const rt5665_if2_1_adc_in_src[] = {
2249 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2250 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2251};
2252
2253static const SOC_ENUM_SINGLE_DECL(
2254 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2255 RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2256
2257static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2258 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2259
2260/* MX-2F [6:4] */
2261static const char * const rt5665_if2_2_adc_in_src[] = {
2262 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2263 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2264};
2265
2266static const SOC_ENUM_SINGLE_DECL(
2267 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2268 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2269
2270static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2271 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2272
2273/* Interface3 ADC Data Input*/
2274/* MX-30 [6:4] */
2275static const char * const rt5665_if3_adc_in_src[] = {
2276 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2277 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2278};
2279
2280static const SOC_ENUM_SINGLE_DECL(
2281 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2282 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2283
2284static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2285 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2286
2287/* PDM 1 L/R*/
2288/* MX-31 [11:10] [9:8] */
2289static const char * const rt5665_pdm_src[] = {
2290 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2291};
2292
2293static const SOC_ENUM_SINGLE_DECL(
2294 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2295 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2296
2297static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2298 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2299
2300static const SOC_ENUM_SINGLE_DECL(
2301 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2302 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2303
2304static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2305 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2306
2307
2308/* I2S1 TDM ADCDAT Source */
2309/* MX-7a[10] */
2310static const char * const rt5665_if1_1_adc1_data_src[] = {
2311 "STO1 ADC", "IF2_1 DAC",
2312};
2313
2314static const SOC_ENUM_SINGLE_DECL(
2315 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2316 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2317
2318static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2319 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2320
2321/* MX-7a[9] */
2322static const char * const rt5665_if1_1_adc2_data_src[] = {
2323 "STO2 ADC", "IF2_2 DAC",
2324};
2325
2326static const SOC_ENUM_SINGLE_DECL(
2327 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2328 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2329
2330static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2331 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2332
2333/* MX-7a[8] */
2334static const char * const rt5665_if1_1_adc3_data_src[] = {
2335 "MONO ADC", "IF3 DAC",
2336};
2337
2338static const SOC_ENUM_SINGLE_DECL(
2339 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2340 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2341
2342static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2343 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2344
2345/* MX-7b[10] */
2346static const char * const rt5665_if1_2_adc1_data_src[] = {
2347 "STO1 ADC", "IF1 DAC",
2348};
2349
2350static const SOC_ENUM_SINGLE_DECL(
2351 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2352 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2353
2354static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2355 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2356
2357/* MX-7b[9] */
2358static const char * const rt5665_if1_2_adc2_data_src[] = {
2359 "STO2 ADC", "IF2_1 DAC",
2360};
2361
2362static const SOC_ENUM_SINGLE_DECL(
2363 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2364 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2365
2366static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2367 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2368
2369/* MX-7b[8] */
2370static const char * const rt5665_if1_2_adc3_data_src[] = {
2371 "MONO ADC", "IF2_2 DAC",
2372};
2373
2374static const SOC_ENUM_SINGLE_DECL(
2375 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2376 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2377
2378static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2379 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2380
2381/* MX-7b[7] */
2382static const char * const rt5665_if1_2_adc4_data_src[] = {
2383 "DAC1", "IF3 DAC",
2384};
2385
2386static const SOC_ENUM_SINGLE_DECL(
2387 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2388 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2389
2390static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2391 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2392
2393/* MX-7a[4:0] MX-7b[4:0] */
2394static const char * const rt5665_tdm_adc_data_src[] = {
2395 "1234", "1243", "1324", "1342", "1432", "1423",
2396 "2134", "2143", "2314", "2341", "2431", "2413",
2397 "3124", "3142", "3214", "3241", "3412", "3421",
2398 "4123", "4132", "4213", "4231", "4312", "4321"
2399};
2400
2401static const SOC_ENUM_SINGLE_DECL(
2402 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2403 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2404
2405static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2406 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2407
2408static const SOC_ENUM_SINGLE_DECL(
2409 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2410 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2411
2412static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2413 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2414
2415/* Out Volume Switch */
2416static const struct snd_kcontrol_new monovol_switch =
2417 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2418
2419static const struct snd_kcontrol_new outvol_l_switch =
2420 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2421
2422static const struct snd_kcontrol_new outvol_r_switch =
2423 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2424
2425/* Out Switch */
2426static const struct snd_kcontrol_new mono_switch =
2427 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2428
2429static const struct snd_kcontrol_new hpo_switch =
2430 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2431 RT5665_VOL_L_SFT, 1, 0);
2432
2433static const struct snd_kcontrol_new lout_l_switch =
2434 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2435
2436static const struct snd_kcontrol_new lout_r_switch =
2437 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2438
2439static const struct snd_kcontrol_new pdm_l_switch =
2440 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2441 RT5665_M_PDM1_L_SFT, 1, 1);
2442
2443static const struct snd_kcontrol_new pdm_r_switch =
2444 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2445 RT5665_M_PDM1_R_SFT, 1, 1);
2446
2447static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2448 struct snd_kcontrol *kcontrol, int event)
2449{
2450 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2451
2452 switch (event) {
2453 case SND_SOC_DAPM_PRE_PMU:
2454 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2455 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2456 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2457 0x0);
2458 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2459 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2460 break;
2461
2462 case SND_SOC_DAPM_POST_PMD:
2463 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2464 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2465 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2466 0x40);
2467 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2468 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2469 break;
2470
2471 default:
2472 return 0;
2473 }
2474
2475 return 0;
2476
2477}
2478
2479static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2480 struct snd_kcontrol *kcontrol, int event)
2481{
2482 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2483
2484 switch (event) {
2485 case SND_SOC_DAPM_PRE_PMU:
2486 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2487 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2488 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2489 break;
2490
2491 case SND_SOC_DAPM_POST_PMD:
2492 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2493 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2494 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2495 break;
2496
2497 default:
2498 return 0;
2499 }
2500
2501 return 0;
2502
2503}
2504
2505static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2506 struct snd_kcontrol *kcontrol, int event)
2507{
2508 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2509
2510 switch (event) {
2511 case SND_SOC_DAPM_POST_PMU:
2512 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2513 RT5665_PUMP_EN, RT5665_PUMP_EN);
2514 break;
2515
2516 case SND_SOC_DAPM_PRE_PMD:
2517 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2518 RT5665_PUMP_EN, 0);
2519 break;
2520
2521 default:
2522 return 0;
2523 }
2524
2525 return 0;
2526
2527}
2528
2529static int set_dmic_power(struct snd_soc_dapm_widget *w,
2530 struct snd_kcontrol *kcontrol, int event)
2531{
2532 switch (event) {
2533 case SND_SOC_DAPM_POST_PMU:
2534 /*Add delay to avoid pop noise*/
2535 msleep(150);
2536 break;
2537
2538 default:
2539 return 0;
2540 }
2541
2542 return 0;
2543}
2544
2545static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2546 struct snd_kcontrol *kcontrol, int event)
2547{
2548 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2549
2550 switch (event) {
2551 case SND_SOC_DAPM_PRE_PMU:
2552 switch (w->shift) {
2553 case RT5665_PWR_VREF1_BIT:
2554 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2555 RT5665_PWR_FV1, 0);
2556 break;
2557
2558 case RT5665_PWR_VREF2_BIT:
2559 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2560 RT5665_PWR_FV2, 0);
2561 break;
2562
2563 case RT5665_PWR_VREF3_BIT:
2564 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2565 RT5665_PWR_FV3, 0);
2566 break;
2567
2568 default:
2569 break;
2570 }
2571 break;
2572
2573 case SND_SOC_DAPM_POST_PMU:
2574 usleep_range(15000, 20000);
2575 switch (w->shift) {
2576 case RT5665_PWR_VREF1_BIT:
2577 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2578 RT5665_PWR_FV1, RT5665_PWR_FV1);
2579 break;
2580
2581 case RT5665_PWR_VREF2_BIT:
2582 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2583 RT5665_PWR_FV2, RT5665_PWR_FV2);
2584 break;
2585
2586 case RT5665_PWR_VREF3_BIT:
2587 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2588 RT5665_PWR_FV3, RT5665_PWR_FV3);
2589 break;
2590
2591 default:
2592 break;
2593 }
2594 break;
2595
2596 default:
2597 return 0;
2598 }
2599
2600 return 0;
2601}
2602
2603
2604static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2605 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2606 NULL, 0),
2607 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2608 NULL, 0),
2609 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2610 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2612 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2613 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2614 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2615 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2616 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2617
2618 /* ASRC */
2619 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2620 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2621 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2622 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2623 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2624 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2625 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2626 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2627 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2628 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2629 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2630 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2631 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2632 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2633 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2634 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2635 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2636 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2638 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2640 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2642 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2643 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2644 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2645 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2646 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2647
2648 /* Input Side */
2649 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2650 0, NULL, 0),
2651 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2652 0, NULL, 0),
2653 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2654 0, NULL, 0),
2655
2656 /* Input Lines */
2657 SND_SOC_DAPM_INPUT("DMIC L1"),
2658 SND_SOC_DAPM_INPUT("DMIC R1"),
2659 SND_SOC_DAPM_INPUT("DMIC L2"),
2660 SND_SOC_DAPM_INPUT("DMIC R2"),
2661
2662 SND_SOC_DAPM_INPUT("IN1P"),
2663 SND_SOC_DAPM_INPUT("IN1N"),
2664 SND_SOC_DAPM_INPUT("IN2P"),
2665 SND_SOC_DAPM_INPUT("IN2N"),
2666 SND_SOC_DAPM_INPUT("IN3P"),
2667 SND_SOC_DAPM_INPUT("IN3N"),
2668 SND_SOC_DAPM_INPUT("IN4P"),
2669 SND_SOC_DAPM_INPUT("IN4N"),
2670
2671 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2673
2674 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2675 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2676 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2677 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2678 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2679 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2680
2681 /* Boost */
2682 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2683 0, 0, NULL, 0),
2684 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2685 0, 0, NULL, 0),
2686 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2687 0, 0, NULL, 0),
2688 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2689 0, 0, NULL, 0),
2690 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2691 0, 0, NULL, 0),
2692 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2693 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2694 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2695 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2696 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2697 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2699 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2701 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2703 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2705 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2707 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2709 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2710
2711
2712 /* Input Volume */
2713 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2714 0, NULL, 0),
2715 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2716 0, NULL, 0),
2717
2718 /* REC Mixer */
2719 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2720 ARRAY_SIZE(rt5665_rec1_l_mix)),
2721 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2722 ARRAY_SIZE(rt5665_rec1_r_mix)),
2723 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2724 ARRAY_SIZE(rt5665_rec2_l_mix)),
2725 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2726 ARRAY_SIZE(rt5665_rec2_r_mix)),
2727 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2728 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2729 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2730 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2731 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2732 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2733 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2734 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2735
2736 /* ADCs */
2737 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2738 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2739 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2740 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2741
2742 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2743 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2744 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2745 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2746 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2747 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2749 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2751 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2753 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2754
2755 /* ADC Mux */
2756 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2757 &rt5665_sto1_dmic_mux),
2758 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2759 &rt5665_sto1_dmic_mux),
2760 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5665_sto1_adc1l_mux),
2762 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2763 &rt5665_sto1_adc1r_mux),
2764 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2765 &rt5665_sto1_adc2l_mux),
2766 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2767 &rt5665_sto1_adc2r_mux),
2768 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2769 &rt5665_sto1_adcl_mux),
2770 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2771 &rt5665_sto1_adcr_mux),
2772 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2773 &rt5665_sto1_dd_l_mux),
2774 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2775 &rt5665_sto1_dd_r_mux),
2776 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2777 &rt5665_mono_adc_l2_mux),
2778 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2779 &rt5665_mono_adc_r2_mux),
2780 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2781 &rt5665_mono_adc_l1_mux),
2782 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2783 &rt5665_mono_adc_r1_mux),
2784 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2785 &rt5665_mono_dmic_l_mux),
2786 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2787 &rt5665_mono_dmic_r_mux),
2788 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2789 &rt5665_mono_adc_l_mux),
2790 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2791 &rt5665_mono_adc_r_mux),
2792 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2793 &rt5665_mono_dd_l_mux),
2794 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2795 &rt5665_mono_dd_r_mux),
2796 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2797 &rt5665_sto2_dmic_mux),
2798 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2799 &rt5665_sto2_dmic_mux),
2800 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2801 &rt5665_sto2_adc1l_mux),
2802 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5665_sto2_adc1r_mux),
2804 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5665_sto2_adc2l_mux),
2806 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5665_sto2_adc2r_mux),
2808 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5665_sto2_adcl_mux),
2810 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5665_sto2_adcr_mux),
2812 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5665_sto2_dd_l_mux),
2814 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5665_sto2_dd_r_mux),
2816 /* ADC Mixer */
2817 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2818 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2819 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2820 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2821 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2822 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2823 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2824 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2825 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2826 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2827 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2828 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2829 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2830 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2831 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2832 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2833 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2834 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2835 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2836 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2837 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2838 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2839 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2840 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2841 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2842 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2843
2844 /* ADC PGA */
2845 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2848
2849 /* Digital Interface */
2850 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2851 0, NULL, 0),
2852 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2853 0, NULL, 0),
2854 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2855 0, NULL, 0),
2856 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2857 0, NULL, 0),
2858 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2859 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2869
2870 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2878
2879 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2883
2884 /* Digital Interface Select */
2885 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2886 &rt5665_if1_1_adc1_mux),
2887 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2888 &rt5665_if1_1_adc2_mux),
2889 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2890 &rt5665_if1_1_adc3_mux),
2891 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2893 &rt5665_if1_2_adc1_mux),
2894 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2895 &rt5665_if1_2_adc2_mux),
2896 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2897 &rt5665_if1_2_adc3_mux),
2898 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2899 &rt5665_if1_2_adc4_mux),
2900 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2901 &rt5665_tdm1_adc_mux),
2902 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2903 &rt5665_tdm1_adc_mux),
2904 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2905 &rt5665_tdm1_adc_mux),
2906 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2907 &rt5665_tdm1_adc_mux),
2908 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2909 &rt5665_tdm2_adc_mux),
2910 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5665_tdm2_adc_mux),
2912 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5665_tdm2_adc_mux),
2914 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5665_tdm2_adc_mux),
2916 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5665_if2_1_adc_in_mux),
2918 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5665_if2_2_adc_in_mux),
2920 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5665_if3_adc_in_mux),
2922 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5665_if1_1_01_adc_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5665_if1_1_01_adc_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5665_if1_1_23_adc_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5665_if1_1_23_adc_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5665_if1_1_45_adc_swap_mux),
2932 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5665_if1_1_45_adc_swap_mux),
2934 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5665_if1_1_67_adc_swap_mux),
2936 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5665_if1_1_67_adc_swap_mux),
2938 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5665_if1_2_01_adc_swap_mux),
2940 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5665_if1_2_01_adc_swap_mux),
2942 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if1_2_23_adc_swap_mux),
2944 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if1_2_23_adc_swap_mux),
2946 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5665_if1_2_45_adc_swap_mux),
2948 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5665_if1_2_45_adc_swap_mux),
2950 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5665_if1_2_67_adc_swap_mux),
2952 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_2_67_adc_swap_mux),
2954 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if2_1_dac_swap_mux),
2956 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_if2_1_adc_swap_mux),
2958 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5665_if2_2_dac_swap_mux),
2960 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5665_if2_2_adc_swap_mux),
2962 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5665_if3_dac_swap_mux),
2964 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5665_if3_adc_swap_mux),
2966
2967 /* Audio Interface */
2968 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
2969 0, SND_SOC_NOPM, 0, 0),
2970 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
2971 1, SND_SOC_NOPM, 0, 0),
2972 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2973 2, SND_SOC_NOPM, 0, 0),
2974 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
2975 3, SND_SOC_NOPM, 0, 0),
2976 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
2977 4, SND_SOC_NOPM, 0, 0),
2978 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
2979 5, SND_SOC_NOPM, 0, 0),
2980 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
2981 6, SND_SOC_NOPM, 0, 0),
2982 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
2983 7, SND_SOC_NOPM, 0, 0),
2984 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
2985 0, SND_SOC_NOPM, 0, 0),
2986 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
2987 1, SND_SOC_NOPM, 0, 0),
2988 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2989 2, SND_SOC_NOPM, 0, 0),
2990 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
2991 3, SND_SOC_NOPM, 0, 0),
2992 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
2993 4, SND_SOC_NOPM, 0, 0),
2994 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
2995 5, SND_SOC_NOPM, 0, 0),
2996 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
2997 6, SND_SOC_NOPM, 0, 0),
2998 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
2999 7, SND_SOC_NOPM, 0, 0),
3000 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3001 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3003 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3005 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3007 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3009 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3011 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3013 0, SND_SOC_NOPM, 0, 0),
3014
3015 /* Output Side */
3016 /* DAC mixer before sound effect */
3017 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3018 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3019 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3020 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3021
3022 /* DAC channel Mux */
3023 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3024 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3025 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3026 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3027 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3028 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3029
3030 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3031 &rt5665_alg_dac_l1_mux),
3032 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3033 &rt5665_alg_dac_r1_mux),
3034 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3035 &rt5665_alg_dac_l2_mux),
3036 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3037 &rt5665_alg_dac_r2_mux),
3038
3039 /* DAC Mixer */
3040 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3041 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3042 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3043 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3044 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3045 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3046 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3047 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3048 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3049 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3050 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3051 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3052 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3053 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3054 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3055 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3056 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3057 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3058 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3059 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3060 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3061 &rt5665_dig_dac_mixl_mux),
3062 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3063 &rt5665_dig_dac_mixr_mux),
3064
3065 /* DACs */
3066 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3068
3069 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3070 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3071 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3072 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3073 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3074 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3075 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3076
3077 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3078 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3079 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3080 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3081
3082 /* OUT Mixer */
3083 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3084 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3085 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3086 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3087 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3088 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3089
3090 /* Output Volume */
3091 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3092 &monovol_switch),
3093 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3094 &outvol_l_switch),
3095 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3096 &outvol_r_switch),
3097
3098 /* MONO/HPO/LOUT */
3099 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3100 ARRAY_SIZE(rt5665_mono_mix)),
3101 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3102 ARRAY_SIZE(rt5665_lout_l_mix)),
3103 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3104 ARRAY_SIZE(rt5665_lout_r_mix)),
3105 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3106 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3107 SND_SOC_DAPM_PRE_PMU),
3108 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3109 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3110 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3111 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3113 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3114
3115 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3116 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3117 SND_SOC_DAPM_POST_PMD),
3118
3119 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3120 &mono_switch),
3121 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3122 &hpo_switch),
3123 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3124 &lout_l_switch),
3125 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3126 &lout_r_switch),
3127 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3128 &pdm_l_switch),
3129 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3130 &pdm_r_switch),
3131
3132 /* PDM */
3133 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3134 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3135 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3136 0, 1, &rt5665_pdm_l_mux),
3137 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3138 0, 1, &rt5665_pdm_r_mux),
3139
3140 /* CLK DET */
3141 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3142 0, NULL, 0),
3143 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3144 0, NULL, 0),
3145 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3146 0, NULL, 0),
3147 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3148 0, NULL, 0),
3149 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3150 0, NULL, 0),
3151
3152 /* Output Lines */
3153 SND_SOC_DAPM_OUTPUT("HPOL"),
3154 SND_SOC_DAPM_OUTPUT("HPOR"),
3155 SND_SOC_DAPM_OUTPUT("LOUTL"),
3156 SND_SOC_DAPM_OUTPUT("LOUTR"),
3157 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3158 SND_SOC_DAPM_OUTPUT("PDML"),
3159 SND_SOC_DAPM_OUTPUT("PDMR"),
3160};
3161
3162static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3163 /*PLL*/
3164 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3165 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3166 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3167 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3168 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3169 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3170 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3171 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3172
3173 /*ASRC*/
3174 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3175 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3176 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3177 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3178 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3179 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3180 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3181
3182 /*Vref*/
3183 {"Mic Det Power", NULL, "Vref2"},
3184 {"MICBIAS1", NULL, "Vref1"},
3185 {"MICBIAS1", NULL, "Vref2"},
3186 {"MICBIAS2", NULL, "Vref1"},
3187 {"MICBIAS2", NULL, "Vref2"},
3188 {"MICBIAS3", NULL, "Vref1"},
3189 {"MICBIAS3", NULL, "Vref2"},
3190
3191 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3192 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3193 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3194 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3195 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3196 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3197
3198 {"I2S1_1", NULL, "I2S1 ASRC"},
3199 {"I2S1_2", NULL, "I2S1 ASRC"},
3200 {"I2S2_1", NULL, "I2S2 ASRC"},
3201 {"I2S2_2", NULL, "I2S2 ASRC"},
3202 {"I2S3", NULL, "I2S3 ASRC"},
3203
3204 {"CLKDET SYS", NULL, "CLKDET"},
3205 {"CLKDET HP", NULL, "CLKDET"},
3206 {"CLKDET MONO", NULL, "CLKDET"},
3207 {"CLKDET LOUT", NULL, "CLKDET"},
3208
3209 {"IN1P", NULL, "LDO2"},
3210 {"IN2P", NULL, "LDO2"},
3211 {"IN3P", NULL, "LDO2"},
3212 {"IN4P", NULL, "LDO2"},
3213
3214 {"DMIC1", NULL, "DMIC L1"},
3215 {"DMIC1", NULL, "DMIC R1"},
3216 {"DMIC2", NULL, "DMIC L2"},
3217 {"DMIC2", NULL, "DMIC R2"},
3218
3219 {"BST1", NULL, "IN1P"},
3220 {"BST1", NULL, "IN1N"},
3221 {"BST1", NULL, "BST1 Power"},
3222 {"BST1", NULL, "BST1P Power"},
3223 {"BST2", NULL, "IN2P"},
3224 {"BST2", NULL, "IN2N"},
3225 {"BST2", NULL, "BST2 Power"},
3226 {"BST2", NULL, "BST2P Power"},
3227 {"BST3", NULL, "IN3P"},
3228 {"BST3", NULL, "IN3N"},
3229 {"BST3", NULL, "BST3 Power"},
3230 {"BST3", NULL, "BST3P Power"},
3231 {"BST4", NULL, "IN4P"},
3232 {"BST4", NULL, "IN4N"},
3233 {"BST4", NULL, "BST4 Power"},
3234 {"BST4", NULL, "BST4P Power"},
3235 {"BST1 CBJ", NULL, "IN1P"},
3236 {"BST1 CBJ", NULL, "IN1N"},
3237 {"BST1 CBJ", NULL, "CBJ Power"},
3238 {"CBJ Power", NULL, "Vref2"},
3239
3240 {"INL VOL", NULL, "IN3P"},
3241 {"INR VOL", NULL, "IN3N"},
3242
3243 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3244 {"RECMIX1L", "INL Switch", "INL VOL"},
3245 {"RECMIX1L", "INR Switch", "INR VOL"},
3246 {"RECMIX1L", "BST4 Switch", "BST4"},
3247 {"RECMIX1L", "BST3 Switch", "BST3"},
3248 {"RECMIX1L", "BST2 Switch", "BST2"},
3249 {"RECMIX1L", "BST1 Switch", "BST1"},
3250 {"RECMIX1L", NULL, "RECMIX1L Power"},
3251
3252 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3253 {"RECMIX1R", "INR Switch", "INR VOL"},
3254 {"RECMIX1R", "BST4 Switch", "BST4"},
3255 {"RECMIX1R", "BST3 Switch", "BST3"},
3256 {"RECMIX1R", "BST2 Switch", "BST2"},
3257 {"RECMIX1R", "BST1 Switch", "BST1"},
3258 {"RECMIX1R", NULL, "RECMIX1R Power"},
3259
3260 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3261 {"RECMIX2L", "INL Switch", "INL VOL"},
3262 {"RECMIX2L", "INR Switch", "INR VOL"},
3263 {"RECMIX2L", "BST4 Switch", "BST4"},
3264 {"RECMIX2L", "BST3 Switch", "BST3"},
3265 {"RECMIX2L", "BST2 Switch", "BST2"},
3266 {"RECMIX2L", "BST1 Switch", "BST1"},
3267 {"RECMIX2L", NULL, "RECMIX2L Power"},
3268
3269 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3270 {"RECMIX2R", "INL Switch", "INL VOL"},
3271 {"RECMIX2R", "INR Switch", "INR VOL"},
3272 {"RECMIX2R", "BST4 Switch", "BST4"},
3273 {"RECMIX2R", "BST3 Switch", "BST3"},
3274 {"RECMIX2R", "BST2 Switch", "BST2"},
3275 {"RECMIX2R", "BST1 Switch", "BST1"},
3276 {"RECMIX2R", NULL, "RECMIX2R Power"},
3277
3278 {"ADC1 L", NULL, "RECMIX1L"},
3279 {"ADC1 L", NULL, "ADC1 L Power"},
3280 {"ADC1 L", NULL, "ADC1 clock"},
3281 {"ADC1 R", NULL, "RECMIX1R"},
3282 {"ADC1 R", NULL, "ADC1 R Power"},
3283 {"ADC1 R", NULL, "ADC1 clock"},
3284
3285 {"ADC2 L", NULL, "RECMIX2L"},
3286 {"ADC2 L", NULL, "ADC2 L Power"},
3287 {"ADC2 L", NULL, "ADC2 clock"},
3288 {"ADC2 R", NULL, "RECMIX2R"},
3289 {"ADC2 R", NULL, "ADC2 R Power"},
3290 {"ADC2 R", NULL, "ADC2 clock"},
3291
3292 {"DMIC L1", NULL, "DMIC CLK"},
3293 {"DMIC L1", NULL, "DMIC1 Power"},
3294 {"DMIC R1", NULL, "DMIC CLK"},
3295 {"DMIC R1", NULL, "DMIC1 Power"},
3296 {"DMIC L2", NULL, "DMIC CLK"},
3297 {"DMIC L2", NULL, "DMIC2 Power"},
3298 {"DMIC R2", NULL, "DMIC CLK"},
3299 {"DMIC R2", NULL, "DMIC2 Power"},
3300
3301 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3302 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3303
3304 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3305 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3306
3307 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3308 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3309
3310 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3311 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3312
3313 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3314 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3315
3316 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3317 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3318
3319 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3320 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3321 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3322 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3323 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3324 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3325 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3326 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3327
3328 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3329 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3330
3331 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3332 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3333
3334 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3335 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3336 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3337 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3338
3339 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3340 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3341 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3342 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3343
3344 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3345 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3346 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3347 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3348
3349 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3350 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3351 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3352 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3353
3354 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3355 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3356
3357 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3358 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3359
3360 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3361 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3362 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3363 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3364
3365 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3366 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3367 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3368 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3369
3370 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3371 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3372 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3373 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3374 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3375 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3376
3377 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3378 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3379
3380 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3381 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3382
3383 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3384 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3385 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3386 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3387
3388 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3389 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3390 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3391 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3392
3393 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3394 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3395 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3396
3397 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3398 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3399 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3400
3401 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3402 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3403 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3404
3405 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3406 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3407 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3408
3409 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3410 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3411 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3412
3413 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3414 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3415 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3416
3417 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3418 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3419 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3420 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3421 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3422 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3423
3424 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3425 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3426 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3427 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3428 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3429 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3430 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3431
3432 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3433 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3434 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3435 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3436 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3437 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3438 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3439 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3440
3441 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3442 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3443 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3444 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3445 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3446 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3447 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3448 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3449 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3450 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3451 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3452 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3453 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3454 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3455 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3456 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3457 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3458 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3459 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3460 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3461 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3462 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3463 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3464 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3465 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3466
3467 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3468 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3469 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3470 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3471 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3472 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3473 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3474 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3475 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3476 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3477 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3478 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3479 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3480 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3481 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3482 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3483 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3484 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3485 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3486 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3487 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3488 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3489 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3490 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3491 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3492
3493 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3494 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3495 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3496 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3497 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3498 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3499 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3500 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3501 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3503 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3504 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3505 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3506 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3507 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3508 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3509 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3510 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3511 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3512 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3514 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3515 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3517 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3518
3519 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3520 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3521 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3522 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3523 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3524 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3525 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3526 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3527 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3528 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3530 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3531 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3532 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3533 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3534 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3535 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3536 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3537 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3538 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3541 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3542 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3543 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3544
3545
3546 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3547 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3548 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3549 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3550 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3551 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3552 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3553 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3554 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3555 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3556 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3557 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3558 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3559 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3560 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3561 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3562 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3563 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3564 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3565 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3566 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3567 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3568 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3569 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3570 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3571
3572 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3573 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3574 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3575 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3576 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3577 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3578 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3579 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3580 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3581 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3582 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3583 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3584 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3585 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3586 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3587 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3588 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3589 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3590 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3591 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3592 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3593 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3594 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3595 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3596 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3597
3598 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3599 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3600 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3601 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3602 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3603 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3604 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3605 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3606 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3608 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3609 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3610 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3611 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3612 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3613 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3614 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3615 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3616 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3617 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3619 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3620 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3622 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3623
3624 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3626 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3627 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3628 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3629 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3630 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3631 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3632 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3633 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3635 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3636 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3638 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3639 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3640 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3641 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3642 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3643 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3646 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3647 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3648 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3649
3650 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3651 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3652 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3653 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3654 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3655 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3656 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3657 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3658 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3659 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3660 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3661 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3662 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3663 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3664 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3665 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3666 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3667 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3668 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3669 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3670 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3671 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3672 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3673 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3674 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3675 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3676 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3677 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3678 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3679 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3680 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3681 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3682
3683 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3684 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3685 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3686 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3687 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3688 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3689 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3690 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3691 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3692 {"IF2_1 ADC", NULL, "I2S2_1"},
3693
3694 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3695 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3696 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3697 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3698 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3699 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3700 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3701 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3702 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3703 {"IF2_2 ADC", NULL, "I2S2_2"},
3704
3705 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3706 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3707 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3708 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3709 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3710 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3711 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3712 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3713 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3714 {"IF3 ADC", NULL, "I2S3"},
3715
3716 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3717 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3718 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3719 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3720 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3721 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3722 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3723 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3724 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3725 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3726 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3727 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3728 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3729 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3730 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3731 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3732 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3733 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3734 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3735 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3736 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3737 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3738 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3739 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3740 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3741 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3742 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3743 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3744 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3745 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3746 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3747
3748 {"IF1 DAC1", NULL, "AIF1RX"},
3749 {"IF1 DAC2", NULL, "AIF1RX"},
3750 {"IF1 DAC3", NULL, "AIF1RX"},
3751 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3752 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3753 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3754 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3755 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3756 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3757 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3758 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3759 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3760 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3761 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3762 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3763 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3764 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3765 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3766
3767 {"IF1 DAC1", NULL, "I2S1_1"},
3768 {"IF1 DAC2", NULL, "I2S1_1"},
3769 {"IF1 DAC3", NULL, "I2S1_1"},
3770 {"IF2_1 DAC", NULL, "I2S2_1"},
3771 {"IF2_2 DAC", NULL, "I2S2_2"},
3772 {"IF3 DAC", NULL, "I2S3"},
3773
3774 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3775 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3776 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3777 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3778 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3779 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3780 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3781 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3782 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3783 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3784 {"IF3 DAC L", NULL, "IF3 DAC"},
3785 {"IF3 DAC R", NULL, "IF3 DAC"},
3786
3787 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3788 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3789 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3790 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3791 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3792
3793 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3794 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3795 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3796 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3797 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3798
3799 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3800 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3801 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3802 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3803
3804 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3805 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3806
3807 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3808 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3809 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3810 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3811 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3812 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3813
3814 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3815 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3816 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3817 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3818 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3819 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3820
3821 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3822 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3823 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3824 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3825 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3826 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3827
3828 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3829 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3830 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3831 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3832 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3833 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3834
3835 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3836 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3837 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3838 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3839
3840 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3841 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3842 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3843 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3844
3845 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3846 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3847 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3848
3849 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3850 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3851 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3852
3853 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3854 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3855 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3856 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3857 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3858 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3859 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3860 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3861
3862 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3863 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3864 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3865 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3866 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3867 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3868
3869 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3870 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3871 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3872 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3873 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3874 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3875
3876 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3877 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3878 {"DAC L2 Source", NULL, "DAC L2 Power"},
3879 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3880 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3881 {"DAC R2 Source", NULL, "DAC R2 Power"},
3882
3883 {"DAC L1", NULL, "DAC L1 Source"},
3884 {"DAC R1", NULL, "DAC R1 Source"},
3885 {"DAC L2", NULL, "DAC L2 Source"},
3886 {"DAC R2", NULL, "DAC R2 Source"},
3887
3888 {"DAC L1", NULL, "DAC 1 Clock"},
3889 {"DAC R1", NULL, "DAC 1 Clock"},
3890 {"DAC L2", NULL, "DAC 2 Clock"},
3891 {"DAC R2", NULL, "DAC 2 Clock"},
3892
3893 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3894 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3895 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3896 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3897 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3898
3899 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3900 {"OUT MIXL", "INL Switch", "INL VOL"},
3901 {"OUT MIXL", "BST1 Switch", "BST1"},
3902 {"OUT MIXL", "BST2 Switch", "BST2"},
3903 {"OUT MIXL", "BST3 Switch", "BST3"},
3904 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3905 {"OUT MIXR", "INR Switch", "INR VOL"},
3906 {"OUT MIXR", "BST2 Switch", "BST2"},
3907 {"OUT MIXR", "BST3 Switch", "BST3"},
3908 {"OUT MIXR", "BST4 Switch", "BST4"},
3909
3910 {"MONOVOL", "Switch", "MONOVOL MIX"},
3911 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3912 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3913 {"Mono Amp", NULL, "Mono MIX"},
3914 {"Mono Amp", NULL, "Vref2"},
3915 {"Mono Amp", NULL, "CLKDET SYS"},
3916 {"Mono Amp", NULL, "CLKDET MONO"},
3917 {"Mono Playback", "Switch", "Mono Amp"},
3918 {"MONOOUT", NULL, "Mono Playback"},
3919
3920 {"HP Amp", NULL, "DAC L1"},
3921 {"HP Amp", NULL, "DAC R1"},
3922 {"HP Amp", NULL, "Charge Pump"},
3923 {"HP Amp", NULL, "CLKDET SYS"},
3924 {"HP Amp", NULL, "CLKDET HP"},
3925 {"HP Amp", NULL, "CBJ Power"},
3926 {"HP Amp", NULL, "Vref2"},
3927 {"HPO Playback", "Switch", "HP Amp"},
3928 {"HPOL", NULL, "HPO Playback"},
3929 {"HPOR", NULL, "HPO Playback"},
3930
3931 {"OUTVOL L", "Switch", "OUT MIXL"},
3932 {"OUTVOL R", "Switch", "OUT MIXR"},
3933 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3934 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3935 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3936 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3937 {"LOUT Amp", NULL, "LOUT L MIX"},
3938 {"LOUT Amp", NULL, "LOUT R MIX"},
3939 {"LOUT Amp", NULL, "Vref1"},
3940 {"LOUT Amp", NULL, "Vref2"},
3941 {"LOUT Amp", NULL, "CLKDET SYS"},
3942 {"LOUT Amp", NULL, "CLKDET LOUT"},
3943 {"LOUT L Playback", "Switch", "LOUT Amp"},
3944 {"LOUT R Playback", "Switch", "LOUT Amp"},
3945 {"LOUTL", NULL, "LOUT L Playback"},
3946 {"LOUTR", NULL, "LOUT R Playback"},
3947
3948 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3949 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3950 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3951 {"PDM L Mux", NULL, "PDM Power"},
3952 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3953 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3954 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3955 {"PDM R Mux", NULL, "PDM Power"},
3956 {"PDM L Playback", "Switch", "PDM L Mux"},
3957 {"PDM R Playback", "Switch", "PDM R Mux"},
3958 {"PDML", NULL, "PDM L Playback"},
3959 {"PDMR", NULL, "PDM R Playback"},
3960};
3961
3962static int rt5665_hw_params(struct snd_pcm_substream *substream,
3963 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3964{
3965 struct snd_soc_codec *codec = dai->codec;
3966 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
3967 unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
3968 int pre_div, frame_size;
3969
3970 rt5665->lrck[dai->id] = params_rate(params);
3971 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
3972 if (pre_div < 0) {
3973 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
3974 rt5665->lrck[dai->id], dai->id);
3975 return -EINVAL;
3976 }
3977 frame_size = snd_soc_params_to_frame_size(params);
3978 if (frame_size < 0) {
3979 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3980 return -EINVAL;
3981 }
3982
3983 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3984 rt5665->lrck[dai->id], pre_div, dai->id);
3985
3986 switch (params_width(params)) {
3987 case 16:
3988 val_bits = 0x0100;
3989 break;
3990 case 20:
3991 val_len |= RT5665_I2S_DL_20;
3992 val_bits = 0x1300;
3993 break;
3994 case 24:
3995 val_len |= RT5665_I2S_DL_24;
3996 val_bits = 0x2500;
3997 break;
3998 case 8:
3999 val_len |= RT5665_I2S_DL_8;
4000 break;
4001 default:
4002 return -EINVAL;
4003 }
4004
4005 switch (dai->id) {
4006 case RT5665_AIF1_1:
4007 case RT5665_AIF1_2:
4008 mask_clk = RT5665_I2S_PD1_MASK;
4009 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4010 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4011 RT5665_I2S_DL_MASK, val_len);
4012 break;
4013 case RT5665_AIF2_1:
4014 case RT5665_AIF2_2:
4015 mask_clk = RT5665_I2S_PD2_MASK;
4016 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4017 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4018 RT5665_I2S_DL_MASK, val_len);
4019 break;
4020 case RT5665_AIF3:
4021 mask_clk = RT5665_I2S_PD3_MASK;
4022 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4023 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4024 RT5665_I2S_DL_MASK, val_len);
4025 break;
4026 default:
4027 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4028 return -EINVAL;
4029 }
4030
4031 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
4032 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4033
4034 switch (rt5665->lrck[dai->id]) {
4035 case 192000:
4036 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4037 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4038 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4039 break;
4040 case 96000:
4041 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4042 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4043 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4044 break;
4045 default:
4046 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4047 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4048 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4049 break;
4050 }
4051
4052 return 0;
4053}
4054
4055static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4056{
4057 struct snd_soc_codec *codec = dai->codec;
4058 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4059 unsigned int reg_val = 0;
4060
4061 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4062 case SND_SOC_DAIFMT_CBM_CFM:
4063 rt5665->master[dai->id] = 1;
4064 break;
4065 case SND_SOC_DAIFMT_CBS_CFS:
4066 reg_val |= RT5665_I2S_MS_S;
4067 rt5665->master[dai->id] = 0;
4068 break;
4069 default:
4070 return -EINVAL;
4071 }
4072
4073 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4074 case SND_SOC_DAIFMT_NB_NF:
4075 break;
4076 case SND_SOC_DAIFMT_IB_NF:
4077 reg_val |= RT5665_I2S_BP_INV;
4078 break;
4079 default:
4080 return -EINVAL;
4081 }
4082
4083 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4084 case SND_SOC_DAIFMT_I2S:
4085 break;
4086 case SND_SOC_DAIFMT_LEFT_J:
4087 reg_val |= RT5665_I2S_DF_LEFT;
4088 break;
4089 case SND_SOC_DAIFMT_DSP_A:
4090 reg_val |= RT5665_I2S_DF_PCM_A;
4091 break;
4092 case SND_SOC_DAIFMT_DSP_B:
4093 reg_val |= RT5665_I2S_DF_PCM_B;
4094 break;
4095 default:
4096 return -EINVAL;
4097 }
4098
4099 switch (dai->id) {
4100 case RT5665_AIF1_1:
4101 case RT5665_AIF1_2:
4102 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4103 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4104 RT5665_I2S_DF_MASK, reg_val);
4105 break;
4106 case RT5665_AIF2_1:
4107 case RT5665_AIF2_2:
4108 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4109 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4110 RT5665_I2S_DF_MASK, reg_val);
4111 break;
4112 case RT5665_AIF3:
4113 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4114 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4115 RT5665_I2S_DF_MASK, reg_val);
4116 break;
4117 default:
4118 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4119 return -EINVAL;
4120 }
4121 return 0;
4122}
4123
4124static int rt5665_set_dai_sysclk(struct snd_soc_dai *dai,
4125 int clk_id, unsigned int freq, int dir)
4126{
4127 struct snd_soc_codec *codec = dai->codec;
4128 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4129 unsigned int reg_val = 0;
4130
4131 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4132 return 0;
4133
4134 switch (clk_id) {
4135 case RT5665_SCLK_S_MCLK:
4136 reg_val |= RT5665_SCLK_SRC_MCLK;
4137 break;
4138 case RT5665_SCLK_S_PLL1:
4139 reg_val |= RT5665_SCLK_SRC_PLL1;
4140 break;
4141 case RT5665_SCLK_S_RCCLK:
4142 reg_val |= RT5665_SCLK_SRC_RCCLK;
4143 break;
4144 default:
4145 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4146 return -EINVAL;
4147 }
4148 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4149 RT5665_SCLK_SRC_MASK, reg_val);
4150 rt5665->sysclk = freq;
4151 rt5665->sysclk_src = clk_id;
4152
4153 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4154
4155 return 0;
4156}
4157
4158static int rt5665_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int Source,
4159 unsigned int freq_in, unsigned int freq_out)
4160{
4161 struct snd_soc_codec *codec = dai->codec;
4162 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4163 struct rl6231_pll_code pll_code;
4164 int ret;
4165
4166 if (Source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4167 freq_out == rt5665->pll_out)
4168 return 0;
4169
4170 if (!freq_in || !freq_out) {
4171 dev_dbg(codec->dev, "PLL disabled\n");
4172
4173 rt5665->pll_in = 0;
4174 rt5665->pll_out = 0;
4175 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4176 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4177 return 0;
4178 }
4179
4180 switch (Source) {
4181 case RT5665_PLL1_S_MCLK:
4182 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4183 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4184 break;
4185 case RT5665_PLL1_S_BCLK1:
4186 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4187 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4188 break;
4189 case RT5665_PLL1_S_BCLK2:
4190 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4191 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4192 break;
4193 case RT5665_PLL1_S_BCLK3:
4194 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4195 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4196 break;
4197 default:
4198 dev_err(codec->dev, "Unknown PLL Source %d\n", Source);
4199 return -EINVAL;
4200 }
4201
4202 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4203 if (ret < 0) {
4204 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4205 return ret;
4206 }
4207
4208 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4209 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4210 pll_code.n_code, pll_code.k_code);
4211
4212 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4213 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4214 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4215 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4216 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4217
4218 rt5665->pll_in = freq_in;
4219 rt5665->pll_out = freq_out;
4220 rt5665->pll_src = Source;
4221
4222 return 0;
4223}
4224
4225static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4226 unsigned int rx_mask, int slots, int slot_width)
4227{
4228 struct snd_soc_codec *codec = dai->codec;
4229 unsigned int val = 0;
4230
4231 if (rx_mask || tx_mask)
4232 val |= RT5665_I2S1_MODE_TDM;
4233
4234 switch (slots) {
4235 case 4:
4236 val |= RT5665_TDM_IN_CH_4;
4237 val |= RT5665_TDM_OUT_CH_4;
4238 break;
4239 case 6:
4240 val |= RT5665_TDM_IN_CH_6;
4241 val |= RT5665_TDM_OUT_CH_6;
4242 break;
4243 case 8:
4244 val |= RT5665_TDM_IN_CH_8;
4245 val |= RT5665_TDM_OUT_CH_8;
4246 break;
4247 case 2:
4248 break;
4249 default:
4250 return -EINVAL;
4251 }
4252
4253 switch (slot_width) {
4254 case 20:
4255 val |= RT5665_TDM_IN_LEN_20;
4256 val |= RT5665_TDM_OUT_LEN_20;
4257 break;
4258 case 24:
4259 val |= RT5665_TDM_IN_LEN_24;
4260 val |= RT5665_TDM_OUT_LEN_24;
4261 break;
4262 case 32:
4263 val |= RT5665_TDM_IN_LEN_32;
4264 val |= RT5665_TDM_OUT_LEN_32;
4265 break;
4266 case 16:
4267 break;
4268 default:
4269 return -EINVAL;
4270 }
4271
4272 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4273 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4274 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4275 RT5665_TDM_OUT_LEN_MASK, val);
4276
4277 return 0;
4278}
4279
4280static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4281{
4282 struct snd_soc_codec *codec = dai->codec;
4283 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4284
4285 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4286
4287 rt5665->bclk[dai->id] = ratio;
4288
4289 if (ratio == 64) {
4290 switch (dai->id) {
4291 case RT5665_AIF2_1:
4292 case RT5665_AIF2_2:
4293 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4294 RT5665_I2S_BCLK_MS2_MASK,
4295 RT5665_I2S_BCLK_MS2_64);
4296 break;
4297 case RT5665_AIF3:
4298 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4299 RT5665_I2S_BCLK_MS3_MASK,
4300 RT5665_I2S_BCLK_MS3_64);
4301 break;
4302 }
4303 }
4304
4305 return 0;
4306}
4307
4308static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4309 enum snd_soc_bias_level level)
4310{
4311 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4312
4313 switch (level) {
4314 case SND_SOC_BIAS_PREPARE:
4315 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4316 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4317 break;
4318
4319 case SND_SOC_BIAS_STANDBY:
4320 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4321 RT5665_PWR_LDO, RT5665_PWR_LDO);
4322 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4323 RT5665_PWR_MB, RT5665_PWR_MB);
4324 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4325 RT5665_DIG_GATE_CTRL, 0);
4326 break;
4327 case SND_SOC_BIAS_OFF:
4328 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4329 RT5665_PWR_LDO, 0);
4330 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4331 RT5665_PWR_MB, 0);
4332 break;
4333
4334 default:
4335 break;
4336 }
4337
4338 return 0;
4339}
4340
4341static int rt5665_probe(struct snd_soc_codec *codec)
4342{
4343 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4344
4345 rt5665->codec = codec;
4346
4347 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4348
4349 return 0;
4350}
4351
4352static int rt5665_remove(struct snd_soc_codec *codec)
4353{
4354 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4355
4356 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4357
4358 return 0;
4359}
4360
4361#ifdef CONFIG_PM
4362static int rt5665_suspend(struct snd_soc_codec *codec)
4363{
4364 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4365
4366 regcache_cache_only(rt5665->regmap, true);
4367 regcache_mark_dirty(rt5665->regmap);
4368 return 0;
4369}
4370
4371static int rt5665_resume(struct snd_soc_codec *codec)
4372{
4373 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4374
4375 regcache_cache_only(rt5665->regmap, false);
4376 regcache_sync(rt5665->regmap);
4377
4378 return 0;
4379}
4380#else
4381#define rt5665_suspend NULL
4382#define rt5665_resume NULL
4383#endif
4384
4385#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4386#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4387 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4388
4389static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4390 .hw_params = rt5665_hw_params,
4391 .set_fmt = rt5665_set_dai_fmt,
4392 .set_sysclk = rt5665_set_dai_sysclk,
4393 .set_tdm_slot = rt5665_set_tdm_slot,
4394 .set_pll = rt5665_set_dai_pll,
4395 .set_bclk_ratio = rt5665_set_bclk_ratio,
4396};
4397
4398static struct snd_soc_dai_driver rt5665_dai[] = {
4399 {
4400 .name = "rt5665-aif1_1",
4401 .id = RT5665_AIF1_1,
4402 .playback = {
4403 .stream_name = "AIF1 Playback",
4404 .channels_min = 1,
4405 .channels_max = 8,
4406 .rates = RT5665_STEREO_RATES,
4407 .formats = RT5665_FORMATS,
4408 },
4409 .capture = {
4410 .stream_name = "AIF1_1 Capture",
4411 .channels_min = 1,
4412 .channels_max = 8,
4413 .rates = RT5665_STEREO_RATES,
4414 .formats = RT5665_FORMATS,
4415 },
4416 .ops = &rt5665_aif_dai_ops,
4417 },
4418 {
4419 .name = "rt5665-aif1_2",
4420 .id = RT5665_AIF1_2,
4421 .capture = {
4422 .stream_name = "AIF1_2 Capture",
4423 .channels_min = 1,
4424 .channels_max = 8,
4425 .rates = RT5665_STEREO_RATES,
4426 .formats = RT5665_FORMATS,
4427 },
4428 .ops = &rt5665_aif_dai_ops,
4429 },
4430 {
4431 .name = "rt5665-aif2_1",
4432 .id = RT5665_AIF2_1,
4433 .playback = {
4434 .stream_name = "AIF2_1 Playback",
4435 .channels_min = 1,
4436 .channels_max = 2,
4437 .rates = RT5665_STEREO_RATES,
4438 .formats = RT5665_FORMATS,
4439 },
4440 .capture = {
4441 .stream_name = "AIF2_1 Capture",
4442 .channels_min = 1,
4443 .channels_max = 2,
4444 .rates = RT5665_STEREO_RATES,
4445 .formats = RT5665_FORMATS,
4446 },
4447 .ops = &rt5665_aif_dai_ops,
4448 },
4449 {
4450 .name = "rt5665-aif2_2",
4451 .id = RT5665_AIF2_2,
4452 .playback = {
4453 .stream_name = "AIF2_2 Playback",
4454 .channels_min = 1,
4455 .channels_max = 2,
4456 .rates = RT5665_STEREO_RATES,
4457 .formats = RT5665_FORMATS,
4458 },
4459 .capture = {
4460 .stream_name = "AIF2_2 Capture",
4461 .channels_min = 1,
4462 .channels_max = 2,
4463 .rates = RT5665_STEREO_RATES,
4464 .formats = RT5665_FORMATS,
4465 },
4466 .ops = &rt5665_aif_dai_ops,
4467 },
4468 {
4469 .name = "rt5665-aif3",
4470 .id = RT5665_AIF3,
4471 .playback = {
4472 .stream_name = "AIF3 Playback",
4473 .channels_min = 1,
4474 .channels_max = 2,
4475 .rates = RT5665_STEREO_RATES,
4476 .formats = RT5665_FORMATS,
4477 },
4478 .capture = {
4479 .stream_name = "AIF3 Capture",
4480 .channels_min = 1,
4481 .channels_max = 2,
4482 .rates = RT5665_STEREO_RATES,
4483 .formats = RT5665_FORMATS,
4484 },
4485 .ops = &rt5665_aif_dai_ops,
4486 },
4487};
4488
4489static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4490 .probe = rt5665_probe,
4491 .remove = rt5665_remove,
4492 .suspend = rt5665_suspend,
4493 .resume = rt5665_resume,
4494 .set_bias_level = rt5665_set_bias_level,
4495 .idle_bias_off = true,
4496 .component_driver = {
4497 .controls = rt5665_snd_controls,
4498 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4499 .dapm_widgets = rt5665_dapm_widgets,
4500 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4501 .dapm_routes = rt5665_dapm_routes,
4502 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4503 }
4504};
4505
4506
4507static const struct regmap_config rt5665_regmap = {
4508 .reg_bits = 16,
4509 .val_bits = 16,
4510 .max_register = 0x0400,
4511 .volatile_reg = rt5665_volatile_register,
4512 .readable_reg = rt5665_readable_register,
4513 .cache_type = REGCACHE_RBTREE,
4514 .reg_defaults = rt5665_reg,
4515 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4516 .use_single_rw = true,
4517};
4518
4519static const struct i2c_device_id rt5665_i2c_id[] = {
4520 {"rt5665", 0},
4521 {}
4522};
4523MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4524
4525static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4526{
4527 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4528 "realtek,in1-differential");
4529 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4530 "realtek,in2-differential");
4531 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4532 "realtek,in3-differential");
4533 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4534 "realtek,in4-differential");
4535
4536 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4537 &rt5665->pdata.dmic1_data_pin);
4538 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4539 &rt5665->pdata.dmic2_data_pin);
4540 of_property_read_u32(dev->of_node, "realtek,jd-src",
4541 &rt5665->pdata.jd_src);
4542
4543 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4544 "realtek,ldo1-en-gpios", 0);
4545
4546 return 0;
4547}
4548
4549static void rt5665_calibrate(struct rt5665_priv *rt5665)
4550{
4551 int value, count;
4552
4553 mutex_lock(&rt5665->calibrate_mutex);
4554
4555 regcache_cache_bypass(rt5665->regmap, true);
4556
4557 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4558 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4559 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4560 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4561 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4562 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4563 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4564 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4565 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4566 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4567 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4568 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4569 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4570 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4571 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4572 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4573 usleep_range(15000, 20000);
4574 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4575 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4576
4577 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4578 count = 0;
4579 while (true) {
4580 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4581 if (value & 0x8000)
4582 usleep_range(10000, 10005);
4583 else
4584 break;
4585
4586 if (count > 60) {
4587 pr_err("HP Calibration Failure\n");
4588 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4589 regcache_cache_bypass(rt5665->regmap, false);
4590 return;
4591 }
4592
4593 count++;
4594 }
4595
4596 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4597 count = 0;
4598 while (true) {
4599 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4600 if (value & 0x8000)
4601 usleep_range(10000, 10005);
4602 else
4603 break;
4604
4605 if (count > 60) {
4606 pr_err("MONO Calibration Failure\n");
4607 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4608 regcache_cache_bypass(rt5665->regmap, false);
4609 return;
4610 }
4611
4612 count++;
4613 }
4614
4615 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4616 regcache_cache_bypass(rt5665->regmap, false);
4617
4618 regcache_mark_dirty(rt5665->regmap);
4619 regcache_sync(rt5665->regmap);
4620
4621 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4622 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4623
4624 mutex_unlock(&rt5665->calibrate_mutex);
4625}
4626
4627static void rt5665_calibrate_handler(struct work_struct *work)
4628{
4629 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4630 calibrate_work.work);
4631
4632 while (!rt5665->codec->component.card->instantiated) {
4633 pr_debug("%s\n", __func__);
4634 usleep_range(10000, 15000);
4635 }
4636
4637 rt5665_calibrate(rt5665);
4638}
4639
4640static int rt5665_i2c_probe(struct i2c_client *i2c,
4641 const struct i2c_device_id *id)
4642{
4643 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4644 struct rt5665_priv *rt5665;
4645 int i, ret;
4646 unsigned int val;
4647
4648 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4649 GFP_KERNEL);
4650
4651 if (rt5665 == NULL)
4652 return -ENOMEM;
4653
4654 i2c_set_clientdata(i2c, rt5665);
4655
4656 if (pdata)
4657 rt5665->pdata = *pdata;
4658 else
4659 rt5665_parse_dt(rt5665, &i2c->dev);
4660
4661 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4662 rt5665->supplies[i].supply = rt5665_supply_names[i];
4663
4664 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4665 rt5665->supplies);
4666 if (ret != 0) {
4667 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4668 return ret;
4669 }
4670
4671 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4672 rt5665->supplies);
4673 if (ret != 0) {
4674 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4675 return ret;
4676 }
4677
4678 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4679 if (devm_gpio_request(&i2c->dev, rt5665->pdata.ldo1_en,
4680 "rt5665"))
4681 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4682 else if (gpio_direction_output(rt5665->pdata.ldo1_en, 1))
4683 dev_err(&i2c->dev, "Fail gpio_direction gpio_ldo\n");
4684 }
4685
4686 /* Sleep for 300 ms miniumum */
4687 usleep_range(300000, 350000);
4688
4689 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4690 if (IS_ERR(rt5665->regmap)) {
4691 ret = PTR_ERR(rt5665->regmap);
4692 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4693 ret);
4694 return ret;
4695 }
4696
4697 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4698 if (val != DEVICE_ID) {
4699 dev_err(&i2c->dev,
4700 "Device with ID register %x is not rt5665\n", val);
4701 return -ENODEV;
4702 }
4703
4704 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4705 switch (val) {
4706 case 0x0:
4707 rt5665->id = CODEC_5666;
4708 break;
4709 case 0x6:
4710 rt5665->id = CODEC_5668;
4711 break;
4712 case 0x3:
4713 default:
4714 rt5665->id = CODEC_5665;
4715 break;
4716 }
4717
4718 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4719
4720 /* line in diff mode*/
4721 if (rt5665->pdata.in1_diff)
4722 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4723 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4724 if (rt5665->pdata.in2_diff)
4725 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4726 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4727 if (rt5665->pdata.in3_diff)
4728 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4729 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4730 if (rt5665->pdata.in4_diff)
4731 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4732 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4733
4734 /* DMIC pin*/
4735 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4736 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4737 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4738 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4739 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4740 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4741 switch (rt5665->pdata.dmic1_data_pin) {
4742 case RT5665_DMIC1_DATA_IN2N:
4743 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4744 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4745 break;
4746
4747 case RT5665_DMIC1_DATA_GPIO4:
4748 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4749 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4750 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4751 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4752 break;
4753
4754 default:
4755 dev_dbg(&i2c->dev, "no DMIC1\n");
4756 break;
4757 }
4758
4759 switch (rt5665->pdata.dmic2_data_pin) {
4760 case RT5665_DMIC2_DATA_IN2P:
4761 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4762 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4763 break;
4764
4765 case RT5665_DMIC2_DATA_GPIO5:
4766 regmap_update_bits(rt5665->regmap,
4767 RT5665_DMIC_CTRL_1,
4768 RT5665_DMIC_2_DP_MASK,
4769 RT5665_DMIC_2_DP_GPIO5);
4770 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4771 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4772 break;
4773
4774 default:
4775 dev_dbg(&i2c->dev, "no DMIC2\n");
4776 break;
4777
4778 }
4779 }
4780
4781 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4782 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4783 0xf000 | RT5665_VREF_POW_MASK, 0xd000 | RT5665_VREF_POW_REG);
4784 /* Work around for pow_pump */
4785 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4786 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4787
4788 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4789 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4790
4791 /* Set GPIO4,8 as input for combo jack */
4792 if (rt5665->id == CODEC_5666) {
4793 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4794 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4795 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4796 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4797 }
4798
4799 /* Enhance performance*/
4800 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4801 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4802 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_09);
4803
4804 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4805 rt5665_jack_detect_handler);
4806 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4807 rt5665_calibrate_handler);
4808 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4809 rt5665_jd_check_handler);
4810
4811 mutex_init(&rt5665->calibrate_mutex);
4812
4813 if (i2c->irq) {
4814 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4815 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4816 | IRQF_ONESHOT, "rt5665", rt5665);
4817 if (ret)
4818 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4819
4820 }
4821
4822 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4823 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4824}
4825
4826static int rt5665_i2c_remove(struct i2c_client *i2c)
4827{
4828 snd_soc_unregister_codec(&i2c->dev);
4829
4830 return 0;
4831}
4832
4833static void rt5665_i2c_shutdown(struct i2c_client *client)
4834{
4835 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4836
4837 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4838}
4839
4840#ifdef CONFIG_OF
4841static const struct of_device_id rt5665_of_match[] = {
4842 {.compatible = "realtek,rt5665"},
4843 {.compatible = "realtek,rt5666"},
4844 {.compatible = "realtek,rt5668"},
4845 {},
4846};
4847MODULE_DEVICE_TABLE(of, rt5665_of_match);
4848#endif
4849
4850#ifdef CONFIG_ACPI
4851static struct acpi_device_id rt5665_acpi_match[] = {
4852 {"10EC5665", 0,},
4853 {"10EC5666", 0,},
4854 {"10EC5668", 0,},
4855 {},
4856};
4857MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4858#endif
4859
4860struct i2c_driver rt5665_i2c_driver = {
4861 .driver = {
4862 .name = "rt5665",
4863 .of_match_table = of_match_ptr(rt5665_of_match),
4864 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4865 },
4866 .probe = rt5665_i2c_probe,
4867 .remove = rt5665_i2c_remove,
4868 .shutdown = rt5665_i2c_shutdown,
4869 .id_table = rt5665_i2c_id,
4870};
4871module_i2c_driver(rt5665_i2c_driver);
4872
4873MODULE_DESCRIPTION("ASoC RT5665 driver");
4874MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4875MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5665.h b/sound/soc/codecs/rt5665.h
new file mode 100644
index 000000000000..12f7080a0d3c
--- /dev/null
+++ b/sound/soc/codecs/rt5665.h
@@ -0,0 +1,1990 @@
1/*
2 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
3 *
4 * Copyright 2016 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5665_H__
13#define __RT5665_H__
14
15#include <sound/rt5665.h>
16
17#define DEVICE_ID 0x6451
18
19/* Info */
20#define RT5665_RESET 0x0000
21#define RT5665_VENDOR_ID 0x00fd
22#define RT5665_VENDOR_ID_1 0x00fe
23#define RT5665_DEVICE_ID 0x00ff
24/* I/O - Output */
25#define RT5665_LOUT 0x0001
26#define RT5665_HP_CTRL_1 0x0002
27#define RT5665_HP_CTRL_2 0x0003
28#define RT5665_MONO_OUT 0x0004
29#define RT5665_HPL_GAIN 0x0005
30#define RT5665_HPR_GAIN 0x0006
31#define RT5665_MONO_GAIN 0x0007
32
33/* I/O - Input */
34#define RT5665_CAL_BST_CTRL 0x000a
35#define RT5665_CBJ_BST_CTRL 0x000b
36#define RT5665_IN1_IN2 0x000c
37#define RT5665_IN3_IN4 0x000d
38#define RT5665_INL1_INR1_VOL 0x000f
39/* I/O - Speaker */
40#define RT5665_EJD_CTRL_1 0x0010
41#define RT5665_EJD_CTRL_2 0x0011
42#define RT5665_EJD_CTRL_3 0x0012
43#define RT5665_EJD_CTRL_4 0x0013
44#define RT5665_EJD_CTRL_5 0x0014
45#define RT5665_EJD_CTRL_6 0x0015
46#define RT5665_EJD_CTRL_7 0x0016
47/* I/O - ADC/DAC/DMIC */
48#define RT5665_DAC2_CTRL 0x0017
49#define RT5665_DAC2_DIG_VOL 0x0018
50#define RT5665_DAC1_DIG_VOL 0x0019
51#define RT5665_DAC3_DIG_VOL 0x001a
52#define RT5665_DAC3_CTRL 0x001b
53#define RT5665_STO1_ADC_DIG_VOL 0x001c
54#define RT5665_MONO_ADC_DIG_VOL 0x001d
55#define RT5665_STO2_ADC_DIG_VOL 0x001e
56#define RT5665_STO1_ADC_BOOST 0x001f
57#define RT5665_MONO_ADC_BOOST 0x0020
58#define RT5665_STO2_ADC_BOOST 0x0021
59#define RT5665_HP_IMP_GAIN_1 0x0022
60#define RT5665_HP_IMP_GAIN_2 0x0023
61/* Mixer - D-D */
62#define RT5665_STO1_ADC_MIXER 0x0026
63#define RT5665_MONO_ADC_MIXER 0x0027
64#define RT5665_STO2_ADC_MIXER 0x0028
65#define RT5665_AD_DA_MIXER 0x0029
66#define RT5665_STO1_DAC_MIXER 0x002a
67#define RT5665_MONO_DAC_MIXER 0x002b
68#define RT5665_STO2_DAC_MIXER 0x002c
69#define RT5665_A_DAC1_MUX 0x002d
70#define RT5665_A_DAC2_MUX 0x002e
71#define RT5665_DIG_INF2_DATA 0x002f
72#define RT5665_DIG_INF3_DATA 0x0030
73/* Mixer - PDM */
74#define RT5665_PDM_OUT_CTRL 0x0031
75#define RT5665_PDM_DATA_CTRL_1 0x0032
76#define RT5665_PDM_DATA_CTRL_2 0x0033
77#define RT5665_PDM_DATA_CTRL_3 0x0034
78#define RT5665_PDM_DATA_CTRL_4 0x0035
79/* Mixer - ADC */
80#define RT5665_REC1_GAIN 0x003a
81#define RT5665_REC1_L1_MIXER 0x003b
82#define RT5665_REC1_L2_MIXER 0x003c
83#define RT5665_REC1_R1_MIXER 0x003d
84#define RT5665_REC1_R2_MIXER 0x003e
85#define RT5665_REC2_GAIN 0x003f
86#define RT5665_REC2_L1_MIXER 0x0040
87#define RT5665_REC2_L2_MIXER 0x0041
88#define RT5665_REC2_R1_MIXER 0x0042
89#define RT5665_REC2_R2_MIXER 0x0043
90#define RT5665_CAL_REC 0x0044
91/* Mixer - DAC */
92#define RT5665_ALC_BACK_GAIN 0x0049
93#define RT5665_MONOMIX_GAIN 0x004a
94#define RT5665_MONOMIX_IN_GAIN 0x004b
95#define RT5665_OUT_L_GAIN 0x004d
96#define RT5665_OUT_L_MIXER 0x004e
97#define RT5665_OUT_R_GAIN 0x004f
98#define RT5665_OUT_R_MIXER 0x0050
99#define RT5665_LOUT_MIXER 0x0052
100/* Power */
101#define RT5665_PWR_DIG_1 0x0061
102#define RT5665_PWR_DIG_2 0x0062
103#define RT5665_PWR_ANLG_1 0x0063
104#define RT5665_PWR_ANLG_2 0x0064
105#define RT5665_PWR_ANLG_3 0x0065
106#define RT5665_PWR_MIXER 0x0066
107#define RT5665_PWR_VOL 0x0067
108/* Clock Detect */
109#define RT5665_CLK_DET 0x006b
110/* Filter */
111#define RT5665_HPF_CTRL1 0x006d
112/* DMIC */
113#define RT5665_DMIC_CTRL_1 0x006e
114#define RT5665_DMIC_CTRL_2 0x006f
115/* Format - ADC/DAC */
116#define RT5665_I2S1_SDP 0x0070
117#define RT5665_I2S2_SDP 0x0071
118#define RT5665_I2S3_SDP 0x0072
119#define RT5665_ADDA_CLK_1 0x0073
120#define RT5665_ADDA_CLK_2 0x0074
121#define RT5665_I2S1_F_DIV_CTRL_1 0x0075
122#define RT5665_I2S1_F_DIV_CTRL_2 0x0076
123/* Format - TDM Control */
124#define RT5665_TDM_CTRL_1 0x0078
125#define RT5665_TDM_CTRL_2 0x0079
126#define RT5665_TDM_CTRL_3 0x007a
127#define RT5665_TDM_CTRL_4 0x007b
128#define RT5665_TDM_CTRL_5 0x007c
129#define RT5665_TDM_CTRL_6 0x007d
130#define RT5665_TDM_CTRL_7 0x007e
131#define RT5665_TDM_CTRL_8 0x007f
132/* Function - Analog */
133#define RT5665_GLB_CLK 0x0080
134#define RT5665_PLL_CTRL_1 0x0081
135#define RT5665_PLL_CTRL_2 0x0082
136#define RT5665_ASRC_1 0x0083
137#define RT5665_ASRC_2 0x0084
138#define RT5665_ASRC_3 0x0085
139#define RT5665_ASRC_4 0x0086
140#define RT5665_ASRC_5 0x0087
141#define RT5665_ASRC_6 0x0088
142#define RT5665_ASRC_7 0x0089
143#define RT5665_ASRC_8 0x008a
144#define RT5665_ASRC_9 0x008b
145#define RT5665_ASRC_10 0x008c
146#define RT5665_DEPOP_1 0x008e
147#define RT5665_DEPOP_2 0x008f
148#define RT5665_HP_CHARGE_PUMP_1 0x0091
149#define RT5665_HP_CHARGE_PUMP_2 0x0092
150#define RT5665_MICBIAS_1 0x0093
151#define RT5665_MICBIAS_2 0x0094
152#define RT5665_ASRC_12 0x0098
153#define RT5665_ASRC_13 0x0099
154#define RT5665_ASRC_14 0x009a
155#define RT5665_RC_CLK_CTRL 0x009f
156#define RT5665_I2S_M_CLK_CTRL_1 0x00a0
157#define RT5665_I2S2_F_DIV_CTRL_1 0x00a1
158#define RT5665_I2S2_F_DIV_CTRL_2 0x00a2
159#define RT5665_I2S3_F_DIV_CTRL_1 0x00a3
160#define RT5665_I2S3_F_DIV_CTRL_2 0x00a4
161/* Function - Digital */
162#define RT5665_EQ_CTRL_1 0x00ae
163#define RT5665_EQ_CTRL_2 0x00af
164#define RT5665_IRQ_CTRL_1 0x00b6
165#define RT5665_IRQ_CTRL_2 0x00b7
166#define RT5665_IRQ_CTRL_3 0x00b8
167#define RT5665_IRQ_CTRL_4 0x00b9
168#define RT5665_IRQ_CTRL_5 0x00ba
169#define RT5665_IRQ_CTRL_6 0x00bb
170#define RT5665_INT_ST_1 0x00be
171#define RT5665_GPIO_CTRL_1 0x00c0
172#define RT5665_GPIO_CTRL_2 0x00c1
173#define RT5665_GPIO_CTRL_3 0x00c2
174#define RT5665_GPIO_CTRL_4 0x00c3
175#define RT5665_GPIO_STA 0x00c4
176#define RT5665_HP_AMP_DET_CTRL_1 0x00d0
177#define RT5665_HP_AMP_DET_CTRL_2 0x00d1
178#define RT5665_MID_HP_AMP_DET 0x00d3
179#define RT5665_LOW_HP_AMP_DET 0x00d4
180#define RT5665_SV_ZCD_1 0x00d9
181#define RT5665_SV_ZCD_2 0x00da
182#define RT5665_IL_CMD_1 0x00db
183#define RT5665_IL_CMD_2 0x00dc
184#define RT5665_IL_CMD_3 0x00dd
185#define RT5665_IL_CMD_4 0x00de
186#define RT5665_4BTN_IL_CMD_1 0x00df
187#define RT5665_4BTN_IL_CMD_2 0x00e0
188#define RT5665_4BTN_IL_CMD_3 0x00e1
189#define RT5665_PSV_IL_CMD_1 0x00e2
190
191#define RT5665_ADC_STO1_HP_CTRL_1 0x00ea
192#define RT5665_ADC_STO1_HP_CTRL_2 0x00eb
193#define RT5665_ADC_MONO_HP_CTRL_1 0x00ec
194#define RT5665_ADC_MONO_HP_CTRL_2 0x00ed
195#define RT5665_ADC_STO2_HP_CTRL_1 0x00ee
196#define RT5665_ADC_STO2_HP_CTRL_2 0x00ef
197#define RT5665_AJD1_CTRL 0x00f0
198#define RT5665_JD1_THD 0x00f1
199#define RT5665_JD2_THD 0x00f2
200#define RT5665_JD_CTRL_1 0x00f6
201#define RT5665_JD_CTRL_2 0x00f7
202#define RT5665_JD_CTRL_3 0x00f8
203/* General Control */
204#define RT5665_DIG_MISC 0x00fa
205#define RT5665_DUMMY_2 0x00fb
206#define RT5665_DUMMY_3 0x00fc
207
208#define RT5665_DAC_ADC_DIG_VOL1 0x0100
209#define RT5665_DAC_ADC_DIG_VOL2 0x0101
210#define RT5665_BIAS_CUR_CTRL_1 0x010a
211#define RT5665_BIAS_CUR_CTRL_2 0x010b
212#define RT5665_BIAS_CUR_CTRL_3 0x010c
213#define RT5665_BIAS_CUR_CTRL_4 0x010d
214#define RT5665_BIAS_CUR_CTRL_5 0x010e
215#define RT5665_BIAS_CUR_CTRL_6 0x010f
216#define RT5665_BIAS_CUR_CTRL_7 0x0110
217#define RT5665_BIAS_CUR_CTRL_8 0x0111
218#define RT5665_BIAS_CUR_CTRL_9 0x0112
219#define RT5665_BIAS_CUR_CTRL_10 0x0113
220#define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117
221#define RT5665_CHARGE_PUMP_1 0x0125
222#define RT5665_DIG_IN_CTRL_1 0x0132
223#define RT5665_DIG_IN_CTRL_2 0x0133
224#define RT5665_PAD_DRIVING_CTRL 0x0137
225#define RT5665_SOFT_RAMP_DEPOP 0x0138
226#define RT5665_PLL 0x0139
227#define RT5665_CHOP_DAC 0x013a
228#define RT5665_CHOP_ADC 0x013b
229#define RT5665_CALIB_ADC_CTRL 0x013c
230#define RT5665_VOL_TEST 0x013f
231#define RT5665_TEST_MODE_CTRL_1 0x0145
232#define RT5665_TEST_MODE_CTRL_2 0x0146
233#define RT5665_TEST_MODE_CTRL_3 0x0147
234#define RT5665_TEST_MODE_CTRL_4 0x0148
235#define RT5665_BASSBACK_CTRL 0x0150
236#define RT5665_STO_NG2_CTRL_1 0x0160
237#define RT5665_STO_NG2_CTRL_2 0x0161
238#define RT5665_STO_NG2_CTRL_3 0x0162
239#define RT5665_STO_NG2_CTRL_4 0x0163
240#define RT5665_STO_NG2_CTRL_5 0x0164
241#define RT5665_STO_NG2_CTRL_6 0x0165
242#define RT5665_STO_NG2_CTRL_7 0x0166
243#define RT5665_STO_NG2_CTRL_8 0x0167
244#define RT5665_MONO_NG2_CTRL_1 0x0170
245#define RT5665_MONO_NG2_CTRL_2 0x0171
246#define RT5665_MONO_NG2_CTRL_3 0x0172
247#define RT5665_MONO_NG2_CTRL_4 0x0173
248#define RT5665_MONO_NG2_CTRL_5 0x0174
249#define RT5665_MONO_NG2_CTRL_6 0x0175
250#define RT5665_STO1_DAC_SIL_DET 0x0190
251#define RT5665_MONOL_DAC_SIL_DET 0x0191
252#define RT5665_MONOR_DAC_SIL_DET 0x0192
253#define RT5665_STO2_DAC_SIL_DET 0x0193
254#define RT5665_SIL_PSV_CTRL1 0x0194
255#define RT5665_SIL_PSV_CTRL2 0x0195
256#define RT5665_SIL_PSV_CTRL3 0x0196
257#define RT5665_SIL_PSV_CTRL4 0x0197
258#define RT5665_SIL_PSV_CTRL5 0x0198
259#define RT5665_SIL_PSV_CTRL6 0x0199
260#define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0
261#define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1
262#define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2
263#define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3
264#define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4
265#define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5
266#define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6
267#define RT5665_MONO_AMP_CALIB_STA1 0x01a7
268#define RT5665_MONO_AMP_CALIB_STA2 0x01a8
269#define RT5665_MONO_AMP_CALIB_STA3 0x01a9
270#define RT5665_MONO_AMP_CALIB_STA4 0x01aa
271#define RT5665_MONO_AMP_CALIB_STA6 0x01ab
272#define RT5665_HP_IMP_SENS_CTRL_01 0x01b5
273#define RT5665_HP_IMP_SENS_CTRL_02 0x01b6
274#define RT5665_HP_IMP_SENS_CTRL_03 0x01b7
275#define RT5665_HP_IMP_SENS_CTRL_04 0x01b8
276#define RT5665_HP_IMP_SENS_CTRL_05 0x01b9
277#define RT5665_HP_IMP_SENS_CTRL_06 0x01ba
278#define RT5665_HP_IMP_SENS_CTRL_07 0x01bb
279#define RT5665_HP_IMP_SENS_CTRL_08 0x01bc
280#define RT5665_HP_IMP_SENS_CTRL_09 0x01bd
281#define RT5665_HP_IMP_SENS_CTRL_10 0x01be
282#define RT5665_HP_IMP_SENS_CTRL_11 0x01bf
283#define RT5665_HP_IMP_SENS_CTRL_12 0x01c0
284#define RT5665_HP_IMP_SENS_CTRL_13 0x01c1
285#define RT5665_HP_IMP_SENS_CTRL_14 0x01c2
286#define RT5665_HP_IMP_SENS_CTRL_15 0x01c3
287#define RT5665_HP_IMP_SENS_CTRL_16 0x01c4
288#define RT5665_HP_IMP_SENS_CTRL_17 0x01c5
289#define RT5665_HP_IMP_SENS_CTRL_18 0x01c6
290#define RT5665_HP_IMP_SENS_CTRL_19 0x01c7
291#define RT5665_HP_IMP_SENS_CTRL_20 0x01c8
292#define RT5665_HP_IMP_SENS_CTRL_21 0x01c9
293#define RT5665_HP_IMP_SENS_CTRL_22 0x01ca
294#define RT5665_HP_IMP_SENS_CTRL_23 0x01cb
295#define RT5665_HP_IMP_SENS_CTRL_24 0x01cc
296#define RT5665_HP_IMP_SENS_CTRL_25 0x01cd
297#define RT5665_HP_IMP_SENS_CTRL_26 0x01ce
298#define RT5665_HP_IMP_SENS_CTRL_27 0x01cf
299#define RT5665_HP_IMP_SENS_CTRL_28 0x01d0
300#define RT5665_HP_IMP_SENS_CTRL_29 0x01d1
301#define RT5665_HP_IMP_SENS_CTRL_30 0x01d2
302#define RT5665_HP_IMP_SENS_CTRL_31 0x01d3
303#define RT5665_HP_IMP_SENS_CTRL_32 0x01d4
304#define RT5665_HP_IMP_SENS_CTRL_33 0x01d5
305#define RT5665_HP_IMP_SENS_CTRL_34 0x01d6
306#define RT5665_HP_LOGIC_CTRL_1 0x01da
307#define RT5665_HP_LOGIC_CTRL_2 0x01db
308#define RT5665_HP_LOGIC_CTRL_3 0x01dc
309#define RT5665_HP_CALIB_CTRL_1 0x01de
310#define RT5665_HP_CALIB_CTRL_2 0x01df
311#define RT5665_HP_CALIB_CTRL_3 0x01e0
312#define RT5665_HP_CALIB_CTRL_4 0x01e1
313#define RT5665_HP_CALIB_CTRL_5 0x01e2
314#define RT5665_HP_CALIB_CTRL_6 0x01e3
315#define RT5665_HP_CALIB_CTRL_7 0x01e4
316#define RT5665_HP_CALIB_CTRL_9 0x01e6
317#define RT5665_HP_CALIB_CTRL_10 0x01e7
318#define RT5665_HP_CALIB_CTRL_11 0x01e8
319#define RT5665_HP_CALIB_STA_1 0x01ea
320#define RT5665_HP_CALIB_STA_2 0x01eb
321#define RT5665_HP_CALIB_STA_3 0x01ec
322#define RT5665_HP_CALIB_STA_4 0x01ed
323#define RT5665_HP_CALIB_STA_5 0x01ee
324#define RT5665_HP_CALIB_STA_6 0x01ef
325#define RT5665_HP_CALIB_STA_7 0x01f0
326#define RT5665_HP_CALIB_STA_8 0x01f1
327#define RT5665_HP_CALIB_STA_9 0x01f2
328#define RT5665_HP_CALIB_STA_10 0x01f3
329#define RT5665_HP_CALIB_STA_11 0x01f4
330#define RT5665_PGM_TAB_CTRL1 0x0200
331#define RT5665_PGM_TAB_CTRL2 0x0201
332#define RT5665_PGM_TAB_CTRL3 0x0202
333#define RT5665_PGM_TAB_CTRL4 0x0203
334#define RT5665_PGM_TAB_CTRL5 0x0204
335#define RT5665_PGM_TAB_CTRL6 0x0205
336#define RT5665_PGM_TAB_CTRL7 0x0206
337#define RT5665_PGM_TAB_CTRL8 0x0207
338#define RT5665_PGM_TAB_CTRL9 0x0208
339#define RT5665_SAR_IL_CMD_1 0x0210
340#define RT5665_SAR_IL_CMD_2 0x0211
341#define RT5665_SAR_IL_CMD_3 0x0212
342#define RT5665_SAR_IL_CMD_4 0x0213
343#define RT5665_SAR_IL_CMD_5 0x0214
344#define RT5665_SAR_IL_CMD_6 0x0215
345#define RT5665_SAR_IL_CMD_7 0x0216
346#define RT5665_SAR_IL_CMD_8 0x0217
347#define RT5665_SAR_IL_CMD_9 0x0218
348#define RT5665_SAR_IL_CMD_10 0x0219
349#define RT5665_SAR_IL_CMD_11 0x021a
350#define RT5665_SAR_IL_CMD_12 0x021b
351#define RT5665_DRC1_CTRL_0 0x02ff
352#define RT5665_DRC1_CTRL_1 0x0300
353#define RT5665_DRC1_CTRL_2 0x0301
354#define RT5665_DRC1_CTRL_3 0x0302
355#define RT5665_DRC1_CTRL_4 0x0303
356#define RT5665_DRC1_CTRL_5 0x0304
357#define RT5665_DRC1_CTRL_6 0x0305
358#define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306
359#define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307
360#define RT5665_DRC1_PRIV_1 0x0310
361#define RT5665_DRC1_PRIV_2 0x0311
362#define RT5665_DRC1_PRIV_3 0x0312
363#define RT5665_DRC1_PRIV_4 0x0313
364#define RT5665_DRC1_PRIV_5 0x0314
365#define RT5665_DRC1_PRIV_6 0x0315
366#define RT5665_DRC1_PRIV_7 0x0316
367#define RT5665_DRC1_PRIV_8 0x0317
368#define RT5665_ALC_PGA_CTRL_1 0x0330
369#define RT5665_ALC_PGA_CTRL_2 0x0331
370#define RT5665_ALC_PGA_CTRL_3 0x0332
371#define RT5665_ALC_PGA_CTRL_4 0x0333
372#define RT5665_ALC_PGA_CTRL_5 0x0334
373#define RT5665_ALC_PGA_CTRL_6 0x0335
374#define RT5665_ALC_PGA_CTRL_7 0x0336
375#define RT5665_ALC_PGA_CTRL_8 0x0337
376#define RT5665_ALC_PGA_STA_1 0x0338
377#define RT5665_ALC_PGA_STA_2 0x0339
378#define RT5665_ALC_PGA_STA_3 0x033a
379#define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0
380#define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1
381#define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2
382#define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3
383#define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4
384#define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5
385#define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6
386#define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7
387#define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8
388#define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9
389#define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca
390#define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb
391#define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc
392#define RT5665_ADC_L_EQ_LPF1_A1 0x03d0
393#define RT5665_R_EQ_LPF1_A1 0x03d1
394#define RT5665_L_EQ_LPF1_H0 0x03d2
395#define RT5665_R_EQ_LPF1_H0 0x03d3
396#define RT5665_L_EQ_BPF1_A1 0x03d4
397#define RT5665_R_EQ_BPF1_A1 0x03d5
398#define RT5665_L_EQ_BPF1_A2 0x03d6
399#define RT5665_R_EQ_BPF1_A2 0x03d7
400#define RT5665_L_EQ_BPF1_H0 0x03d8
401#define RT5665_R_EQ_BPF1_H0 0x03d9
402#define RT5665_L_EQ_BPF2_A1 0x03da
403#define RT5665_R_EQ_BPF2_A1 0x03db
404#define RT5665_L_EQ_BPF2_A2 0x03dc
405#define RT5665_R_EQ_BPF2_A2 0x03dd
406#define RT5665_L_EQ_BPF2_H0 0x03de
407#define RT5665_R_EQ_BPF2_H0 0x03df
408#define RT5665_L_EQ_BPF3_A1 0x03e0
409#define RT5665_R_EQ_BPF3_A1 0x03e1
410#define RT5665_L_EQ_BPF3_A2 0x03e2
411#define RT5665_R_EQ_BPF3_A2 0x03e3
412#define RT5665_L_EQ_BPF3_H0 0x03e4
413#define RT5665_R_EQ_BPF3_H0 0x03e5
414#define RT5665_L_EQ_BPF4_A1 0x03e6
415#define RT5665_R_EQ_BPF4_A1 0x03e7
416#define RT5665_L_EQ_BPF4_A2 0x03e8
417#define RT5665_R_EQ_BPF4_A2 0x03e9
418#define RT5665_L_EQ_BPF4_H0 0x03ea
419#define RT5665_R_EQ_BPF4_H0 0x03eb
420#define RT5665_L_EQ_HPF1_A1 0x03ec
421#define RT5665_R_EQ_HPF1_A1 0x03ed
422#define RT5665_L_EQ_HPF1_H0 0x03ee
423#define RT5665_R_EQ_HPF1_H0 0x03ef
424#define RT5665_L_EQ_PRE_VOL 0x03f0
425#define RT5665_R_EQ_PRE_VOL 0x03f1
426#define RT5665_L_EQ_POST_VOL 0x03f2
427#define RT5665_R_EQ_POST_VOL 0x03f3
428#define RT5665_SCAN_MODE_CTRL 0x07f0
429#define RT5665_I2C_MODE 0x07fa
430
431
432
433/* global definition */
434#define RT5665_L_MUTE (0x1 << 15)
435#define RT5665_L_MUTE_SFT 15
436#define RT5665_VOL_L_MUTE (0x1 << 14)
437#define RT5665_VOL_L_SFT 14
438#define RT5665_R_MUTE (0x1 << 7)
439#define RT5665_R_MUTE_SFT 7
440#define RT5665_VOL_R_MUTE (0x1 << 6)
441#define RT5665_VOL_R_SFT 6
442#define RT5665_L_VOL_MASK (0x3f << 8)
443#define RT5665_L_VOL_SFT 8
444#define RT5665_R_VOL_MASK (0x3f)
445#define RT5665_R_VOL_SFT 0
446
447/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
448#define RT5665_G_HP (0xf << 8)
449#define RT5665_G_HP_SFT 8
450#define RT5665_G_STO_DA_DMIX (0xf)
451#define RT5665_G_STO_DA_SFT 0
452
453/* CBJ Control (0x000b) */
454#define RT5665_BST_CBJ_MASK (0xf << 8)
455#define RT5665_BST_CBJ_SFT 8
456
457/* IN1/IN2 Control (0x000c) */
458#define RT5665_IN1_DF_MASK (0x1 << 15)
459#define RT5665_IN1_DF 15
460#define RT5665_BST1_MASK (0x7f << 8)
461#define RT5665_BST1_SFT 8
462#define RT5665_IN2_DF_MASK (0x1 << 7)
463#define RT5665_IN2_DF 7
464#define RT5665_BST2_MASK (0x7f)
465#define RT5665_BST2_SFT 0
466
467/* IN3/IN4 Control (0x000d) */
468#define RT5665_IN3_DF_MASK (0x1 << 15)
469#define RT5665_IN3_DF 15
470#define RT5665_BST3_MASK (0x7f << 8)
471#define RT5665_BST3_SFT 8
472#define RT5665_IN4_DF_MASK (0x1 << 7)
473#define RT5665_IN4_DF 7
474#define RT5665_BST4_MASK (0x7f)
475#define RT5665_BST4_SFT 0
476
477/* INL and INR Volume Control (0x000f) */
478#define RT5665_INL_VOL_MASK (0x1f << 8)
479#define RT5665_INL_VOL_SFT 8
480#define RT5665_INR_VOL_MASK (0x1f)
481#define RT5665_INR_VOL_SFT 0
482
483/* Embeeded Jack and Type Detection Control 1 (0x0010) */
484#define RT5665_EMB_JD_EN (0x1 << 15)
485#define RT5665_EMB_JD_EN_SFT 15
486#define RT5665_JD_MODE (0x1 << 13)
487#define RT5665_JD_MODE_SFT 13
488#define RT5665_POLA_EXT_JD_MASK (0x1 << 11)
489#define RT5665_POLA_EXT_JD_LOW (0x1 << 11)
490#define RT5665_POLA_EXT_JD_HIGH (0x0 << 11)
491#define RT5665_EXT_JD_DIG (0x1 << 9)
492#define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
493#define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
494#define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
495#define RT5665_VREF_POW_MASK (0x1 << 6)
496#define RT5665_VREF_POW_FSM (0x0 << 6)
497#define RT5665_VREF_POW_REG (0x1 << 6)
498#define RT5665_MB1_PATH_MASK (0x1 << 5)
499#define RT5665_CTRL_MB1_REG (0x1 << 5)
500#define RT5665_CTRL_MB1_FSM (0x0 << 5)
501#define RT5665_MB2_PATH_MASK (0x1 << 4)
502#define RT5665_CTRL_MB2_REG (0x1 << 4)
503#define RT5665_CTRL_MB2_FSM (0x0 << 4)
504#define RT5665_TRIG_JD_MASK (0x1 << 3)
505#define RT5665_TRIG_JD_HIGH (0x1 << 3)
506#define RT5665_TRIG_JD_LOW (0x0 << 3)
507
508/* Embeeded Jack and Type Detection Control 2 (0x0011) */
509#define RT5665_EXT_JD_SRC (0x7 << 4)
510#define RT5665_EXT_JD_SRC_SFT 4
511#define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
512#define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
513#define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)
514#define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)
515#define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)
516#define RT5665_EXT_JD_SRC_JD3 (0x5 << 4)
517#define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4)
518
519/* Combo Jack and Type Detection Control 4 (0x0013) */
520#define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
521#define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
522#define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
523#define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)
524#define RT5665_CBJ_JD_TEST_NORM (0x0 << 6)
525#define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)
526
527/* Slience Detection Control (0x0015) */
528#define RT5665_SIL_DET_MASK (0x1 << 15)
529#define RT5665_SIL_DET_DIS (0x0 << 15)
530#define RT5665_SIL_DET_EN (0x1 << 15)
531
532/* DAC2 Control (0x0017) */
533#define RT5665_M_DAC2_L_VOL (0x1 << 13)
534#define RT5665_M_DAC2_L_VOL_SFT 13
535#define RT5665_M_DAC2_R_VOL (0x1 << 12)
536#define RT5665_M_DAC2_R_VOL_SFT 12
537#define RT5665_DAC_L2_SEL_MASK (0x7 << 4)
538#define RT5665_DAC_L2_SEL_SFT 4
539#define RT5665_DAC_R2_SEL_MASK (0x7 << 0)
540#define RT5665_DAC_R2_SEL_SFT 0
541
542/* Sidetone Control (0x0018) */
543#define RT5665_ST_SEL_MASK (0x7 << 9)
544#define RT5665_ST_SEL_SFT 9
545#define RT5665_ST_EN (0x1 << 6)
546#define RT5665_ST_EN_SFT 6
547
548/* DAC1 Digital Volume (0x0019) */
549#define RT5665_DAC_L1_VOL_MASK (0xff << 8)
550#define RT5665_DAC_L1_VOL_SFT 8
551#define RT5665_DAC_R1_VOL_MASK (0xff)
552#define RT5665_DAC_R1_VOL_SFT 0
553
554/* DAC2 Digital Volume (0x001a) */
555#define RT5665_DAC_L2_VOL_MASK (0xff << 8)
556#define RT5665_DAC_L2_VOL_SFT 8
557#define RT5665_DAC_R2_VOL_MASK (0xff)
558#define RT5665_DAC_R2_VOL_SFT 0
559
560/* DAC3 Control (0x001b) */
561#define RT5665_M_DAC3_L_VOL (0x1 << 13)
562#define RT5665_M_DAC3_L_VOL_SFT 13
563#define RT5665_M_DAC3_R_VOL (0x1 << 12)
564#define RT5665_M_DAC3_R_VOL_SFT 12
565#define RT5665_DAC_L3_SEL_MASK (0x7 << 4)
566#define RT5665_DAC_L3_SEL_SFT 4
567#define RT5665_DAC_R3_SEL_MASK (0x7 << 0)
568#define RT5665_DAC_R3_SEL_SFT 0
569
570/* ADC Digital Volume Control (0x001c) */
571#define RT5665_ADC_L_VOL_MASK (0x7f << 8)
572#define RT5665_ADC_L_VOL_SFT 8
573#define RT5665_ADC_R_VOL_MASK (0x7f)
574#define RT5665_ADC_R_VOL_SFT 0
575
576/* Mono ADC Digital Volume Control (0x001d) */
577#define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
578#define RT5665_MONO_ADC_L_VOL_SFT 8
579#define RT5665_MONO_ADC_R_VOL_MASK (0x7f)
580#define RT5665_MONO_ADC_R_VOL_SFT 0
581
582/* Stereo1 ADC Boost Gain Control (0x001f) */
583#define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)
584#define RT5665_STO1_ADC_L_BST_SFT 14
585#define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
586#define RT5665_STO1_ADC_R_BST_SFT 12
587
588/* Mono ADC Boost Gain Control (0x0020) */
589#define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)
590#define RT5665_MONO_ADC_L_BST_SFT 14
591#define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
592#define RT5665_MONO_ADC_R_BST_SFT 12
593
594/* Stereo1 ADC Boost Gain Control (0x001f) */
595#define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)
596#define RT5665_STO2_ADC_L_BST_SFT 14
597#define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
598#define RT5665_STO2_ADC_R_BST_SFT 12
599
600/* Stereo1 ADC Mixer Control (0x0026) */
601#define RT5665_M_STO1_ADC_L1 (0x1 << 15)
602#define RT5665_M_STO1_ADC_L1_SFT 15
603#define RT5665_M_STO1_ADC_L2 (0x1 << 14)
604#define RT5665_M_STO1_ADC_L2_SFT 14
605#define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
606#define RT5665_STO1_ADC1L_SRC_SFT 13
607#define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
608#define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)
609#define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
610#define RT5665_STO1_ADC2L_SRC_SFT 12
611#define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)
612#define RT5665_STO1_ADCL_SRC_SFT 10
613#define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
614#define RT5665_STO1_DD_L_SRC_SFT 9
615#define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
616#define RT5665_STO1_DMIC_SRC_SFT 8
617#define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
618#define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
619#define RT5665_M_STO1_ADC_R1 (0x1 << 7)
620#define RT5665_M_STO1_ADC_R1_SFT 7
621#define RT5665_M_STO1_ADC_R2 (0x1 << 6)
622#define RT5665_M_STO1_ADC_R2_SFT 6
623#define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)
624#define RT5665_STO1_ADC1R_SRC_SFT 5
625#define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)
626#define RT5665_STO1_ADC2R_SRC_SFT 4
627#define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2)
628#define RT5665_STO1_ADCR_SRC_SFT 2
629#define RT5665_STO1_DD_R_SRC_MASK (0x3)
630#define RT5665_STO1_DD_R_SRC_SFT 0
631
632
633/* Mono1 ADC Mixer control (0x0027) */
634#define RT5665_M_MONO_ADC_L1 (0x1 << 15)
635#define RT5665_M_MONO_ADC_L1_SFT 15
636#define RT5665_M_MONO_ADC_L2 (0x1 << 14)
637#define RT5665_M_MONO_ADC_L2_SFT 14
638#define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
639#define RT5665_MONO_ADC_L1_SRC_SFT 13
640#define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
641#define RT5665_MONO_ADC_L2_SRC_SFT 12
642#define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10)
643#define RT5665_MONO_ADC_L_SRC_SFT 10
644#define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
645#define RT5665_MONO_DD_L_SRC_SFT 9
646#define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
647#define RT5665_MONO_DMIC_L_SRC_SFT 8
648#define RT5665_M_MONO_ADC_R1 (0x1 << 7)
649#define RT5665_M_MONO_ADC_R1_SFT 7
650#define RT5665_M_MONO_ADC_R2 (0x1 << 6)
651#define RT5665_M_MONO_ADC_R2_SFT 6
652#define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)
653#define RT5665_MONO_ADC_R1_SRC_SFT 5
654#define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)
655#define RT5665_MONO_ADC_R2_SRC_SFT 4
656#define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2)
657#define RT5665_MONO_ADC_R_SRC_SFT 2
658#define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)
659#define RT5665_MONO_DD_R_SRC_SFT 1
660#define RT5665_MONO_DMIC_R_SRC_MASK 0x1
661#define RT5665_MONO_DMIC_R_SRC_SFT 0
662
663/* Stereo2 ADC Mixer Control (0x0028) */
664#define RT5665_M_STO2_ADC_L1 (0x1 << 15)
665#define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)
666#define RT5665_M_STO2_ADC_L1_SFT 15
667#define RT5665_M_STO2_ADC_L2 (0x1 << 14)
668#define RT5665_M_STO2_ADC_L2_SFT 14
669#define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
670#define RT5665_STO2_ADC1L_SRC_SFT 13
671#define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
672#define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)
673#define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
674#define RT5665_STO2_ADC2L_SRC_SFT 12
675#define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10)
676#define RT5665_STO2_ADCL_SRC_SFT 10
677#define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
678#define RT5665_STO2_DD_L_SRC_SFT 9
679#define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
680#define RT5665_STO2_DMIC_SRC_SFT 8
681#define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
682#define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
683#define RT5665_M_STO2_ADC_R1 (0x1 << 7)
684#define RT5665_M_STO2_ADC_R1_UN (0x0 << 7)
685#define RT5665_M_STO2_ADC_R1_SFT 7
686#define RT5665_M_STO2_ADC_R2 (0x1 << 6)
687#define RT5665_M_STO2_ADC_R2_SFT 6
688#define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)
689#define RT5665_STO2_ADC1R_SRC_SFT 5
690#define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)
691#define RT5665_STO2_ADC2R_SRC_SFT 4
692#define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2)
693#define RT5665_STO2_ADCR_SRC_SFT 2
694#define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)
695#define RT5665_STO2_DD_R_SRC_SFT 1
696
697/* ADC Mixer to DAC Mixer Control (0x0029) */
698#define RT5665_M_ADCMIX_L (0x1 << 15)
699#define RT5665_M_ADCMIX_L_SFT 15
700#define RT5665_M_DAC1_L (0x1 << 14)
701#define RT5665_M_DAC1_L_SFT 14
702#define RT5665_DAC1_R_SEL_MASK (0x3 << 10)
703#define RT5665_DAC1_R_SEL_SFT 10
704#define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
705#define RT5665_DAC1_L_SEL_SFT 8
706#define RT5665_M_ADCMIX_R (0x1 << 7)
707#define RT5665_M_ADCMIX_R_SFT 7
708#define RT5665_M_DAC1_R (0x1 << 6)
709#define RT5665_M_DAC1_R_SFT 6
710
711/* Stereo1 DAC Mixer Control (0x002a) */
712#define RT5665_M_DAC_L1_STO_L (0x1 << 15)
713#define RT5665_M_DAC_L1_STO_L_SFT 15
714#define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)
715#define RT5665_G_DAC_L1_STO_L_SFT 14
716#define RT5665_M_DAC_R1_STO_L (0x1 << 13)
717#define RT5665_M_DAC_R1_STO_L_SFT 13
718#define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
719#define RT5665_G_DAC_R1_STO_L_SFT 12
720#define RT5665_M_DAC_L2_STO_L (0x1 << 11)
721#define RT5665_M_DAC_L2_STO_L_SFT 11
722#define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)
723#define RT5665_G_DAC_L2_STO_L_SFT 10
724#define RT5665_M_DAC_R2_STO_L (0x1 << 9)
725#define RT5665_M_DAC_R2_STO_L_SFT 9
726#define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
727#define RT5665_G_DAC_R2_STO_L_SFT 8
728#define RT5665_M_DAC_L1_STO_R (0x1 << 7)
729#define RT5665_M_DAC_L1_STO_R_SFT 7
730#define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)
731#define RT5665_G_DAC_L1_STO_R_SFT 6
732#define RT5665_M_DAC_R1_STO_R (0x1 << 5)
733#define RT5665_M_DAC_R1_STO_R_SFT 5
734#define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)
735#define RT5665_G_DAC_R1_STO_R_SFT 4
736#define RT5665_M_DAC_L2_STO_R (0x1 << 3)
737#define RT5665_M_DAC_L2_STO_R_SFT 3
738#define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)
739#define RT5665_G_DAC_L2_STO_R_SFT 2
740#define RT5665_M_DAC_R2_STO_R (0x1 << 1)
741#define RT5665_M_DAC_R2_STO_R_SFT 1
742#define RT5665_G_DAC_R2_STO_R_MASK (0x1)
743#define RT5665_G_DAC_R2_STO_R_SFT 0
744
745/* Mono DAC Mixer Control (0x002b) */
746#define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
747#define RT5665_M_DAC_L1_MONO_L_SFT 15
748#define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)
749#define RT5665_G_DAC_L1_MONO_L_SFT 14
750#define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
751#define RT5665_M_DAC_R1_MONO_L_SFT 13
752#define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
753#define RT5665_G_DAC_R1_MONO_L_SFT 12
754#define RT5665_M_DAC_L2_MONO_L (0x1 << 11)
755#define RT5665_M_DAC_L2_MONO_L_SFT 11
756#define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)
757#define RT5665_G_DAC_L2_MONO_L_SFT 10
758#define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
759#define RT5665_M_DAC_R2_MONO_L_SFT 9
760#define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
761#define RT5665_G_DAC_R2_MONO_L_SFT 8
762#define RT5665_M_DAC_L1_MONO_R (0x1 << 7)
763#define RT5665_M_DAC_L1_MONO_R_SFT 7
764#define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)
765#define RT5665_G_DAC_L1_MONO_R_SFT 6
766#define RT5665_M_DAC_R1_MONO_R (0x1 << 5)
767#define RT5665_M_DAC_R1_MONO_R_SFT 5
768#define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)
769#define RT5665_G_DAC_R1_MONO_R_SFT 4
770#define RT5665_M_DAC_L2_MONO_R (0x1 << 3)
771#define RT5665_M_DAC_L2_MONO_R_SFT 3
772#define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)
773#define RT5665_G_DAC_L2_MONO_R_SFT 2
774#define RT5665_M_DAC_R2_MONO_R (0x1 << 1)
775#define RT5665_M_DAC_R2_MONO_R_SFT 1
776#define RT5665_G_DAC_R2_MONO_R_MASK (0x1)
777#define RT5665_G_DAC_R2_MONO_R_SFT 0
778
779/* Stereo2 DAC Mixer Control (0x002c) */
780#define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
781#define RT5665_M_DAC_L1_STO2_L_SFT 15
782#define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)
783#define RT5665_G_DAC_L1_STO2_L_SFT 14
784#define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
785#define RT5665_M_DAC_L2_STO2_L_SFT 13
786#define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
787#define RT5665_G_DAC_L2_STO2_L_SFT 12
788#define RT5665_M_DAC_L3_STO2_L (0x1 << 11)
789#define RT5665_M_DAC_L3_STO2_L_SFT 11
790#define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)
791#define RT5665_G_DAC_L3_STO2_L_SFT 10
792#define RT5665_M_ST_DAC_L1 (0x1 << 9)
793#define RT5665_M_ST_DAC_L1_SFT 9
794#define RT5665_M_ST_DAC_R1 (0x1 << 8)
795#define RT5665_M_ST_DAC_R1_SFT 8
796#define RT5665_M_DAC_R1_STO2_R (0x1 << 7)
797#define RT5665_M_DAC_R1_STO2_R_SFT 7
798#define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)
799#define RT5665_G_DAC_R1_STO2_R_SFT 6
800#define RT5665_M_DAC_R2_STO2_R (0x1 << 5)
801#define RT5665_M_DAC_R2_STO2_R_SFT 5
802#define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)
803#define RT5665_G_DAC_R2_STO2_R_SFT 4
804#define RT5665_M_DAC_R3_STO2_R (0x1 << 3)
805#define RT5665_M_DAC_R3_STO2_R_SFT 3
806#define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)
807#define RT5665_G_DAC_R3_STO2_R_SFT 2
808
809/* Analog DAC1 Input Source Control (0x002d) */
810#define RT5665_DAC_MIX_L_MASK (0x3 << 12)
811#define RT5665_DAC_MIX_L_SFT 12
812#define RT5665_DAC_MIX_R_MASK (0x3 << 8)
813#define RT5665_DAC_MIX_R_SFT 8
814#define RT5665_DAC_L1_SRC_MASK (0x3 << 4)
815#define RT5665_A_DACL1_SFT 4
816#define RT5665_DAC_R1_SRC_MASK (0x3)
817#define RT5665_A_DACR1_SFT 0
818
819/* Analog DAC Input Source Control (0x002e) */
820#define RT5665_A_DACL2_SEL (0x1 << 4)
821#define RT5665_A_DACL2_SFT 4
822#define RT5665_A_DACR2_SEL (0x1 << 0)
823#define RT5665_A_DACR2_SFT 0
824
825/* Digital Interface Data Control (0x002f) */
826#define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
827#define RT5665_IF2_1_ADC_IN_SFT 12
828#define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10)
829#define RT5665_IF2_1_DAC_SEL_SFT 10
830#define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
831#define RT5665_IF2_1_ADC_SEL_SFT 8
832#define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4)
833#define RT5665_IF2_2_ADC_IN_SFT 4
834#define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2)
835#define RT5665_IF2_2_DAC_SEL_SFT 2
836#define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0)
837#define RT5665_IF2_2_ADC_SEL_SFT 0
838
839/* Digital Interface Data Control (0x0030) */
840#define RT5665_IF3_ADC_IN_MASK (0x7 << 4)
841#define RT5665_IF3_ADC_IN_SFT 4
842#define RT5665_IF3_DAC_SEL_MASK (0x3 << 2)
843#define RT5665_IF3_DAC_SEL_SFT 2
844#define RT5665_IF3_ADC_SEL_MASK (0x3 << 0)
845#define RT5665_IF3_ADC_SEL_SFT 0
846
847/* PDM Output Control (0x0031) */
848#define RT5665_M_PDM1_L (0x1 << 14)
849#define RT5665_M_PDM1_L_SFT 14
850#define RT5665_M_PDM1_R (0x1 << 12)
851#define RT5665_M_PDM1_R_SFT 12
852#define RT5665_PDM1_L_MASK (0x3 << 10)
853#define RT5665_PDM1_L_SFT 10
854#define RT5665_PDM1_R_MASK (0x3 << 8)
855#define RT5665_PDM1_R_SFT 8
856#define RT5665_PDM1_BUSY (0x1 << 6)
857#define RT5665_PDM_PATTERN (0x1 << 5)
858#define RT5665_PDM_GAIN (0x1 << 4)
859#define RT5665_LRCK_PDM_PI2C (0x1 << 3)
860#define RT5665_PDM_DIV_MASK (0x3)
861
862/*S/PDIF Output Control (0x0036) */
863#define RT5665_SPDIF_SEL_MASK (0x3 << 0)
864#define RT5665_SPDIF_SEL_SFT 0
865
866/* REC Left Mixer Control 2 (0x003c) */
867#define RT5665_M_CBJ_RM1_L (0x1 << 7)
868#define RT5665_M_CBJ_RM1_L_SFT 7
869#define RT5665_M_BST1_RM1_L (0x1 << 5)
870#define RT5665_M_BST1_RM1_L_SFT 5
871#define RT5665_M_BST2_RM1_L (0x1 << 4)
872#define RT5665_M_BST2_RM1_L_SFT 4
873#define RT5665_M_BST3_RM1_L (0x1 << 3)
874#define RT5665_M_BST3_RM1_L_SFT 3
875#define RT5665_M_BST4_RM1_L (0x1 << 2)
876#define RT5665_M_BST4_RM1_L_SFT 2
877#define RT5665_M_INL_RM1_L (0x1 << 1)
878#define RT5665_M_INL_RM1_L_SFT 1
879#define RT5665_M_INR_RM1_L (0x1)
880#define RT5665_M_INR_RM1_L_SFT 0
881
882/* REC Right Mixer Control 2 (0x003e) */
883#define RT5665_M_AEC_REF_RM1_R (0x1 << 7)
884#define RT5665_M_AEC_REF_RM1_R_SFT 7
885#define RT5665_M_BST1_RM1_R (0x1 << 5)
886#define RT5665_M_BST1_RM1_R_SFT 5
887#define RT5665_M_BST2_RM1_R (0x1 << 4)
888#define RT5665_M_BST2_RM1_R_SFT 4
889#define RT5665_M_BST3_RM1_R (0x1 << 3)
890#define RT5665_M_BST3_RM1_R_SFT 3
891#define RT5665_M_BST4_RM1_R (0x1 << 2)
892#define RT5665_M_BST4_RM1_R_SFT 2
893#define RT5665_M_INR_RM1_R (0x1 << 1)
894#define RT5665_M_INR_RM1_R_SFT 1
895#define RT5665_M_MONOVOL_RM1_R (0x1)
896#define RT5665_M_MONOVOL_RM1_R_SFT 0
897
898/* REC Mixer 2 Left Control 2 (0x0041) */
899#define RT5665_M_CBJ_RM2_L (0x1 << 7)
900#define RT5665_M_CBJ_RM2_L_SFT 7
901#define RT5665_M_BST1_RM2_L (0x1 << 5)
902#define RT5665_M_BST1_RM2_L_SFT 5
903#define RT5665_M_BST2_RM2_L (0x1 << 4)
904#define RT5665_M_BST2_RM2_L_SFT 4
905#define RT5665_M_BST3_RM2_L (0x1 << 3)
906#define RT5665_M_BST3_RM2_L_SFT 3
907#define RT5665_M_BST4_RM2_L (0x1 << 2)
908#define RT5665_M_BST4_RM2_L_SFT 2
909#define RT5665_M_INL_RM2_L (0x1 << 1)
910#define RT5665_M_INL_RM2_L_SFT 1
911#define RT5665_M_INR_RM2_L (0x1)
912#define RT5665_M_INR_RM2_L_SFT 0
913
914/* REC Mixer 2 Right Control 2 (0x0043) */
915#define RT5665_M_MONOVOL_RM2_R (0x1 << 7)
916#define RT5665_M_MONOVOL_RM2_R_SFT 7
917#define RT5665_M_BST1_RM2_R (0x1 << 5)
918#define RT5665_M_BST1_RM2_R_SFT 5
919#define RT5665_M_BST2_RM2_R (0x1 << 4)
920#define RT5665_M_BST2_RM2_R_SFT 4
921#define RT5665_M_BST3_RM2_R (0x1 << 3)
922#define RT5665_M_BST3_RM2_R_SFT 3
923#define RT5665_M_BST4_RM2_R (0x1 << 2)
924#define RT5665_M_BST4_RM2_R_SFT 2
925#define RT5665_M_INL_RM2_R (0x1 << 1)
926#define RT5665_M_INL_RM2_R_SFT 1
927#define RT5665_M_INR_RM2_R (0x1)
928#define RT5665_M_INR_RM2_R_SFT 0
929
930/* SPK Left Mixer Control (0x0046) */
931#define RT5665_M_BST3_SM_L (0x1 << 4)
932#define RT5665_M_BST3_SM_L_SFT 4
933#define RT5665_M_IN_R_SM_L (0x1 << 3)
934#define RT5665_M_IN_R_SM_L_SFT 3
935#define RT5665_M_IN_L_SM_L (0x1 << 2)
936#define RT5665_M_IN_L_SM_L_SFT 2
937#define RT5665_M_BST1_SM_L (0x1 << 1)
938#define RT5665_M_BST1_SM_L_SFT 1
939#define RT5665_M_DAC_L2_SM_L (0x1)
940#define RT5665_M_DAC_L2_SM_L_SFT 0
941
942/* SPK Right Mixer Control (0x0047) */
943#define RT5665_M_BST3_SM_R (0x1 << 4)
944#define RT5665_M_BST3_SM_R_SFT 4
945#define RT5665_M_IN_R_SM_R (0x1 << 3)
946#define RT5665_M_IN_R_SM_R_SFT 3
947#define RT5665_M_IN_L_SM_R (0x1 << 2)
948#define RT5665_M_IN_L_SM_R_SFT 2
949#define RT5665_M_BST4_SM_R (0x1 << 1)
950#define RT5665_M_BST4_SM_R_SFT 1
951#define RT5665_M_DAC_R2_SM_R (0x1)
952#define RT5665_M_DAC_R2_SM_R_SFT 0
953
954/* SPO Amp Input and Gain Control (0x0048) */
955#define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
956#define RT5665_M_DAC_L2_SPKOMIX_SFT 13
957#define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
958#define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
959#define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
960#define RT5665_M_DAC_R2_SPKOMIX_SFT 9
961#define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
962#define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
963
964/* MONOMIX Input and Gain Control (0x004b) */
965#define RT5665_G_MONOVOL_MA (0x1 << 10)
966#define RT5665_G_MONOVOL_MA_SFT 10
967#define RT5665_M_MONOVOL_MA (0x1 << 9)
968#define RT5665_M_MONOVOL_MA_SFT 9
969#define RT5665_M_DAC_L2_MA (0x1 << 8)
970#define RT5665_M_DAC_L2_MA_SFT 8
971#define RT5665_M_BST3_MM (0x1 << 4)
972#define RT5665_M_BST3_MM_SFT 4
973#define RT5665_M_BST2_MM (0x1 << 3)
974#define RT5665_M_BST2_MM_SFT 3
975#define RT5665_M_BST1_MM (0x1 << 2)
976#define RT5665_M_BST1_MM_SFT 2
977#define RT5665_M_RECMIC2L_MM (0x1 << 1)
978#define RT5665_M_RECMIC2L_MM_SFT 1
979#define RT5665_M_DAC_L2_MM (0x1)
980#define RT5665_M_DAC_L2_MM_SFT 0
981
982/* Output Left Mixer Control 1 (0x004d) */
983#define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
984#define RT5665_G_BST3_OM_L_SFT 12
985#define RT5665_G_BST2_OM_L_MASK (0x7 << 9)
986#define RT5665_G_BST2_OM_L_SFT 9
987#define RT5665_G_BST1_OM_L_MASK (0x7 << 6)
988#define RT5665_G_BST1_OM_L_SFT 6
989#define RT5665_G_IN_L_OM_L_MASK (0x7 << 3)
990#define RT5665_G_IN_L_OM_L_SFT 3
991#define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0)
992#define RT5665_G_DAC_L2_OM_L_SFT 0
993
994/* Output Left Mixer Input Control (0x004e) */
995#define RT5665_M_BST3_OM_L (0x1 << 4)
996#define RT5665_M_BST3_OM_L_SFT 4
997#define RT5665_M_BST2_OM_L (0x1 << 3)
998#define RT5665_M_BST2_OM_L_SFT 3
999#define RT5665_M_BST1_OM_L (0x1 << 2)
1000#define RT5665_M_BST1_OM_L_SFT 2
1001#define RT5665_M_IN_L_OM_L (0x1 << 1)
1002#define RT5665_M_IN_L_OM_L_SFT 1
1003#define RT5665_M_DAC_L2_OM_L (0x1)
1004#define RT5665_M_DAC_L2_OM_L_SFT 0
1005
1006/* Output Right Mixer Input Control (0x0050) */
1007#define RT5665_M_BST4_OM_R (0x1 << 4)
1008#define RT5665_M_BST4_OM_R_SFT 4
1009#define RT5665_M_BST3_OM_R (0x1 << 3)
1010#define RT5665_M_BST3_OM_R_SFT 3
1011#define RT5665_M_BST2_OM_R (0x1 << 2)
1012#define RT5665_M_BST2_OM_R_SFT 2
1013#define RT5665_M_IN_R_OM_R (0x1 << 1)
1014#define RT5665_M_IN_R_OM_R_SFT 1
1015#define RT5665_M_DAC_R2_OM_R (0x1)
1016#define RT5665_M_DAC_R2_OM_R_SFT 0
1017
1018/* LOUT Mixer Control (0x0052) */
1019#define RT5665_M_DAC_L2_LM (0x1 << 15)
1020#define RT5665_M_DAC_L2_LM_SFT 15
1021#define RT5665_M_DAC_R2_LM (0x1 << 14)
1022#define RT5665_M_DAC_R2_LM_SFT 14
1023#define RT5665_M_OV_L_LM (0x1 << 13)
1024#define RT5665_M_OV_L_LM_SFT 13
1025#define RT5665_M_OV_R_LM (0x1 << 12)
1026#define RT5665_M_OV_R_LM_SFT 12
1027#define RT5665_LOUT_BST_SFT 11
1028#define RT5665_LOUT_DF (0x1 << 11)
1029#define RT5665_LOUT_DF_SFT 11
1030
1031/* Power Management for Digital 1 (0x0061) */
1032#define RT5665_PWR_I2S1_1 (0x1 << 15)
1033#define RT5665_PWR_I2S1_1_BIT 15
1034#define RT5665_PWR_I2S1_2 (0x1 << 14)
1035#define RT5665_PWR_I2S1_2_BIT 14
1036#define RT5665_PWR_I2S2_1 (0x1 << 13)
1037#define RT5665_PWR_I2S2_1_BIT 13
1038#define RT5665_PWR_I2S2_2 (0x1 << 12)
1039#define RT5665_PWR_I2S2_2_BIT 12
1040#define RT5665_PWR_DAC_L1 (0x1 << 11)
1041#define RT5665_PWR_DAC_L1_BIT 11
1042#define RT5665_PWR_DAC_R1 (0x1 << 10)
1043#define RT5665_PWR_DAC_R1_BIT 10
1044#define RT5665_PWR_I2S3 (0x1 << 9)
1045#define RT5665_PWR_I2S3_BIT 9
1046#define RT5665_PWR_LDO (0x1 << 8)
1047#define RT5665_PWR_LDO_BIT 8
1048#define RT5665_PWR_DAC_L2 (0x1 << 7)
1049#define RT5665_PWR_DAC_L2_BIT 7
1050#define RT5665_PWR_DAC_R2 (0x1 << 6)
1051#define RT5665_PWR_DAC_R2_BIT 6
1052#define RT5665_PWR_ADC_L1 (0x1 << 4)
1053#define RT5665_PWR_ADC_L1_BIT 4
1054#define RT5665_PWR_ADC_R1 (0x1 << 3)
1055#define RT5665_PWR_ADC_R1_BIT 3
1056#define RT5665_PWR_ADC_L2 (0x1 << 2)
1057#define RT5665_PWR_ADC_L2_BIT 2
1058#define RT5665_PWR_ADC_R2 (0x1 << 1)
1059#define RT5665_PWR_ADC_R2_BIT 1
1060
1061/* Power Management for Digital 2 (0x0062) */
1062#define RT5665_PWR_ADC_S1F (0x1 << 15)
1063#define RT5665_PWR_ADC_S1F_BIT 15
1064#define RT5665_PWR_ADC_S2F (0x1 << 14)
1065#define RT5665_PWR_ADC_S2F_BIT 14
1066#define RT5665_PWR_ADC_MF_L (0x1 << 13)
1067#define RT5665_PWR_ADC_MF_L_BIT 13
1068#define RT5665_PWR_ADC_MF_R (0x1 << 12)
1069#define RT5665_PWR_ADC_MF_R_BIT 12
1070#define RT5665_PWR_DAC_S2F (0x1 << 11)
1071#define RT5665_PWR_DAC_S2F_BIT 11
1072#define RT5665_PWR_DAC_S1F (0x1 << 10)
1073#define RT5665_PWR_DAC_S1F_BIT 10
1074#define RT5665_PWR_DAC_MF_L (0x1 << 9)
1075#define RT5665_PWR_DAC_MF_L_BIT 9
1076#define RT5665_PWR_DAC_MF_R (0x1 << 8)
1077#define RT5665_PWR_DAC_MF_R_BIT 8
1078#define RT5665_PWR_PDM1 (0x1 << 7)
1079#define RT5665_PWR_PDM1_BIT 7
1080
1081/* Power Management for Analog 1 (0x0063) */
1082#define RT5665_PWR_VREF1 (0x1 << 15)
1083#define RT5665_PWR_VREF1_BIT 15
1084#define RT5665_PWR_FV1 (0x1 << 14)
1085#define RT5665_PWR_FV1_BIT 14
1086#define RT5665_PWR_VREF2 (0x1 << 13)
1087#define RT5665_PWR_VREF2_BIT 13
1088#define RT5665_PWR_FV2 (0x1 << 12)
1089#define RT5665_PWR_FV2_BIT 12
1090#define RT5665_PWR_VREF3 (0x1 << 11)
1091#define RT5665_PWR_VREF3_BIT 11
1092#define RT5665_PWR_FV3 (0x1 << 10)
1093#define RT5665_PWR_FV3_BIT 10
1094#define RT5665_PWR_MB (0x1 << 9)
1095#define RT5665_PWR_MB_BIT 9
1096#define RT5665_PWR_LM (0x1 << 8)
1097#define RT5665_PWR_LM_BIT 8
1098#define RT5665_PWR_BG (0x1 << 7)
1099#define RT5665_PWR_BG_BIT 7
1100#define RT5665_PWR_MA (0x1 << 6)
1101#define RT5665_PWR_MA_BIT 6
1102#define RT5665_PWR_HA_L (0x1 << 5)
1103#define RT5665_PWR_HA_L_BIT 5
1104#define RT5665_PWR_HA_R (0x1 << 4)
1105#define RT5665_PWR_HA_R_BIT 4
1106#define RT5665_HP_DRIVER_MASK (0x3 << 2)
1107#define RT5665_HP_DRIVER_1X (0x0 << 2)
1108#define RT5665_HP_DRIVER_3X (0x1 << 2)
1109#define RT5665_HP_DRIVER_5X (0x2 << 2)
1110#define RT5665_LDO1_DVO_MASK (0x3)
1111#define RT5665_LDO1_DVO_09 (0x0)
1112#define RT5665_LDO1_DVO_10 (0x1)
1113#define RT5665_LDO1_DVO_12 (0x2)
1114#define RT5665_LDO1_DVO_14 (0x3)
1115
1116/* Power Management for Analog 2 (0x0064) */
1117#define RT5665_PWR_BST1 (0x1 << 15)
1118#define RT5665_PWR_BST1_BIT 15
1119#define RT5665_PWR_BST2 (0x1 << 14)
1120#define RT5665_PWR_BST2_BIT 14
1121#define RT5665_PWR_BST3 (0x1 << 13)
1122#define RT5665_PWR_BST3_BIT 13
1123#define RT5665_PWR_BST4 (0x1 << 12)
1124#define RT5665_PWR_BST4_BIT 12
1125#define RT5665_PWR_MB1 (0x1 << 11)
1126#define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11)
1127#define RT5665_PWR_MB1_BIT 11
1128#define RT5665_PWR_MB2 (0x1 << 10)
1129#define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10)
1130#define RT5665_PWR_MB2_BIT 10
1131#define RT5665_PWR_MB3 (0x1 << 9)
1132#define RT5665_PWR_MB3_BIT 9
1133#define RT5665_PWR_BST1_P (0x1 << 7)
1134#define RT5665_PWR_BST1_P_BIT 7
1135#define RT5665_PWR_BST2_P (0x1 << 6)
1136#define RT5665_PWR_BST2_P_BIT 6
1137#define RT5665_PWR_BST3_P (0x1 << 5)
1138#define RT5665_PWR_BST3_P_BIT 5
1139#define RT5665_PWR_BST4_P (0x1 << 4)
1140#define RT5665_PWR_BST4_P_BIT 4
1141#define RT5665_PWR_JD1 (0x1 << 3)
1142#define RT5665_PWR_JD1_BIT 3
1143#define RT5665_PWR_JD2 (0x1 << 2)
1144#define RT5665_PWR_JD2_BIT 2
1145#define RT5665_PWR_RM1_L (0x1 << 1)
1146#define RT5665_PWR_RM1_L_BIT 1
1147#define RT5665_PWR_RM1_R (0x1)
1148#define RT5665_PWR_RM1_R_BIT 0
1149
1150/* Power Management for Analog 3 (0x0065) */
1151#define RT5665_PWR_CBJ (0x1 << 9)
1152#define RT5665_PWR_CBJ_BIT 9
1153#define RT5665_PWR_BST_L (0x1 << 8)
1154#define RT5665_PWR_BST_L_BIT 8
1155#define RT5665_PWR_BST_R (0x1 << 7)
1156#define RT5665_PWR_BST_R_BIT 7
1157#define RT5665_PWR_PLL (0x1 << 6)
1158#define RT5665_PWR_PLL_BIT 6
1159#define RT5665_PWR_LDO2 (0x1 << 2)
1160#define RT5665_PWR_LDO2_BIT 2
1161#define RT5665_PWR_SVD (0x1 << 1)
1162#define RT5665_PWR_SVD_BIT 1
1163
1164/* Power Management for Mixer (0x0066) */
1165#define RT5665_PWR_RM2_L (0x1 << 15)
1166#define RT5665_PWR_RM2_L_BIT 15
1167#define RT5665_PWR_RM2_R (0x1 << 14)
1168#define RT5665_PWR_RM2_R_BIT 14
1169#define RT5665_PWR_OM_L (0x1 << 13)
1170#define RT5665_PWR_OM_L_BIT 13
1171#define RT5665_PWR_OM_R (0x1 << 12)
1172#define RT5665_PWR_OM_R_BIT 12
1173#define RT5665_PWR_MM (0x1 << 11)
1174#define RT5665_PWR_MM_BIT 11
1175#define RT5665_PWR_AEC_REF (0x1 << 6)
1176#define RT5665_PWR_AEC_REF_BIT 6
1177#define RT5665_PWR_STO1_DAC_L (0x1 << 5)
1178#define RT5665_PWR_STO1_DAC_L_BIT 5
1179#define RT5665_PWR_STO1_DAC_R (0x1 << 4)
1180#define RT5665_PWR_STO1_DAC_R_BIT 4
1181#define RT5665_PWR_MONO_DAC_L (0x1 << 3)
1182#define RT5665_PWR_MONO_DAC_L_BIT 3
1183#define RT5665_PWR_MONO_DAC_R (0x1 << 2)
1184#define RT5665_PWR_MONO_DAC_R_BIT 2
1185#define RT5665_PWR_STO2_DAC_L (0x1 << 1)
1186#define RT5665_PWR_STO2_DAC_L_BIT 1
1187#define RT5665_PWR_STO2_DAC_R (0x1)
1188#define RT5665_PWR_STO2_DAC_R_BIT 0
1189
1190/* Power Management for Volume (0x0067) */
1191#define RT5665_PWR_OV_L (0x1 << 13)
1192#define RT5665_PWR_OV_L_BIT 13
1193#define RT5665_PWR_OV_R (0x1 << 12)
1194#define RT5665_PWR_OV_R_BIT 12
1195#define RT5665_PWR_IN_L (0x1 << 9)
1196#define RT5665_PWR_IN_L_BIT 9
1197#define RT5665_PWR_IN_R (0x1 << 8)
1198#define RT5665_PWR_IN_R_BIT 8
1199#define RT5665_PWR_MV (0x1 << 7)
1200#define RT5665_PWR_MV_BIT 7
1201#define RT5665_PWR_MIC_DET (0x1 << 5)
1202#define RT5665_PWR_MIC_DET_BIT 5
1203
1204/* (0x006b) */
1205#define RT5665_SYS_CLK_DET 15
1206#define RT5665_HP_CLK_DET 14
1207#define RT5665_MONO_CLK_DET 13
1208#define RT5665_LOUT_CLK_DET 12
1209#define RT5665_POW_CLK_DET 0
1210
1211/* Digital Microphone Control 1 (0x006e) */
1212#define RT5665_DMIC_1_EN_MASK (0x1 << 15)
1213#define RT5665_DMIC_1_EN_SFT 15
1214#define RT5665_DMIC_1_DIS (0x0 << 15)
1215#define RT5665_DMIC_1_EN (0x1 << 15)
1216#define RT5665_DMIC_2_EN_MASK (0x1 << 14)
1217#define RT5665_DMIC_2_EN_SFT 14
1218#define RT5665_DMIC_2_DIS (0x0 << 14)
1219#define RT5665_DMIC_2_EN (0x1 << 14)
1220#define RT5665_DMIC_2_DP_MASK (0x1 << 9)
1221#define RT5665_DMIC_2_DP_SFT 9
1222#define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)
1223#define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
1224#define RT5665_DMIC_CLK_MASK (0x7 << 5)
1225#define RT5665_DMIC_CLK_SFT 5
1226#define RT5665_DMIC_1_DP_MASK (0x1 << 1)
1227#define RT5665_DMIC_1_DP_SFT 1
1228#define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1)
1229#define RT5665_DMIC_1_DP_IN2N (0x1 << 1)
1230
1231
1232/* Digital Microphone Control 1 (0x006f) */
1233#define RT5665_DMIC_2L_LH_MASK (0x1 << 3)
1234#define RT5665_DMIC_2L_LH_SFT 3
1235#define RT5665_DMIC_2L_LH_RISING (0x0 << 3)
1236#define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)
1237#define RT5665_DMIC_2R_LH_MASK (0x1 << 2)
1238#define RT5665_DMIC_2R_LH_SFT 2
1239#define RT5665_DMIC_2R_LH_RISING (0x0 << 2)
1240#define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)
1241#define RT5665_DMIC_1L_LH_MASK (0x1 << 1)
1242#define RT5665_DMIC_1L_LH_SFT 1
1243#define RT5665_DMIC_1L_LH_RISING (0x0 << 1)
1244#define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)
1245#define RT5665_DMIC_1R_LH_MASK (0x1 << 0)
1246#define RT5665_DMIC_1R_LH_SFT 0
1247#define RT5665_DMIC_1R_LH_RISING (0x0)
1248#define RT5665_DMIC_1R_LH_FALLING (0x1)
1249
1250/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
1251#define RT5665_I2S_MS_MASK (0x1 << 15)
1252#define RT5665_I2S_MS_SFT 15
1253#define RT5665_I2S_MS_M (0x0 << 15)
1254#define RT5665_I2S_MS_S (0x1 << 15)
1255#define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)
1256#define RT5665_I2S_PIN_CFG_SFT 14
1257#define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)
1258#define RT5665_I2S_CLK_SEL_SFT 11
1259#define RT5665_I2S_BP_MASK (0x1 << 8)
1260#define RT5665_I2S_BP_SFT 8
1261#define RT5665_I2S_BP_NOR (0x0 << 8)
1262#define RT5665_I2S_BP_INV (0x1 << 8)
1263#define RT5665_I2S_DL_MASK (0x3 << 4)
1264#define RT5665_I2S_DL_SFT 4
1265#define RT5665_I2S_DL_16 (0x0 << 4)
1266#define RT5665_I2S_DL_20 (0x1 << 4)
1267#define RT5665_I2S_DL_24 (0x2 << 4)
1268#define RT5665_I2S_DL_8 (0x3 << 4)
1269#define RT5665_I2S_DF_MASK (0x7)
1270#define RT5665_I2S_DF_SFT 0
1271#define RT5665_I2S_DF_I2S (0x0)
1272#define RT5665_I2S_DF_LEFT (0x1)
1273#define RT5665_I2S_DF_PCM_A (0x2)
1274#define RT5665_I2S_DF_PCM_B (0x3)
1275#define RT5665_I2S_DF_PCM_A_N (0x6)
1276#define RT5665_I2S_DF_PCM_B_N (0x7)
1277
1278/* ADC/DAC Clock Control 1 (0x0073) */
1279#define RT5665_I2S_PD1_MASK (0x7 << 12)
1280#define RT5665_I2S_PD1_SFT 12
1281#define RT5665_I2S_PD1_1 (0x0 << 12)
1282#define RT5665_I2S_PD1_2 (0x1 << 12)
1283#define RT5665_I2S_PD1_3 (0x2 << 12)
1284#define RT5665_I2S_PD1_4 (0x3 << 12)
1285#define RT5665_I2S_PD1_6 (0x4 << 12)
1286#define RT5665_I2S_PD1_8 (0x5 << 12)
1287#define RT5665_I2S_PD1_12 (0x6 << 12)
1288#define RT5665_I2S_PD1_16 (0x7 << 12)
1289#define RT5665_I2S_M_PD2_MASK (0x7 << 8)
1290#define RT5665_I2S_M_PD2_SFT 8
1291#define RT5665_I2S_M_PD2_1 (0x0 << 8)
1292#define RT5665_I2S_M_PD2_2 (0x1 << 8)
1293#define RT5665_I2S_M_PD2_3 (0x2 << 8)
1294#define RT5665_I2S_M_PD2_4 (0x3 << 8)
1295#define RT5665_I2S_M_PD2_6 (0x4 << 8)
1296#define RT5665_I2S_M_PD2_8 (0x5 << 8)
1297#define RT5665_I2S_M_PD2_12 (0x6 << 8)
1298#define RT5665_I2S_M_PD2_16 (0x7 << 8)
1299#define RT5665_I2S_CLK_SRC_MASK (0x3 << 4)
1300#define RT5665_I2S_CLK_SRC_SFT 4
1301#define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4)
1302#define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)
1303#define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4)
1304#define RT5665_DAC_OSR_MASK (0x3 << 2)
1305#define RT5665_DAC_OSR_SFT 2
1306#define RT5665_DAC_OSR_128 (0x0 << 2)
1307#define RT5665_DAC_OSR_64 (0x1 << 2)
1308#define RT5665_DAC_OSR_32 (0x2 << 2)
1309#define RT5665_ADC_OSR_MASK (0x3)
1310#define RT5665_ADC_OSR_SFT 0
1311#define RT5665_ADC_OSR_128 (0x0)
1312#define RT5665_ADC_OSR_64 (0x1)
1313#define RT5665_ADC_OSR_32 (0x2)
1314
1315/* ADC/DAC Clock Control 2 (0x0074) */
1316#define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
1317#define RT5665_I2S_BCLK_MS2_SFT 15
1318#define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)
1319#define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
1320#define RT5665_I2S_PD2_MASK (0x7 << 12)
1321#define RT5665_I2S_PD2_SFT 12
1322#define RT5665_I2S_PD2_1 (0x0 << 12)
1323#define RT5665_I2S_PD2_2 (0x1 << 12)
1324#define RT5665_I2S_PD2_3 (0x2 << 12)
1325#define RT5665_I2S_PD2_4 (0x3 << 12)
1326#define RT5665_I2S_PD2_6 (0x4 << 12)
1327#define RT5665_I2S_PD2_8 (0x5 << 12)
1328#define RT5665_I2S_PD2_12 (0x6 << 12)
1329#define RT5665_I2S_PD2_16 (0x7 << 12)
1330#define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)
1331#define RT5665_I2S_BCLK_MS3_SFT 11
1332#define RT5665_I2S_BCLK_MS3_32 (0x0 << 11)
1333#define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)
1334#define RT5665_I2S_PD3_MASK (0x7 << 8)
1335#define RT5665_I2S_PD3_SFT 8
1336#define RT5665_I2S_PD3_1 (0x0 << 8)
1337#define RT5665_I2S_PD3_2 (0x1 << 8)
1338#define RT5665_I2S_PD3_3 (0x2 << 8)
1339#define RT5665_I2S_PD3_4 (0x3 << 8)
1340#define RT5665_I2S_PD3_6 (0x4 << 8)
1341#define RT5665_I2S_PD3_8 (0x5 << 8)
1342#define RT5665_I2S_PD3_12 (0x6 << 8)
1343#define RT5665_I2S_PD3_16 (0x7 << 8)
1344#define RT5665_I2S_PD4_MASK (0x7 << 4)
1345#define RT5665_I2S_PD4_SFT 4
1346#define RT5665_I2S_PD4_1 (0x0 << 4)
1347#define RT5665_I2S_PD4_2 (0x1 << 4)
1348#define RT5665_I2S_PD4_3 (0x2 << 4)
1349#define RT5665_I2S_PD4_4 (0x3 << 4)
1350#define RT5665_I2S_PD4_6 (0x4 << 4)
1351#define RT5665_I2S_PD4_8 (0x5 << 4)
1352#define RT5665_I2S_PD4_12 (0x6 << 4)
1353#define RT5665_I2S_PD4_16 (0x7 << 4)
1354
1355/* TDM control 1 (0x0078) */
1356#define RT5665_I2S1_MODE_MASK (0x1 << 15)
1357#define RT5665_I2S1_MODE_I2S (0x0 << 15)
1358#define RT5665_I2S1_MODE_TDM (0x1 << 15)
1359#define RT5665_TDM_IN_CH_MASK (0x3 << 10)
1360#define RT5665_TDM_IN_CH_2 (0x0 << 10)
1361#define RT5665_TDM_IN_CH_4 (0x1 << 10)
1362#define RT5665_TDM_IN_CH_6 (0x2 << 10)
1363#define RT5665_TDM_IN_CH_8 (0x3 << 10)
1364#define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
1365#define RT5665_TDM_OUT_CH_2 (0x0 << 8)
1366#define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1367#define RT5665_TDM_OUT_CH_6 (0x2 << 8)
1368#define RT5665_TDM_OUT_CH_8 (0x3 << 8)
1369#define RT5665_TDM_IN_LEN_MASK (0x3 << 6)
1370#define RT5665_TDM_IN_LEN_16 (0x0 << 6)
1371#define RT5665_TDM_IN_LEN_20 (0x1 << 6)
1372#define RT5665_TDM_IN_LEN_24 (0x2 << 6)
1373#define RT5665_TDM_IN_LEN_32 (0x3 << 6)
1374#define RT5665_TDM_OUT_LEN_MASK (0x3 << 4)
1375#define RT5665_TDM_OUT_LEN_16 (0x0 << 4)
1376#define RT5665_TDM_OUT_LEN_20 (0x1 << 4)
1377#define RT5665_TDM_OUT_LEN_24 (0x2 << 4)
1378#define RT5665_TDM_OUT_LEN_32 (0x3 << 4)
1379
1380
1381/* TDM control 2 (0x0079) */
1382#define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 14
1383#define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
1384#define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 10
1385#define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
1386#define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 6
1387#define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 4
1388#define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 2
1389#define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 0
1390
1391/* TDM control 3/4 (0x007a) (0x007b) */
1392#define RT5665_IF1_ADC1_SEL_SFT 10
1393#define RT5665_IF1_ADC2_SEL_SFT 9
1394#define RT5665_IF1_ADC3_SEL_SFT 8
1395#define RT5665_IF1_ADC4_SEL_SFT 7
1396#define RT5665_TDM_ADC_SEL_SFT 0
1397#define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0)
1398#define RT5665_TDM_ADC_DATA_06 (0x6 << 0)
1399
1400/* Global Clock Control (0x0080) */
1401#define RT5665_SCLK_SRC_MASK (0x3 << 14)
1402#define RT5665_SCLK_SRC_SFT 14
1403#define RT5665_SCLK_SRC_MCLK (0x0 << 14)
1404#define RT5665_SCLK_SRC_PLL1 (0x1 << 14)
1405#define RT5665_SCLK_SRC_RCCLK (0x2 << 14)
1406#define RT5665_PLL1_SRC_MASK (0x7 << 8)
1407#define RT5665_PLL1_SRC_SFT 8
1408#define RT5665_PLL1_SRC_MCLK (0x0 << 8)
1409#define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1410#define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
1411#define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
1412#define RT5665_PLL1_PD_MASK (0x7 << 4)
1413#define RT5665_PLL1_PD_SFT 4
1414
1415
1416#define RT5665_PLL_INP_MAX 40000000
1417#define RT5665_PLL_INP_MIN 256000
1418/* PLL M/N/K Code Control 1 (0x0081) */
1419#define RT5665_PLL_N_MAX 0x001ff
1420#define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7)
1421#define RT5665_PLL_N_SFT 7
1422#define RT5665_PLL_K_MAX 0x001f
1423#define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX)
1424#define RT5665_PLL_K_SFT 0
1425
1426/* PLL M/N/K Code Control 2 (0x0082) */
1427#define RT5665_PLL_M_MAX 0x00f
1428#define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
1429#define RT5665_PLL_M_SFT 12
1430#define RT5665_PLL_M_BP (0x1 << 11)
1431#define RT5665_PLL_M_BP_SFT 11
1432#define RT5665_PLL_K_BP (0x1 << 10)
1433#define RT5665_PLL_K_BP_SFT 10
1434
1435/* PLL tracking mode 1 (0x0083) */
1436#define RT5665_I2S3_ASRC_MASK (0x1 << 15)
1437#define RT5665_I2S3_ASRC_SFT 15
1438#define RT5665_I2S2_ASRC_MASK (0x1 << 14)
1439#define RT5665_I2S2_ASRC_SFT 14
1440#define RT5665_I2S1_ASRC_MASK (0x1 << 13)
1441#define RT5665_I2S1_ASRC_SFT 13
1442#define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
1443#define RT5665_DAC_STO1_ASRC_SFT 12
1444#define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)
1445#define RT5665_DAC_STO2_ASRC_SFT 11
1446#define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)
1447#define RT5665_DAC_MONO_L_ASRC_SFT 10
1448#define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
1449#define RT5665_DAC_MONO_R_ASRC_SFT 9
1450#define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1451#define RT5665_DMIC_STO1_ASRC_SFT 8
1452#define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)
1453#define RT5665_DMIC_STO2_ASRC_SFT 7
1454#define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)
1455#define RT5665_DMIC_MONO_L_ASRC_SFT 6
1456#define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)
1457#define RT5665_DMIC_MONO_R_ASRC_SFT 5
1458#define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)
1459#define RT5665_ADC_STO1_ASRC_SFT 4
1460#define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)
1461#define RT5665_ADC_STO2_ASRC_SFT 3
1462#define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)
1463#define RT5665_ADC_MONO_L_ASRC_SFT 2
1464#define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)
1465#define RT5665_ADC_MONO_R_ASRC_SFT 1
1466
1467/* PLL tracking mode 2 (0x0084)*/
1468#define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
1469#define RT5665_DA_STO1_CLK_SEL_SFT 12
1470#define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
1471#define RT5665_DA_STO2_CLK_SEL_SFT 8
1472#define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4)
1473#define RT5665_DA_MONOL_CLK_SEL_SFT 4
1474#define RT5665_DA_MONOR_CLK_SEL_MASK (0x7)
1475#define RT5665_DA_MONOR_CLK_SEL_SFT 0
1476
1477/* PLL tracking mode 3 (0x0085)*/
1478#define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
1479#define RT5665_AD_STO1_CLK_SEL_SFT 12
1480#define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
1481#define RT5665_AD_STO2_CLK_SEL_SFT 8
1482#define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4)
1483#define RT5665_AD_MONOL_CLK_SEL_SFT 4
1484#define RT5665_AD_MONOR_CLK_SEL_MASK (0x7)
1485#define RT5665_AD_MONOR_CLK_SEL_SFT 0
1486
1487/* ASRC Control 4 (0x0086) */
1488#define RT5665_I2S1_RATE_MASK (0xf << 12)
1489#define RT5665_I2S1_RATE_SFT 12
1490#define RT5665_I2S2_RATE_MASK (0xf << 8)
1491#define RT5665_I2S2_RATE_SFT 8
1492#define RT5665_I2S3_RATE_MASK (0xf << 4)
1493#define RT5665_I2S3_RATE_SFT 4
1494
1495/* Depop Mode Control 1 (0x008e) */
1496#define RT5665_PUMP_EN (0x1 << 3)
1497
1498/* Depop Mode Control 2 (0x8f) */
1499#define RT5665_DEPOP_MASK (0x1 << 13)
1500#define RT5665_DEPOP_SFT 13
1501#define RT5665_DEPOP_AUTO (0x0 << 13)
1502#define RT5665_DEPOP_MAN (0x1 << 13)
1503#define RT5665_RAMP_MASK (0x1 << 12)
1504#define RT5665_RAMP_SFT 12
1505#define RT5665_RAMP_DIS (0x0 << 12)
1506#define RT5665_RAMP_EN (0x1 << 12)
1507#define RT5665_BPS_MASK (0x1 << 11)
1508#define RT5665_BPS_SFT 11
1509#define RT5665_BPS_DIS (0x0 << 11)
1510#define RT5665_BPS_EN (0x1 << 11)
1511#define RT5665_FAST_UPDN_MASK (0x1 << 10)
1512#define RT5665_FAST_UPDN_SFT 10
1513#define RT5665_FAST_UPDN_DIS (0x0 << 10)
1514#define RT5665_FAST_UPDN_EN (0x1 << 10)
1515#define RT5665_MRES_MASK (0x3 << 8)
1516#define RT5665_MRES_SFT 8
1517#define RT5665_MRES_15MO (0x0 << 8)
1518#define RT5665_MRES_25MO (0x1 << 8)
1519#define RT5665_MRES_35MO (0x2 << 8)
1520#define RT5665_MRES_45MO (0x3 << 8)
1521#define RT5665_VLO_MASK (0x1 << 7)
1522#define RT5665_VLO_SFT 7
1523#define RT5665_VLO_3V (0x0 << 7)
1524#define RT5665_VLO_32V (0x1 << 7)
1525#define RT5665_DIG_DP_MASK (0x1 << 6)
1526#define RT5665_DIG_DP_SFT 6
1527#define RT5665_DIG_DP_DIS (0x0 << 6)
1528#define RT5665_DIG_DP_EN (0x1 << 6)
1529#define RT5665_DP_TH_MASK (0x3 << 4)
1530#define RT5665_DP_TH_SFT 4
1531
1532/* Depop Mode Control 3 (0x90) */
1533#define RT5665_CP_SYS_MASK (0x7 << 12)
1534#define RT5665_CP_SYS_SFT 12
1535#define RT5665_CP_FQ1_MASK (0x7 << 8)
1536#define RT5665_CP_FQ1_SFT 8
1537#define RT5665_CP_FQ2_MASK (0x7 << 4)
1538#define RT5665_CP_FQ2_SFT 4
1539#define RT5665_CP_FQ3_MASK (0x7)
1540#define RT5665_CP_FQ3_SFT 0
1541#define RT5665_CP_FQ_1_5_KHZ 0
1542#define RT5665_CP_FQ_3_KHZ 1
1543#define RT5665_CP_FQ_6_KHZ 2
1544#define RT5665_CP_FQ_12_KHZ 3
1545#define RT5665_CP_FQ_24_KHZ 4
1546#define RT5665_CP_FQ_48_KHZ 5
1547#define RT5665_CP_FQ_96_KHZ 6
1548#define RT5665_CP_FQ_192_KHZ 7
1549
1550/* HPOUT charge pump 1 (0x0091) */
1551#define RT5665_OSW_L_MASK (0x1 << 11)
1552#define RT5665_OSW_L_SFT 11
1553#define RT5665_OSW_L_DIS (0x0 << 11)
1554#define RT5665_OSW_L_EN (0x1 << 11)
1555#define RT5665_OSW_R_MASK (0x1 << 10)
1556#define RT5665_OSW_R_SFT 10
1557#define RT5665_OSW_R_DIS (0x0 << 10)
1558#define RT5665_OSW_R_EN (0x1 << 10)
1559#define RT5665_PM_HP_MASK (0x3 << 8)
1560#define RT5665_PM_HP_SFT 8
1561#define RT5665_PM_HP_LV (0x0 << 8)
1562#define RT5665_PM_HP_MV (0x1 << 8)
1563#define RT5665_PM_HP_HV (0x2 << 8)
1564#define RT5665_IB_HP_MASK (0x3 << 6)
1565#define RT5665_IB_HP_SFT 6
1566#define RT5665_IB_HP_125IL (0x0 << 6)
1567#define RT5665_IB_HP_25IL (0x1 << 6)
1568#define RT5665_IB_HP_5IL (0x2 << 6)
1569#define RT5665_IB_HP_1IL (0x3 << 6)
1570
1571/* PV detection and SPK gain control (0x92) */
1572#define RT5665_PVDD_DET_MASK (0x1 << 15)
1573#define RT5665_PVDD_DET_SFT 15
1574#define RT5665_PVDD_DET_DIS (0x0 << 15)
1575#define RT5665_PVDD_DET_EN (0x1 << 15)
1576#define RT5665_SPK_AG_MASK (0x1 << 14)
1577#define RT5665_SPK_AG_SFT 14
1578#define RT5665_SPK_AG_DIS (0x0 << 14)
1579#define RT5665_SPK_AG_EN (0x1 << 14)
1580
1581/* Micbias Control1 (0x93) */
1582#define RT5665_MIC1_BS_MASK (0x1 << 15)
1583#define RT5665_MIC1_BS_SFT 15
1584#define RT5665_MIC1_BS_9AV (0x0 << 15)
1585#define RT5665_MIC1_BS_75AV (0x1 << 15)
1586#define RT5665_MIC2_BS_MASK (0x1 << 14)
1587#define RT5665_MIC2_BS_SFT 14
1588#define RT5665_MIC2_BS_9AV (0x0 << 14)
1589#define RT5665_MIC2_BS_75AV (0x1 << 14)
1590#define RT5665_MIC1_CLK_MASK (0x1 << 13)
1591#define RT5665_MIC1_CLK_SFT 13
1592#define RT5665_MIC1_CLK_DIS (0x0 << 13)
1593#define RT5665_MIC1_CLK_EN (0x1 << 13)
1594#define RT5665_MIC2_CLK_MASK (0x1 << 12)
1595#define RT5665_MIC2_CLK_SFT 12
1596#define RT5665_MIC2_CLK_DIS (0x0 << 12)
1597#define RT5665_MIC2_CLK_EN (0x1 << 12)
1598#define RT5665_MIC1_OVCD_MASK (0x1 << 11)
1599#define RT5665_MIC1_OVCD_SFT 11
1600#define RT5665_MIC1_OVCD_DIS (0x0 << 11)
1601#define RT5665_MIC1_OVCD_EN (0x1 << 11)
1602#define RT5665_MIC1_OVTH_MASK (0x3 << 9)
1603#define RT5665_MIC1_OVTH_SFT 9
1604#define RT5665_MIC1_OVTH_600UA (0x0 << 9)
1605#define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
1606#define RT5665_MIC1_OVTH_2000UA (0x2 << 9)
1607#define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1608#define RT5665_MIC2_OVCD_SFT 8
1609#define RT5665_MIC2_OVCD_DIS (0x0 << 8)
1610#define RT5665_MIC2_OVCD_EN (0x1 << 8)
1611#define RT5665_MIC2_OVTH_MASK (0x3 << 6)
1612#define RT5665_MIC2_OVTH_SFT 6
1613#define RT5665_MIC2_OVTH_600UA (0x0 << 6)
1614#define RT5665_MIC2_OVTH_1500UA (0x1 << 6)
1615#define RT5665_MIC2_OVTH_2000UA (0x2 << 6)
1616#define RT5665_PWR_MB_MASK (0x1 << 5)
1617#define RT5665_PWR_MB_SFT 5
1618#define RT5665_PWR_MB_PD (0x0 << 5)
1619#define RT5665_PWR_MB_PU (0x1 << 5)
1620
1621/* Micbias Control2 (0x94) */
1622#define RT5665_PWR_CLK25M_MASK (0x1 << 9)
1623#define RT5665_PWR_CLK25M_SFT 9
1624#define RT5665_PWR_CLK25M_PD (0x0 << 9)
1625#define RT5665_PWR_CLK25M_PU (0x1 << 9)
1626#define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1627#define RT5665_PWR_CLK1M_SFT 8
1628#define RT5665_PWR_CLK1M_PD (0x0 << 8)
1629#define RT5665_PWR_CLK1M_PU (0x1 << 8)
1630
1631
1632/* EQ Control 1 (0x00b0) */
1633#define RT5665_EQ_SRC_DAC (0x0 << 15)
1634#define RT5665_EQ_SRC_ADC (0x1 << 15)
1635#define RT5665_EQ_UPD (0x1 << 14)
1636#define RT5665_EQ_UPD_BIT 14
1637#define RT5665_EQ_CD_MASK (0x1 << 13)
1638#define RT5665_EQ_CD_SFT 13
1639#define RT5665_EQ_CD_DIS (0x0 << 13)
1640#define RT5665_EQ_CD_EN (0x1 << 13)
1641#define RT5665_EQ_DITH_MASK (0x3 << 8)
1642#define RT5665_EQ_DITH_SFT 8
1643#define RT5665_EQ_DITH_NOR (0x0 << 8)
1644#define RT5665_EQ_DITH_LSB (0x1 << 8)
1645#define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
1646#define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
1647
1648/* IRQ Control 1 (0x00b7) */
1649#define RT5665_JD1_1_EN_MASK (0x1 << 15)
1650#define RT5665_JD1_1_EN_SFT 15
1651#define RT5665_JD1_1_DIS (0x0 << 15)
1652#define RT5665_JD1_1_EN (0x1 << 15)
1653#define RT5665_JD1_2_EN_MASK (0x1 << 12)
1654#define RT5665_JD1_2_EN_SFT 12
1655#define RT5665_JD1_2_DIS (0x0 << 12)
1656#define RT5665_JD1_2_EN (0x1 << 12)
1657
1658/* IRQ Control 2 (0x00b8) */
1659#define RT5665_IL_IRQ_MASK (0x1 << 6)
1660#define RT5665_IL_IRQ_DIS (0x0 << 6)
1661#define RT5665_IL_IRQ_EN (0x1 << 6)
1662
1663/* IRQ Control 5 (0x00ba) */
1664#define RT5665_IRQ_JD_EN (0x1 << 3)
1665#define RT5665_IRQ_JD_EN_SFT 3
1666
1667/* GPIO Control 1 (0x00c0) */
1668#define RT5665_GP1_PIN_MASK (0x1 << 15)
1669#define RT5665_GP1_PIN_SFT 15
1670#define RT5665_GP1_PIN_GPIO1 (0x0 << 15)
1671#define RT5665_GP1_PIN_IRQ (0x1 << 15)
1672#define RT5665_GP2_PIN_MASK (0x3 << 13)
1673#define RT5665_GP2_PIN_SFT 13
1674#define RT5665_GP2_PIN_GPIO2 (0x0 << 13)
1675#define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
1676#define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)
1677#define RT5665_GP3_PIN_MASK (0x3 << 11)
1678#define RT5665_GP3_PIN_SFT 11
1679#define RT5665_GP3_PIN_GPIO3 (0x0 << 11)
1680#define RT5665_GP3_PIN_LRCK2 (0x1 << 11)
1681#define RT5665_GP3_PIN_PDM_SDA (0x2 << 11)
1682#define RT5665_GP4_PIN_MASK (0x3 << 9)
1683#define RT5665_GP4_PIN_SFT 9
1684#define RT5665_GP4_PIN_GPIO4 (0x0 << 9)
1685#define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
1686#define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)
1687#define RT5665_GP5_PIN_MASK (0x3 << 7)
1688#define RT5665_GP5_PIN_SFT 7
1689#define RT5665_GP5_PIN_GPIO5 (0x0 << 7)
1690#define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)
1691#define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7)
1692#define RT5665_GP6_PIN_MASK (0x3 << 5)
1693#define RT5665_GP6_PIN_SFT 5
1694#define RT5665_GP6_PIN_GPIO6 (0x0 << 5)
1695#define RT5665_GP6_PIN_BCLK3 (0x0 << 5)
1696#define RT5665_GP6_PIN_PDM_SCL (0x1 << 5)
1697#define RT5665_GP7_PIN_MASK (0x3 << 3)
1698#define RT5665_GP7_PIN_SFT 3
1699#define RT5665_GP7_PIN_GPIO7 (0x0 << 3)
1700#define RT5665_GP7_PIN_LRCK3 (0x1 << 3)
1701#define RT5665_GP7_PIN_PDM_SDA (0x2 << 3)
1702#define RT5665_GP8_PIN_MASK (0x3 << 1)
1703#define RT5665_GP8_PIN_SFT 1
1704#define RT5665_GP8_PIN_GPIO8 (0x0 << 1)
1705#define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)
1706#define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1)
1707#define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1)
1708
1709
1710/* GPIO Control 2 (0x00c1)*/
1711#define RT5665_GP9_PIN_MASK (0x3 << 14)
1712#define RT5665_GP9_PIN_SFT 14
1713#define RT5665_GP9_PIN_GPIO9 (0x0 << 14)
1714#define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)
1715#define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14)
1716#define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14)
1717#define RT5665_GP10_PIN_MASK (0x3 << 12)
1718#define RT5665_GP10_PIN_SFT 12
1719#define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
1720#define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
1721#define RT5665_GP10_PIN_LPD (0x2 << 12)
1722#define RT5665_GP1_PF_MASK (0x1 << 11)
1723#define RT5665_GP1_PF_IN (0x0 << 11)
1724#define RT5665_GP1_PF_OUT (0x1 << 11)
1725#define RT5665_GP1_OUT_MASK (0x1 << 10)
1726#define RT5665_GP1_OUT_H (0x0 << 10)
1727#define RT5665_GP1_OUT_L (0x1 << 10)
1728#define RT5665_GP2_PF_MASK (0x1 << 9)
1729#define RT5665_GP2_PF_IN (0x0 << 9)
1730#define RT5665_GP2_PF_OUT (0x1 << 9)
1731#define RT5665_GP2_OUT_MASK (0x1 << 8)
1732#define RT5665_GP2_OUT_H (0x0 << 8)
1733#define RT5665_GP2_OUT_L (0x1 << 8)
1734#define RT5665_GP3_PF_MASK (0x1 << 7)
1735#define RT5665_GP3_PF_IN (0x0 << 7)
1736#define RT5665_GP3_PF_OUT (0x1 << 7)
1737#define RT5665_GP3_OUT_MASK (0x1 << 6)
1738#define RT5665_GP3_OUT_H (0x0 << 6)
1739#define RT5665_GP3_OUT_L (0x1 << 6)
1740#define RT5665_GP4_PF_MASK (0x1 << 5)
1741#define RT5665_GP4_PF_IN (0x0 << 5)
1742#define RT5665_GP4_PF_OUT (0x1 << 5)
1743#define RT5665_GP4_OUT_MASK (0x1 << 4)
1744#define RT5665_GP4_OUT_H (0x0 << 4)
1745#define RT5665_GP4_OUT_L (0x1 << 4)
1746#define RT5665_GP5_PF_MASK (0x1 << 3)
1747#define RT5665_GP5_PF_IN (0x0 << 3)
1748#define RT5665_GP5_PF_OUT (0x1 << 3)
1749#define RT5665_GP5_OUT_MASK (0x1 << 2)
1750#define RT5665_GP5_OUT_H (0x0 << 2)
1751#define RT5665_GP5_OUT_L (0x1 << 2)
1752#define RT5665_GP6_PF_MASK (0x1 << 1)
1753#define RT5665_GP6_PF_IN (0x0 << 1)
1754#define RT5665_GP6_PF_OUT (0x1 << 1)
1755#define RT5665_GP6_OUT_MASK (0x1)
1756#define RT5665_GP6_OUT_H (0x0)
1757#define RT5665_GP6_OUT_L (0x1)
1758
1759
1760/* GPIO Control 3 (0x00c2) */
1761#define RT5665_GP7_PF_MASK (0x1 << 15)
1762#define RT5665_GP7_PF_IN (0x0 << 15)
1763#define RT5665_GP7_PF_OUT (0x1 << 15)
1764#define RT5665_GP7_OUT_MASK (0x1 << 14)
1765#define RT5665_GP7_OUT_H (0x0 << 14)
1766#define RT5665_GP7_OUT_L (0x1 << 14)
1767#define RT5665_GP8_PF_MASK (0x1 << 13)
1768#define RT5665_GP8_PF_IN (0x0 << 13)
1769#define RT5665_GP8_PF_OUT (0x1 << 13)
1770#define RT5665_GP8_OUT_MASK (0x1 << 12)
1771#define RT5665_GP8_OUT_H (0x0 << 12)
1772#define RT5665_GP8_OUT_L (0x1 << 12)
1773#define RT5665_GP9_PF_MASK (0x1 << 11)
1774#define RT5665_GP9_PF_IN (0x0 << 11)
1775#define RT5665_GP9_PF_OUT (0x1 << 11)
1776#define RT5665_GP9_OUT_MASK (0x1 << 10)
1777#define RT5665_GP9_OUT_H (0x0 << 10)
1778#define RT5665_GP9_OUT_L (0x1 << 10)
1779#define RT5665_GP10_PF_MASK (0x1 << 9)
1780#define RT5665_GP10_PF_IN (0x0 << 9)
1781#define RT5665_GP10_PF_OUT (0x1 << 9)
1782#define RT5665_GP10_OUT_MASK (0x1 << 8)
1783#define RT5665_GP10_OUT_H (0x0 << 8)
1784#define RT5665_GP10_OUT_L (0x1 << 8)
1785#define RT5665_GP11_PF_MASK (0x1 << 7)
1786#define RT5665_GP11_PF_IN (0x0 << 7)
1787#define RT5665_GP11_PF_OUT (0x1 << 7)
1788#define RT5665_GP11_OUT_MASK (0x1 << 6)
1789#define RT5665_GP11_OUT_H (0x0 << 6)
1790#define RT5665_GP11_OUT_L (0x1 << 6)
1791
1792/* Soft volume and zero cross control 1 (0x00d9) */
1793#define RT5665_SV_MASK (0x1 << 15)
1794#define RT5665_SV_SFT 15
1795#define RT5665_SV_DIS (0x0 << 15)
1796#define RT5665_SV_EN (0x1 << 15)
1797#define RT5665_OUT_SV_MASK (0x1 << 13)
1798#define RT5665_OUT_SV_SFT 13
1799#define RT5665_OUT_SV_DIS (0x0 << 13)
1800#define RT5665_OUT_SV_EN (0x1 << 13)
1801#define RT5665_HP_SV_MASK (0x1 << 12)
1802#define RT5665_HP_SV_SFT 12
1803#define RT5665_HP_SV_DIS (0x0 << 12)
1804#define RT5665_HP_SV_EN (0x1 << 12)
1805#define RT5665_ZCD_DIG_MASK (0x1 << 11)
1806#define RT5665_ZCD_DIG_SFT 11
1807#define RT5665_ZCD_DIG_DIS (0x0 << 11)
1808#define RT5665_ZCD_DIG_EN (0x1 << 11)
1809#define RT5665_ZCD_MASK (0x1 << 10)
1810#define RT5665_ZCD_SFT 10
1811#define RT5665_ZCD_PD (0x0 << 10)
1812#define RT5665_ZCD_PU (0x1 << 10)
1813#define RT5665_SV_DLY_MASK (0xf)
1814#define RT5665_SV_DLY_SFT 0
1815
1816/* Soft volume and zero cross control 2 (0x00da) */
1817#define RT5665_ZCD_HP_MASK (0x1 << 15)
1818#define RT5665_ZCD_HP_SFT 15
1819#define RT5665_ZCD_HP_DIS (0x0 << 15)
1820#define RT5665_ZCD_HP_EN (0x1 << 15)
1821
1822/* 4 Button Inline Command Control 2 (0x00e0) */
1823#define RT5665_4BTN_IL_MASK (0x1 << 15)
1824#define RT5665_4BTN_IL_EN (0x1 << 15)
1825#define RT5665_4BTN_IL_DIS (0x0 << 15)
1826#define RT5665_4BTN_IL_RST_MASK (0x1 << 14)
1827#define RT5665_4BTN_IL_NOR (0x1 << 14)
1828#define RT5665_4BTN_IL_RST (0x0 << 14)
1829
1830/* Analog JD Control 1 (0x00f0) */
1831#define RT5665_JD1_MODE_MASK (0x3 << 0)
1832#define RT5665_JD1_MODE_0 (0x0 << 0)
1833#define RT5665_JD1_MODE_1 (0x1 << 0)
1834#define RT5665_JD1_MODE_2 (0x2 << 0)
1835
1836/* Jack Detect Control 3 (0x00f8) */
1837#define RT5665_JD_TRI_HPO_SEL_MASK (0x7)
1838#define RT5665_JD_TRI_HPO_SEL_SFT (0)
1839#define RT5665_JD_HPO_GPIO_JD1 (0x0)
1840#define RT5665_JD_HPO_JD1_1 (0x1)
1841#define RT5665_JD_HPO_JD1_2 (0x2)
1842#define RT5665_JD_HPO_JD2 (0x3)
1843#define RT5665_JD_HPO_GPIO_JD2 (0x4)
1844#define RT5665_JD_HPO_JD3 (0x5)
1845#define RT5665_JD_HPO_JD_D (0x6)
1846
1847/* Digital Misc Control (0x00fa) */
1848#define RT5665_AM_MASK (0x1 << 7)
1849#define RT5665_AM_EN (0x1 << 7)
1850#define RT5665_AM_DIS (0x1 << 7)
1851#define RT5665_DIG_GATE_CTRL 0x1
1852#define RT5665_DIG_GATE_CTRL_SFT (0)
1853
1854/* Chopper and Clock control for ADC (0x011c)*/
1855#define RT5665_M_RF_DIG_MASK (0x1 << 12)
1856#define RT5665_M_RF_DIG_SFT 12
1857#define RT5665_M_RI_DIG (0x1 << 11)
1858
1859/* Chopper and Clock control for DAC (0x013a)*/
1860#define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
1861#define RT5665_CKXEN_DAC1_SFT 13
1862#define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
1863#define RT5665_CKGEN_DAC1_SFT 12
1864#define RT5665_CKXEN_DAC2_MASK (0x1 << 5)
1865#define RT5665_CKXEN_DAC2_SFT 5
1866#define RT5665_CKGEN_DAC2_MASK (0x1 << 4)
1867#define RT5665_CKGEN_DAC2_SFT 4
1868
1869/* Chopper and Clock control for ADC (0x013b)*/
1870#define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
1871#define RT5665_CKXEN_ADC1_SFT 13
1872#define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
1873#define RT5665_CKGEN_ADC1_SFT 12
1874#define RT5665_CKXEN_ADC2_MASK (0x1 << 5)
1875#define RT5665_CKXEN_ADC2_SFT 5
1876#define RT5665_CKGEN_ADC2_MASK (0x1 << 4)
1877#define RT5665_CKGEN_ADC2_SFT 4
1878
1879/* Volume test (0x013f)*/
1880#define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
1881#define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
1882#define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)
1883
1884/* Test Mode Control 1 (0x0145) */
1885#define RT5665_AD2DA_LB_MASK (0x1 << 9)
1886#define RT5665_AD2DA_LB_SFT 9
1887
1888/* Stereo Noise Gate Control 1 (0x0160) */
1889#define RT5665_NG2_EN_MASK (0x1 << 15)
1890#define RT5665_NG2_EN (0x1 << 15)
1891#define RT5665_NG2_DIS (0x0 << 15)
1892
1893/* Stereo1 DAC Silence Detection Control (0x0190) */
1894#define RT5665_DEB_STO_DAC_MASK (0x7 << 4)
1895#define RT5665_DEB_80_MS (0x0 << 4)
1896
1897/* SAR ADC Inline Command Control 1 (0x0210) */
1898#define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
1899#define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
1900#define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)
1901#define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)
1902#define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)
1903#define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14)
1904#define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
1905#define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1906#define RT5665_SAR_BUTDET_RST (0x0 << 13)
1907#define RT5665_SAR_POW_MASK (0x1 << 12)
1908#define RT5665_SAR_POW_EN (0x1 << 12)
1909#define RT5665_SAR_POW_DIS (0x0 << 12)
1910#define RT5665_SAR_RST_MASK (0x1 << 11)
1911#define RT5665_SAR_RST_NORMAL (0x1 << 11)
1912#define RT5665_SAR_RST (0x0 << 11)
1913#define RT5665_SAR_BYPASS_MASK (0x1 << 10)
1914#define RT5665_SAR_BYPASS_EN (0x1 << 10)
1915#define RT5665_SAR_BYPASS_DIS (0x0 << 10)
1916#define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
1917#define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
1918#define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)
1919#define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1920#define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1921#define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)
1922#define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)
1923#define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)
1924#define RT5665_SAR_SEL_MODE_ADC (0x0 << 7)
1925#define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1926#define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1927#define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
1928#define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1929#define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1930#define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1931
1932/* System Clock Source */
1933enum {
1934 RT5665_SCLK_S_MCLK,
1935 RT5665_SCLK_S_PLL1,
1936 RT5665_SCLK_S_RCCLK,
1937};
1938
1939/* PLL1 Source */
1940enum {
1941 RT5665_PLL1_S_MCLK,
1942 RT5665_PLL1_S_BCLK1,
1943 RT5665_PLL1_S_BCLK2,
1944 RT5665_PLL1_S_BCLK3,
1945 RT5665_PLL1_S_BCLK4,
1946};
1947
1948enum {
1949 RT5665_AIF1_1,
1950 RT5665_AIF1_2,
1951 RT5665_AIF2_1,
1952 RT5665_AIF2_2,
1953 RT5665_AIF3,
1954 RT5665_AIFS
1955};
1956
1957enum {
1958 CODEC_5665,
1959 CODEC_5666,
1960 CODEC_5668,
1961};
1962
1963/* filter mask */
1964enum {
1965 RT5665_DA_STEREO1_FILTER = 0x1,
1966 RT5665_DA_STEREO2_FILTER = (0x1 << 1),
1967 RT5665_DA_MONO_L_FILTER = (0x1 << 2),
1968 RT5665_DA_MONO_R_FILTER = (0x1 << 3),
1969 RT5665_AD_STEREO1_FILTER = (0x1 << 4),
1970 RT5665_AD_STEREO2_FILTER = (0x1 << 5),
1971 RT5665_AD_MONO_L_FILTER = (0x1 << 6),
1972 RT5665_AD_MONO_R_FILTER = (0x1 << 7),
1973};
1974
1975enum {
1976 RT5665_CLK_SEL_SYS,
1977 RT5665_CLK_SEL_I2S1_ASRC,
1978 RT5665_CLK_SEL_I2S2_ASRC,
1979 RT5665_CLK_SEL_I2S3_ASRC,
1980 RT5665_CLK_SEL_SYS2,
1981 RT5665_CLK_SEL_SYS3,
1982 RT5665_CLK_SEL_SYS4,
1983};
1984
1985int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1986 unsigned int filter_mask, unsigned int clk_src);
1987int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1988 struct snd_soc_jack *hs_jack);
1989
1990#endif /* __RT5665_H__ */
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