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authorMadhavan Srinivasan <maddy@linux.vnet.ibm.com>2018-12-09 04:25:35 -0500
committerMichael Ellerman <mpe@ellerman.id.au>2018-12-20 04:53:11 -0500
commit333804dc3b7a92158ab63a48febff0d8ef89ada3 (patch)
tree065d35d515de5ee5051e1c2602f715502bf0a3ff
parent17cfccc91545682513541924245abb876d296063 (diff)
powerpc/perf: Update perf_regs structure to include SIER
On each sample, Sample Instruction Event Register (SIER) content is saved in pt_regs. SIER does not have a entry as-is in the pt_regs but instead, SIER content is saved in the "dar" register of pt_regs. Patch adds another entry to the perf_regs structure to include the "SIER" printing which internally maps to the "dar" of pt_regs. It also check for the SIER availability in the platform and present value accordingly Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/include/asm/perf_event.h3
-rw-r--r--arch/powerpc/include/uapi/asm/perf_regs.h1
-rw-r--r--arch/powerpc/perf/core-book3s.c8
-rw-r--r--arch/powerpc/perf/perf_regs.c7
-rw-r--r--tools/arch/powerpc/include/uapi/asm/perf_regs.h1
-rw-r--r--tools/perf/arch/powerpc/include/perf_regs.h3
-rw-r--r--tools/perf/arch/powerpc/util/perf_regs.c1
7 files changed, 23 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index 16a49819da9a..35926cd6cd0b 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -39,4 +39,7 @@
39 (regs)->gpr[1] = current_stack_pointer(); \ 39 (regs)->gpr[1] = current_stack_pointer(); \
40 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \ 40 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
41 } while (0) 41 } while (0)
42
43/* To support perf_regs sier update */
44extern bool is_sier_available(void);
42#endif 45#endif
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h
index 9e52c86ccbd3..ff91192407d1 100644
--- a/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -46,6 +46,7 @@ enum perf_event_powerpc_regs {
46 PERF_REG_POWERPC_TRAP, 46 PERF_REG_POWERPC_TRAP,
47 PERF_REG_POWERPC_DAR, 47 PERF_REG_POWERPC_DAR,
48 PERF_REG_POWERPC_DSISR, 48 PERF_REG_POWERPC_DSISR,
49 PERF_REG_POWERPC_SIER,
49 PERF_REG_POWERPC_MAX, 50 PERF_REG_POWERPC_MAX,
50}; 51};
51#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ 52#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 81f8a0c838ae..b4976cae1005 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -130,6 +130,14 @@ static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
130static void pmao_restore_workaround(bool ebb) { } 130static void pmao_restore_workaround(bool ebb) { }
131#endif /* CONFIG_PPC32 */ 131#endif /* CONFIG_PPC32 */
132 132
133bool is_sier_available(void)
134{
135 if (ppmu->flags & PPMU_HAS_SIER)
136 return true;
137
138 return false;
139}
140
133static bool regs_use_siar(struct pt_regs *regs) 141static bool regs_use_siar(struct pt_regs *regs)
134{ 142{
135 /* 143 /*
diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
index 09ceea6175ba..5c36b3a8d47a 100644
--- a/arch/powerpc/perf/perf_regs.c
+++ b/arch/powerpc/perf/perf_regs.c
@@ -69,6 +69,7 @@ static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
69 PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap), 69 PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap),
70 PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar), 70 PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
71 PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr), 71 PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
72 PT_REGS_OFFSET(PERF_REG_POWERPC_SIER, dar),
72}; 73};
73 74
74u64 perf_reg_value(struct pt_regs *regs, int idx) 75u64 perf_reg_value(struct pt_regs *regs, int idx)
@@ -76,6 +77,12 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
76 if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX)) 77 if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))
77 return 0; 78 return 0;
78 79
80 if (idx == PERF_REG_POWERPC_SIER &&
81 (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
82 IS_ENABLED(CONFIG_PPC32) ||
83 !is_sier_available()))
84 return 0;
85
79 return regs_get_register(regs, pt_regs_offset[idx]); 86 return regs_get_register(regs, pt_regs_offset[idx]);
80} 87}
81 88
diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
index 9e52c86ccbd3..ff91192407d1 100644
--- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h
+++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -46,6 +46,7 @@ enum perf_event_powerpc_regs {
46 PERF_REG_POWERPC_TRAP, 46 PERF_REG_POWERPC_TRAP,
47 PERF_REG_POWERPC_DAR, 47 PERF_REG_POWERPC_DAR,
48 PERF_REG_POWERPC_DSISR, 48 PERF_REG_POWERPC_DSISR,
49 PERF_REG_POWERPC_SIER,
49 PERF_REG_POWERPC_MAX, 50 PERF_REG_POWERPC_MAX,
50}; 51};
51#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ 52#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h
index 00e37b106913..1076393e6f43 100644
--- a/tools/perf/arch/powerpc/include/perf_regs.h
+++ b/tools/perf/arch/powerpc/include/perf_regs.h
@@ -62,7 +62,8 @@ static const char *reg_names[] = {
62 [PERF_REG_POWERPC_SOFTE] = "softe", 62 [PERF_REG_POWERPC_SOFTE] = "softe",
63 [PERF_REG_POWERPC_TRAP] = "trap", 63 [PERF_REG_POWERPC_TRAP] = "trap",
64 [PERF_REG_POWERPC_DAR] = "dar", 64 [PERF_REG_POWERPC_DAR] = "dar",
65 [PERF_REG_POWERPC_DSISR] = "dsisr" 65 [PERF_REG_POWERPC_DSISR] = "dsisr",
66 [PERF_REG_POWERPC_SIER] = "sier"
66}; 67};
67 68
68static inline const char *perf_reg_name(int id) 69static inline const char *perf_reg_name(int id)
diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c
index ec50939b0418..07fcd977d93e 100644
--- a/tools/perf/arch/powerpc/util/perf_regs.c
+++ b/tools/perf/arch/powerpc/util/perf_regs.c
@@ -52,6 +52,7 @@ const struct sample_reg sample_reg_masks[] = {
52 SMPL_REG(trap, PERF_REG_POWERPC_TRAP), 52 SMPL_REG(trap, PERF_REG_POWERPC_TRAP),
53 SMPL_REG(dar, PERF_REG_POWERPC_DAR), 53 SMPL_REG(dar, PERF_REG_POWERPC_DAR),
54 SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR), 54 SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
55 SMPL_REG(sier, PERF_REG_POWERPC_SIER),
55 SMPL_REG_END 56 SMPL_REG_END
56}; 57};
57 58