diff options
author | Marc Gonzalez <marc.w.gonzalez@free.fr> | 2019-03-25 11:42:55 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-05-07 09:50:36 -0400 |
commit | 322f03436692481993d389f539c016d20bb0fa1d (patch) | |
tree | 41aa6d9673219e3bef1ec5b7444e35975137f11b | |
parent | 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff) |
PCI: qcom: Use default config space read function
Move the device class fudge to a proper fixup function, and remove
qcom_pcie_rd_own_conf() which has become useless.
dw_pcie_setup_rc() already did the right thing, but it's broken
on older qcom chips, such as 8064.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
-rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom.c | 23 |
1 files changed, 6 insertions, 17 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a7f703556790..0ed235d560e3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c | |||
@@ -1129,25 +1129,8 @@ err_deinit: | |||
1129 | return ret; | 1129 | return ret; |
1130 | } | 1130 | } |
1131 | 1131 | ||
1132 | static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, | ||
1133 | u32 *val) | ||
1134 | { | ||
1135 | struct dw_pcie *pci = to_dw_pcie_from_pp(pp); | ||
1136 | |||
1137 | /* the device class is not reported correctly from the register */ | ||
1138 | if (where == PCI_CLASS_REVISION && size == 4) { | ||
1139 | *val = readl(pci->dbi_base + PCI_CLASS_REVISION); | ||
1140 | *val &= 0xff; /* keep revision id */ | ||
1141 | *val |= PCI_CLASS_BRIDGE_PCI << 16; | ||
1142 | return PCIBIOS_SUCCESSFUL; | ||
1143 | } | ||
1144 | |||
1145 | return dw_pcie_read(pci->dbi_base + where, size, val); | ||
1146 | } | ||
1147 | |||
1148 | static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { | 1132 | static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { |
1149 | .host_init = qcom_pcie_host_init, | 1133 | .host_init = qcom_pcie_host_init, |
1150 | .rd_own_conf = qcom_pcie_rd_own_conf, | ||
1151 | }; | 1134 | }; |
1152 | 1135 | ||
1153 | /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ | 1136 | /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ |
@@ -1309,6 +1292,12 @@ static const struct of_device_id qcom_pcie_match[] = { | |||
1309 | { } | 1292 | { } |
1310 | }; | 1293 | }; |
1311 | 1294 | ||
1295 | static void qcom_fixup_class(struct pci_dev *dev) | ||
1296 | { | ||
1297 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | ||
1298 | } | ||
1299 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class); | ||
1300 | |||
1312 | static struct platform_driver qcom_pcie_driver = { | 1301 | static struct platform_driver qcom_pcie_driver = { |
1313 | .probe = qcom_pcie_probe, | 1302 | .probe = qcom_pcie_probe, |
1314 | .driver = { | 1303 | .driver = { |