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authorFabrice Gasnier <fabrice.gasnier@st.com>2019-09-17 08:38:15 -0400
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-10-09 14:11:26 -0400
commit31922f62bb527d749b99dbc776e514bcba29b7fe (patch)
treea980880235175dc4e13027de1b774cf1113ebf2d
parentd9a997bd4d762d5bd8cc548d762902f58b5e0a74 (diff)
iio: adc: stm32-adc: move registers definitions
Move STM32 ADC registers definitions to common header. This is precursor patch to: - iio: adc: stm32-adc: fix a race when using several adcs with dma and irq It keeps registers definitions as a whole block, to ease readability and allow simple access path to EOC bits (readl) in stm32-adc-core driver. Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat
-rw-r--r--drivers/iio/adc/stm32-adc-core.c27
-rw-r--r--drivers/iio/adc/stm32-adc-core.h136
-rw-r--r--drivers/iio/adc/stm32-adc.c109
3 files changed, 136 insertions, 136 deletions
diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
index 9b85fefc0a96..84ac326bb714 100644
--- a/drivers/iio/adc/stm32-adc-core.c
+++ b/drivers/iio/adc/stm32-adc-core.c
@@ -24,33 +24,6 @@
24 24
25#include "stm32-adc-core.h" 25#include "stm32-adc-core.h"
26 26
27/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
28#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
29#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
30
31/* STM32F4_ADC_CSR - bit fields */
32#define STM32F4_EOC3 BIT(17)
33#define STM32F4_EOC2 BIT(9)
34#define STM32F4_EOC1 BIT(1)
35
36/* STM32F4_ADC_CCR - bit fields */
37#define STM32F4_ADC_ADCPRE_SHIFT 16
38#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
39
40/* STM32H7 - common registers for all ADC instances */
41#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
42#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
43
44/* STM32H7_ADC_CSR - bit fields */
45#define STM32H7_EOC_SLV BIT(18)
46#define STM32H7_EOC_MST BIT(2)
47
48/* STM32H7_ADC_CCR - bit fields */
49#define STM32H7_PRESC_SHIFT 18
50#define STM32H7_PRESC_MASK GENMASK(21, 18)
51#define STM32H7_CKMODE_SHIFT 16
52#define STM32H7_CKMODE_MASK GENMASK(17, 16)
53
54#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 27#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
55 28
56/* SYSCFG registers */ 29/* SYSCFG registers */
diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h
index 8af507b3f32d..94aa2d2577dc 100644
--- a/drivers/iio/adc/stm32-adc-core.h
+++ b/drivers/iio/adc/stm32-adc-core.h
@@ -27,6 +27,142 @@
27#define STM32_ADC_MAX_ADCS 3 27#define STM32_ADC_MAX_ADCS 3
28#define STM32_ADCX_COMN_OFFSET 0x300 28#define STM32_ADCX_COMN_OFFSET 0x300
29 29
30/* STM32F4 - Registers for each ADC instance */
31#define STM32F4_ADC_SR 0x00
32#define STM32F4_ADC_CR1 0x04
33#define STM32F4_ADC_CR2 0x08
34#define STM32F4_ADC_SMPR1 0x0C
35#define STM32F4_ADC_SMPR2 0x10
36#define STM32F4_ADC_HTR 0x24
37#define STM32F4_ADC_LTR 0x28
38#define STM32F4_ADC_SQR1 0x2C
39#define STM32F4_ADC_SQR2 0x30
40#define STM32F4_ADC_SQR3 0x34
41#define STM32F4_ADC_JSQR 0x38
42#define STM32F4_ADC_JDR1 0x3C
43#define STM32F4_ADC_JDR2 0x40
44#define STM32F4_ADC_JDR3 0x44
45#define STM32F4_ADC_JDR4 0x48
46#define STM32F4_ADC_DR 0x4C
47
48/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
49#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
50#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
51
52/* STM32F4_ADC_SR - bit fields */
53#define STM32F4_STRT BIT(4)
54#define STM32F4_EOC BIT(1)
55
56/* STM32F4_ADC_CR1 - bit fields */
57#define STM32F4_RES_SHIFT 24
58#define STM32F4_RES_MASK GENMASK(25, 24)
59#define STM32F4_SCAN BIT(8)
60#define STM32F4_EOCIE BIT(5)
61
62/* STM32F4_ADC_CR2 - bit fields */
63#define STM32F4_SWSTART BIT(30)
64#define STM32F4_EXTEN_SHIFT 28
65#define STM32F4_EXTEN_MASK GENMASK(29, 28)
66#define STM32F4_EXTSEL_SHIFT 24
67#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
68#define STM32F4_EOCS BIT(10)
69#define STM32F4_DDS BIT(9)
70#define STM32F4_DMA BIT(8)
71#define STM32F4_ADON BIT(0)
72
73/* STM32F4_ADC_CSR - bit fields */
74#define STM32F4_EOC3 BIT(17)
75#define STM32F4_EOC2 BIT(9)
76#define STM32F4_EOC1 BIT(1)
77
78/* STM32F4_ADC_CCR - bit fields */
79#define STM32F4_ADC_ADCPRE_SHIFT 16
80#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
81
82/* STM32H7 - Registers for each ADC instance */
83#define STM32H7_ADC_ISR 0x00
84#define STM32H7_ADC_IER 0x04
85#define STM32H7_ADC_CR 0x08
86#define STM32H7_ADC_CFGR 0x0C
87#define STM32H7_ADC_SMPR1 0x14
88#define STM32H7_ADC_SMPR2 0x18
89#define STM32H7_ADC_PCSEL 0x1C
90#define STM32H7_ADC_SQR1 0x30
91#define STM32H7_ADC_SQR2 0x34
92#define STM32H7_ADC_SQR3 0x38
93#define STM32H7_ADC_SQR4 0x3C
94#define STM32H7_ADC_DR 0x40
95#define STM32H7_ADC_DIFSEL 0xC0
96#define STM32H7_ADC_CALFACT 0xC4
97#define STM32H7_ADC_CALFACT2 0xC8
98
99/* STM32H7 - common registers for all ADC instances */
100#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
101#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
102
103/* STM32H7_ADC_ISR - bit fields */
104#define STM32MP1_VREGREADY BIT(12)
105#define STM32H7_EOC BIT(2)
106#define STM32H7_ADRDY BIT(0)
107
108/* STM32H7_ADC_IER - bit fields */
109#define STM32H7_EOCIE STM32H7_EOC
110
111/* STM32H7_ADC_CR - bit fields */
112#define STM32H7_ADCAL BIT(31)
113#define STM32H7_ADCALDIF BIT(30)
114#define STM32H7_DEEPPWD BIT(29)
115#define STM32H7_ADVREGEN BIT(28)
116#define STM32H7_LINCALRDYW6 BIT(27)
117#define STM32H7_LINCALRDYW5 BIT(26)
118#define STM32H7_LINCALRDYW4 BIT(25)
119#define STM32H7_LINCALRDYW3 BIT(24)
120#define STM32H7_LINCALRDYW2 BIT(23)
121#define STM32H7_LINCALRDYW1 BIT(22)
122#define STM32H7_ADCALLIN BIT(16)
123#define STM32H7_BOOST BIT(8)
124#define STM32H7_ADSTP BIT(4)
125#define STM32H7_ADSTART BIT(2)
126#define STM32H7_ADDIS BIT(1)
127#define STM32H7_ADEN BIT(0)
128
129/* STM32H7_ADC_CFGR bit fields */
130#define STM32H7_EXTEN_SHIFT 10
131#define STM32H7_EXTEN_MASK GENMASK(11, 10)
132#define STM32H7_EXTSEL_SHIFT 5
133#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
134#define STM32H7_RES_SHIFT 2
135#define STM32H7_RES_MASK GENMASK(4, 2)
136#define STM32H7_DMNGT_SHIFT 0
137#define STM32H7_DMNGT_MASK GENMASK(1, 0)
138
139enum stm32h7_adc_dmngt {
140 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
141 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
142 STM32H7_DMNGT_DFSDM, /* DFSDM mode */
143 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
144};
145
146/* STM32H7_ADC_CALFACT - bit fields */
147#define STM32H7_CALFACT_D_SHIFT 16
148#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
149#define STM32H7_CALFACT_S_SHIFT 0
150#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
151
152/* STM32H7_ADC_CALFACT2 - bit fields */
153#define STM32H7_LINCALFACT_SHIFT 0
154#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
155
156/* STM32H7_ADC_CSR - bit fields */
157#define STM32H7_EOC_SLV BIT(18)
158#define STM32H7_EOC_MST BIT(2)
159
160/* STM32H7_ADC_CCR - bit fields */
161#define STM32H7_PRESC_SHIFT 18
162#define STM32H7_PRESC_MASK GENMASK(21, 18)
163#define STM32H7_CKMODE_SHIFT 16
164#define STM32H7_CKMODE_MASK GENMASK(17, 16)
165
30/** 166/**
31 * struct stm32_adc_common - stm32 ADC driver common data (for all instances) 167 * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
32 * @base: control registers base cpu addr 168 * @base: control registers base cpu addr
diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index 6a7dd08b1e0b..663f8a5012d6 100644
--- a/drivers/iio/adc/stm32-adc.c
+++ b/drivers/iio/adc/stm32-adc.c
@@ -28,115 +28,6 @@
28 28
29#include "stm32-adc-core.h" 29#include "stm32-adc-core.h"
30 30
31/* STM32F4 - Registers for each ADC instance */
32#define STM32F4_ADC_SR 0x00
33#define STM32F4_ADC_CR1 0x04
34#define STM32F4_ADC_CR2 0x08
35#define STM32F4_ADC_SMPR1 0x0C
36#define STM32F4_ADC_SMPR2 0x10
37#define STM32F4_ADC_HTR 0x24
38#define STM32F4_ADC_LTR 0x28
39#define STM32F4_ADC_SQR1 0x2C
40#define STM32F4_ADC_SQR2 0x30
41#define STM32F4_ADC_SQR3 0x34
42#define STM32F4_ADC_JSQR 0x38
43#define STM32F4_ADC_JDR1 0x3C
44#define STM32F4_ADC_JDR2 0x40
45#define STM32F4_ADC_JDR3 0x44
46#define STM32F4_ADC_JDR4 0x48
47#define STM32F4_ADC_DR 0x4C
48
49/* STM32F4_ADC_SR - bit fields */
50#define STM32F4_STRT BIT(4)
51#define STM32F4_EOC BIT(1)
52
53/* STM32F4_ADC_CR1 - bit fields */
54#define STM32F4_RES_SHIFT 24
55#define STM32F4_RES_MASK GENMASK(25, 24)
56#define STM32F4_SCAN BIT(8)
57#define STM32F4_EOCIE BIT(5)
58
59/* STM32F4_ADC_CR2 - bit fields */
60#define STM32F4_SWSTART BIT(30)
61#define STM32F4_EXTEN_SHIFT 28
62#define STM32F4_EXTEN_MASK GENMASK(29, 28)
63#define STM32F4_EXTSEL_SHIFT 24
64#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
65#define STM32F4_EOCS BIT(10)
66#define STM32F4_DDS BIT(9)
67#define STM32F4_DMA BIT(8)
68#define STM32F4_ADON BIT(0)
69
70/* STM32H7 - Registers for each ADC instance */
71#define STM32H7_ADC_ISR 0x00
72#define STM32H7_ADC_IER 0x04
73#define STM32H7_ADC_CR 0x08
74#define STM32H7_ADC_CFGR 0x0C
75#define STM32H7_ADC_SMPR1 0x14
76#define STM32H7_ADC_SMPR2 0x18
77#define STM32H7_ADC_PCSEL 0x1C
78#define STM32H7_ADC_SQR1 0x30
79#define STM32H7_ADC_SQR2 0x34
80#define STM32H7_ADC_SQR3 0x38
81#define STM32H7_ADC_SQR4 0x3C
82#define STM32H7_ADC_DR 0x40
83#define STM32H7_ADC_DIFSEL 0xC0
84#define STM32H7_ADC_CALFACT 0xC4
85#define STM32H7_ADC_CALFACT2 0xC8
86
87/* STM32H7_ADC_ISR - bit fields */
88#define STM32MP1_VREGREADY BIT(12)
89#define STM32H7_EOC BIT(2)
90#define STM32H7_ADRDY BIT(0)
91
92/* STM32H7_ADC_IER - bit fields */
93#define STM32H7_EOCIE STM32H7_EOC
94
95/* STM32H7_ADC_CR - bit fields */
96#define STM32H7_ADCAL BIT(31)
97#define STM32H7_ADCALDIF BIT(30)
98#define STM32H7_DEEPPWD BIT(29)
99#define STM32H7_ADVREGEN BIT(28)
100#define STM32H7_LINCALRDYW6 BIT(27)
101#define STM32H7_LINCALRDYW5 BIT(26)
102#define STM32H7_LINCALRDYW4 BIT(25)
103#define STM32H7_LINCALRDYW3 BIT(24)
104#define STM32H7_LINCALRDYW2 BIT(23)
105#define STM32H7_LINCALRDYW1 BIT(22)
106#define STM32H7_ADCALLIN BIT(16)
107#define STM32H7_BOOST BIT(8)
108#define STM32H7_ADSTP BIT(4)
109#define STM32H7_ADSTART BIT(2)
110#define STM32H7_ADDIS BIT(1)
111#define STM32H7_ADEN BIT(0)
112
113/* STM32H7_ADC_CFGR bit fields */
114#define STM32H7_EXTEN_SHIFT 10
115#define STM32H7_EXTEN_MASK GENMASK(11, 10)
116#define STM32H7_EXTSEL_SHIFT 5
117#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
118#define STM32H7_RES_SHIFT 2
119#define STM32H7_RES_MASK GENMASK(4, 2)
120#define STM32H7_DMNGT_SHIFT 0
121#define STM32H7_DMNGT_MASK GENMASK(1, 0)
122
123enum stm32h7_adc_dmngt {
124 STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
125 STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
126 STM32H7_DMNGT_DFSDM, /* DFSDM mode */
127 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
128};
129
130/* STM32H7_ADC_CALFACT - bit fields */
131#define STM32H7_CALFACT_D_SHIFT 16
132#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
133#define STM32H7_CALFACT_S_SHIFT 0
134#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
135
136/* STM32H7_ADC_CALFACT2 - bit fields */
137#define STM32H7_LINCALFACT_SHIFT 0
138#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
139
140/* Number of linear calibration shadow registers / LINCALRDYW control bits */ 31/* Number of linear calibration shadow registers / LINCALRDYW control bits */
141#define STM32H7_LINCALFACT_NUM 6 32#define STM32H7_LINCALFACT_NUM 6
142 33
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 07:46:30 -0400