Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

 - Add a "cut here" to make it clearer where oops dumps should be cut
   from - we already have a marker for the end of the dumps.

 - Add logging severity to show_pte()

 - Drop unnecessary common-page-size linker flag

 - Errata workarounds for Cortex A12 857271, Cortex A17 857272 and
   Cortex A7 814220.

 - Remove some unused variables that had started to provoke a compiler
   warning.

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
  ARM: 8863/1: stm32: select ARM errata 814220
  ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute out of order
  ARM: 8865/1: mm: remove unused variables
  ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores
  ARM: 8861/1: errata: Workaround errata A12 857271 / A17 857272
  ARM: 8860/1: VDSO: Drop implicit common-page-size linker flag
  ARM: arrange show_pte() to issue severity-based messages
  ARM: add "8<--- cut here ---" to kernel dumps

14 files changed, 107 insertions, 19 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8869742a85df..c87cc9a6fb3c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1175,6 +1175,14 @@ config ARM_ERRATA_825619
           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
           and Device/Strongly-Ordered loads and stores might cause deadlock
 
+config ARM_ERRATA_857271
+        bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 857271 Cortex-A12
+          (all revs) erratum. Under very rare timing conditions, the CPU might
+          hang. The workaround is expected to have a < 1% performance impact.
+
 config ARM_ERRATA_852421
         bool "ARM errata: A17: DMB ST might fail to create order between stores"
         depends on CPU_V7
@@ -1196,6 +1204,16 @@ config ARM_ERRATA_852423
           config option from the A12 erratum due to the way errata are checked
           for and handled.
 
+config ARM_ERRATA_857272
+        bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 857272 Cortex-A17 erratum.
+          This erratum is not known to be fixed in any A17 revision.
+          This is identical to Cortex-A12 erratum 857271.  It is a separate
+          config option from the A12 erratum due to the way errata are checked
+          for and handled.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1232,6 +1250,18 @@ config PCI_HOST_ITE8152
         default y
         select DMABOUNCE
 
+config ARM_ERRATA_814220
+        bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+        depends on CPU_V7
+        help
+          The v7 ARM states that all cache and branch predictor maintenance
+          operations that do not specify an address execute, relative to
+          each other, in program order.
+          However, because of this erratum, an L2 set/way cache maintenance
+          operation can overtake an L1 set/way cache maintenance operation.
+          This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
+          r0p4, r0p5.
+
 endmenu
 
 menu "Kernel Features"
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index c95c54284da2..9b959afaaa12 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS3=y
+CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
 CONFIG_SMP=y
 CONFIG_BIG_LITTLE=y
 CONFIG_NR_CPUS=8
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index 36c951dd23b8..deef4d0cb3b5 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -85,7 +85,7 @@ void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
 
 struct mm_struct;
-extern void show_pte(struct mm_struct *mm, unsigned long addr);
+void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr);
 extern void __show_regs(struct pt_regs *);
 
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d6667b8cfca5..7114b9aa46b8 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -476,4 +476,11 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
 void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
                              void *kaddr, unsigned long len);
 
+
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+void check_cpu_icache_size(int cpuid);
+#else
+static inline void check_cpu_icache_size(int cpuid) { }
+#endif
+
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index a137608cd197..aab8ba40ce38 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -372,6 +372,7 @@ static void smp_store_cpu_info(unsigned int cpuid)
         cpu_info->cpuid = read_cpuid_id();
 
         store_cpu_topology(cpuid);
+        check_cpu_icache_size(cpuid);
 }
 
 /*
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 7e2f1cba84e5..b6d6b1a6f156 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -722,10 +722,11 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs)
 
 #ifdef CONFIG_DEBUG_USER
         if (user_debug & UDBG_BADABORT) {
+                pr_err("8<--- cut here ---\n");
                 pr_err("[%d] %s: bad data abort: code %d instr 0x%08lx\n",
                        task_pid_nr(current), current->comm, code, instr);
                 dump_instr(KERN_ERR, regs);
-                show_pte(current->mm, addr);
+                show_pte(KERN_ERR, current->mm, addr);
         }
 #endif
 
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 36e6c68c0b57..05d6b5aada80 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -44,6 +44,7 @@ if ARCH_MULTI_V7
 
 config MACH_STM32MP157
         bool "STMicroelectronics STM32MP157"
+        select ARM_ERRATA_814220
         default y
 
 endif # ARMv7-A
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index b169e580bf82..cc798115aa9b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -780,6 +780,14 @@ config CPU_ICACHE_DISABLE
           Say Y here to disable the processor instruction cache. Unless
           you have a reason not to or are unsure, say N.
 
+config CPU_ICACHE_MISMATCH_WORKAROUND
+        bool "Workaround for I-Cache line size mismatch between CPU cores"
+        depends on SMP && CPU_V7
+        help
+          Some big.LITTLE systems have I-Cache line size mismatch between
+          LITTLE and big cores.  Say Y here to enable a workaround for
+          proper I-Cache support on such systems.  If unsure, say N.
+
 config CPU_DCACHE_DISABLE
         bool "Disable D-Cache (C-bit)"
         depends on (CPU_CP15 && !SMP) || CPU_V7M
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 8c83b4586883..0ee8fc4b4672 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -16,6 +16,14 @@
 
 #include "proc-macros.S"
 
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+        .data
+        .align  2
+icache_size:
+        .long   64
+        .text
+#endif
 /*
  * The secondary kernel init calls v7_flush_dcache_all before it enables
  * the L1; however, the L1 comes out of reset in an undefined state, so
@@ -160,6 +168,9 @@ loop2:
 skip:
         add     r10, r10, #2                    @ increment cache number
         cmp     r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+        dsb
+#endif
         bgt     flush_levels
 finished:
         mov     r10, #0                         @ switch back to cache level 0
@@ -281,7 +292,12 @@ ENTRY(v7_coherent_user_range)
         cmp     r12, r1
         blo     1b
         dsb     ishst
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+        ldr     r3, =icache_size
+        ldr     r2, [r3, #0]
+#else
         icache_line_size r2, r3
+#endif
         sub     r3, r2, #1
         bic     r12, r0, r3
 2:
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 0048eadd0681..ec83c8fca62d 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -53,17 +53,16 @@ static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr)
  * This is useful to dump out the page tables associated with
  * 'addr' in mm 'mm'.
  */
-void show_pte(struct mm_struct *mm, unsigned long addr)
+void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr)
 {
         pgd_t *pgd;
 
         if (!mm)
                 mm = &init_mm;
 
-        pr_alert("pgd = %p\n", mm->pgd);
+        printk("%spgd = %p\n", lvl, mm->pgd);
         pgd = pgd_offset(mm, addr);
-        pr_alert("[%08lx] *pgd=%08llx",
-                        addr, (long long)pgd_val(*pgd));
+        printk("%s[%08lx] *pgd=%08llx", lvl, addr, (long long)pgd_val(*pgd));
 
         do {
                 pud_t *pud;
@@ -118,7 +117,7 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
         pr_cont("\n");
 }
 #else                                   /* CONFIG_MMU */
-void show_pte(struct mm_struct *mm, unsigned long addr)
+void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr)
 { }
 #endif                                  /* CONFIG_MMU */
 
@@ -139,11 +138,12 @@ __do_kernel_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
          * No handler, we'll have to terminate things with extreme prejudice.
          */
         bust_spinlocks(1);
+        pr_alert("8<--- cut here ---\n");
         pr_alert("Unable to handle kernel %s at virtual address %08lx\n",
                  (addr < PAGE_SIZE) ? "NULL pointer dereference" :
                  "paging request", addr);
 
-        show_pte(mm, addr);
+        show_pte(KERN_ALERT, mm, addr);
         die("Oops", regs, fsr);
         bust_spinlocks(0);
         do_exit(SIGKILL);
@@ -164,9 +164,10 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr,
 #ifdef CONFIG_DEBUG_USER
         if (((user_debug & UDBG_SEGV) && (sig == SIGSEGV)) ||
             ((user_debug & UDBG_BUS)  && (sig == SIGBUS))) {
-                printk(KERN_DEBUG "%s: unhandled page fault (%d) at 0x%08lx, code 0x%03x\n",
+                pr_err("8<--- cut here ---\n");
+                pr_err("%s: unhandled page fault (%d) at 0x%08lx, code 0x%03x\n",
                        tsk->comm, sig, addr, fsr);
-                show_pte(tsk->mm, addr);
+                show_pte(KERN_ERR, tsk->mm, addr);
                 show_regs(regs);
         }
 #endif
@@ -553,9 +554,10 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         if (!inf->fn(addr, fsr & ~FSR_LNX_PF, regs))
                 return;
 
+        pr_alert("8<--- cut here ---\n");
         pr_alert("Unhandled fault: %s (0x%03x) at 0x%08lx\n",
                 inf->name, fsr, addr);
-        show_pte(current->mm, addr);
+        show_pte(KERN_ALERT, current->mm, addr);
 
         arm_notify_die("", regs, inf->sig, inf->code, (void __user *)addr,
                        fsr, 0);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 749a5a6f6143..4920a206dce9 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -239,6 +239,22 @@ static void __init arm_initrd_init(void)
 #endif
 }
 
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+void check_cpu_icache_size(int cpuid)
+{
+        u32 size, ctr;
+
+        asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+
+        size = 1 << ((ctr & 0xf) + 2);
+        if (cpuid != 0 && icache_size != size)
+                pr_info("CPU%u: detected I-Cache line size mismatch, workaround enabled\n",
+                        cpuid);
+        if (icache_size > size)
+                icache_size = size;
+}
+#endif
+
 void __init arm_memblock_init(const struct machine_desc *mdesc)
 {
         /* Register the kernel text, kernel data and initrd with memblock. */
@@ -447,12 +463,6 @@ static void __init free_highpages(void)
  */
 void __init mem_init(void)
 {
-#ifdef CONFIG_HAVE_TCM
-        /* These pointers are filled in on TCM detection */
-        extern u32 dtcm_end;
-        extern u32 itcm_end;
-#endif
-
         set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
 
         /* this will put all unused low memory onto the freelists */
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 6b045c6653ea..941356d95a67 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -8,6 +8,8 @@
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
 
+extern int icache_size;
+
 /*
  * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
  * specific hacks for copying pages efficiently, while 0xffff4000
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 83741c31757d..c4e8006a1a8c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -389,6 +389,11 @@ __ca12_errata:
         orr     r10, r10, #1 << 24              @ set bit #24
         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_857271
+        mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orr     r10, r10, #3 << 10              @ set bits #10 and #11
+        mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
         b       __errata_finish
 
 __ca17_errata:
@@ -404,6 +409,11 @@ __ca17_errata:
         orrle   r10, r10, #1 << 12              @ set bit #12
         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_857272
+        mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orr     r10, r10, #3 << 10              @ set bits #10 and #11
+        mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
         b       __errata_finish
 
 __v7_pj4b_setup:
diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile
index 1f5ec9741e6d..ca85df247775 100644
--- a/arch/arm/vdso/Makefile
+++ b/arch/arm/vdso/Makefile
@@ -12,8 +12,7 @@ ccflags-y += -DDISABLE_BRANCH_PROFILING
 
 ldflags-$(CONFIG_CPU_ENDIAN_BE8) := --be8
 ldflags-y := -Bsymbolic --no-undefined -soname=linux-vdso.so.1 \
-            -z max-page-size=4096 -z common-page-size=4096 \
-            -nostdlib -shared $(ldflags-y) \
+            -z max-page-size=4096 -nostdlib -shared $(ldflags-y) \
             $(call ld-option, --hash-style=sysv) \
             $(call ld-option, --build-id) \
             -T