diff options
author | Sam Shih <sam.shih@mediatek.com> | 2019-09-19 18:49:05 -0400 |
---|---|---|
committer | Thierry Reding <thierry.reding@gmail.com> | 2019-09-25 03:49:15 -0400 |
commit | 2503781c97fa66f1ee7ffac21f8c5c330b82b5eb (patch) | |
tree | a6437f16b3f2418e993797d7be45d98689274407 | |
parent | efecdeb82f21d4100566ce85bda2d7ffb9c9edff (diff) |
pwm: mediatek: Use pwm_mediatek as common prefix
Use pwm_mediatek as common prefix to match the filename. No functional
change intended.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r-- | drivers/pwm/pwm-mediatek.c | 117 |
1 files changed, 60 insertions, 57 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index db986b77e556..6b9a5857b5b6 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c | |||
@@ -35,13 +35,13 @@ | |||
35 | 35 | ||
36 | #define PWM_CLK_DIV_MAX 7 | 36 | #define PWM_CLK_DIV_MAX 7 |
37 | 37 | ||
38 | struct mtk_pwm_platform_data { | 38 | struct pwm_mediatek_of_data { |
39 | unsigned int num_pwms; | 39 | unsigned int num_pwms; |
40 | bool pwm45_fixup; | 40 | bool pwm45_fixup; |
41 | }; | 41 | }; |
42 | 42 | ||
43 | /** | 43 | /** |
44 | * struct mtk_pwm_chip - struct representing PWM chip | 44 | * struct pwm_mediatek_chip - struct representing PWM chip |
45 | * @chip: linux PWM chip representation | 45 | * @chip: linux PWM chip representation |
46 | * @regs: base address of PWM chip | 46 | * @regs: base address of PWM chip |
47 | * @clk_top: the top clock generator | 47 | * @clk_top: the top clock generator |
@@ -49,27 +49,29 @@ struct mtk_pwm_platform_data { | |||
49 | * @clk_pwms: the clock used by each PWM channel | 49 | * @clk_pwms: the clock used by each PWM channel |
50 | * @clk_freq: the fix clock frequency of legacy MIPS SoC | 50 | * @clk_freq: the fix clock frequency of legacy MIPS SoC |
51 | */ | 51 | */ |
52 | struct mtk_pwm_chip { | 52 | struct pwm_mediatek_chip { |
53 | struct pwm_chip chip; | 53 | struct pwm_chip chip; |
54 | void __iomem *regs; | 54 | void __iomem *regs; |
55 | struct clk *clk_top; | 55 | struct clk *clk_top; |
56 | struct clk *clk_main; | 56 | struct clk *clk_main; |
57 | struct clk **clk_pwms; | 57 | struct clk **clk_pwms; |
58 | const struct mtk_pwm_platform_data *soc; | 58 | const struct pwm_mediatek_of_data *soc; |
59 | }; | 59 | }; |
60 | 60 | ||
61 | static const unsigned int mtk_pwm_reg_offset[] = { | 61 | static const unsigned int pwm_mediatek_reg_offset[] = { |
62 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 | 62 | 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 |
63 | }; | 63 | }; |
64 | 64 | ||
65 | static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) | 65 | static inline struct pwm_mediatek_chip * |
66 | to_pwm_mediatek_chip(struct pwm_chip *chip) | ||
66 | { | 67 | { |
67 | return container_of(chip, struct mtk_pwm_chip, chip); | 68 | return container_of(chip, struct pwm_mediatek_chip, chip); |
68 | } | 69 | } |
69 | 70 | ||
70 | static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) | 71 | static int pwm_mediatek_clk_enable(struct pwm_chip *chip, |
72 | struct pwm_device *pwm) | ||
71 | { | 73 | { |
72 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | 74 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
73 | int ret; | 75 | int ret; |
74 | 76 | ||
75 | ret = clk_prepare_enable(pc->clk_top); | 77 | ret = clk_prepare_enable(pc->clk_top); |
@@ -94,45 +96,46 @@ disable_clk_top: | |||
94 | return ret; | 96 | return ret; |
95 | } | 97 | } |
96 | 98 | ||
97 | static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) | 99 | static void pwm_mediatek_clk_disable(struct pwm_chip *chip, |
100 | struct pwm_device *pwm) | ||
98 | { | 101 | { |
99 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | 102 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
100 | 103 | ||
101 | clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); | 104 | clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); |
102 | clk_disable_unprepare(pc->clk_main); | 105 | clk_disable_unprepare(pc->clk_main); |
103 | clk_disable_unprepare(pc->clk_top); | 106 | clk_disable_unprepare(pc->clk_top); |
104 | } | 107 | } |
105 | 108 | ||
106 | static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, | 109 | static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, |
107 | unsigned int offset) | 110 | unsigned int num, unsigned int offset) |
108 | { | 111 | { |
109 | return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); | 112 | return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset); |
110 | } | 113 | } |
111 | 114 | ||
112 | static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, | 115 | static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, |
113 | unsigned int num, unsigned int offset, | 116 | unsigned int num, unsigned int offset, |
114 | u32 value) | 117 | u32 value) |
115 | { | 118 | { |
116 | writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); | 119 | writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); |
117 | } | 120 | } |
118 | 121 | ||
119 | static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | 122 | static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, |
120 | int duty_ns, int period_ns) | 123 | int duty_ns, int period_ns) |
121 | { | 124 | { |
122 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | 125 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
123 | struct clk *clk = pc->clk_pwms[pwm->hwpwm]; | ||
124 | u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, | 126 | u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, |
125 | reg_thres = PWMTHRES; | 127 | reg_thres = PWMTHRES; |
126 | u64 resolution; | 128 | u64 resolution; |
127 | int ret; | 129 | int ret; |
128 | 130 | ||
129 | ret = mtk_pwm_clk_enable(chip, pwm); | 131 | ret = pwm_mediatek_clk_enable(chip, pwm); |
132 | |||
130 | if (ret < 0) | 133 | if (ret < 0) |
131 | return ret; | 134 | return ret; |
132 | 135 | ||
133 | /* Using resolution in picosecond gets accuracy higher */ | 136 | /* Using resolution in picosecond gets accuracy higher */ |
134 | resolution = (u64)NSEC_PER_SEC * 1000; | 137 | resolution = (u64)NSEC_PER_SEC * 1000; |
135 | do_div(resolution, clk_get_rate(clk)); | 138 | do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); |
136 | 139 | ||
137 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); | 140 | cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); |
138 | while (cnt_period > 8191) { | 141 | while (cnt_period > 8191) { |
@@ -143,7 +146,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
143 | } | 146 | } |
144 | 147 | ||
145 | if (clkdiv > PWM_CLK_DIV_MAX) { | 148 | if (clkdiv > PWM_CLK_DIV_MAX) { |
146 | mtk_pwm_clk_disable(chip, pwm); | 149 | pwm_mediatek_clk_disable(chip, pwm); |
147 | dev_err(chip->dev, "period %d not supported\n", period_ns); | 150 | dev_err(chip->dev, "period %d not supported\n", period_ns); |
148 | return -EINVAL; | 151 | return -EINVAL; |
149 | } | 152 | } |
@@ -158,22 +161,22 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
158 | } | 161 | } |
159 | 162 | ||
160 | cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); | 163 | cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); |
161 | mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); | 164 | pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); |
162 | mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period); | 165 | pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); |
163 | mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); | 166 | pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); |
164 | 167 | ||
165 | mtk_pwm_clk_disable(chip, pwm); | 168 | pwm_mediatek_clk_disable(chip, pwm); |
166 | 169 | ||
167 | return 0; | 170 | return 0; |
168 | } | 171 | } |
169 | 172 | ||
170 | static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | 173 | static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
171 | { | 174 | { |
172 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | 175 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
173 | u32 value; | 176 | u32 value; |
174 | int ret; | 177 | int ret; |
175 | 178 | ||
176 | ret = mtk_pwm_clk_enable(chip, pwm); | 179 | ret = pwm_mediatek_clk_enable(chip, pwm); |
177 | if (ret < 0) | 180 | if (ret < 0) |
178 | return ret; | 181 | return ret; |
179 | 182 | ||
@@ -184,28 +187,28 @@ static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |||
184 | return 0; | 187 | return 0; |
185 | } | 188 | } |
186 | 189 | ||
187 | static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | 190 | static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
188 | { | 191 | { |
189 | struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); | 192 | struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); |
190 | u32 value; | 193 | u32 value; |
191 | 194 | ||
192 | value = readl(pc->regs); | 195 | value = readl(pc->regs); |
193 | value &= ~BIT(pwm->hwpwm); | 196 | value &= ~BIT(pwm->hwpwm); |
194 | writel(value, pc->regs); | 197 | writel(value, pc->regs); |
195 | 198 | ||
196 | mtk_pwm_clk_disable(chip, pwm); | 199 | pwm_mediatek_clk_disable(chip, pwm); |
197 | } | 200 | } |
198 | 201 | ||
199 | static const struct pwm_ops mtk_pwm_ops = { | 202 | static const struct pwm_ops pwm_mediatek_ops = { |
200 | .config = mtk_pwm_config, | 203 | .config = pwm_mediatek_config, |
201 | .enable = mtk_pwm_enable, | 204 | .enable = pwm_mediatek_enable, |
202 | .disable = mtk_pwm_disable, | 205 | .disable = pwm_mediatek_disable, |
203 | .owner = THIS_MODULE, | 206 | .owner = THIS_MODULE, |
204 | }; | 207 | }; |
205 | 208 | ||
206 | static int mtk_pwm_probe(struct platform_device *pdev) | 209 | static int pwm_mediatek_probe(struct platform_device *pdev) |
207 | { | 210 | { |
208 | struct mtk_pwm_chip *pc; | 211 | struct pwm_mediatek_chip *pc; |
209 | struct resource *res; | 212 | struct resource *res; |
210 | unsigned int i; | 213 | unsigned int i; |
211 | int ret; | 214 | int ret; |
@@ -256,7 +259,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) | |||
256 | platform_set_drvdata(pdev, pc); | 259 | platform_set_drvdata(pdev, pc); |
257 | 260 | ||
258 | pc->chip.dev = &pdev->dev; | 261 | pc->chip.dev = &pdev->dev; |
259 | pc->chip.ops = &mtk_pwm_ops; | 262 | pc->chip.ops = &pwm_mediatek_ops; |
260 | pc->chip.base = -1; | 263 | pc->chip.base = -1; |
261 | pc->chip.npwm = pc->soc->num_pwms; | 264 | pc->chip.npwm = pc->soc->num_pwms; |
262 | 265 | ||
@@ -269,39 +272,39 @@ static int mtk_pwm_probe(struct platform_device *pdev) | |||
269 | return 0; | 272 | return 0; |
270 | } | 273 | } |
271 | 274 | ||
272 | static int mtk_pwm_remove(struct platform_device *pdev) | 275 | static int pwm_mediatek_remove(struct platform_device *pdev) |
273 | { | 276 | { |
274 | struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); | 277 | struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev); |
275 | 278 | ||
276 | return pwmchip_remove(&pc->chip); | 279 | return pwmchip_remove(&pc->chip); |
277 | } | 280 | } |
278 | 281 | ||
279 | static const struct mtk_pwm_platform_data mt2712_pwm_data = { | 282 | static const struct pwm_mediatek_of_data mt2712_pwm_data = { |
280 | .num_pwms = 8, | 283 | .num_pwms = 8, |
281 | .pwm45_fixup = false, | 284 | .pwm45_fixup = false, |
282 | }; | 285 | }; |
283 | 286 | ||
284 | static const struct mtk_pwm_platform_data mt7622_pwm_data = { | 287 | static const struct pwm_mediatek_of_data mt7622_pwm_data = { |
285 | .num_pwms = 6, | 288 | .num_pwms = 6, |
286 | .pwm45_fixup = false, | 289 | .pwm45_fixup = false, |
287 | }; | 290 | }; |
288 | 291 | ||
289 | static const struct mtk_pwm_platform_data mt7623_pwm_data = { | 292 | static const struct pwm_mediatek_of_data mt7623_pwm_data = { |
290 | .num_pwms = 5, | 293 | .num_pwms = 5, |
291 | .pwm45_fixup = true, | 294 | .pwm45_fixup = true, |
292 | }; | 295 | }; |
293 | 296 | ||
294 | static const struct mtk_pwm_platform_data mt7628_pwm_data = { | 297 | static const struct pwm_mediatek_of_data mt7628_pwm_data = { |
295 | .num_pwms = 4, | 298 | .num_pwms = 4, |
296 | .pwm45_fixup = true, | 299 | .pwm45_fixup = true, |
297 | }; | 300 | }; |
298 | 301 | ||
299 | static const struct mtk_pwm_platform_data mt8516_pwm_data = { | 302 | static const struct pwm_mediatek_of_data mt8516_pwm_data = { |
300 | .num_pwms = 5, | 303 | .num_pwms = 5, |
301 | .pwm45_fixup = false, | 304 | .pwm45_fixup = false, |
302 | }; | 305 | }; |
303 | 306 | ||
304 | static const struct of_device_id mtk_pwm_of_match[] = { | 307 | static const struct of_device_id pwm_mediatek_of_match[] = { |
305 | { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, | 308 | { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, |
306 | { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, | 309 | { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, |
307 | { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, | 310 | { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, |
@@ -309,17 +312,17 @@ static const struct of_device_id mtk_pwm_of_match[] = { | |||
309 | { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, | 312 | { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, |
310 | { }, | 313 | { }, |
311 | }; | 314 | }; |
312 | MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); | 315 | MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); |
313 | 316 | ||
314 | static struct platform_driver mtk_pwm_driver = { | 317 | static struct platform_driver pwm_mediatek_driver = { |
315 | .driver = { | 318 | .driver = { |
316 | .name = "mtk-pwm", | 319 | .name = "pwm-mediatek", |
317 | .of_match_table = mtk_pwm_of_match, | 320 | .of_match_table = pwm_mediatek_of_match, |
318 | }, | 321 | }, |
319 | .probe = mtk_pwm_probe, | 322 | .probe = pwm_mediatek_probe, |
320 | .remove = mtk_pwm_remove, | 323 | .remove = pwm_mediatek_remove, |
321 | }; | 324 | }; |
322 | module_platform_driver(mtk_pwm_driver); | 325 | module_platform_driver(pwm_mediatek_driver); |
323 | 326 | ||
324 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); | 327 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
325 | MODULE_LICENSE("GPL"); | 328 | MODULE_LICENSE("GPL"); |