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authorKishon Vijay Abraham I <kishon@ti.com>2019-03-25 05:39:26 -0400
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2019-04-11 05:58:25 -0400
commit2341ab4fd5d7ee3db5c67e8ff8506722910df8e9 (patch)
treefa89ff4928eda238162fb0f9d5427c55e7e068cc
parentf3560a9f88ae3aa2b2976a1a0175478f6fd32fe8 (diff)
PCI: keystone: Use platform_get_resource_byname() to get memory resources
Use platform_get_resource_byname() instead of platform_get_resource() which uses an index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since the pci-keystone driver has never worked in the mainline kernel, DT backward compatibility is not an issue. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 566718ea7ebf..5eebef9b9ada 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -44,7 +44,6 @@
44#define CFG_TYPE1 BIT(24) 44#define CFG_TYPE1 BIT(24)
45 45
46#define OB_SIZE 0x030 46#define OB_SIZE 0x030
47#define SPACE0_REMOTE_CFG_OFFSET 0x1000
48#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) 47#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
49#define OB_OFFSET_HI(n) (0x204 + (8 * (n))) 48#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
50#define OB_ENABLEN BIT(0) 49#define OB_ENABLEN BIT(0)
@@ -807,21 +806,19 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
807 struct resource *res; 806 struct resource *res;
808 int ret; 807 int ret;
809 808
810 /* Index 0 is the config reg. space address */ 809 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics");
811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
812 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 810 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
813 if (IS_ERR(pci->dbi_base)) 811 if (IS_ERR(pci->dbi_base))
814 return PTR_ERR(pci->dbi_base); 812 return PTR_ERR(pci->dbi_base);
815 813
816 /* 814 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
817 * We set these same and is used in pcie rd/wr_other_conf 815 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
818 * functions 816 if (IS_ERR(pp->va_cfg0_base))
819 */ 817 return PTR_ERR(pp->va_cfg0_base);
820 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; 818
821 pp->va_cfg1_base = pp->va_cfg0_base; 819 pp->va_cfg1_base = pp->va_cfg0_base;
822 820
823 /* Index 1 is the application reg. space address */ 821 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app");
824 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
825 ks_pcie->va_app_base = devm_ioremap_resource(dev, res); 822 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
826 if (IS_ERR(ks_pcie->va_app_base)) 823 if (IS_ERR(ks_pcie->va_app_base))
827 return PTR_ERR(ks_pcie->va_app_base); 824 return PTR_ERR(ks_pcie->va_app_base);