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authorMatti Vaittinen <matti.vaittinen@fi.rohmeurope.com>2019-06-03 03:25:08 -0400
committerLee Jones <lee.jones@linaro.org>2019-06-27 05:57:24 -0400
commit21b7c58fc1943f3aa8c18a994ab9bed4ae5aa72d (patch)
treec6e650600dfe6c644e1e7e7046574986629f345f
parent2a6a7aacd4e557a4c7007f8858bcc9654b098fea (diff)
mfd: bd70528: Support ROHM bd70528 PMIC core
ROHM BD70528MWV is an ultra-low quiescent current general purpose single-chip power management IC for battery-powered portable devices. Add MFD core which enables chip access for following subdevices: - regulators/LED drivers - battery-charger - gpios - 32.768kHz clk - RTC - watchdog Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat
-rw-r--r--drivers/mfd/Kconfig17
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/rohm-bd70528.c316
-rw-r--r--include/linux/mfd/rohm-bd70528.h408
4 files changed, 743 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 294d9567cc71..11fc53d78c5f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1890,6 +1890,23 @@ config MFD_ROHM_BD718XX
1890 NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring 1890 NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring
1891 and emergency shut down as well as 32,768KHz clock output. 1891 and emergency shut down as well as 32,768KHz clock output.
1892 1892
1893config MFD_ROHM_BD70528
1894 tristate "ROHM BD70528 Power Management IC"
1895 depends on I2C=y
1896 depends on OF
1897 select REGMAP_I2C
1898 select REGMAP_IRQ
1899 select MFD_CORE
1900 help
1901 Select this option to get support for the ROHM BD70528 Power
1902 Management IC. BD71837 is general purpose single-chip power
1903 management IC for battery-powered portable devices. It contains
1904 3 ultra-low current consumption buck converters, 3 LDOs and 2 LED
1905 drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
1906 crystal oscillator, high-accuracy VREF for use with an external ADC,
1907 10 bits SAR ADC for battery temperature monitor and 1S battery
1908 charger.
1909
1893config MFD_STM32_LPTIMER 1910config MFD_STM32_LPTIMER
1894 tristate "Support for STM32 Low-Power Timer" 1911 tristate "Support for STM32 Low-Power Timer"
1895 depends on (ARCH_STM32 && OF) || COMPILE_TEST 1912 depends on (ARCH_STM32 && OF) || COMPILE_TEST
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 52b1a90ff515..643d65bcb6ea 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -247,5 +247,7 @@ obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
247obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o 247obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o
248obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o 248obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o
249obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o 249obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
250obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o
250obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o 251obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
251obj-$(CONFIG_MFD_STMFX) += stmfx.o 252obj-$(CONFIG_MFD_STMFX) += stmfx.o
253
diff --git a/drivers/mfd/rohm-bd70528.c b/drivers/mfd/rohm-bd70528.c
new file mode 100644
index 000000000000..55599d5c5c86
--- /dev/null
+++ b/drivers/mfd/rohm-bd70528.c
@@ -0,0 +1,316 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2//
3// Copyright (C) 2019 ROHM Semiconductors
4//
5// ROHM BD70528 PMIC driver
6
7#include <linux/i2c.h>
8#include <linux/interrupt.h>
9#include <linux/ioport.h>
10#include <linux/irq.h>
11#include <linux/mfd/core.h>
12#include <linux/mfd/rohm-bd70528.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/regmap.h>
16#include <linux/types.h>
17
18#define BD70528_NUM_OF_GPIOS 4
19
20static const struct resource rtc_irqs[] = {
21 DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"),
22 DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"),
23};
24
25static const struct resource charger_irqs[] = {
26 DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"),
27 DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"),
28 DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"),
29 DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"),
30 DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"),
31 DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"),
32 DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"),
33 DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"),
34 DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"),
35 DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"),
36 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"),
37 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"),
38 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"),
39 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"),
40 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"),
41 DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"),
42};
43
44static struct mfd_cell bd70528_mfd_cells[] = {
45 { .name = "bd70528-pmic", },
46 { .name = "bd70528-gpio", },
47 /*
48 * We use BD71837 driver to drive the clock block. Only differences to
49 * BD70528 clock gate are the register address and mask.
50 */
51 { .name = "bd718xx-clk", },
52 { .name = "bd70528-wdt", },
53 {
54 .name = "bd70528-power",
55 .resources = charger_irqs,
56 .num_resources = ARRAY_SIZE(charger_irqs),
57 }, {
58 .name = "bd70528-rtc",
59 .resources = rtc_irqs,
60 .num_resources = ARRAY_SIZE(rtc_irqs),
61 },
62};
63
64static const struct regmap_range volatile_ranges[] = {
65 {
66 .range_min = BD70528_REG_INT_MAIN,
67 .range_max = BD70528_REG_INT_OP_FAIL,
68 }, {
69 .range_min = BD70528_REG_RTC_COUNT_H,
70 .range_max = BD70528_REG_RTC_ALM_REPEAT,
71 }, {
72 /*
73 * WDT control reg is special. Magic values must be written to
74 * it in order to change the control. Should not be cached.
75 */
76 .range_min = BD70528_REG_WDT_CTRL,
77 .range_max = BD70528_REG_WDT_CTRL,
78 }, {
79 /*
80 * BD70528 also contains a few other registers which require
81 * magic sequences to be written in order to update the value.
82 * At least SHIPMODE, HWRESET, WARMRESET,and STANDBY
83 */
84 .range_min = BD70528_REG_SHIPMODE,
85 .range_max = BD70528_REG_STANDBY,
86 },
87};
88
89static const struct regmap_access_table volatile_regs = {
90 .yes_ranges = &volatile_ranges[0],
91 .n_yes_ranges = ARRAY_SIZE(volatile_ranges),
92};
93
94static struct regmap_config bd70528_regmap = {
95 .reg_bits = 8,
96 .val_bits = 8,
97 .volatile_table = &volatile_regs,
98 .max_register = BD70528_MAX_REGISTER,
99 .cache_type = REGCACHE_RBTREE,
100};
101
102/*
103 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
104 * access corect sub-IRQ registers based on bits that are set in main IRQ
105 * register.
106 */
107
108/* bit [0] - Shutdown register */
109unsigned int bit0_offsets[] = {0}; /* Shutdown register */
110unsigned int bit1_offsets[] = {1}; /* Power failure register */
111unsigned int bit2_offsets[] = {2}; /* VR FAULT register */
112unsigned int bit3_offsets[] = {3}; /* PMU register interrupts */
113unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 registers */
114unsigned int bit5_offsets[] = {6}; /* RTC register */
115unsigned int bit6_offsets[] = {7}; /* GPIO register */
116unsigned int bit7_offsets[] = {8}; /* Invalid operation register */
117
118static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = {
119 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
120 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
121 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
122 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
123 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
124 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),
125 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),
126 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
127};
128
129static struct regmap_irq bd70528_irqs[] = {
130 REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK),
131 REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK),
132 REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK),
133 REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK),
134 REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK),
135 REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK),
136 REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK),
137 REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1,
138 BD70528_INT_BUCK1_FAULT_MASK),
139 REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1,
140 BD70528_INT_BUCK2_FAULT_MASK),
141 REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1,
142 BD70528_INT_BUCK3_FAULT_MASK),
143 REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK),
144 REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK),
145 REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK),
146 REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK),
147 REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK),
148 REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK),
149 REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK),
150 REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK),
151 REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK),
152 REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK),
153 REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2,
154 BD70528_INT_BUCK1_FULLON_MASK),
155 REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2,
156 BD70528_INT_BUCK2_FULLON_MASK),
157 REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK),
158 REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3,
159 BD70528_INT_AUTO_WAKEUP_MASK),
160 REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3,
161 BD70528_INT_STATE_CHANGE_MASK),
162 REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK),
163 REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK),
164 REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK),
165 REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4,
166 BD70528_INT_BATTSD_COLD_RES_MASK),
167 REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4,
168 BD70528_INT_BATTSD_COLD_DET_MASK),
169 REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4,
170 BD70528_INT_BATTSD_HOT_RES_MASK),
171 REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4,
172 BD70528_INT_BATTSD_HOT_DET_MASK),
173 REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK),
174 REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK),
175 REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK),
176 REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5,
177 BD70528_INT_DCIN2_OV_RES_MASK),
178 REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5,
179 BD70528_INT_DCIN2_OV_DET_MASK),
180 REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK),
181 REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK),
182 REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK),
183 REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK),
184 REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK),
185 REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK),
186 REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK),
187 REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK),
188 REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK),
189 REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK),
190 REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8,
191 BD70528_INT_BUCK1_DVS_OPFAIL_MASK),
192 REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8,
193 BD70528_INT_BUCK2_DVS_OPFAIL_MASK),
194 REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8,
195 BD70528_INT_BUCK3_DVS_OPFAIL_MASK),
196 REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8,
197 BD70528_INT_LED1_VOLT_OPFAIL_MASK),
198 REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8,
199 BD70528_INT_LED2_VOLT_OPFAIL_MASK),
200};
201
202static struct regmap_irq_chip bd70528_irq_chip = {
203 .name = "bd70528_irq",
204 .main_status = BD70528_REG_INT_MAIN,
205 .irqs = &bd70528_irqs[0],
206 .num_irqs = ARRAY_SIZE(bd70528_irqs),
207 .status_base = BD70528_REG_INT_SHDN,
208 .mask_base = BD70528_REG_INT_SHDN_MASK,
209 .ack_base = BD70528_REG_INT_SHDN,
210 .type_base = BD70528_REG_GPIO1_IN,
211 .init_ack_masked = true,
212 .num_regs = 9,
213 .num_main_regs = 1,
214 .num_type_reg = 4,
215 .sub_reg_offsets = &bd70528_sub_irq_offsets[0],
216 .num_main_status_bits = 8,
217 .irq_reg_stride = 1,
218};
219
220static int bd70528_i2c_probe(struct i2c_client *i2c,
221 const struct i2c_device_id *id)
222{
223 struct bd70528_data *bd70528;
224 struct regmap_irq_chip_data *irq_data;
225 int ret, i;
226
227 if (!i2c->irq) {
228 dev_err(&i2c->dev, "No IRQ configured\n");
229 return -EINVAL;
230 }
231
232 bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL);
233 if (!bd70528)
234 return -ENOMEM;
235
236 mutex_init(&bd70528->rtc_timer_lock);
237
238 dev_set_drvdata(&i2c->dev, &bd70528->chip);
239
240 bd70528->chip.chip_type = ROHM_CHIP_TYPE_BD70528;
241 bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap);
242 if (IS_ERR(bd70528->chip.regmap)) {
243 dev_err(&i2c->dev, "Failed to initialize Regmap\n");
244 return PTR_ERR(bd70528->chip.regmap);
245 }
246
247 /*
248 * Disallow type setting for all IRQs by default as most of them do not
249 * support setting type.
250 */
251 for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++)
252 bd70528_irqs[i].type.types_supported = 0;
253
254 /* Set IRQ typesetting information for GPIO pins 0 - 3 */
255 for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) {
256 struct regmap_irq_type *type;
257
258 type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type;
259 type->type_reg_offset = 2 * i;
260 type->type_rising_val = 0x20;
261 type->type_falling_val = 0x10;
262 type->type_level_high_val = 0x40;
263 type->type_level_low_val = 0x50;
264 type->types_supported = (IRQ_TYPE_EDGE_BOTH |
265 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
266 }
267
268 ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap,
269 i2c->irq, IRQF_ONESHOT, 0,
270 &bd70528_irq_chip, &irq_data);
271 if (ret) {
272 dev_err(&i2c->dev, "Failed to add IRQ chip\n");
273 return ret;
274 }
275 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
276 bd70528_irq_chip.num_irqs);
277
278 /*
279 * BD70528 IRQ controller is not touching the main mask register.
280 * So enable the GPIO block interrupts at main level. We can just leave
281 * them enabled as the IRQ controller should disable IRQs from
282 * sub-registers when IRQ is disabled or freed.
283 */
284 ret = regmap_update_bits(bd70528->chip.regmap,
285 BD70528_REG_INT_MAIN_MASK,
286 BD70528_INT_GPIO_MASK, 0);
287
288 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
289 bd70528_mfd_cells,
290 ARRAY_SIZE(bd70528_mfd_cells), NULL, 0,
291 regmap_irq_get_domain(irq_data));
292 if (ret)
293 dev_err(&i2c->dev, "Failed to create subdevices\n");
294
295 return ret;
296}
297
298static const struct of_device_id bd70528_of_match[] = {
299 { .compatible = "rohm,bd70528", },
300 { },
301};
302MODULE_DEVICE_TABLE(of, bd70528_of_match);
303
304static struct i2c_driver bd70528_drv = {
305 .driver = {
306 .name = "rohm-bd70528",
307 .of_match_table = bd70528_of_match,
308 },
309 .probe = &bd70528_i2c_probe,
310};
311
312module_i2c_driver(bd70528_drv);
313
314MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
315MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver");
316MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/rohm-bd70528.h b/include/linux/mfd/rohm-bd70528.h
new file mode 100644
index 000000000000..1013e60c5b25
--- /dev/null
+++ b/include/linux/mfd/rohm-bd70528.h
@@ -0,0 +1,408 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Copyright (C) 2018 ROHM Semiconductors */
3
4#ifndef __LINUX_MFD_BD70528_H__
5#define __LINUX_MFD_BD70528_H__
6
7#include <linux/bits.h>
8#include <linux/device.h>
9#include <linux/mfd/rohm-generic.h>
10#include <linux/regmap.h>
11
12enum {
13 BD70528_BUCK1,
14 BD70528_BUCK2,
15 BD70528_BUCK3,
16 BD70528_LDO1,
17 BD70528_LDO2,
18 BD70528_LDO3,
19 BD70528_LED1,
20 BD70528_LED2,
21};
22
23struct bd70528_data {
24 struct rohm_regmap_dev chip;
25 struct mutex rtc_timer_lock;
26};
27
28#define BD70528_BUCK_VOLTS 17
29#define BD70528_BUCK_VOLTS 17
30#define BD70528_BUCK_VOLTS 17
31#define BD70528_LDO_VOLTS 0x20
32
33#define BD70528_REG_BUCK1_EN 0x0F
34#define BD70528_REG_BUCK1_VOLT 0x15
35#define BD70528_REG_BUCK2_EN 0x10
36#define BD70528_REG_BUCK2_VOLT 0x16
37#define BD70528_REG_BUCK3_EN 0x11
38#define BD70528_REG_BUCK3_VOLT 0x17
39#define BD70528_REG_LDO1_EN 0x1b
40#define BD70528_REG_LDO1_VOLT 0x1e
41#define BD70528_REG_LDO2_EN 0x1c
42#define BD70528_REG_LDO2_VOLT 0x1f
43#define BD70528_REG_LDO3_EN 0x1d
44#define BD70528_REG_LDO3_VOLT 0x20
45#define BD70528_REG_LED_CTRL 0x2b
46#define BD70528_REG_LED_VOLT 0x29
47#define BD70528_REG_LED_EN 0x2a
48
49/* main irq registers */
50#define BD70528_REG_INT_MAIN 0x7E
51#define BD70528_REG_INT_MAIN_MASK 0x74
52
53/* 'sub irq' registers */
54#define BD70528_REG_INT_SHDN 0x7F
55#define BD70528_REG_INT_PWR_FLT 0x80
56#define BD70528_REG_INT_VR_FLT 0x81
57#define BD70528_REG_INT_MISC 0x82
58#define BD70528_REG_INT_BAT1 0x83
59#define BD70528_REG_INT_BAT2 0x84
60#define BD70528_REG_INT_RTC 0x85
61#define BD70528_REG_INT_GPIO 0x86
62#define BD70528_REG_INT_OP_FAIL 0x87
63
64#define BD70528_REG_INT_SHDN_MASK 0x75
65#define BD70528_REG_INT_PWR_FLT_MASK 0x76
66#define BD70528_REG_INT_VR_FLT_MASK 0x77
67#define BD70528_REG_INT_MISC_MASK 0x78
68#define BD70528_REG_INT_BAT1_MASK 0x79
69#define BD70528_REG_INT_BAT2_MASK 0x7a
70#define BD70528_REG_INT_RTC_MASK 0x7b
71#define BD70528_REG_INT_GPIO_MASK 0x7c
72#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
73
74/* Reset related 'magic' registers */
75#define BD70528_REG_SHIPMODE 0x03
76#define BD70528_REG_HWRESET 0x04
77#define BD70528_REG_WARMRESET 0x05
78#define BD70528_REG_STANDBY 0x06
79
80/* GPIO registers */
81#define BD70528_REG_GPIO_STATE 0x8F
82
83#define BD70528_REG_GPIO1_IN 0x4d
84#define BD70528_REG_GPIO2_IN 0x4f
85#define BD70528_REG_GPIO3_IN 0x51
86#define BD70528_REG_GPIO4_IN 0x53
87#define BD70528_REG_GPIO1_OUT 0x4e
88#define BD70528_REG_GPIO2_OUT 0x50
89#define BD70528_REG_GPIO3_OUT 0x52
90#define BD70528_REG_GPIO4_OUT 0x54
91
92/* clk control */
93
94#define BD70528_REG_CLK_OUT 0x2c
95
96/* RTC */
97
98#define BD70528_REG_RTC_COUNT_H 0x2d
99#define BD70528_REG_RTC_COUNT_L 0x2e
100#define BD70528_REG_RTC_SEC 0x2f
101#define BD70528_REG_RTC_MINUTE 0x30
102#define BD70528_REG_RTC_HOUR 0x31
103#define BD70528_REG_RTC_WEEK 0x32
104#define BD70528_REG_RTC_DAY 0x33
105#define BD70528_REG_RTC_MONTH 0x34
106#define BD70528_REG_RTC_YEAR 0x35
107
108#define BD70528_REG_RTC_ALM_SEC 0x36
109#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
110#define BD70528_REG_RTC_ALM_MINUTE 0x37
111#define BD70528_REG_RTC_ALM_HOUR 0x38
112#define BD70528_REG_RTC_ALM_WEEK 0x39
113#define BD70528_REG_RTC_ALM_DAY 0x3a
114#define BD70528_REG_RTC_ALM_MONTH 0x3b
115#define BD70528_REG_RTC_ALM_YEAR 0x3c
116#define BD70528_REG_RTC_ALM_MASK 0x3d
117#define BD70528_REG_RTC_ALM_REPEAT 0x3e
118#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
119
120#define BD70528_REG_RTC_WAKE_SEC 0x43
121#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
122#define BD70528_REG_RTC_WAKE_MIN 0x44
123#define BD70528_REG_RTC_WAKE_HOUR 0x45
124#define BD70528_REG_RTC_WAKE_CTRL 0x46
125
126#define BD70528_REG_ELAPSED_TIMER_EN 0x42
127#define BD70528_REG_WAKE_EN 0x46
128
129/* WDT registers */
130#define BD70528_REG_WDT_CTRL 0x4A
131#define BD70528_REG_WDT_HOUR 0x49
132#define BD70528_REG_WDT_MINUTE 0x48
133#define BD70528_REG_WDT_SEC 0x47
134
135/* Charger / Battery */
136#define BD70528_REG_CHG_CURR_STAT 0x59
137#define BD70528_REG_CHG_BAT_STAT 0x57
138#define BD70528_REG_CHG_BAT_TEMP 0x58
139#define BD70528_REG_CHG_IN_STAT 0x56
140#define BD70528_REG_CHG_DCIN_ILIM 0x5d
141#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
142#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
143
144/* Masks for main IRQ register bits */
145enum {
146 BD70528_INT_SHDN,
147#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
148 BD70528_INT_PWR_FLT,
149#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
150 BD70528_INT_VR_FLT,
151#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
152 BD70528_INT_MISC,
153#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
154 BD70528_INT_BAT1,
155#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
156 BD70528_INT_RTC,
157#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
158 BD70528_INT_GPIO,
159#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
160 BD70528_INT_OP_FAIL,
161#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
162};
163
164/* IRQs */
165enum {
166 /* Shutdown register IRQs */
167 BD70528_INT_LONGPUSH,
168 BD70528_INT_WDT,
169 BD70528_INT_HWRESET,
170 BD70528_INT_RSTB_FAULT,
171 BD70528_INT_VBAT_UVLO,
172 BD70528_INT_TSD,
173 BD70528_INT_RSTIN,
174 /* Power failure register IRQs */
175 BD70528_INT_BUCK1_FAULT,
176 BD70528_INT_BUCK2_FAULT,
177 BD70528_INT_BUCK3_FAULT,
178 BD70528_INT_LDO1_FAULT,
179 BD70528_INT_LDO2_FAULT,
180 BD70528_INT_LDO3_FAULT,
181 BD70528_INT_LED1_FAULT,
182 BD70528_INT_LED2_FAULT,
183 /* VR FAULT register IRQs */
184 BD70528_INT_BUCK1_OCP,
185 BD70528_INT_BUCK2_OCP,
186 BD70528_INT_BUCK3_OCP,
187 BD70528_INT_LED1_OCP,
188 BD70528_INT_LED2_OCP,
189 BD70528_INT_BUCK1_FULLON,
190 BD70528_INT_BUCK2_FULLON,
191 /* PMU register interrupts */
192 BD70528_INT_SHORTPUSH,
193 BD70528_INT_AUTO_WAKEUP,
194 BD70528_INT_STATE_CHANGE,
195 /* Charger 1 register IRQs */
196 BD70528_INT_BAT_OV_RES,
197 BD70528_INT_BAT_OV_DET,
198 BD70528_INT_DBAT_DET,
199 BD70528_INT_BATTSD_COLD_RES,
200 BD70528_INT_BATTSD_COLD_DET,
201 BD70528_INT_BATTSD_HOT_RES,
202 BD70528_INT_BATTSD_HOT_DET,
203 BD70528_INT_CHG_TSD,
204 /* Charger 2 register IRQs */
205 BD70528_INT_BAT_RMV,
206 BD70528_INT_BAT_DET,
207 BD70528_INT_DCIN2_OV_RES,
208 BD70528_INT_DCIN2_OV_DET,
209 BD70528_INT_DCIN2_RMV,
210 BD70528_INT_DCIN2_DET,
211 BD70528_INT_DCIN1_RMV,
212 BD70528_INT_DCIN1_DET,
213 /* RTC register IRQs */
214 BD70528_INT_RTC_ALARM,
215 BD70528_INT_ELPS_TIM,
216 /* GPIO register IRQs */
217 BD70528_INT_GPIO0,
218 BD70528_INT_GPIO1,
219 BD70528_INT_GPIO2,
220 BD70528_INT_GPIO3,
221 /* Invalid operation register IRQs */
222 BD70528_INT_BUCK1_DVS_OPFAIL,
223 BD70528_INT_BUCK2_DVS_OPFAIL,
224 BD70528_INT_BUCK3_DVS_OPFAIL,
225 BD70528_INT_LED1_VOLT_OPFAIL,
226 BD70528_INT_LED2_VOLT_OPFAIL,
227};
228
229/* Masks */
230#define BD70528_INT_LONGPUSH_MASK 0x1
231#define BD70528_INT_WDT_MASK 0x2
232#define BD70528_INT_HWRESET_MASK 0x4
233#define BD70528_INT_RSTB_FAULT_MASK 0x8
234#define BD70528_INT_VBAT_UVLO_MASK 0x10
235#define BD70528_INT_TSD_MASK 0x20
236#define BD70528_INT_RSTIN_MASK 0x40
237
238#define BD70528_INT_BUCK1_FAULT_MASK 0x1
239#define BD70528_INT_BUCK2_FAULT_MASK 0x2
240#define BD70528_INT_BUCK3_FAULT_MASK 0x4
241#define BD70528_INT_LDO1_FAULT_MASK 0x8
242#define BD70528_INT_LDO2_FAULT_MASK 0x10
243#define BD70528_INT_LDO3_FAULT_MASK 0x20
244#define BD70528_INT_LED1_FAULT_MASK 0x40
245#define BD70528_INT_LED2_FAULT_MASK 0x80
246
247#define BD70528_INT_BUCK1_OCP_MASK 0x1
248#define BD70528_INT_BUCK2_OCP_MASK 0x2
249#define BD70528_INT_BUCK3_OCP_MASK 0x4
250#define BD70528_INT_LED1_OCP_MASK 0x8
251#define BD70528_INT_LED2_OCP_MASK 0x10
252#define BD70528_INT_BUCK1_FULLON_MASK 0x20
253#define BD70528_INT_BUCK2_FULLON_MASK 0x40
254
255#define BD70528_INT_SHORTPUSH_MASK 0x1
256#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
257#define BD70528_INT_STATE_CHANGE_MASK 0x10
258
259#define BD70528_INT_BAT_OV_RES_MASK 0x1
260#define BD70528_INT_BAT_OV_DET_MASK 0x2
261#define BD70528_INT_DBAT_DET_MASK 0x4
262#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
263#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
264#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
265#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
266#define BD70528_INT_CHG_TSD_MASK 0x80
267
268#define BD70528_INT_BAT_RMV_MASK 0x1
269#define BD70528_INT_BAT_DET_MASK 0x2
270#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
271#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
272#define BD70528_INT_DCIN2_RMV_MASK 0x10
273#define BD70528_INT_DCIN2_DET_MASK 0x20
274#define BD70528_INT_DCIN1_RMV_MASK 0x40
275#define BD70528_INT_DCIN1_DET_MASK 0x80
276
277#define BD70528_INT_RTC_ALARM_MASK 0x1
278#define BD70528_INT_ELPS_TIM_MASK 0x2
279
280#define BD70528_INT_GPIO0_MASK 0x1
281#define BD70528_INT_GPIO1_MASK 0x2
282#define BD70528_INT_GPIO2_MASK 0x4
283#define BD70528_INT_GPIO3_MASK 0x8
284
285#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
286#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
287#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
288#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
289#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
290
291#define BD70528_DEBOUNCE_MASK 0x3
292
293#define BD70528_DEBOUNCE_DISABLE 0
294#define BD70528_DEBOUNCE_15MS 1
295#define BD70528_DEBOUNCE_30MS 2
296#define BD70528_DEBOUNCE_50MS 3
297
298#define BD70528_GPIO_DRIVE_MASK 0x2
299#define BD70528_GPIO_PUSH_PULL 0x0
300#define BD70528_GPIO_OPEN_DRAIN 0x2
301
302#define BD70528_GPIO_OUT_EN_MASK 0x80
303#define BD70528_GPIO_OUT_ENABLE 0x80
304#define BD70528_GPIO_OUT_DISABLE 0x0
305
306#define BD70528_GPIO_OUT_HI 0x1
307#define BD70528_GPIO_OUT_LO 0x0
308#define BD70528_GPIO_OUT_MASK 0x1
309
310#define BD70528_GPIO_IN_STATE_BASE 1
311
312#define BD70528_CLK_OUT_EN_MASK 0x1
313
314/* RTC masks to mask out reserved bits */
315
316#define BD70528_MASK_RTC_SEC 0x7f
317#define BD70528_MASK_RTC_MINUTE 0x7f
318#define BD70528_MASK_RTC_HOUR_24H 0x80
319#define BD70528_MASK_RTC_HOUR_PM 0x20
320#define BD70528_MASK_RTC_HOUR 0x1f
321#define BD70528_MASK_RTC_DAY 0x3f
322#define BD70528_MASK_RTC_WEEK 0x07
323#define BD70528_MASK_RTC_MONTH 0x1f
324#define BD70528_MASK_RTC_YEAR 0xff
325#define BD70528_MASK_RTC_COUNT_L 0x7f
326
327#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
328/* Mask second, min and hour fields
329 * HW would support ALM irq for over 24h
330 * (by setting day, month and year too)
331 * but as we wish to keep this same as for
332 * wake-up we limit ALM to 24H and only
333 * unmask sec, min and hour
334 */
335#define BD70528_MASK_ALM_EN 0x7
336#define BD70528_MASK_WAKE_EN 0x1
337
338/* WDT masks */
339#define BD70528_MASK_WDT_EN 0x1
340#define BD70528_MASK_WDT_HOUR 0x1
341#define BD70528_MASK_WDT_MINUTE 0x7f
342#define BD70528_MASK_WDT_SEC 0x7f
343
344#define BD70528_WDT_STATE_BIT 0x1
345#define BD70528_ELAPSED_STATE_BIT 0x2
346#define BD70528_WAKE_STATE_BIT 0x4
347
348/* Charger masks */
349#define BD70528_MASK_CHG_STAT 0x7f
350#define BD70528_MASK_CHG_BAT_TIMER 0x20
351#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
352#define BD70528_MASK_CHG_BAT_DETECT 0x1
353#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
354#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
355#define BD70528_MASK_CHG_CHG_CURR 0x1f
356#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
357
358/*
359 * Note, external battery register is the lonely rider at
360 * address 0xc5. See how to stuff that in the regmap
361 */
362#define BD70528_MAX_REGISTER 0x94
363
364/* Buck control masks */
365#define BD70528_MASK_RUN_EN 0x4
366#define BD70528_MASK_STBY_EN 0x2
367#define BD70528_MASK_IDLE_EN 0x1
368#define BD70528_MASK_LED1_EN 0x1
369#define BD70528_MASK_LED2_EN 0x10
370
371#define BD70528_MASK_BUCK_VOLT 0xf
372#define BD70528_MASK_LDO_VOLT 0x1f
373#define BD70528_MASK_LED1_VOLT 0x1
374#define BD70528_MASK_LED2_VOLT 0x10
375
376/* Misc irq masks */
377#define BD70528_INT_MASK_SHORT_PUSH 1
378#define BD70528_INT_MASK_AUTO_WAKE 2
379#define BD70528_INT_MASK_POWER_STATE 4
380
381#define BD70528_MASK_BUCK_RAMP 0x10
382#define BD70528_SIFT_BUCK_RAMP 4
383
384#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
385
386int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
387void bd70528_wdt_lock(struct rohm_regmap_dev *data);
388void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
389
390#else /* CONFIG_BD70528_WATCHDOG */
391
392static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
393 int *old_state)
394{
395 return 0;
396}
397
398static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
399{
400}
401
402static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
403{
404}
405
406#endif /* CONFIG_BD70528_WATCHDOG */
407
408#endif /* __LINUX_MFD_BD70528_H__ */
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