diff options
author | Dhaval Shah <dhaval.shah@softnautics.com> | 2017-12-08 00:56:55 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-12-18 10:00:57 -0500 |
commit | 1e3ae175fd47482933d59ac561057d5d80089388 (patch) | |
tree | eb8121bc80e3a7f74a5d8588720bb91f7223b017 | |
parent | 67d0833f050d2554fd652b745ea76934fe308a6a (diff) |
misc: ics932s401: please, no space before tabs
Resolved all the please, no space beofore tabs checkpatch
warnings. Issue found by checkpatch.
Signed-off-by: Dhaval Shah <dhaval.shah@softnautics.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/misc/ics932s401.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/misc/ics932s401.c b/drivers/misc/ics932s401.c index d22e2dc62907..12177db99ce1 100644 --- a/drivers/misc/ics932s401.c +++ b/drivers/misc/ics932s401.c | |||
@@ -33,7 +33,7 @@ static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END }; | |||
33 | 33 | ||
34 | /* ICS932S401 registers */ | 34 | /* ICS932S401 registers */ |
35 | #define ICS932S401_REG_CFG2 0x01 | 35 | #define ICS932S401_REG_CFG2 0x01 |
36 | #define ICS932S401_CFG1_SPREAD 0x01 | 36 | #define ICS932S401_CFG1_SPREAD 0x01 |
37 | #define ICS932S401_REG_CFG7 0x06 | 37 | #define ICS932S401_REG_CFG7 0x06 |
38 | #define ICS932S401_FS_MASK 0x07 | 38 | #define ICS932S401_FS_MASK 0x07 |
39 | #define ICS932S401_REG_VENDOR_REV 0x07 | 39 | #define ICS932S401_REG_VENDOR_REV 0x07 |
@@ -58,7 +58,7 @@ static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END }; | |||
58 | #define ICS932S401_REG_SRC_SPREAD1 0x11 | 58 | #define ICS932S401_REG_SRC_SPREAD1 0x11 |
59 | #define ICS932S401_REG_SRC_SPREAD2 0x12 | 59 | #define ICS932S401_REG_SRC_SPREAD2 0x12 |
60 | #define ICS932S401_REG_CPU_DIVISOR 0x13 | 60 | #define ICS932S401_REG_CPU_DIVISOR 0x13 |
61 | #define ICS932S401_CPU_DIVISOR_SHIFT 4 | 61 | #define ICS932S401_CPU_DIVISOR_SHIFT 4 |
62 | #define ICS932S401_REG_PCISRC_DIVISOR 0x14 | 62 | #define ICS932S401_REG_PCISRC_DIVISOR 0x14 |
63 | #define ICS932S401_SRC_DIVISOR_MASK 0x0F | 63 | #define ICS932S401_SRC_DIVISOR_MASK 0x0F |
64 | #define ICS932S401_PCI_DIVISOR_SHIFT 4 | 64 | #define ICS932S401_PCI_DIVISOR_SHIFT 4 |