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authorArnd Bergmann <arnd@arndb.de>2018-03-09 10:20:26 -0500
committerArnd Bergmann <arnd@arndb.de>2018-03-26 09:56:39 -0400
commit10a27a29de9d20825d07e3bbd4187eb292a1d0df (patch)
tree05912f8843f71387ee8d78ea49bd3775af87937c
parentdabad54949930844d237af4b55c14eaff829c888 (diff)
pcmcia: remove m32r drivers
The m32r architecture is getting removed, so these drivers are no longer needed. Acked-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--drivers/pcmcia/Kconfig19
-rw-r--r--drivers/pcmcia/Makefile2
-rw-r--r--drivers/pcmcia/m32r_cfc.c786
-rw-r--r--drivers/pcmcia/m32r_cfc.h88
-rw-r--r--drivers/pcmcia/m32r_pcc.c763
-rw-r--r--drivers/pcmcia/m32r_pcc.h66
6 files changed, 0 insertions, 1724 deletions
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index d3c378b4db6c..49540d13dea4 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -232,25 +232,6 @@ config PCMCIA_PROBE
232 bool 232 bool
233 default y if ISA && !ARCH_SA1100 && !PARISC 233 default y if ISA && !ARCH_SA1100 && !PARISC
234 234
235config M32R_PCC
236 bool "M32R PCMCIA I/F"
237 depends on M32R && CHIP_M32700 && PCMCIA
238 help
239 Say Y here to use the M32R PCMCIA controller.
240
241config M32R_CFC
242 bool "M32R CF I/F Controller"
243 depends on M32R && (PLAT_USRV || PLAT_M32700UT || PLAT_MAPPI2 || PLAT_MAPPI3 || PLAT_OPSPUT)
244 help
245 Say Y here to use the M32R CompactFlash controller.
246
247config M32R_CFC_NUM
248 int "M32R CF I/F number"
249 depends on M32R_CFC
250 default "1" if PLAT_USRV || PLAT_M32700UT || PLAT_MAPPI2 || PLAT_MAPPI3 || PLAT_OPSPUT
251 help
252 Set the number of M32R CF slots.
253
254config PCMCIA_VRC4171 235config PCMCIA_VRC4171
255 tristate "NEC VRC4171 Card Controllers support" 236 tristate "NEC VRC4171 Card Controllers support"
256 depends on CPU_VR41XX && ISA && PCMCIA 237 depends on CPU_VR41XX && ISA && PCMCIA
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index e7dae16b9a43..ca361266d055 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -28,8 +28,6 @@ obj-$(CONFIG_PCMCIA_SOC_COMMON) += soc_common.o
28obj-$(CONFIG_PCMCIA_SA11XX_BASE) += sa11xx_base.o 28obj-$(CONFIG_PCMCIA_SA11XX_BASE) += sa11xx_base.o
29obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o 29obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
30obj-$(CONFIG_PCMCIA_SA1111) += sa1111_cs.o 30obj-$(CONFIG_PCMCIA_SA1111) += sa1111_cs.o
31obj-$(CONFIG_M32R_PCC) += m32r_pcc.o
32obj-$(CONFIG_M32R_CFC) += m32r_cfc.o
33obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o 31obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o
34obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o 32obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o
35obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o 33obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o
diff --git a/drivers/pcmcia/m32r_cfc.c b/drivers/pcmcia/m32r_cfc.c
deleted file mode 100644
index 9a4940e56e2f..000000000000
--- a/drivers/pcmcia/m32r_cfc.c
+++ /dev/null
@@ -1,786 +0,0 @@
1/*
2 * drivers/pcmcia/m32r_cfc.c
3 *
4 * Device driver for the CFC functionality of M32R.
5 *
6 * Copyright (c) 2001, 2002, 2003, 2004
7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/fcntl.h>
15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/timer.h>
19#include <linux/ioport.h>
20#include <linux/delay.h>
21#include <linux/workqueue.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/bitops.h>
25#include <asm/irq.h>
26#include <asm/io.h>
27
28#include <pcmcia/ss.h>
29
30#undef MAX_IO_WIN /* FIXME */
31#define MAX_IO_WIN 1
32#undef MAX_WIN /* FIXME */
33#define MAX_WIN 1
34
35#include "m32r_cfc.h"
36
37/* Poll status interval -- 0 means default to interrupt */
38static int poll_interval = 0;
39
40typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
41
42typedef struct pcc_socket {
43 u_short type, flags;
44 struct pcmcia_socket socket;
45 unsigned int number;
46 unsigned int ioaddr;
47 u_long mapaddr;
48 u_long base; /* PCC register base */
49 u_char cs_irq1, cs_irq2, intr;
50 pccard_io_map io_map[MAX_IO_WIN];
51 pccard_mem_map mem_map[MAX_WIN];
52 u_char io_win;
53 u_char mem_win;
54 pcc_as_t current_space;
55 u_char last_iodbex;
56#ifdef CONFIG_PROC_FS
57 struct proc_dir_entry *proc;
58#endif
59} pcc_socket_t;
60
61static int pcc_sockets = 0;
62static pcc_socket_t socket[M32R_MAX_PCC] = {
63 { 0, }, /* ... */
64};
65
66/*====================================================================*/
67
68static unsigned int pcc_get(u_short, unsigned int);
69static void pcc_set(u_short, unsigned int , unsigned int );
70
71static DEFINE_SPINLOCK(pcc_lock);
72
73#if !defined(CONFIG_PLAT_USRV)
74static inline u_long pcc_port2addr(unsigned long port, int size) {
75 u_long addr = 0;
76 u_long odd;
77
78 if (size == 1) { /* byte access */
79 odd = (port&1) << 11;
80 port -= port & 1;
81 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
82 } else if (size == 2)
83 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
84
85 return addr;
86}
87#else /* CONFIG_PLAT_USRV */
88static inline u_long pcc_port2addr(unsigned long port, int size) {
89 u_long odd;
90 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
91
92 if (size == 1) { /* byte access */
93 odd = port & 1;
94 port -= odd;
95 odd <<= 11;
96 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
97 } else if (size == 2) /* word access */
98 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
99
100 return addr;
101}
102#endif /* CONFIG_PLAT_USRV */
103
104void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
105 size_t nmemb, int flag)
106{
107 u_long addr;
108 unsigned char *bp = (unsigned char *)buf;
109 unsigned long flags;
110
111 pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
112 "size=%u, nmemb=%d, flag=%d\n",
113 sock, port, buf, size, nmemb, flag);
114
115 addr = pcc_port2addr(port, 1);
116 if (!addr) {
117 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
118 return;
119 }
120 pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
121
122 spin_lock_irqsave(&pcc_lock, flags);
123 /* read Byte */
124 while (nmemb--)
125 *bp++ = readb(addr);
126 spin_unlock_irqrestore(&pcc_lock, flags);
127}
128
129void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
130 size_t nmemb, int flag)
131{
132 u_long addr;
133 unsigned short *bp = (unsigned short *)buf;
134 unsigned long flags;
135
136 pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
137 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
138 sock, port, buf, size, nmemb, flag);
139
140 if (size != 2)
141 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
142 port);
143 if (size == 9)
144 printk("m32r_cfc: ioread_word :insw \n");
145
146 addr = pcc_port2addr(port, 2);
147 if (!addr) {
148 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
149 return;
150 }
151 pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
152
153 spin_lock_irqsave(&pcc_lock, flags);
154 /* read Word */
155 while (nmemb--)
156 *bp++ = readw(addr);
157 spin_unlock_irqrestore(&pcc_lock, flags);
158}
159
160void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
161 size_t nmemb, int flag)
162{
163 u_long addr;
164 unsigned char *bp = (unsigned char *)buf;
165 unsigned long flags;
166
167 pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
168 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
169 sock, port, buf, size, nmemb, flag);
170
171 /* write Byte */
172 addr = pcc_port2addr(port, 1);
173 if (!addr) {
174 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
175 return;
176 }
177 pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
178
179 spin_lock_irqsave(&pcc_lock, flags);
180 while (nmemb--)
181 writeb(*bp++, addr);
182 spin_unlock_irqrestore(&pcc_lock, flags);
183}
184
185void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
186 size_t nmemb, int flag)
187{
188 u_long addr;
189 unsigned short *bp = (unsigned short *)buf;
190 unsigned long flags;
191
192 pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
193 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
194 sock, port, buf, size, nmemb, flag);
195
196 if(size != 2)
197 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
198 size, port);
199 if(size == 9)
200 printk("m32r_cfc: iowrite_word :outsw \n");
201
202 addr = pcc_port2addr(port, 2);
203 if (!addr) {
204 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
205 return;
206 }
207#if 1
208 if (addr & 1) {
209 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
210 addr);
211 return;
212 }
213#endif
214 pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
215
216 spin_lock_irqsave(&pcc_lock, flags);
217 while (nmemb--)
218 writew(*bp++, addr);
219 spin_unlock_irqrestore(&pcc_lock, flags);
220}
221
222/*====================================================================*/
223
224#define IS_REGISTERED 0x2000
225#define IS_ALIVE 0x8000
226
227typedef struct pcc_t {
228 char *name;
229 u_short flags;
230} pcc_t;
231
232static pcc_t pcc[] = {
233#if !defined(CONFIG_PLAT_USRV)
234 { "m32r_cfc", 0 }, { "", 0 },
235#else /* CONFIG_PLAT_USRV */
236 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
237 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
238#endif /* CONFIG_PLAT_USRV */
239};
240
241static irqreturn_t pcc_interrupt(int, void *);
242
243/*====================================================================*/
244
245static struct timer_list poll_timer;
246
247static unsigned int pcc_get(u_short sock, unsigned int reg)
248{
249 unsigned int val = inw(reg);
250 pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
251 return val;
252}
253
254
255static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
256{
257 outw(data, reg);
258 pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
259}
260
261/*======================================================================
262
263 See if a card is present, powered up, in IO mode, and already
264 bound to a (non PC Card) Linux driver. We leave these alone.
265
266 We make an exception for cards that seem to be serial devices.
267
268======================================================================*/
269
270static int __init is_alive(u_short sock)
271{
272 unsigned int stat;
273
274 pr_debug("m32r_cfc: is_alive:\n");
275
276 printk("CF: ");
277 stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
278 if (!stat)
279 printk("No ");
280 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
281 pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
282
283 return 0;
284}
285
286static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
287 unsigned int ioaddr)
288{
289 pcc_socket_t *t = &socket[pcc_sockets];
290
291 pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
292 "mapaddr=%#lx, ioaddr=%08x\n",
293 base, irq, mapaddr, ioaddr);
294
295 /* add sockets */
296 t->ioaddr = ioaddr;
297 t->mapaddr = mapaddr;
298#if !defined(CONFIG_PLAT_USRV)
299 t->base = 0;
300 t->flags = 0;
301 t->cs_irq1 = irq; // insert irq
302 t->cs_irq2 = irq + 1; // eject irq
303#else /* CONFIG_PLAT_USRV */
304 t->base = base;
305 t->flags = 0;
306 t->cs_irq1 = 0; // insert irq
307 t->cs_irq2 = 0; // eject irq
308#endif /* CONFIG_PLAT_USRV */
309
310 if (is_alive(pcc_sockets))
311 t->flags |= IS_ALIVE;
312
313 /* add pcc */
314#if !defined(CONFIG_PLAT_USRV)
315 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
316#else /* CONFIG_PLAT_USRV */
317 {
318 unsigned int reg_base;
319
320 reg_base = (unsigned int)PLD_CFRSTCR;
321 reg_base |= pcc_sockets << 8;
322 request_region(reg_base, 0x20, "m32r_cfc");
323 }
324#endif /* CONFIG_PLAT_USRV */
325 printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
326 printk("pcc at 0x%08lx\n", t->base);
327
328 /* Update socket interrupt information, capabilities */
329 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
330 t->socket.map_size = M32R_PCC_MAPSIZE;
331 t->socket.io_offset = ioaddr; /* use for io access offset */
332 t->socket.irq_mask = 0;
333#if !defined(CONFIG_PLAT_USRV)
334 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
335#else /* CONFIG_PLAT_USRV */
336 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
337#endif /* CONFIG_PLAT_USRV */
338
339#ifndef CONFIG_PLAT_USRV
340 /* insert interrupt */
341 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
342#ifndef CONFIG_PLAT_MAPPI3
343 /* eject interrupt */
344 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
345#endif
346 pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n");
347 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
348#endif /* CONFIG_PLAT_USRV */
349#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
350 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
351#endif
352 pcc_sockets++;
353
354 return;
355}
356
357
358/*====================================================================*/
359
360static irqreturn_t pcc_interrupt(int irq, void *dev)
361{
362 int i;
363 u_int events = 0;
364 int handled = 0;
365
366 pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
367 for (i = 0; i < pcc_sockets; i++) {
368 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
369 continue;
370
371 handled = 1;
372 pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
373 i, irq);
374 events |= SS_DETECT; /* insert or eject */
375 if (events)
376 pcmcia_parse_events(&socket[i].socket, events);
377 }
378 pr_debug("m32r_cfc: pcc_interrupt: done\n");
379
380 return IRQ_RETVAL(handled);
381} /* pcc_interrupt */
382
383static void pcc_interrupt_wrapper(struct timer_list *unused)
384{
385 pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n");
386 pcc_interrupt(0, NULL);
387 poll_timer.expires = jiffies + poll_interval;
388 add_timer(&poll_timer);
389}
390
391/*====================================================================*/
392
393static int _pcc_get_status(u_short sock, u_int *value)
394{
395 u_int status;
396
397 pr_debug("m32r_cfc: _pcc_get_status:\n");
398 status = pcc_get(sock, (unsigned int)PLD_CFSTS);
399 *value = (status) ? SS_DETECT : 0;
400 pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
401
402#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
403 if ( status ) {
404 /* enable CF power */
405 status = inw((unsigned int)PLD_CPCR);
406 if (!(status & PLD_CPCR_CF)) {
407 pr_debug("m32r_cfc: _pcc_get_status: "
408 "power on (CPCR=0x%08x)\n", status);
409 status |= PLD_CPCR_CF;
410 outw(status, (unsigned int)PLD_CPCR);
411 udelay(100);
412 }
413 *value |= SS_POWERON;
414
415 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
416 udelay(100);
417
418 *value |= SS_READY; /* always ready */
419 *value |= SS_3VCARD;
420 } else {
421 /* disable CF power */
422 status = inw((unsigned int)PLD_CPCR);
423 status &= ~PLD_CPCR_CF;
424 outw(status, (unsigned int)PLD_CPCR);
425 udelay(100);
426 pr_debug("m32r_cfc: _pcc_get_status: "
427 "power off (CPCR=0x%08x)\n", status);
428 }
429#elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
430 if ( status ) {
431 status = pcc_get(sock, (unsigned int)PLD_CPCR);
432 if (status == 0) { /* power off */
433 pcc_set(sock, (unsigned int)PLD_CPCR, 1);
434 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
435 udelay(50);
436 }
437 *value |= SS_POWERON;
438
439 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
440 udelay(50);
441 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
442 udelay(25); /* for IDE reset */
443 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
444 mdelay(2); /* for IDE reset */
445
446 *value |= SS_READY;
447 *value |= SS_3VCARD;
448 } else {
449 /* disable CF power */
450 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
451 udelay(100);
452 pr_debug("m32r_cfc: _pcc_get_status: "
453 "power off (CPCR=0x%08x)\n", status);
454 }
455#else
456#error no platform configuration
457#endif
458 pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
459 sock, *value);
460 return 0;
461} /* _get_status */
462
463/*====================================================================*/
464
465static int _pcc_set_socket(u_short sock, socket_state_t *state)
466{
467 pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
468 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
469 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
470
471#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
472 if (state->Vcc) {
473 if ((state->Vcc != 50) && (state->Vcc != 33))
474 return -EINVAL;
475 /* accept 5V and 3.3V */
476 }
477#endif
478 if (state->flags & SS_RESET) {
479 pr_debug(":RESET\n");
480 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
481 }else{
482 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
483 }
484 if (state->flags & SS_OUTPUT_ENA){
485 pr_debug(":OUTPUT_ENA\n");
486 /* bit clear */
487 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
488 } else {
489 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
490 }
491
492 if(state->flags & SS_IOCARD){
493 pr_debug(":IOCARD");
494 }
495 if (state->flags & SS_PWR_AUTO) {
496 pr_debug(":PWR_AUTO");
497 }
498 if (state->csc_mask & SS_DETECT)
499 pr_debug(":csc-SS_DETECT");
500 if (state->flags & SS_IOCARD) {
501 if (state->csc_mask & SS_STSCHG)
502 pr_debug(":STSCHG");
503 } else {
504 if (state->csc_mask & SS_BATDEAD)
505 pr_debug(":BATDEAD");
506 if (state->csc_mask & SS_BATWARN)
507 pr_debug(":BATWARN");
508 if (state->csc_mask & SS_READY)
509 pr_debug(":READY");
510 }
511 pr_debug("\n");
512 return 0;
513} /* _set_socket */
514
515/*====================================================================*/
516
517static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
518{
519 u_char map;
520
521 pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
522 "%#llx-%#llx)\n", sock, io->map, io->flags,
523 io->speed, (unsigned long long)io->start,
524 (unsigned long long)io->stop);
525 map = io->map;
526
527 return 0;
528} /* _set_io_map */
529
530/*====================================================================*/
531
532static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
533{
534
535 u_char map = mem->map;
536 u_long addr;
537 pcc_socket_t *t = &socket[sock];
538
539 pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
540 "%#llx, %#x)\n", sock, map, mem->flags,
541 mem->speed, (unsigned long long)mem->static_start,
542 mem->card_start);
543
544 /*
545 * sanity check
546 */
547 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
548 return -EINVAL;
549 }
550
551 /*
552 * de-activate
553 */
554 if ((mem->flags & MAP_ACTIVE) == 0) {
555 t->current_space = as_none;
556 return 0;
557 }
558
559 /*
560 * Set mode
561 */
562 if (mem->flags & MAP_ATTRIB) {
563 t->current_space = as_attr;
564 } else {
565 t->current_space = as_comm;
566 }
567
568 /*
569 * Set address
570 */
571 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
572 mem->static_start = addr + mem->card_start;
573
574 return 0;
575
576} /* _set_mem_map */
577
578#if 0 /* driver model ordering issue */
579/*======================================================================
580
581 Routines for accessing socket information and register dumps via
582 /proc/bus/pccard/...
583
584======================================================================*/
585
586static ssize_t show_info(struct class_device *class_dev, char *buf)
587{
588 pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
589 socket.dev);
590
591 return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
592 pcc[s->type].name, s->base);
593}
594
595static ssize_t show_exca(struct class_device *class_dev, char *buf)
596{
597 /* FIXME */
598
599 return 0;
600}
601
602static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
603static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
604#endif
605
606/*====================================================================*/
607
608/* this is horribly ugly... proper locking needs to be done here at
609 * some time... */
610#define LOCKED(x) do { \
611 int retval; \
612 unsigned long flags; \
613 spin_lock_irqsave(&pcc_lock, flags); \
614 retval = x; \
615 spin_unlock_irqrestore(&pcc_lock, flags); \
616 return retval; \
617} while (0)
618
619
620static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
621{
622 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
623
624 if (socket[sock].flags & IS_ALIVE) {
625 dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock);
626 *value = 0;
627 return -EINVAL;
628 }
629 dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock);
630 LOCKED(_pcc_get_status(sock, value));
631}
632
633static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
634{
635 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
636
637 if (socket[sock].flags & IS_ALIVE) {
638 dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock);
639 return -EINVAL;
640 }
641 dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock);
642 LOCKED(_pcc_set_socket(sock, state));
643}
644
645static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
646{
647 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
648
649 if (socket[sock].flags & IS_ALIVE) {
650 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock);
651 return -EINVAL;
652 }
653 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock);
654 LOCKED(_pcc_set_io_map(sock, io));
655}
656
657static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
658{
659 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
660
661 if (socket[sock].flags & IS_ALIVE) {
662 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
663 return -EINVAL;
664 }
665 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock);
666 LOCKED(_pcc_set_mem_map(sock, mem));
667}
668
669static int pcc_init(struct pcmcia_socket *s)
670{
671 dev_dbg(&s->dev, "pcc_init()\n");
672 return 0;
673}
674
675static struct pccard_operations pcc_operations = {
676 .init = pcc_init,
677 .get_status = pcc_get_status,
678 .set_socket = pcc_set_socket,
679 .set_io_map = pcc_set_io_map,
680 .set_mem_map = pcc_set_mem_map,
681};
682
683
684/*====================================================================*/
685
686static struct platform_driver pcc_driver = {
687 .driver = {
688 .name = "cfc",
689 },
690};
691
692static struct platform_device pcc_device = {
693 .name = "cfc",
694 .id = 0,
695};
696
697/*====================================================================*/
698
699static int __init init_m32r_pcc(void)
700{
701 int i, ret;
702
703 ret = platform_driver_register(&pcc_driver);
704 if (ret)
705 return ret;
706
707 ret = platform_device_register(&pcc_device);
708 if (ret){
709 platform_driver_unregister(&pcc_driver);
710 return ret;
711 }
712
713#if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
714 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
715 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
716#endif
717
718 pcc_sockets = 0;
719
720#if !defined(CONFIG_PLAT_USRV)
721 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
722 CFC_IOPORT_BASE);
723#else /* CONFIG_PLAT_USRV */
724 {
725 ulong base, mapaddr;
726 unsigned int ioaddr;
727
728 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
729 base = (ulong)PLD_CFRSTCR;
730 base = base | (i << 8);
731 ioaddr = (i + 1) << 12;
732 mapaddr = CFC_ATTR_MAPBASE | (i << 20);
733 add_pcc_socket(base, 0, mapaddr, ioaddr);
734 }
735 }
736#endif /* CONFIG_PLAT_USRV */
737
738 if (pcc_sockets == 0) {
739 printk("socket is not found.\n");
740 platform_device_unregister(&pcc_device);
741 platform_driver_unregister(&pcc_driver);
742 return -ENODEV;
743 }
744
745 /* Set up interrupt handler(s) */
746
747 for (i = 0 ; i < pcc_sockets ; i++) {
748 socket[i].socket.dev.parent = &pcc_device.dev;
749 socket[i].socket.ops = &pcc_operations;
750 socket[i].socket.resource_ops = &pccard_static_ops;
751 socket[i].socket.owner = THIS_MODULE;
752 socket[i].number = i;
753 ret = pcmcia_register_socket(&socket[i].socket);
754 if (!ret)
755 socket[i].flags |= IS_REGISTERED;
756 }
757
758 /* Finally, schedule a polling interrupt */
759 if (poll_interval != 0) {
760 timer_setup(&poll_timer, pcc_interrupt_wrapper, 0);
761 poll_timer.expires = jiffies + poll_interval;
762 add_timer(&poll_timer);
763 }
764
765 return 0;
766} /* init_m32r_pcc */
767
768static void __exit exit_m32r_pcc(void)
769{
770 int i;
771
772 for (i = 0; i < pcc_sockets; i++)
773 if (socket[i].flags & IS_REGISTERED)
774 pcmcia_unregister_socket(&socket[i].socket);
775
776 platform_device_unregister(&pcc_device);
777 if (poll_interval != 0)
778 del_timer_sync(&poll_timer);
779
780 platform_driver_unregister(&pcc_driver);
781} /* exit_m32r_pcc */
782
783module_init(init_m32r_pcc);
784module_exit(exit_m32r_pcc);
785MODULE_LICENSE("Dual MPL/GPL");
786/*====================================================================*/
diff --git a/drivers/pcmcia/m32r_cfc.h b/drivers/pcmcia/m32r_cfc.h
deleted file mode 100644
index 05fec98617d0..000000000000
--- a/drivers/pcmcia/m32r_cfc.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2001 by Hiroyuki Kondo
4 */
5
6#if !defined(CONFIG_M32R_CFC_NUM)
7#define M32R_MAX_PCC 2
8#else
9#define M32R_MAX_PCC CONFIG_M32R_CFC_NUM
10#endif
11
12/*
13 * M32R PC Card Controller
14 */
15#define M32R_PCC0_BASE 0x00ef7000
16#define M32R_PCC1_BASE 0x00ef7020
17
18/*
19 * Register offsets
20 */
21#define PCCR 0x00
22#define PCADR 0x04
23#define PCMOD 0x08
24#define PCIRC 0x0c
25#define PCCSIGCR 0x10
26#define PCATCR 0x14
27
28/*
29 * PCCR
30 */
31#define PCCR_PCEN (1UL<<(31-31))
32
33/*
34 * PCIRC
35 */
36#define PCIRC_BWERR (1UL<<(31-7))
37#define PCIRC_CDIN1 (1UL<<(31-14))
38#define PCIRC_CDIN2 (1UL<<(31-15))
39#define PCIRC_BEIEN (1UL<<(31-23))
40#define PCIRC_CIIEN (1UL<<(31-30))
41#define PCIRC_COIEN (1UL<<(31-31))
42
43/*
44 * PCCSIGCR
45 */
46#define PCCSIGCR_SEN (1UL<<(31-3))
47#define PCCSIGCR_VEN (1UL<<(31-7))
48#define PCCSIGCR_CRST (1UL<<(31-15))
49#define PCCSIGCR_COCR (1UL<<(31-31))
50
51/*
52 *
53 */
54#define PCMOD_AS_ATTRIB (1UL<<(31-19))
55#define PCMOD_AS_IO (1UL<<(31-18))
56
57#define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */
58
59#define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */
60
61/*
62 * M32R PCC Map addr
63 */
64
65#define M32R_PCC0_MAPBASE 0x14000000
66#define M32R_PCC1_MAPBASE 0x16000000
67
68#define M32R_PCC_MAPMAX 0x02000000
69
70#define M32R_PCC_MAPSIZE 0x00001000 /* XXX */
71#define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1))
72
73#define CFC_IOPORT_BASE 0x1000
74
75#if defined(CONFIG_PLAT_MAPPI3)
76#define CFC_ATTR_MAPBASE 0x14014000
77#define CFC_IO_MAPBASE_BYTE 0xb4012000
78#define CFC_IO_MAPBASE_WORD 0xb4002000
79#elif !defined(CONFIG_PLAT_USRV)
80#define CFC_ATTR_MAPBASE 0x0c014000
81#define CFC_IO_MAPBASE_BYTE 0xac012000
82#define CFC_IO_MAPBASE_WORD 0xac002000
83#else
84#define CFC_ATTR_MAPBASE 0x04014000
85#define CFC_IO_MAPBASE_BYTE 0xa4012000
86#define CFC_IO_MAPBASE_WORD 0xa4002000
87#endif /* CONFIG_PLAT_USRV */
88
diff --git a/drivers/pcmcia/m32r_pcc.c b/drivers/pcmcia/m32r_pcc.c
deleted file mode 100644
index c2239a7e383a..000000000000
--- a/drivers/pcmcia/m32r_pcc.c
+++ /dev/null
@@ -1,763 +0,0 @@
1/*
2 * drivers/pcmcia/m32r_pcc.c
3 *
4 * Device driver for the PCMCIA functionality of M32R.
5 *
6 * Copyright (c) 2001, 2002, 2003, 2004
7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/fcntl.h>
15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/timer.h>
19#include <linux/ioport.h>
20#include <linux/delay.h>
21#include <linux/workqueue.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/bitops.h>
25#include <asm/irq.h>
26#include <asm/io.h>
27#include <asm/addrspace.h>
28
29#include <pcmcia/ss.h>
30
31/* XXX: should be moved into asm/irq.h */
32#define PCC0_IRQ 24
33#define PCC1_IRQ 25
34
35#include "m32r_pcc.h"
36
37#define CHAOS_PCC_DEBUG
38#ifdef CHAOS_PCC_DEBUG
39 static volatile u_short dummy_readbuf;
40#endif
41
42#define PCC_DEBUG_DBEX
43
44
45/* Poll status interval -- 0 means default to interrupt */
46static int poll_interval = 0;
47
48typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
49
50typedef struct pcc_socket {
51 u_short type, flags;
52 struct pcmcia_socket socket;
53 unsigned int number;
54 unsigned int ioaddr;
55 u_long mapaddr;
56 u_long base; /* PCC register base */
57 u_char cs_irq, intr;
58 pccard_io_map io_map[MAX_IO_WIN];
59 pccard_mem_map mem_map[MAX_WIN];
60 u_char io_win;
61 u_char mem_win;
62 pcc_as_t current_space;
63 u_char last_iodbex;
64#ifdef CHAOS_PCC_DEBUG
65 u_char last_iosize;
66#endif
67#ifdef CONFIG_PROC_FS
68 struct proc_dir_entry *proc;
69#endif
70} pcc_socket_t;
71
72static int pcc_sockets = 0;
73static pcc_socket_t socket[M32R_MAX_PCC] = {
74 { 0, }, /* ... */
75};
76
77/*====================================================================*/
78
79static unsigned int pcc_get(u_short, unsigned int);
80static void pcc_set(u_short, unsigned int , unsigned int );
81
82static DEFINE_SPINLOCK(pcc_lock);
83
84void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
85{
86 u_long addr;
87 u_long flags;
88 int need_ex;
89#ifdef PCC_DEBUG_DBEX
90 int _dbex;
91#endif
92 pcc_socket_t *t = &socket[sock];
93#ifdef CHAOS_PCC_DEBUG
94 int map_changed = 0;
95#endif
96
97 /* Need lock ? */
98 spin_lock_irqsave(&pcc_lock, flags);
99
100 /*
101 * Check if need dbex
102 */
103 need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
104#ifdef PCC_DEBUG_DBEX
105 _dbex = need_ex;
106 need_ex = 0;
107#endif
108
109 /*
110 * calculate access address
111 */
112 addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */
113
114 /*
115 * Check current mapping
116 */
117 if (t->current_space != as_io || t->last_iodbex != need_ex) {
118
119 u_long cbsz;
120
121 /*
122 * Disable first
123 */
124 pcc_set(sock, PCCR, 0);
125
126 /*
127 * Set mode and io address
128 */
129 cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
130 pcc_set(sock, PCMOD, PCMOD_AS_IO | cbsz | need_ex);
131 pcc_set(sock, PCADR, addr & 0x1ff00000);
132
133 /*
134 * Enable and read it
135 */
136 pcc_set(sock, PCCR, 1);
137
138#ifdef CHAOS_PCC_DEBUG
139#if 0
140 map_changed = (t->current_space == as_attr && size == 2); /* XXX */
141#else
142 map_changed = 1;
143#endif
144#endif
145 t->current_space = as_io;
146 }
147
148 /*
149 * access to IO space
150 */
151 if (size == 1) {
152 /* Byte */
153 unsigned char *bp = (unsigned char *)buf;
154
155#ifdef CHAOS_DEBUG
156 if (map_changed) {
157 dummy_readbuf = readb(addr);
158 }
159#endif
160 if (wr) {
161 /* write Byte */
162 while (nmemb--) {
163 writeb(*bp++, addr);
164 }
165 } else {
166 /* read Byte */
167 while (nmemb--) {
168 *bp++ = readb(addr);
169 }
170 }
171 } else {
172 /* Word */
173 unsigned short *bp = (unsigned short *)buf;
174
175#ifdef CHAOS_PCC_DEBUG
176 if (map_changed) {
177 dummy_readbuf = readw(addr);
178 }
179#endif
180 if (wr) {
181 /* write Word */
182 while (nmemb--) {
183#ifdef PCC_DEBUG_DBEX
184 if (_dbex) {
185 unsigned char *cp = (unsigned char *)bp;
186 unsigned short tmp;
187 tmp = cp[1] << 8 | cp[0];
188 writew(tmp, addr);
189 bp++;
190 } else
191#endif
192 writew(*bp++, addr);
193 }
194 } else {
195 /* read Word */
196 while (nmemb--) {
197#ifdef PCC_DEBUG_DBEX
198 if (_dbex) {
199 unsigned char *cp = (unsigned char *)bp;
200 unsigned short tmp;
201 tmp = readw(addr);
202 cp[0] = tmp & 0xff;
203 cp[1] = (tmp >> 8) & 0xff;
204 bp++;
205 } else
206#endif
207 *bp++ = readw(addr);
208 }
209 }
210 }
211
212#if 1
213 /* addr is no longer used */
214 if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
215 printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
216 port, size * 8);
217 pcc_set(sock, PCIRC, addr);
218 }
219#endif
220 /*
221 * save state
222 */
223 t->last_iosize = size;
224 t->last_iodbex = need_ex;
225
226 /* Need lock ? */
227
228 spin_unlock_irqrestore(&pcc_lock,flags);
229
230 return;
231}
232
233void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
234 pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
235}
236
237void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
238 pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
239}
240
241/*====================================================================*/
242
243#define IS_REGISTERED 0x2000
244#define IS_ALIVE 0x8000
245
246typedef struct pcc_t {
247 char *name;
248 u_short flags;
249} pcc_t;
250
251static pcc_t pcc[] = {
252 { "xnux2", 0 }, { "xnux2", 0 },
253};
254
255static irqreturn_t pcc_interrupt(int, void *);
256
257/*====================================================================*/
258
259static struct timer_list poll_timer;
260
261static unsigned int pcc_get(u_short sock, unsigned int reg)
262{
263 return inl(socket[sock].base + reg);
264}
265
266
267static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
268{
269 outl(data, socket[sock].base + reg);
270}
271
272/*======================================================================
273
274 See if a card is present, powered up, in IO mode, and already
275 bound to a (non PC Card) Linux driver. We leave these alone.
276
277 We make an exception for cards that seem to be serial devices.
278
279======================================================================*/
280
281static int __init is_alive(u_short sock)
282{
283 unsigned int stat;
284 unsigned int f;
285
286 stat = pcc_get(sock, PCIRC);
287 f = (stat & (PCIRC_CDIN1 | PCIRC_CDIN2)) >> 16;
288 if(!f){
289 printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
290 return 0;
291 }
292 if(f!=3)
293 printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
294 else
295 printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
296 return 0;
297}
298
299static int add_pcc_socket(ulong base, int irq, ulong mapaddr,
300 unsigned int ioaddr)
301{
302 pcc_socket_t *t = &socket[pcc_sockets];
303 int err;
304
305 /* add sockets */
306 t->ioaddr = ioaddr;
307 t->mapaddr = mapaddr;
308 t->base = base;
309#ifdef CHAOS_PCC_DEBUG
310 t->flags = MAP_16BIT;
311#else
312 t->flags = 0;
313#endif
314 if (is_alive(pcc_sockets))
315 t->flags |= IS_ALIVE;
316
317 /* add pcc */
318 if (t->base > 0) {
319 request_region(t->base, 0x20, "m32r-pcc");
320 }
321
322 printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
323 printk("pcc at 0x%08lx\n", t->base);
324
325 /* Update socket interrupt information, capabilities */
326 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
327 t->socket.map_size = M32R_PCC_MAPSIZE;
328 t->socket.io_offset = ioaddr; /* use for io access offset */
329 t->socket.irq_mask = 0;
330 t->socket.pci_irq = 2 + pcc_sockets; /* XXX */
331
332 err = request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);
333 if (err) {
334 if (t->base > 0)
335 release_region(t->base, 0x20);
336 return err;
337 }
338
339 pcc_sockets++;
340
341 return 0;
342}
343
344
345/*====================================================================*/
346
347static irqreturn_t pcc_interrupt(int irq, void *dev)
348{
349 int i, j, irc;
350 u_int events, active;
351 int handled = 0;
352
353 pr_debug("m32r_pcc: pcc_interrupt(%d)\n", irq);
354
355 for (j = 0; j < 20; j++) {
356 active = 0;
357 for (i = 0; i < pcc_sockets; i++) {
358 if ((socket[i].cs_irq != irq) &&
359 (socket[i].socket.pci_irq != irq))
360 continue;
361 handled = 1;
362 irc = pcc_get(i, PCIRC);
363 irc >>=16;
364 pr_debug("m32r_pcc: interrupt: socket %d pcirc 0x%02x ",
365 i, irc);
366 if (!irc)
367 continue;
368
369 events = (irc) ? SS_DETECT : 0;
370 events |= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
371 pr_debug("m32r_pcc: event 0x%02x\n", events);
372
373 if (events)
374 pcmcia_parse_events(&socket[i].socket, events);
375
376 active |= events;
377 active = 0;
378 }
379 if (!active) break;
380 }
381 if (j == 20)
382 printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");
383
384 pr_debug("m32r_pcc: interrupt done\n");
385
386 return IRQ_RETVAL(handled);
387} /* pcc_interrupt */
388
389static void pcc_interrupt_wrapper(struct timer_list *unused)
390{
391 pcc_interrupt(0, NULL);
392 poll_timer.expires = jiffies + poll_interval;
393 add_timer(&poll_timer);
394}
395
396/*====================================================================*/
397
398static int _pcc_get_status(u_short sock, u_int *value)
399{
400 u_int status;
401
402 status = pcc_get(sock,PCIRC);
403 *value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
404 ? SS_DETECT : 0;
405
406 status = pcc_get(sock,PCCR);
407
408#if 0
409 *value |= (status & PCCR_PCEN) ? SS_READY : 0;
410#else
411 *value |= SS_READY; /* XXX: always */
412#endif
413
414 status = pcc_get(sock,PCCSIGCR);
415 *value |= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;
416
417 pr_debug("m32r_pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
418 return 0;
419} /* _get_status */
420
421/*====================================================================*/
422
423static int _pcc_set_socket(u_short sock, socket_state_t *state)
424{
425 u_long reg = 0;
426
427 pr_debug("m32r_pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
428 "io_irq %d, csc_mask %#2.2x)", sock, state->flags,
429 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
430
431 if (state->Vcc) {
432 /*
433 * 5V only
434 */
435 if (state->Vcc == 50) {
436 reg |= PCCSIGCR_VEN;
437 } else {
438 return -EINVAL;
439 }
440 }
441
442 if (state->flags & SS_RESET) {
443 pr_debug("m32r_pcc: :RESET\n");
444 reg |= PCCSIGCR_CRST;
445 }
446 if (state->flags & SS_OUTPUT_ENA){
447 pr_debug("m32r_pcc: :OUTPUT_ENA\n");
448 /* bit clear */
449 } else {
450 reg |= PCCSIGCR_SEN;
451 }
452
453 pcc_set(sock,PCCSIGCR,reg);
454
455 if(state->flags & SS_IOCARD){
456 pr_debug("m32r_pcc: :IOCARD");
457 }
458 if (state->flags & SS_PWR_AUTO) {
459 pr_debug("m32r_pcc: :PWR_AUTO");
460 }
461 if (state->csc_mask & SS_DETECT)
462 pr_debug("m32r_pcc: :csc-SS_DETECT");
463 if (state->flags & SS_IOCARD) {
464 if (state->csc_mask & SS_STSCHG)
465 pr_debug("m32r_pcc: :STSCHG");
466 } else {
467 if (state->csc_mask & SS_BATDEAD)
468 pr_debug("m32r_pcc: :BATDEAD");
469 if (state->csc_mask & SS_BATWARN)
470 pr_debug("m32r_pcc: :BATWARN");
471 if (state->csc_mask & SS_READY)
472 pr_debug("m32r_pcc: :READY");
473 }
474 pr_debug("m32r_pcc: \n");
475 return 0;
476} /* _set_socket */
477
478/*====================================================================*/
479
480static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
481{
482 u_char map;
483
484 pr_debug("m32r_pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
485 "%#llx-%#llx)\n", sock, io->map, io->flags,
486 io->speed, (unsigned long long)io->start,
487 (unsigned long long)io->stop);
488 map = io->map;
489
490 return 0;
491} /* _set_io_map */
492
493/*====================================================================*/
494
495static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
496{
497
498 u_char map = mem->map;
499 u_long mode;
500 u_long addr;
501 pcc_socket_t *t = &socket[sock];
502#ifdef CHAOS_PCC_DEBUG
503#if 0
504 pcc_as_t last = t->current_space;
505#endif
506#endif
507
508 pr_debug("m32r_pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
509 "%#llx, %#x)\n", sock, map, mem->flags,
510 mem->speed, (unsigned long long)mem->static_start,
511 mem->card_start);
512
513 /*
514 * sanity check
515 */
516 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
517 return -EINVAL;
518 }
519
520 /*
521 * de-activate
522 */
523 if ((mem->flags & MAP_ACTIVE) == 0) {
524 t->current_space = as_none;
525 return 0;
526 }
527
528 /*
529 * Disable first
530 */
531 pcc_set(sock, PCCR, 0);
532
533 /*
534 * Set mode
535 */
536 if (mem->flags & MAP_ATTRIB) {
537 mode = PCMOD_AS_ATTRIB | PCMOD_CBSZ;
538 t->current_space = as_attr;
539 } else {
540 mode = 0; /* common memory */
541 t->current_space = as_comm;
542 }
543 pcc_set(sock, PCMOD, mode);
544
545 /*
546 * Set address
547 */
548 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
549 pcc_set(sock, PCADR, addr);
550
551 mem->static_start = addr + mem->card_start;
552
553 /*
554 * Enable again
555 */
556 pcc_set(sock, PCCR, 1);
557
558#ifdef CHAOS_PCC_DEBUG
559#if 0
560 if (last != as_attr) {
561#else
562 if (1) {
563#endif
564 dummy_readbuf = *(u_char *)(addr + KSEG1);
565 }
566#endif
567
568 return 0;
569
570} /* _set_mem_map */
571
572#if 0 /* driver model ordering issue */
573/*======================================================================
574
575 Routines for accessing socket information and register dumps via
576 /proc/bus/pccard/...
577
578======================================================================*/
579
580static ssize_t show_info(struct class_device *class_dev, char *buf)
581{
582 pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
583 socket.dev);
584
585 return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
586 pcc[s->type].name, s->base);
587}
588
589static ssize_t show_exca(struct class_device *class_dev, char *buf)
590{
591 /* FIXME */
592
593 return 0;
594}
595
596static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
597static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
598#endif
599
600/*====================================================================*/
601
602/* this is horribly ugly... proper locking needs to be done here at
603 * some time... */
604#define LOCKED(x) do { \
605 int retval; \
606 unsigned long flags; \
607 spin_lock_irqsave(&pcc_lock, flags); \
608 retval = x; \
609 spin_unlock_irqrestore(&pcc_lock, flags); \
610 return retval; \
611} while (0)
612
613
614static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
615{
616 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
617
618 if (socket[sock].flags & IS_ALIVE) {
619 *value = 0;
620 return -EINVAL;
621 }
622 LOCKED(_pcc_get_status(sock, value));
623}
624
625static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
626{
627 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
628
629 if (socket[sock].flags & IS_ALIVE)
630 return -EINVAL;
631
632 LOCKED(_pcc_set_socket(sock, state));
633}
634
635static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
636{
637 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
638
639 if (socket[sock].flags & IS_ALIVE)
640 return -EINVAL;
641 LOCKED(_pcc_set_io_map(sock, io));
642}
643
644static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
645{
646 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
647
648 if (socket[sock].flags & IS_ALIVE)
649 return -EINVAL;
650 LOCKED(_pcc_set_mem_map(sock, mem));
651}
652
653static int pcc_init(struct pcmcia_socket *s)
654{
655 pr_debug("m32r_pcc: init call\n");
656 return 0;
657}
658
659static struct pccard_operations pcc_operations = {
660 .init = pcc_init,
661 .get_status = pcc_get_status,
662 .set_socket = pcc_set_socket,
663 .set_io_map = pcc_set_io_map,
664 .set_mem_map = pcc_set_mem_map,
665};
666
667/*====================================================================*/
668
669static struct platform_driver pcc_driver = {
670 .driver = {
671 .name = "pcc",
672 },
673};
674
675static struct platform_device pcc_device = {
676 .name = "pcc",
677 .id = 0,
678};
679
680/*====================================================================*/
681
682static int __init init_m32r_pcc(void)
683{
684 int i, ret;
685
686 ret = platform_driver_register(&pcc_driver);
687 if (ret)
688 return ret;
689
690 ret = platform_device_register(&pcc_device);
691 if (ret)
692 goto unreg_driv;
693
694 printk(KERN_INFO "m32r PCC probe:\n");
695
696 pcc_sockets = 0;
697
698 ret = add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE,
699 0x1000);
700 if (ret)
701 goto unreg_dev;
702
703#ifdef CONFIG_M32RPCC_SLOT2
704 ret = add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE,
705 0x2000);
706 if (ret)
707 goto unreg_dev;
708#endif
709
710 if (pcc_sockets == 0) {
711 printk("socket is not found.\n");
712 ret = -ENODEV;
713 goto unreg_dev;
714 }
715
716 /* Set up interrupt handler(s) */
717
718 for (i = 0 ; i < pcc_sockets ; i++) {
719 socket[i].socket.dev.parent = &pcc_device.dev;
720 socket[i].socket.ops = &pcc_operations;
721 socket[i].socket.resource_ops = &pccard_static_ops;
722 socket[i].socket.owner = THIS_MODULE;
723 socket[i].number = i;
724 ret = pcmcia_register_socket(&socket[i].socket);
725 if (!ret)
726 socket[i].flags |= IS_REGISTERED;
727 }
728
729 /* Finally, schedule a polling interrupt */
730 if (poll_interval != 0) {
731 timer_setup(&poll_timer, pcc_interrupt_wrapper, 0);
732 poll_timer.expires = jiffies + poll_interval;
733 add_timer(&poll_timer);
734 }
735
736 return 0;
737
738unreg_dev:
739 platform_device_unregister(&pcc_device);
740unreg_driv:
741 platform_driver_unregister(&pcc_driver);
742 return ret;
743} /* init_m32r_pcc */
744
745static void __exit exit_m32r_pcc(void)
746{
747 int i;
748
749 for (i = 0; i < pcc_sockets; i++)
750 if (socket[i].flags & IS_REGISTERED)
751 pcmcia_unregister_socket(&socket[i].socket);
752
753 platform_device_unregister(&pcc_device);
754 if (poll_interval != 0)
755 del_timer_sync(&poll_timer);
756
757 platform_driver_unregister(&pcc_driver);
758} /* exit_m32r_pcc */
759
760module_init(init_m32r_pcc);
761module_exit(exit_m32r_pcc);
762MODULE_LICENSE("Dual MPL/GPL");
763/*====================================================================*/
diff --git a/drivers/pcmcia/m32r_pcc.h b/drivers/pcmcia/m32r_pcc.h
deleted file mode 100644
index d99ad3864ff3..000000000000
--- a/drivers/pcmcia/m32r_pcc.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2001 by Hiroyuki Kondo
4 */
5
6#define M32R_MAX_PCC 2
7
8/*
9 * M32R PC Card Controller
10 */
11#define M32R_PCC0_BASE 0x00ef7000
12#define M32R_PCC1_BASE 0x00ef7020
13
14/*
15 * Register offsets
16 */
17#define PCCR 0x00
18#define PCADR 0x04
19#define PCMOD 0x08
20#define PCIRC 0x0c
21#define PCCSIGCR 0x10
22#define PCATCR 0x14
23
24/*
25 * PCCR
26 */
27#define PCCR_PCEN (1UL<<(31-31))
28
29/*
30 * PCIRC
31 */
32#define PCIRC_BWERR (1UL<<(31-7))
33#define PCIRC_CDIN1 (1UL<<(31-14))
34#define PCIRC_CDIN2 (1UL<<(31-15))
35#define PCIRC_BEIEN (1UL<<(31-23))
36#define PCIRC_CIIEN (1UL<<(31-30))
37#define PCIRC_COIEN (1UL<<(31-31))
38
39/*
40 * PCCSIGCR
41 */
42#define PCCSIGCR_SEN (1UL<<(31-3))
43#define PCCSIGCR_VEN (1UL<<(31-7))
44#define PCCSIGCR_CRST (1UL<<(31-15))
45#define PCCSIGCR_COCR (1UL<<(31-31))
46
47/*
48 *
49 */
50#define PCMOD_AS_ATTRIB (1UL<<(31-19))
51#define PCMOD_AS_IO (1UL<<(31-18))
52
53#define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */
54
55#define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */
56
57/*
58 * M32R PCC Map addr
59 */
60#define M32R_PCC0_MAPBASE 0x14000000
61#define M32R_PCC1_MAPBASE 0x16000000
62
63#define M32R_PCC_MAPMAX 0x02000000
64
65#define M32R_PCC_MAPSIZE 0x00001000 /* XXX */
66#define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1))
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 17:58:01 -0500