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authorHeiko Stuebner <heiko@sntech.de>2013-06-02 17:09:41 -0400
committerHeiko Stuebner <heiko@sntech.de>2013-06-21 03:21:02 -0400
commitd63dc0514d56e108cc96e334ca26b538263e52a2 (patch)
tree73bbb24b8ac743d2bf61126d64f086ba8c2d0f7d
parent38bd6892abbf7d60b1e9ff7f1a2b8019b552eed3 (diff)
arm: add basic support for Rockchip RK3066a boards
This adds a generic devicetree board file and a dtsi for boards based on the RK3066a SoCs from Rockchip. Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based). Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi390
-rw-r--r--arch/arm/mach-rockchip/Kconfig16
-rw-r--r--arch/arm/mach-rockchip/Makefile1
-rw-r--r--arch/arm/mach-rockchip/rockchip.c52
6 files changed, 462 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993cee512..94d3491ae40a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -981,6 +981,8 @@ source "arch/arm/mach-mmp/Kconfig"
981 981
982source "arch/arm/mach-realview/Kconfig" 982source "arch/arm/mach-realview/Kconfig"
983 983
984source "arch/arm/mach-rockchip/Kconfig"
985
984source "arch/arm/mach-sa1100/Kconfig" 986source "arch/arm/mach-sa1100/Kconfig"
985 987
986source "arch/arm/plat-samsung/Kconfig" 988source "arch/arm/plat-samsung/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1ba358ba16b8..126313fcc594 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
171machine-$(CONFIG_ARCH_PRIMA2) += prima2 171machine-$(CONFIG_ARCH_PRIMA2) += prima2
172machine-$(CONFIG_ARCH_PXA) += pxa 172machine-$(CONFIG_ARCH_PXA) += pxa
173machine-$(CONFIG_ARCH_REALVIEW) += realview 173machine-$(CONFIG_ARCH_REALVIEW) += realview
174machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
174machine-$(CONFIG_ARCH_RPC) += rpc 175machine-$(CONFIG_ARCH_RPC) += rpc
175machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx 176machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
176machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx 177machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
new file mode 100644
index 000000000000..56bfac93d3f6
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -0,0 +1,390 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/pinctrl/rockchip.h>
20#include "skeleton.dtsi"
21#include "rk3066a-clocks.dtsi"
22
23/ {
24 compatible = "rockchip,rk3066a";
25 interrupt-parent = <&gic>;
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
35 reg = <0x0>;
36 };
37 cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
41 reg = <0x1>;
42 };
43 };
44
45 soc {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
49 ranges;
50
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
56 <0x1013c100 0x0100>;
57 };
58
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 };
65
66 local-timer@1013c600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0x1013c600 0x20>;
69 interrupts = <GIC_PPI 13 0x304>;
70 clocks = <&dummy150m>;
71 };
72
73 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates1 0>, <&clk_gates7 7>;
78 clock-names = "timer", "pclk";
79 };
80
81 timer@2003a000 {
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&clk_gates1 1>, <&clk_gates7 8>;
86 clock-names = "timer", "pclk";
87 };
88
89 timer@2000e000 {
90 compatible = "snps,dw-apb-timer-osc";
91 reg = <0x2000e000 0x100>;
92 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clk_gates1 2>, <&clk_gates7 9>;
94 clock-names = "timer", "pclk";
95 };
96
97 pinctrl@20008000 {
98 compatible = "rockchip,rk3066a-pinctrl";
99 reg = <0x20008000 0x150>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 gpio0: gpio0@20034000 {
105 compatible = "rockchip,gpio-bank";
106 reg = <0x20034000 0x100>;
107 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&clk_gates8 9>;
109
110 gpio-controller;
111 #gpio-cells = <2>;
112
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
117 gpio1: gpio1@2003c000 {
118 compatible = "rockchip,gpio-bank";
119 reg = <0x2003c000 0x100>;
120 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clk_gates8 10>;
122
123 gpio-controller;
124 #gpio-cells = <2>;
125
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 };
129
130 gpio2: gpio2@2003e000 {
131 compatible = "rockchip,gpio-bank";
132 reg = <0x2003e000 0x100>;
133 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clk_gates8 11>;
135
136 gpio-controller;
137 #gpio-cells = <2>;
138
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 };
142
143 gpio3: gpio3@20080000 {
144 compatible = "rockchip,gpio-bank";
145 reg = <0x20080000 0x100>;
146 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clk_gates8 12>;
148
149 gpio-controller;
150 #gpio-cells = <2>;
151
152 interrupt-controller;
153 #interrupt-cells = <2>;
154 };
155
156 gpio4: gpio4@20084000 {
157 compatible = "rockchip,gpio-bank";
158 reg = <0x20084000 0x100>;
159 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk_gates8 13>;
161
162 gpio-controller;
163 #gpio-cells = <2>;
164
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 };
168
169 gpio6: gpio6@2000a000 {
170 compatible = "rockchip,gpio-bank";
171 reg = <0x2000a000 0x100>;
172 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&clk_gates8 15>;
174
175 gpio-controller;
176 #gpio-cells = <2>;
177
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 };
181
182 pcfg_pull_default: pcfg_pull_default {
183 bias-pull-pin-default;
184 };
185
186 pcfg_pull_none: pcfg_pull_none {
187 bias-disable;
188 };
189
190 uart0 {
191 uart0_xfer: uart0-xfer {
192 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
193 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
194 rockchip,config = <&pcfg_pull_default>;
195 };
196
197 uart0_cts: uart0-cts {
198 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
199 rockchip,config = <&pcfg_pull_default>;
200 };
201
202 uart0_rts: uart0-rts {
203 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
204 rockchip,config = <&pcfg_pull_default>;
205 };
206 };
207
208 uart1 {
209 uart1_xfer: uart1-xfer {
210 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
211 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
212 rockchip,config = <&pcfg_pull_default>;
213 };
214
215 uart1_cts: uart1-cts {
216 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
217 rockchip,config = <&pcfg_pull_default>;
218 };
219
220 uart1_rts: uart1-rts {
221 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
222 rockchip,config = <&pcfg_pull_default>;
223 };
224 };
225
226 uart2 {
227 uart2_xfer: uart2-xfer {
228 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
229 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
230 rockchip,config = <&pcfg_pull_default>;
231 };
232 /* no rts / cts for uart2 */
233 };
234
235 uart3 {
236 uart3_xfer: uart3-xfer {
237 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
238 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
239 rockchip,config = <&pcfg_pull_default>;
240 };
241
242 uart3_cts: uart3-cts {
243 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
244 rockchip,config = <&pcfg_pull_default>;
245 };
246
247 uart3_rts: uart3-rts {
248 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
249 rockchip,config = <&pcfg_pull_default>;
250 };
251 };
252
253 sd0 {
254 sd0_clk: sd0-clk {
255 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
256 rockchip,config = <&pcfg_pull_default>;
257 };
258
259 sd0_cmd: sd0-cmd {
260 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
261 rockchip,config = <&pcfg_pull_default>;
262 };
263
264 sd0_cd: sd0-cd {
265 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
266 rockchip,config = <&pcfg_pull_default>;
267 };
268
269 sd0_wp: sd0-wp {
270 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
271 rockchip,config = <&pcfg_pull_default>;
272 };
273
274 sd0_bus1: sd0-bus-width1 {
275 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
276 rockchip,config = <&pcfg_pull_default>;
277 };
278
279 sd0_bus4: sd0-bus-width4 {
280 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
281 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
282 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
283 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
284 rockchip,config = <&pcfg_pull_default>;
285 };
286 };
287
288 sd1 {
289 sd1_clk: sd1-clk {
290 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
291 rockchip,config = <&pcfg_pull_default>;
292 };
293
294 sd1_cmd: sd1-cmd {
295 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
296 rockchip,config = <&pcfg_pull_default>;
297 };
298
299 sd1_cd: sd1-cd {
300 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
301 rockchip,config = <&pcfg_pull_default>;
302 };
303
304 sd1_wp: sd1-wp {
305 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
306 rockchip,config = <&pcfg_pull_default>;
307 };
308
309 sd1_bus1: sd1-bus-width1 {
310 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
311 rockchip,config = <&pcfg_pull_default>;
312 };
313
314 sd1_bus4: sd1-bus-width4 {
315 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
316 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
317 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
318 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
319 rockchip,config = <&pcfg_pull_default>;
320 };
321 };
322 };
323
324 uart0: serial@10124000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x10124000 0x400>;
327 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
328 reg-shift = <2>;
329 reg-io-width = <1>;
330 clocks = <&clk_gates1 8>;
331 status = "disabled";
332 };
333
334 uart1: serial@10126000 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0x10126000 0x400>;
337 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <1>;
340 clocks = <&clk_gates1 10>;
341 status = "disabled";
342 };
343
344 uart2: serial@20064000 {
345 compatible = "snps,dw-apb-uart";
346 reg = <0x20064000 0x400>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 reg-shift = <2>;
349 reg-io-width = <1>;
350 clocks = <&clk_gates1 12>;
351 status = "disabled";
352 };
353
354 uart3: serial@20068000 {
355 compatible = "snps,dw-apb-uart";
356 reg = <0x20068000 0x400>;
357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>;
359 reg-io-width = <1>;
360 clocks = <&clk_gates1 14>;
361 status = "disabled";
362 };
363
364 dwmmc@10214000 {
365 compatible = "rockchip,rk2928-dw-mshc";
366 reg = <0x10214000 0x1000>;
367 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370
371 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
372 clock-names = "biu", "ciu";
373
374 status = "disabled";
375 };
376
377 dwmmc@10218000 {
378 compatible = "rockchip,rk2928-dw-mshc";
379 reg = <0x10218000 0x1000>;
380 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
385 clock-names = "biu", "ciu";
386
387 status = "disabled";
388 };
389 };
390};
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 000000000000..25ee12b21f01
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,16 @@
1config ARCH_ROCKCHIP
2 bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
3 select PINCTRL
4 select PINCTRL_ROCKCHIP
5 select ARCH_REQUIRE_GPIOLIB
6 select ARM_GIC
7 select CACHE_L2X0
8 select HAVE_ARM_TWD if LOCAL_TIMERS
9 select HAVE_SMP
10 select LOCAL_TIMERS if SMP
11 select COMMON_CLK
12 select GENERIC_CLOCKEVENTS
13 select DW_APB_TIMER_OF
14 help
15 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
16 containing the RK2928, RK30xx and RK31xx series.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 000000000000..1547d4fc920a
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
new file mode 100644
index 000000000000..724d2d81f976
--- /dev/null
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -0,0 +1,52 @@
1/*
2 * Device Tree support for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/of_platform.h>
21#include <linux/irqchip.h>
22#include <linux/dw_apb_timer.h>
23#include <linux/clk-provider.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/hardware/cache-l2x0.h>
27
28static void __init rockchip_timer_init(void)
29{
30 of_clk_init(NULL);
31 clocksource_of_init();
32}
33
34static void __init rockchip_dt_init(void)
35{
36 l2x0_of_init(0, ~0UL);
37 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
38}
39
40static const char * const rockchip_board_dt_compat[] = {
41 "rockchip,rk2928",
42 "rockchip,rk3066a",
43 "rockchip,rk3066b",
44 "rockchip,rk3188",
45 NULL,
46};
47
48DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
49 .init_machine = rockchip_dt_init,
50 .init_time = rockchip_timer_init,
51 .dt_compat = rockchip_board_dt_compat,
52MACHINE_END
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