diff options
author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-08-10 05:51:08 -0400 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-16 17:41:15 -0400 |
commit | a35bcf7c7f28623271c733dd4d41f24a79237754 (patch) | |
tree | 67f585915965aded11d56fcd3663a9979d4fd1fe | |
parent | 73a5e67efa0822ce1773718d7ae24c80bf816c1e (diff) |
dt-bindings: reset: Add binding constants for Actions Semi S900 RMU
Add device tree binding constants for Actions Semi S900 SoC Reset
Management Unit (RMU).
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r-- | include/dt-bindings/reset/actions,s900-reset.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h new file mode 100644 index 000000000000..42c19d02e43b --- /dev/null +++ b/include/dt-bindings/reset/actions,s900-reset.h | |||
@@ -0,0 +1,65 @@ | |||
1 | // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) | ||
2 | // | ||
3 | // Device Tree binding constants for Actions Semi S900 Reset Management Unit | ||
4 | // | ||
5 | // Copyright (c) 2018 Linaro Ltd. | ||
6 | |||
7 | #ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H | ||
8 | #define __DT_BINDINGS_ACTIONS_S900_RESET_H | ||
9 | |||
10 | #define RESET_CHIPID 0 | ||
11 | #define RESET_CPU_SCNT 1 | ||
12 | #define RESET_SRAMI 2 | ||
13 | #define RESET_DDR_CTL_PHY 3 | ||
14 | #define RESET_DMAC 4 | ||
15 | #define RESET_GPIO 5 | ||
16 | #define RESET_BISP_AXI 6 | ||
17 | #define RESET_CSI0 7 | ||
18 | #define RESET_CSI1 8 | ||
19 | #define RESET_DE 9 | ||
20 | #define RESET_DSI 10 | ||
21 | #define RESET_GPU3D_PA 11 | ||
22 | #define RESET_GPU3D_PB 12 | ||
23 | #define RESET_HDE 13 | ||
24 | #define RESET_I2C0 14 | ||
25 | #define RESET_I2C1 15 | ||
26 | #define RESET_I2C2 16 | ||
27 | #define RESET_I2C3 17 | ||
28 | #define RESET_I2C4 18 | ||
29 | #define RESET_I2C5 19 | ||
30 | #define RESET_IMX 20 | ||
31 | #define RESET_NANDC0 21 | ||
32 | #define RESET_NANDC1 22 | ||
33 | #define RESET_SD0 23 | ||
34 | #define RESET_SD1 24 | ||
35 | #define RESET_SD2 25 | ||
36 | #define RESET_SD3 26 | ||
37 | #define RESET_SPI0 27 | ||
38 | #define RESET_SPI1 28 | ||
39 | #define RESET_SPI2 29 | ||
40 | #define RESET_SPI3 30 | ||
41 | #define RESET_UART0 31 | ||
42 | #define RESET_UART1 32 | ||
43 | #define RESET_UART2 33 | ||
44 | #define RESET_UART3 34 | ||
45 | #define RESET_UART4 35 | ||
46 | #define RESET_UART5 36 | ||
47 | #define RESET_UART6 37 | ||
48 | #define RESET_HDMI 38 | ||
49 | #define RESET_LVDS 39 | ||
50 | #define RESET_EDP 40 | ||
51 | #define RESET_USB2HUB 41 | ||
52 | #define RESET_USB2HSIC 42 | ||
53 | #define RESET_USB3 43 | ||
54 | #define RESET_PCM1 44 | ||
55 | #define RESET_AUDIO 45 | ||
56 | #define RESET_PCM0 46 | ||
57 | #define RESET_SE 47 | ||
58 | #define RESET_GIC 48 | ||
59 | #define RESET_DDR_CTL_PHY_AXI 49 | ||
60 | #define RESET_CMU_DDR 50 | ||
61 | #define RESET_DMM 51 | ||
62 | #define RESET_HDCP2TX 52 | ||
63 | #define RESET_ETHERNET 53 | ||
64 | |||
65 | #endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ | ||