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authorTomer Tayar <Tomer.Tayar@cavium.com>2017-12-27 12:30:05 -0500
committerDavid S. Miller <davem@davemloft.net>2018-01-02 13:59:15 -0500
commita2e7699eb50fda6450036129f7c0642b3349b879 (patch)
treef9e01f366f2cc2c1fa2b3e1a4b80be03c951cccf
parentbbb6189df4077cde8592cd2f804bb1122067dd32 (diff)
qed*: Refactoring and rearranging FW API with no functional impact
This patch refactors and reorders the FW API files in preparation of upgrading the code to support new FW. - Make use of the BIT macro in appropriate places. - Whitespace changes to align values and code blocks. - Comments are updated (spelling mistakes, removed if not clear). - Group together code blocks which are related or deal with similar matters. Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com> Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com> Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/infiniband/hw/qedr/qedr_hsi_rdma.h108
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed.h2
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_cxt.c6
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_debug.c102
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_dev.c4
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_hsi.h7675
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c142
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_int.c6
-rw-r--r--drivers/net/ethernet/qlogic/qed/qed_iscsi.c36
-rw-r--r--drivers/scsi/qedi/qedi_fw_api.c77
-rw-r--r--include/linux/qed/common_hsi.h1165
-rw-r--r--include/linux/qed/eth_common.h363
-rw-r--r--include/linux/qed/fcoe_common.h874
-rw-r--r--include/linux/qed/iscsi_common.h1462
-rw-r--r--include/linux/qed/iwarp_common.h17
-rw-r--r--include/linux/qed/qed_if.h20
-rw-r--r--include/linux/qed/rdma_common.h25
-rw-r--r--include/linux/qed/roce_common.h15
-rw-r--r--include/linux/qed/storage_common.h45
-rw-r--r--include/linux/qed/tcp_common.h129
20 files changed, 6357 insertions, 5916 deletions
diff --git a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
index b7587f10e7de..b67a89b39553 100644
--- a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
+++ b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
@@ -180,12 +180,12 @@ struct rdma_pwm_val32_data {
180 __le16 icid; 180 __le16 icid;
181 u8 agg_flags; 181 u8 agg_flags;
182 u8 params; 182 u8 params;
183#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 183#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3
184#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 184#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0
185#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 185#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
186#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 186#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2
187#define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x1F 187#define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x1F
188#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 3 188#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 3
189 __le32 value; 189 __le32 value;
190}; 190};
191 191
@@ -478,23 +478,23 @@ struct rdma_sq_fmr_wqe {
478 __le16 dif_app_tag_mask; 478 __le16 dif_app_tag_mask;
479 __le16 dif_runt_crc_value; 479 __le16 dif_runt_crc_value;
480 __le16 dif_flags; 480 __le16 dif_flags;
481#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK 0x1 481#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_MASK 0x1
482#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT 0 482#define RDMA_SQ_FMR_WQE_DIF_IO_DIRECTION_FLG_SHIFT 0
483#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK 0x1 483#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_MASK 0x1
484#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT 1 484#define RDMA_SQ_FMR_WQE_DIF_BLOCK_SIZE_SHIFT 1
485#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK 0x1 485#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_MASK 0x1
486#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT 2 486#define RDMA_SQ_FMR_WQE_DIF_RUNT_VALID_FLG_SHIFT 2
487#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK 0x1 487#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_MASK 0x1
488#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT 3 488#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_CRC_GUARD_SHIFT 3
489#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK 0x1 489#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_MASK 0x1
490#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT 4 490#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_REF_TAG_SHIFT 4
491#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK 0x1 491#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_MASK 0x1
492#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT 5 492#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT 5
493#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK 0x1 493#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK 0x1
494#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT 6 494#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT 6
495#define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0x1FF 495#define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0x1FF
496#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 7 496#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 7
497 __le32 Reserved5; 497 __le32 reserved5;
498}; 498};
499 499
500/* First element (16 bytes) of fmr wqe */ 500/* First element (16 bytes) of fmr wqe */
@@ -558,23 +558,23 @@ struct rdma_sq_fmr_wqe_3rd {
558 __le16 dif_app_tag_mask; 558 __le16 dif_app_tag_mask;
559 __le16 dif_runt_crc_value; 559 __le16 dif_runt_crc_value;
560 __le16 dif_flags; 560 __le16 dif_flags;
561#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK 0x1 561#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_MASK 0x1
562#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT 0 562#define RDMA_SQ_FMR_WQE_3RD_DIF_IO_DIRECTION_FLG_SHIFT 0
563#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK 0x1 563#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_MASK 0x1
564#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT 1 564#define RDMA_SQ_FMR_WQE_3RD_DIF_BLOCK_SIZE_SHIFT 1
565#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK 0x1 565#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_MASK 0x1
566#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT 2 566#define RDMA_SQ_FMR_WQE_3RD_DIF_RUNT_VALID_FLG_SHIFT 2
567#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK 0x1 567#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_MASK 0x1
568#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT 3 568#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_CRC_GUARD_SHIFT 3
569#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK 0x1 569#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_MASK 0x1
570#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT 4 570#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_REF_TAG_SHIFT 4
571#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK 0x1 571#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_MASK 0x1
572#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT 5 572#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT 5
573#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK 0x1 573#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK 0x1
574#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT 6 574#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT 6
575#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0x1FF 575#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0x1FF
576#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT 7 576#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT 7
577 __le32 Reserved5; 577 __le32 reserved5;
578}; 578};
579 579
580struct rdma_sq_local_inv_wqe { 580struct rdma_sq_local_inv_wqe {
@@ -606,20 +606,20 @@ struct rdma_sq_rdma_wqe {
606 __le32 xrc_srq; 606 __le32 xrc_srq;
607 u8 req_type; 607 u8 req_type;
608 u8 flags; 608 u8 flags;
609#define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 609#define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1
610#define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 610#define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT 0
611#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 611#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1
612#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 612#define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1
613#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 613#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1
614#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 614#define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2
615#define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1 615#define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1
616#define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT 3 616#define RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT 3
617#define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 617#define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1
618#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 618#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4
619#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1 619#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1
620#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT 5 620#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT 5
621#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK 0x3 621#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK 0x3
622#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT 6 622#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT 6
623 u8 wqe_size; 623 u8 wqe_size;
624 u8 prev_wqe_size; 624 u8 prev_wqe_size;
625 struct regpair remote_va; 625 struct regpair remote_va;
diff --git a/drivers/net/ethernet/qlogic/qed/qed.h b/drivers/net/ethernet/qlogic/qed/qed.h
index 91003bc6f00b..34b3ca38318d 100644
--- a/drivers/net/ethernet/qlogic/qed/qed.h
+++ b/drivers/net/ethernet/qlogic/qed/qed.h
@@ -779,7 +779,7 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
779} 779}
780 780
781#define PURE_LB_TC 8 781#define PURE_LB_TC 8
782#define PKT_LB_TC 9 782#define PKT_LB_TC 9
783 783
784int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 784int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
785void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 785void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
index afd07ad91631..043f2cb9c471 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
@@ -109,8 +109,8 @@ struct src_ent {
109 u64 next; 109 u64 next;
110}; 110};
111 111
112#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 112#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
113#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12)) 113#define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12)
114 114
115#define CONN_CXT_SIZE(p_hwfn) \ 115#define CONN_CXT_SIZE(p_hwfn) \
116 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 116 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
@@ -2326,7 +2326,7 @@ qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn,
2326 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2326 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2327 elem = (union type1_task_context *)elem_start; 2327 elem = (union type1_task_context *)elem_start;
2328 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2328 SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2329 TDIF_TASK_CONTEXT_REFTAGMASK, 0xf); 2329 TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
2330 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2330 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2331 } 2331 }
2332 } 2332 }
diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c
index 03c3cf77aaff..0fbeaf9b518b 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_debug.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c
@@ -358,20 +358,14 @@ struct phy_defs {
358 (arr)[i] = qed_rd(dev, ptt, addr); \ 358 (arr)[i] = qed_rd(dev, ptt, addr); \
359 } while (0) 359 } while (0)
360 360
361#ifndef DWORDS_TO_BYTES
362#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD) 361#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD)
363#endif
364#ifndef BYTES_TO_DWORDS
365#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD) 362#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
366#endif
367 363
368/* extra lines include a signature line + optional latency events line */ 364/* Extra lines include a signature line + optional latency events line */
369#ifndef NUM_DBG_LINES
370#define NUM_EXTRA_DBG_LINES(block_desc) \ 365#define NUM_EXTRA_DBG_LINES(block_desc) \
371 (1 + ((block_desc)->has_latency_events ? 1 : 0)) 366 (1 + ((block_desc)->has_latency_events ? 1 : 0))
372#define NUM_DBG_LINES(block_desc) \ 367#define NUM_DBG_LINES(block_desc) \
373 ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 368 ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
374#endif
375 369
376#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2) 370#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2)
377#define RAM_LINES_TO_BYTES(lines) \ 371#define RAM_LINES_TO_BYTES(lines) \
@@ -441,23 +435,17 @@ struct phy_defs {
441 435
442#define FW_IMG_MAIN 1 436#define FW_IMG_MAIN 1
443 437
444#ifndef REG_FIFO_ELEMENT_DWORDS
445#define REG_FIFO_ELEMENT_DWORDS 2 438#define REG_FIFO_ELEMENT_DWORDS 2
446#endif
447#define REG_FIFO_DEPTH_ELEMENTS 32 439#define REG_FIFO_DEPTH_ELEMENTS 32
448#define REG_FIFO_DEPTH_DWORDS \ 440#define REG_FIFO_DEPTH_DWORDS \
449 (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS) 441 (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
450 442
451#ifndef IGU_FIFO_ELEMENT_DWORDS
452#define IGU_FIFO_ELEMENT_DWORDS 4 443#define IGU_FIFO_ELEMENT_DWORDS 4
453#endif
454#define IGU_FIFO_DEPTH_ELEMENTS 64 444#define IGU_FIFO_DEPTH_ELEMENTS 64
455#define IGU_FIFO_DEPTH_DWORDS \ 445#define IGU_FIFO_DEPTH_DWORDS \
456 (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS) 446 (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
457 447
458#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
459#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2 448#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
460#endif
461#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20 449#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
462#define PROTECTION_OVERRIDE_DEPTH_DWORDS \ 450#define PROTECTION_OVERRIDE_DEPTH_DWORDS \
463 (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \ 451 (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \
@@ -1089,6 +1077,20 @@ static struct block_defs block_xyld_defs = {
1089 true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 1077 true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
1090}; 1078};
1091 1079
1080static struct block_defs block_ptld_defs = {
1081 "ptld", {false, false}, false, 0,
1082 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1083 0, 0, 0, 0, 0,
1084 false, false, MAX_DBG_RESET_REGS, 0
1085};
1086
1087static struct block_defs block_ypld_defs = {
1088 "ypld", {false, false}, false, 0,
1089 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1090 0, 0, 0, 0, 0,
1091 false, false, MAX_DBG_RESET_REGS, 0
1092};
1093
1092static struct block_defs block_prm_defs = { 1094static struct block_defs block_prm_defs = {
1093 "prm", 1095 "prm",
1094 {true, true}, false, 0, 1096 {true, true}, false, 0,
@@ -1221,6 +1223,34 @@ static struct block_defs block_cau_defs = {
1221 true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 1223 true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
1222}; 1224};
1223 1225
1226static struct block_defs block_rgfs_defs = {
1227 "rgfs", {false, false}, false, 0,
1228 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1229 0, 0, 0, 0, 0,
1230 false, false, MAX_DBG_RESET_REGS, 0
1231};
1232
1233static struct block_defs block_rgsrc_defs = {
1234 "rgsrc", {false, false}, false, 0,
1235 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1236 0, 0, 0, 0, 0,
1237 false, false, MAX_DBG_RESET_REGS, 0
1238};
1239
1240static struct block_defs block_tgfs_defs = {
1241 "tgfs", {false, false}, false, 0,
1242 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1243 0, 0, 0, 0, 0,
1244 false, false, MAX_DBG_RESET_REGS, 0
1245};
1246
1247static struct block_defs block_tgsrc_defs = {
1248 "tgsrc", {false, false}, false, 0,
1249 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1250 0, 0, 0, 0, 0,
1251 false, false, MAX_DBG_RESET_REGS, 0
1252};
1253
1224static struct block_defs block_umac_defs = { 1254static struct block_defs block_umac_defs = {
1225 "umac", 1255 "umac",
1226 {false, true}, false, 0, 1256 {false, true}, false, 0,
@@ -1338,48 +1368,6 @@ static struct block_defs block_avs_wrap_defs = {
1338 true, false, DBG_RESET_REG_MISCS_PL_UA, 11 1368 true, false, DBG_RESET_REG_MISCS_PL_UA, 11
1339}; 1369};
1340 1370
1341static struct block_defs block_rgfs_defs = {
1342 "rgfs", {false, false}, false, 0,
1343 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1344 0, 0, 0, 0, 0,
1345 false, false, MAX_DBG_RESET_REGS, 0
1346};
1347
1348static struct block_defs block_rgsrc_defs = {
1349 "rgsrc", {false, false}, false, 0,
1350 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1351 0, 0, 0, 0, 0,
1352 false, false, MAX_DBG_RESET_REGS, 0
1353};
1354
1355static struct block_defs block_tgfs_defs = {
1356 "tgfs", {false, false}, false, 0,
1357 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1358 0, 0, 0, 0, 0,
1359 false, false, MAX_DBG_RESET_REGS, 0
1360};
1361
1362static struct block_defs block_tgsrc_defs = {
1363 "tgsrc", {false, false}, false, 0,
1364 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1365 0, 0, 0, 0, 0,
1366 false, false, MAX_DBG_RESET_REGS, 0
1367};
1368
1369static struct block_defs block_ptld_defs = {
1370 "ptld", {false, false}, false, 0,
1371 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1372 0, 0, 0, 0, 0,
1373 false, false, MAX_DBG_RESET_REGS, 0
1374};
1375
1376static struct block_defs block_ypld_defs = {
1377 "ypld", {false, false}, false, 0,
1378 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1379 0, 0, 0, 0, 0,
1380 false, false, MAX_DBG_RESET_REGS, 0
1381};
1382
1383static struct block_defs block_misc_aeu_defs = { 1371static struct block_defs block_misc_aeu_defs = {
1384 "misc_aeu", {false, false}, false, 0, 1372 "misc_aeu", {false, false}, false, 0,
1385 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1373 {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
@@ -5596,10 +5584,6 @@ struct igu_fifo_addr_data {
5596 5584
5597#define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4 5585#define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4
5598 5586
5599/********************************* Macros ************************************/
5600
5601#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
5602
5603/***************************** Constant Arrays *******************************/ 5587/***************************** Constant Arrays *******************************/
5604 5588
5605struct user_dbg_array { 5589struct user_dbg_array {
diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c
index 58a689fb04db..6d8dcbe671cb 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_dev.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c
@@ -758,7 +758,7 @@ static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
758/* This function reconfigures the QM pf on the fly. 758/* This function reconfigures the QM pf on the fly.
759 * For this purpose we: 759 * For this purpose we:
760 * 1. reconfigure the QM database 760 * 1. reconfigure the QM database
761 * 2. set new values to runtime arrat 761 * 2. set new values to runtime array
762 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 762 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
763 * 4. activate init tool in QM_PF stage 763 * 4. activate init tool in QM_PF stage
764 * 5. send an sdm_qm_cmd through rbc interface to release the QM 764 * 5. send an sdm_qm_cmd through rbc interface to release the QM
@@ -1515,7 +1515,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1515 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1515 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1516 } 1516 }
1517 1517
1518 /* Protocl Configuration */ 1518 /* Protocol Configuration */
1519 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1519 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1520 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 1520 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1521 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 1521 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
index 3427fe7049b5..302a253fbc33 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
@@ -54,7 +54,7 @@
54struct qed_hwfn; 54struct qed_hwfn;
55struct qed_ptt; 55struct qed_ptt;
56 56
57/* opcodes for the event ring */ 57/* Opcodes for the event ring */
58enum common_event_opcode { 58enum common_event_opcode {
59 COMMON_EVENT_PF_START, 59 COMMON_EVENT_PF_START,
60 COMMON_EVENT_PF_STOP, 60 COMMON_EVENT_PF_STOP,
@@ -82,6 +82,286 @@ enum common_ramrod_cmd_id {
82 MAX_COMMON_RAMROD_CMD_ID 82 MAX_COMMON_RAMROD_CMD_ID
83}; 83};
84 84
85/* How ll2 should deal with packet upon errors */
86enum core_error_handle {
87 LL2_DROP_PACKET,
88 LL2_DO_NOTHING,
89 LL2_ASSERT,
90 MAX_CORE_ERROR_HANDLE
91};
92
93/* Opcodes for the event ring */
94enum core_event_opcode {
95 CORE_EVENT_TX_QUEUE_START,
96 CORE_EVENT_TX_QUEUE_STOP,
97 CORE_EVENT_RX_QUEUE_START,
98 CORE_EVENT_RX_QUEUE_STOP,
99 CORE_EVENT_RX_QUEUE_FLUSH,
100 MAX_CORE_EVENT_OPCODE
101};
102
103/* The L4 pseudo checksum mode for Core */
104enum core_l4_pseudo_checksum_mode {
105 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
106 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
107 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
108};
109
110/* Light-L2 RX Producers in Tstorm RAM */
111struct core_ll2_port_stats {
112 struct regpair gsi_invalid_hdr;
113 struct regpair gsi_invalid_pkt_length;
114 struct regpair gsi_unsupported_pkt_typ;
115 struct regpair gsi_crcchksm_error;
116};
117
118/* Ethernet TX Per Queue Stats */
119struct core_ll2_pstorm_per_queue_stat {
120 struct regpair sent_ucast_bytes;
121 struct regpair sent_mcast_bytes;
122 struct regpair sent_bcast_bytes;
123 struct regpair sent_ucast_pkts;
124 struct regpair sent_mcast_pkts;
125 struct regpair sent_bcast_pkts;
126};
127
128/* Light-L2 RX Producers in Tstorm RAM */
129struct core_ll2_rx_prod {
130 __le16 bd_prod;
131 __le16 cqe_prod;
132 __le32 reserved;
133};
134
135struct core_ll2_tstorm_per_queue_stat {
136 struct regpair packet_too_big_discard;
137 struct regpair no_buff_discard;
138};
139
140struct core_ll2_ustorm_per_queue_stat {
141 struct regpair rcv_ucast_bytes;
142 struct regpair rcv_mcast_bytes;
143 struct regpair rcv_bcast_bytes;
144 struct regpair rcv_ucast_pkts;
145 struct regpair rcv_mcast_pkts;
146 struct regpair rcv_bcast_pkts;
147};
148
149/* Core Ramrod Command IDs (light L2) */
150enum core_ramrod_cmd_id {
151 CORE_RAMROD_UNUSED,
152 CORE_RAMROD_RX_QUEUE_START,
153 CORE_RAMROD_TX_QUEUE_START,
154 CORE_RAMROD_RX_QUEUE_STOP,
155 CORE_RAMROD_TX_QUEUE_STOP,
156 CORE_RAMROD_RX_QUEUE_FLUSH,
157 MAX_CORE_RAMROD_CMD_ID
158};
159
160/* Core RX CQE Type for Light L2 */
161enum core_roce_flavor_type {
162 CORE_ROCE,
163 CORE_RROCE,
164 MAX_CORE_ROCE_FLAVOR_TYPE
165};
166
167/* Specifies how ll2 should deal with packets errors: packet_too_big and
168 * no_buff.
169 */
170struct core_rx_action_on_error {
171 u8 error_type;
172#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
173#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
174#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
175#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
176#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
177#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
178};
179
180/* Core RX BD for Light L2 */
181struct core_rx_bd {
182 struct regpair addr;
183 __le16 reserved[4];
184};
185
186/* Core RX CM offload BD for Light L2 */
187struct core_rx_bd_with_buff_len {
188 struct regpair addr;
189 __le16 buff_length;
190 __le16 reserved[3];
191};
192
193/* Core RX CM offload BD for Light L2 */
194union core_rx_bd_union {
195 struct core_rx_bd rx_bd;
196 struct core_rx_bd_with_buff_len rx_bd_with_len;
197};
198
199/* Opaque Data for Light L2 RX CQE */
200struct core_rx_cqe_opaque_data {
201 __le32 data[2];
202};
203
204/* Core RX CQE Type for Light L2 */
205enum core_rx_cqe_type {
206 CORE_RX_CQE_ILLEGAL_TYPE,
207 CORE_RX_CQE_TYPE_REGULAR,
208 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
209 CORE_RX_CQE_TYPE_SLOW_PATH,
210 MAX_CORE_RX_CQE_TYPE
211};
212
213/* Core RX CQE for Light L2 */
214struct core_rx_fast_path_cqe {
215 u8 type;
216 u8 placement_offset;
217 struct parsing_and_err_flags parse_flags;
218 __le16 packet_length;
219 __le16 vlan;
220 struct core_rx_cqe_opaque_data opaque_data;
221 struct parsing_err_flags err_flags;
222 __le16 reserved0;
223 __le32 reserved1[3];
224};
225
226/* Core Rx CM offload CQE */
227struct core_rx_gsi_offload_cqe {
228 u8 type;
229 u8 data_length_error;
230 struct parsing_and_err_flags parse_flags;
231 __le16 data_length;
232 __le16 vlan;
233 __le32 src_mac_addrhi;
234 __le16 src_mac_addrlo;
235 __le16 qp_id;
236 __le32 gid_dst[4];
237};
238
239/* Core RX CQE for Light L2 */
240struct core_rx_slow_path_cqe {
241 u8 type;
242 u8 ramrod_cmd_id;
243 __le16 echo;
244 struct core_rx_cqe_opaque_data opaque_data;
245 __le32 reserved1[5];
246};
247
248/* Core RX CM offload BD for Light L2 */
249union core_rx_cqe_union {
250 struct core_rx_fast_path_cqe rx_cqe_fp;
251 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
252 struct core_rx_slow_path_cqe rx_cqe_sp;
253};
254
255/* Ramrod data for rx queue start ramrod */
256struct core_rx_start_ramrod_data {
257 struct regpair bd_base;
258 struct regpair cqe_pbl_addr;
259 __le16 mtu;
260 __le16 sb_id;
261 u8 sb_index;
262 u8 complete_cqe_flg;
263 u8 complete_event_flg;
264 u8 drop_ttl0_flg;
265 __le16 num_of_pbl_pages;
266 u8 inner_vlan_removal_en;
267 u8 queue_id;
268 u8 main_func_queue;
269 u8 mf_si_bcast_accept_all;
270 u8 mf_si_mcast_accept_all;
271 struct core_rx_action_on_error action_on_error;
272 u8 gsi_offload_flag;
273 u8 reserved[7];
274};
275
276/* Ramrod data for rx queue stop ramrod */
277struct core_rx_stop_ramrod_data {
278 u8 complete_cqe_flg;
279 u8 complete_event_flg;
280 u8 queue_id;
281 u8 reserved1;
282 __le16 reserved2[2];
283};
284
285/* Flags for Core TX BD */
286struct core_tx_bd_data {
287 __le16 as_bitfield;
288#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
289#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
290#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
291#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
292#define CORE_TX_BD_DATA_START_BD_MASK 0x1
293#define CORE_TX_BD_DATA_START_BD_SHIFT 2
294#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
295#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
296#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
297#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
298#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
299#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
300#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
301#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
302#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
303#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
304#define CORE_TX_BD_DATA_NBDS_MASK 0xF
305#define CORE_TX_BD_DATA_NBDS_SHIFT 8
306#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
307#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
308#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
309#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
310#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
311#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
312};
313
314/* Core TX BD for Light L2 */
315struct core_tx_bd {
316 struct regpair addr;
317 __le16 nbytes;
318 __le16 nw_vlan_or_lb_echo;
319 struct core_tx_bd_data bd_data;
320 __le16 bitfield1;
321#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
322#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
323#define CORE_TX_BD_TX_DST_MASK 0x3
324#define CORE_TX_BD_TX_DST_SHIFT 14
325};
326
327/* Light L2 TX Destination */
328enum core_tx_dest {
329 CORE_TX_DEST_NW,
330 CORE_TX_DEST_LB,
331 CORE_TX_DEST_RESERVED,
332 CORE_TX_DEST_DROP,
333 MAX_CORE_TX_DEST
334};
335
336/* Ramrod data for tx queue start ramrod */
337struct core_tx_start_ramrod_data {
338 struct regpair pbl_base_addr;
339 __le16 mtu;
340 __le16 sb_id;
341 u8 sb_index;
342 u8 stats_en;
343 u8 stats_id;
344 u8 conn_type;
345 __le16 pbl_size;
346 __le16 qm_pq_id;
347 u8 gsi_offload_flag;
348 u8 resrved[3];
349};
350
351/* Ramrod data for tx queue stop ramrod */
352struct core_tx_stop_ramrod_data {
353 __le32 reserved0[2];
354};
355
356/* Enum flag for what type of dcb data to update */
357enum dcb_dscp_update_mode {
358 DONT_UPDATE_DCB_DSCP,
359 UPDATE_DCB,
360 UPDATE_DSCP,
361 UPDATE_DCB_DSCP,
362 MAX_DCB_DSCP_UPDATE_MODE
363};
364
85/* The core storm context for the Ystorm */ 365/* The core storm context for the Ystorm */
86struct ystorm_core_conn_st_ctx { 366struct ystorm_core_conn_st_ctx {
87 __le32 reserved[4]; 367 __le32 reserved[4];
@@ -369,85 +649,85 @@ struct tstorm_core_conn_ag_ctx {
369 u8 byte0; 649 u8 byte0;
370 u8 byte1; 650 u8 byte1;
371 u8 flags0; 651 u8 flags0;
372#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 652#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
373#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 653#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
374#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 654#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
375#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 655#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
376#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 656#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
377#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 657#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
378#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 658#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
379#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 659#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
380#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 660#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
381#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 661#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
382#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 662#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
383#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 663#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
384#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 664#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
385#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 665#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
386 u8 flags1; 666 u8 flags1;
387#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 667#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
388#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 668#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
389#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 669#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
390#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 670#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
391#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 671#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
392#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 672#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
393#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 673#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
394#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 674#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
395 u8 flags2; 675 u8 flags2;
396#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 676#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
397#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 677#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
398#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 678#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
399#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 679#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
400#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 680#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
401#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 681#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
402#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 682#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
403#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 683#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
404 u8 flags3; 684 u8 flags3;
405#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 685#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
406#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 686#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
407#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 687#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
408#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 688#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
409#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 689#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
410#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 690#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
411#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 691#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
412#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 692#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
413#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 693#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
414#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 694#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
415#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 695#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
416#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 696#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
417 u8 flags4; 697 u8 flags4;
418#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 698#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
419#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 699#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
420#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 700#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
421#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 701#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
422#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 702#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
423#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 703#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
424#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 704#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
425#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 705#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
426#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 706#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
427#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 707#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
428#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 708#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
429#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 709#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
430#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 710#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
431#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 711#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
432#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 712#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
433#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 713#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
434 u8 flags5; 714 u8 flags5;
435#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 715#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
436#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 716#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
437#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 717#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
438#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 718#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
439#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 719#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
440#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 720#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
441#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 721#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
442#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 722#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
443#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 723#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
444#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 724#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
445#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 725#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
446#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 726#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
447#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 727#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
448#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 728#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
449#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 729#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
450#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 730#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
451 __le32 reg0; 731 __le32 reg0;
452 __le32 reg1; 732 __le32 reg1;
453 __le32 reg2; 733 __le32 reg2;
@@ -563,258 +843,6 @@ struct core_conn_context {
563 struct regpair ustorm_st_padding[2]; 843 struct regpair ustorm_st_padding[2];
564}; 844};
565 845
566enum core_error_handle {
567 LL2_DROP_PACKET,
568 LL2_DO_NOTHING,
569 LL2_ASSERT,
570 MAX_CORE_ERROR_HANDLE
571};
572
573enum core_event_opcode {
574 CORE_EVENT_TX_QUEUE_START,
575 CORE_EVENT_TX_QUEUE_STOP,
576 CORE_EVENT_RX_QUEUE_START,
577 CORE_EVENT_RX_QUEUE_STOP,
578 CORE_EVENT_RX_QUEUE_FLUSH,
579 MAX_CORE_EVENT_OPCODE
580};
581
582enum core_l4_pseudo_checksum_mode {
583 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
584 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
585 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
586};
587
588struct core_ll2_port_stats {
589 struct regpair gsi_invalid_hdr;
590 struct regpair gsi_invalid_pkt_length;
591 struct regpair gsi_unsupported_pkt_typ;
592 struct regpair gsi_crcchksm_error;
593};
594
595struct core_ll2_pstorm_per_queue_stat {
596 struct regpair sent_ucast_bytes;
597 struct regpair sent_mcast_bytes;
598 struct regpair sent_bcast_bytes;
599 struct regpair sent_ucast_pkts;
600 struct regpair sent_mcast_pkts;
601 struct regpair sent_bcast_pkts;
602};
603
604struct core_ll2_rx_prod {
605 __le16 bd_prod;
606 __le16 cqe_prod;
607 __le32 reserved;
608};
609
610struct core_ll2_tstorm_per_queue_stat {
611 struct regpair packet_too_big_discard;
612 struct regpair no_buff_discard;
613};
614
615struct core_ll2_ustorm_per_queue_stat {
616 struct regpair rcv_ucast_bytes;
617 struct regpair rcv_mcast_bytes;
618 struct regpair rcv_bcast_bytes;
619 struct regpair rcv_ucast_pkts;
620 struct regpair rcv_mcast_pkts;
621 struct regpair rcv_bcast_pkts;
622};
623
624enum core_ramrod_cmd_id {
625 CORE_RAMROD_UNUSED,
626 CORE_RAMROD_RX_QUEUE_START,
627 CORE_RAMROD_TX_QUEUE_START,
628 CORE_RAMROD_RX_QUEUE_STOP,
629 CORE_RAMROD_TX_QUEUE_STOP,
630 CORE_RAMROD_RX_QUEUE_FLUSH,
631 MAX_CORE_RAMROD_CMD_ID
632};
633
634enum core_roce_flavor_type {
635 CORE_ROCE,
636 CORE_RROCE,
637 MAX_CORE_ROCE_FLAVOR_TYPE
638};
639
640struct core_rx_action_on_error {
641 u8 error_type;
642#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
643#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
644#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
645#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
646#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
647#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
648};
649
650struct core_rx_bd {
651 struct regpair addr;
652 __le16 reserved[4];
653};
654
655struct core_rx_bd_with_buff_len {
656 struct regpair addr;
657 __le16 buff_length;
658 __le16 reserved[3];
659};
660
661union core_rx_bd_union {
662 struct core_rx_bd rx_bd;
663 struct core_rx_bd_with_buff_len rx_bd_with_len;
664};
665
666struct core_rx_cqe_opaque_data {
667 __le32 data[2];
668};
669
670enum core_rx_cqe_type {
671 CORE_RX_CQE_ILLIGAL_TYPE,
672 CORE_RX_CQE_TYPE_REGULAR,
673 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
674 CORE_RX_CQE_TYPE_SLOW_PATH,
675 MAX_CORE_RX_CQE_TYPE
676};
677
678struct core_rx_fast_path_cqe {
679 u8 type;
680 u8 placement_offset;
681 struct parsing_and_err_flags parse_flags;
682 __le16 packet_length;
683 __le16 vlan;
684 struct core_rx_cqe_opaque_data opaque_data;
685 struct parsing_err_flags err_flags;
686 __le16 reserved0;
687 __le32 reserved1[3];
688};
689
690struct core_rx_gsi_offload_cqe {
691 u8 type;
692 u8 data_length_error;
693 struct parsing_and_err_flags parse_flags;
694 __le16 data_length;
695 __le16 vlan;
696 __le32 src_mac_addrhi;
697 __le16 src_mac_addrlo;
698 __le16 qp_id;
699 __le32 gid_dst[4];
700};
701
702struct core_rx_slow_path_cqe {
703 u8 type;
704 u8 ramrod_cmd_id;
705 __le16 echo;
706 struct core_rx_cqe_opaque_data opaque_data;
707 __le32 reserved1[5];
708};
709
710union core_rx_cqe_union {
711 struct core_rx_fast_path_cqe rx_cqe_fp;
712 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
713 struct core_rx_slow_path_cqe rx_cqe_sp;
714};
715
716struct core_rx_start_ramrod_data {
717 struct regpair bd_base;
718 struct regpair cqe_pbl_addr;
719 __le16 mtu;
720 __le16 sb_id;
721 u8 sb_index;
722 u8 complete_cqe_flg;
723 u8 complete_event_flg;
724 u8 drop_ttl0_flg;
725 __le16 num_of_pbl_pages;
726 u8 inner_vlan_removal_en;
727 u8 queue_id;
728 u8 main_func_queue;
729 u8 mf_si_bcast_accept_all;
730 u8 mf_si_mcast_accept_all;
731 struct core_rx_action_on_error action_on_error;
732 u8 gsi_offload_flag;
733 u8 reserved[7];
734};
735
736struct core_rx_stop_ramrod_data {
737 u8 complete_cqe_flg;
738 u8 complete_event_flg;
739 u8 queue_id;
740 u8 reserved1;
741 __le16 reserved2[2];
742};
743
744struct core_tx_bd_data {
745 __le16 as_bitfield;
746#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
747#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
748#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
749#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
750#define CORE_TX_BD_DATA_START_BD_MASK 0x1
751#define CORE_TX_BD_DATA_START_BD_SHIFT 2
752#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
753#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
754#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
755#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
756#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
757#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
758#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
759#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
760#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
761#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
762#define CORE_TX_BD_DATA_NBDS_MASK 0xF
763#define CORE_TX_BD_DATA_NBDS_SHIFT 8
764#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
765#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
766#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
767#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
768#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
769#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
770};
771
772struct core_tx_bd {
773 struct regpair addr;
774 __le16 nbytes;
775 __le16 nw_vlan_or_lb_echo;
776 struct core_tx_bd_data bd_data;
777 __le16 bitfield1;
778#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
779#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
780#define CORE_TX_BD_TX_DST_MASK 0x3
781#define CORE_TX_BD_TX_DST_SHIFT 14
782};
783
784enum core_tx_dest {
785 CORE_TX_DEST_NW,
786 CORE_TX_DEST_LB,
787 CORE_TX_DEST_RESERVED,
788 CORE_TX_DEST_DROP,
789 MAX_CORE_TX_DEST
790};
791
792struct core_tx_start_ramrod_data {
793 struct regpair pbl_base_addr;
794 __le16 mtu;
795 __le16 sb_id;
796 u8 sb_index;
797 u8 stats_en;
798 u8 stats_id;
799 u8 conn_type;
800 __le16 pbl_size;
801 __le16 qm_pq_id;
802 u8 gsi_offload_flag;
803 u8 resrved[3];
804};
805
806struct core_tx_stop_ramrod_data {
807 __le32 reserved0[2];
808};
809
810enum dcb_dscp_update_mode {
811 DONT_UPDATE_DCB_DSCP,
812 UPDATE_DCB,
813 UPDATE_DSCP,
814 UPDATE_DCB_DSCP,
815 MAX_DCB_DSCP_UPDATE_MODE
816};
817
818struct eth_mstorm_per_pf_stat { 846struct eth_mstorm_per_pf_stat {
819 struct regpair gre_discard_pkts; 847 struct regpair gre_discard_pkts;
820 struct regpair vxlan_discard_pkts; 848 struct regpair vxlan_discard_pkts;
@@ -896,6 +924,49 @@ struct eth_ustorm_per_queue_stat {
896 struct regpair rcv_bcast_pkts; 924 struct regpair rcv_bcast_pkts;
897}; 925};
898 926
927/* Event Ring VF-PF Channel data */
928struct vf_pf_channel_eqe_data {
929 struct regpair msg_addr;
930};
931
932/* Event Ring malicious VF data */
933struct malicious_vf_eqe_data {
934 u8 vf_id;
935 u8 err_id;
936 __le16 reserved[3];
937};
938
939/* Event Ring initial cleanup data */
940struct initial_cleanup_eqe_data {
941 u8 vf_id;
942 u8 reserved[7];
943};
944
945/* Event Data Union */
946union event_ring_data {
947 u8 bytes[8];
948 struct vf_pf_channel_eqe_data vf_pf_channel;
949 struct iscsi_eqe_data iscsi_info;
950 union rdma_eqe_data rdma_data;
951 struct malicious_vf_eqe_data malicious_vf;
952 struct initial_cleanup_eqe_data vf_init_cleanup;
953};
954
955/* Event Ring Entry */
956struct event_ring_entry {
957 u8 protocol_id;
958 u8 opcode;
959 __le16 reserved0;
960 __le16 echo;
961 u8 fw_return_code;
962 u8 flags;
963#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
964#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
965#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
966#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
967 union event_ring_data data;
968};
969
899/* Event Ring Next Page Address */ 970/* Event Ring Next Page Address */
900struct event_ring_next_addr { 971struct event_ring_next_addr {
901 struct regpair addr; 972 struct regpair addr;
@@ -908,6 +979,7 @@ union event_ring_element {
908 struct event_ring_next_addr next_addr; 979 struct event_ring_next_addr next_addr;
909}; 980};
910 981
982/* Ports mode */
911enum fw_flow_ctrl_mode { 983enum fw_flow_ctrl_mode {
912 flow_ctrl_pause, 984 flow_ctrl_pause,
913 flow_ctrl_pfc, 985 flow_ctrl_pfc,
@@ -921,14 +993,14 @@ struct hsi_fp_ver_struct {
921}; 993};
922 994
923enum iwarp_ll2_tx_queues { 995enum iwarp_ll2_tx_queues {
924 IWARP_LL2_IN_ORDER_TX_QUEUE = 1, 996 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
925 IWARP_LL2_ALIGNED_TX_QUEUE, 997 IWARP_LL2_ALIGNED_TX_QUEUE,
926 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, 998 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
927 IWARP_LL2_ERROR, 999 IWARP_LL2_ERROR,
928 MAX_IWARP_LL2_TX_QUEUES 1000 MAX_IWARP_LL2_TX_QUEUES
929}; 1001};
930 1002
931/* Mstorm non-triggering VF zone */ 1003/* Malicious VF error ID */
932enum malicious_vf_error_id { 1004enum malicious_vf_error_id {
933 MALICIOUS_VF_NO_ERROR, 1005 MALICIOUS_VF_NO_ERROR,
934 VF_PF_CHANNEL_NOT_READY, 1006 VF_PF_CHANNEL_NOT_READY,
@@ -954,6 +1026,7 @@ enum malicious_vf_error_id {
954 MAX_MALICIOUS_VF_ERROR_ID 1026 MAX_MALICIOUS_VF_ERROR_ID
955}; 1027};
956 1028
1029/* Mstorm non-triggering VF zone */
957struct mstorm_non_trigger_vf_zone { 1030struct mstorm_non_trigger_vf_zone {
958 struct eth_mstorm_per_queue_stat eth_queue_stat; 1031 struct eth_mstorm_per_queue_stat eth_queue_stat;
959 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD]; 1032 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
@@ -962,7 +1035,6 @@ struct mstorm_non_trigger_vf_zone {
962/* Mstorm VF zone */ 1035/* Mstorm VF zone */
963struct mstorm_vf_zone { 1036struct mstorm_vf_zone {
964 struct mstorm_non_trigger_vf_zone non_trigger; 1037 struct mstorm_non_trigger_vf_zone non_trigger;
965
966}; 1038};
967 1039
968/* personality per PF */ 1040/* personality per PF */
@@ -974,7 +1046,7 @@ enum personality_type {
974 PERSONALITY_RDMA, 1046 PERSONALITY_RDMA,
975 PERSONALITY_CORE, 1047 PERSONALITY_CORE,
976 PERSONALITY_ETH, 1048 PERSONALITY_ETH,
977 PERSONALITY_RESERVED4, 1049 PERSONALITY_RESERVED,
978 MAX_PERSONALITY_TYPE 1050 MAX_PERSONALITY_TYPE
979}; 1051};
980 1052
@@ -1017,6 +1089,7 @@ struct pf_start_ramrod_data {
1017 struct hsi_fp_ver_struct hsi_fp_ver; 1089 struct hsi_fp_ver_struct hsi_fp_ver;
1018}; 1090};
1019 1091
1092/* Data for port update ramrod */
1020struct protocol_dcb_data { 1093struct protocol_dcb_data {
1021 u8 dcb_enable_flag; 1094 u8 dcb_enable_flag;
1022 u8 reserved_a; 1095 u8 reserved_a;
@@ -1026,6 +1099,7 @@ struct protocol_dcb_data {
1026 u8 reserved0; 1099 u8 reserved0;
1027}; 1100};
1028 1101
1102/* Update tunnel configuration */
1029struct pf_update_tunnel_config { 1103struct pf_update_tunnel_config {
1030 u8 update_rx_pf_clss; 1104 u8 update_rx_pf_clss;
1031 u8 update_rx_def_ucast_clss; 1105 u8 update_rx_def_ucast_clss;
@@ -1042,6 +1116,7 @@ struct pf_update_tunnel_config {
1042 __le16 reserved; 1116 __le16 reserved;
1043}; 1117};
1044 1118
1119/* Data for port update ramrod */
1045struct pf_update_ramrod_data { 1120struct pf_update_ramrod_data {
1046 u8 pf_id; 1121 u8 pf_id;
1047 u8 update_eth_dcb_data_mode; 1122 u8 update_eth_dcb_data_mode;
@@ -1079,11 +1154,13 @@ enum protocol_version_array_key {
1079 MAX_PROTOCOL_VERSION_ARRAY_KEY 1154 MAX_PROTOCOL_VERSION_ARRAY_KEY
1080}; 1155};
1081 1156
1157/* RDMA TX Stats */
1082struct rdma_sent_stats { 1158struct rdma_sent_stats {
1083 struct regpair sent_bytes; 1159 struct regpair sent_bytes;
1084 struct regpair sent_pkts; 1160 struct regpair sent_pkts;
1085}; 1161};
1086 1162
1163/* Pstorm non-triggering VF zone */
1087struct pstorm_non_trigger_vf_zone { 1164struct pstorm_non_trigger_vf_zone {
1088 struct eth_pstorm_per_queue_stat eth_queue_stat; 1165 struct eth_pstorm_per_queue_stat eth_queue_stat;
1089 struct rdma_sent_stats rdma_stats; 1166 struct rdma_sent_stats rdma_stats;
@@ -1103,11 +1180,13 @@ struct ramrod_header {
1103 __le16 echo; 1180 __le16 echo;
1104}; 1181};
1105 1182
1183/* RDMA RX Stats */
1106struct rdma_rcv_stats { 1184struct rdma_rcv_stats {
1107 struct regpair rcv_bytes; 1185 struct regpair rcv_bytes;
1108 struct regpair rcv_pkts; 1186 struct regpair rcv_pkts;
1109}; 1187};
1110 1188
1189/* Slowpath Element (SPQE) */
1111struct slow_path_element { 1190struct slow_path_element {
1112 struct ramrod_header hdr; 1191 struct ramrod_header hdr;
1113 struct regpair data_ptr; 1192 struct regpair data_ptr;
@@ -1197,6 +1276,7 @@ struct vf_stop_ramrod_data {
1197 __le32 reserved2; 1276 __le32 reserved2;
1198}; 1277};
1199 1278
1279/* VF zone size mode */
1200enum vf_zone_size_mode { 1280enum vf_zone_size_mode {
1201 VF_ZONE_SIZE_MODE_DEFAULT, 1281 VF_ZONE_SIZE_MODE_DEFAULT,
1202 VF_ZONE_SIZE_MODE_DOUBLE, 1282 VF_ZONE_SIZE_MODE_DOUBLE,
@@ -1204,6 +1284,7 @@ enum vf_zone_size_mode {
1204 MAX_VF_ZONE_SIZE_MODE 1284 MAX_VF_ZONE_SIZE_MODE
1205}; 1285};
1206 1286
1287/* Attentions status block */
1207struct atten_status_block { 1288struct atten_status_block {
1208 __le32 atten_bits; 1289 __le32 atten_bits;
1209 __le32 atten_ack; 1290 __le32 atten_ack;
@@ -1212,12 +1293,6 @@ struct atten_status_block {
1212 __le32 reserved1; 1293 __le32 reserved1;
1213}; 1294};
1214 1295
1215enum command_type_bit {
1216 IGU_COMMAND_TYPE_NOP = 0,
1217 IGU_COMMAND_TYPE_SET = 1,
1218 MAX_COMMAND_TYPE_BIT
1219};
1220
1221/* DMAE command */ 1296/* DMAE command */
1222struct dmae_cmd { 1297struct dmae_cmd {
1223 __le32 opcode; 1298 __le32 opcode;
@@ -1841,7 +1916,7 @@ struct dbg_attn_block_result {
1841 struct dbg_attn_reg_result reg_results[15]; 1916 struct dbg_attn_reg_result reg_results[15];
1842}; 1917};
1843 1918
1844/* mode header */ 1919/* Mode header */
1845struct dbg_mode_hdr { 1920struct dbg_mode_hdr {
1846 __le16 data; 1921 __le16 data;
1847#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 1922#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
@@ -1863,80 +1938,83 @@ struct dbg_attn_reg {
1863 __le32 mask_address; 1938 __le32 mask_address;
1864}; 1939};
1865 1940
1866/* attention types */ 1941/* Attention types */
1867enum dbg_attn_type { 1942enum dbg_attn_type {
1868 ATTN_TYPE_INTERRUPT, 1943 ATTN_TYPE_INTERRUPT,
1869 ATTN_TYPE_PARITY, 1944 ATTN_TYPE_PARITY,
1870 MAX_DBG_ATTN_TYPE 1945 MAX_DBG_ATTN_TYPE
1871}; 1946};
1872 1947
1948/* Debug Bus block data */
1873struct dbg_bus_block { 1949struct dbg_bus_block {
1874 u8 num_of_lines; 1950 u8 num_of_lines;
1875 u8 has_latency_events; 1951 u8 has_latency_events;
1876 __le16 lines_offset; 1952 __le16 lines_offset;
1877}; 1953};
1878 1954
1955/* Debug Bus block user data */
1879struct dbg_bus_block_user_data { 1956struct dbg_bus_block_user_data {
1880 u8 num_of_lines; 1957 u8 num_of_lines;
1881 u8 has_latency_events; 1958 u8 has_latency_events;
1882 __le16 names_offset; 1959 __le16 names_offset;
1883}; 1960};
1884 1961
1962/* Block Debug line data */
1885struct dbg_bus_line { 1963struct dbg_bus_line {
1886 u8 data; 1964 u8 data;
1887#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF 1965#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
1888#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 1966#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
1889#define DBG_BUS_LINE_IS_256B_MASK 0x1 1967#define DBG_BUS_LINE_IS_256B_MASK 0x1
1890#define DBG_BUS_LINE_IS_256B_SHIFT 4 1968#define DBG_BUS_LINE_IS_256B_SHIFT 4
1891#define DBG_BUS_LINE_RESERVED_MASK 0x7 1969#define DBG_BUS_LINE_RESERVED_MASK 0x7
1892#define DBG_BUS_LINE_RESERVED_SHIFT 5 1970#define DBG_BUS_LINE_RESERVED_SHIFT 5
1893 u8 group_sizes; 1971 u8 group_sizes;
1894}; 1972};
1895 1973
1896/* condition header for registers dump */ 1974/* Condition header for registers dump */
1897struct dbg_dump_cond_hdr { 1975struct dbg_dump_cond_hdr {
1898 struct dbg_mode_hdr mode; /* Mode header */ 1976 struct dbg_mode_hdr mode; /* Mode header */
1899 u8 block_id; /* block ID */ 1977 u8 block_id; /* block ID */
1900 u8 data_size; /* size in dwords of the data following this header */ 1978 u8 data_size; /* size in dwords of the data following this header */
1901}; 1979};
1902 1980
1903/* memory data for registers dump */ 1981/* Memory data for registers dump */
1904struct dbg_dump_mem { 1982struct dbg_dump_mem {
1905 __le32 dword0; 1983 __le32 dword0;
1906#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF 1984#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
1907#define DBG_DUMP_MEM_ADDRESS_SHIFT 0 1985#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
1908#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF 1986#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
1909#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 1987#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
1910 __le32 dword1; 1988 __le32 dword1;
1911#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF 1989#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
1912#define DBG_DUMP_MEM_LENGTH_SHIFT 0 1990#define DBG_DUMP_MEM_LENGTH_SHIFT 0
1913#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 1991#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
1914#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 1992#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
1915#define DBG_DUMP_MEM_RESERVED_MASK 0x7F 1993#define DBG_DUMP_MEM_RESERVED_MASK 0x7F
1916#define DBG_DUMP_MEM_RESERVED_SHIFT 25 1994#define DBG_DUMP_MEM_RESERVED_SHIFT 25
1917}; 1995};
1918 1996
1919/* register data for registers dump */ 1997/* Register data for registers dump */
1920struct dbg_dump_reg { 1998struct dbg_dump_reg {
1921 __le32 data; 1999 __le32 data;
1922#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 2000#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
1923#define DBG_DUMP_REG_ADDRESS_SHIFT 0 2001#define DBG_DUMP_REG_ADDRESS_SHIFT 0
1924#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates register is wide-bus */ 2002#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
1925#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 2003#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
1926#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 2004#define DBG_DUMP_REG_LENGTH_MASK 0xFF
1927#define DBG_DUMP_REG_LENGTH_SHIFT 24 2005#define DBG_DUMP_REG_LENGTH_SHIFT 24
1928}; 2006};
1929 2007
1930/* split header for registers dump */ 2008/* Split header for registers dump */
1931struct dbg_dump_split_hdr { 2009struct dbg_dump_split_hdr {
1932 __le32 hdr; 2010 __le32 hdr;
1933#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF 2011#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
1934#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 2012#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
1935#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF 2013#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
1936#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 2014#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
1937}; 2015};
1938 2016
1939/* condition header for idle check */ 2017/* Condition header for idle check */
1940struct dbg_idle_chk_cond_hdr { 2018struct dbg_idle_chk_cond_hdr {
1941 struct dbg_mode_hdr mode; /* Mode header */ 2019 struct dbg_mode_hdr mode; /* Mode header */
1942 __le16 data_size; /* size in dwords of the data following this header */ 2020 __le16 data_size; /* size in dwords of the data following this header */
@@ -1945,12 +2023,12 @@ struct dbg_idle_chk_cond_hdr {
1945/* Idle Check condition register */ 2023/* Idle Check condition register */
1946struct dbg_idle_chk_cond_reg { 2024struct dbg_idle_chk_cond_reg {
1947 __le32 data; 2025 __le32 data;
1948#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF 2026#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
1949#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 2027#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
1950#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 2028#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
1951#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 2029#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
1952#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF 2030#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
1953#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 2031#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
1954 __le16 num_entries; 2032 __le16 num_entries;
1955 u8 entry_size; 2033 u8 entry_size;
1956 u8 start_entry; 2034 u8 start_entry;
@@ -1959,12 +2037,12 @@ struct dbg_idle_chk_cond_reg {
1959/* Idle Check info register */ 2037/* Idle Check info register */
1960struct dbg_idle_chk_info_reg { 2038struct dbg_idle_chk_info_reg {
1961 __le32 data; 2039 __le32 data;
1962#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF 2040#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
1963#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 2041#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
1964#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 2042#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
1965#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 2043#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
1966#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF 2044#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
1967#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 2045#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
1968 __le16 size; /* register size in dwords */ 2046 __le16 size; /* register size in dwords */
1969 struct dbg_mode_hdr mode; /* Mode header */ 2047 struct dbg_mode_hdr mode; /* Mode header */
1970}; 2048};
@@ -2016,13 +2094,13 @@ struct dbg_idle_chk_rule {
2016/* Idle Check rule parsing data */ 2094/* Idle Check rule parsing data */
2017struct dbg_idle_chk_rule_parsing_data { 2095struct dbg_idle_chk_rule_parsing_data {
2018 __le32 data; 2096 __le32 data;
2019#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 2097#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2020#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 2098#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2021#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF 2099#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2022#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 2100#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2023}; 2101};
2024 2102
2025/* idle check severity types */ 2103/* Idle check severity types */
2026enum dbg_idle_chk_severity_types { 2104enum dbg_idle_chk_severity_types {
2027 /* idle check failure should cause an error */ 2105 /* idle check failure should cause an error */
2028 IDLE_CHK_SEVERITY_ERROR, 2106 IDLE_CHK_SEVERITY_ERROR,
@@ -2036,14 +2114,14 @@ enum dbg_idle_chk_severity_types {
2036/* Debug Bus block data */ 2114/* Debug Bus block data */
2037struct dbg_bus_block_data { 2115struct dbg_bus_block_data {
2038 __le16 data; 2116 __le16 data;
2039#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF 2117#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2040#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 2118#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2041#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF 2119#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2042#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 2120#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2043#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF 2121#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2044#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 2122#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2045#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF 2123#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2046#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 2124#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
2047 u8 line_num; 2125 u8 line_num;
2048 u8 hw_id; 2126 u8 hw_id;
2049}; 2127};
@@ -2072,6 +2150,7 @@ enum dbg_bus_clients {
2072 MAX_DBG_BUS_CLIENTS 2150 MAX_DBG_BUS_CLIENTS
2073}; 2151};
2074 2152
2153/* Debug Bus constraint operation types */
2075enum dbg_bus_constraint_ops { 2154enum dbg_bus_constraint_ops {
2076 DBG_BUS_CONSTRAINT_OP_EQ, 2155 DBG_BUS_CONSTRAINT_OP_EQ,
2077 DBG_BUS_CONSTRAINT_OP_NE, 2156 DBG_BUS_CONSTRAINT_OP_NE,
@@ -2086,12 +2165,13 @@ enum dbg_bus_constraint_ops {
2086 MAX_DBG_BUS_CONSTRAINT_OPS 2165 MAX_DBG_BUS_CONSTRAINT_OPS
2087}; 2166};
2088 2167
2168/* Debug Bus trigger state data */
2089struct dbg_bus_trigger_state_data { 2169struct dbg_bus_trigger_state_data {
2090 u8 data; 2170 u8 data;
2091#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF 2171#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2092#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 2172#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2093#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF 2173#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2094#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 2174#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
2095}; 2175};
2096 2176
2097/* Debug Bus memory address */ 2177/* Debug Bus memory address */
@@ -2165,6 +2245,7 @@ struct dbg_bus_data {
2165 struct dbg_bus_storm_data storms[6]; 2245 struct dbg_bus_storm_data storms[6];
2166}; 2246};
2167 2247
2248/* Debug bus filter types */
2168enum dbg_bus_filter_types { 2249enum dbg_bus_filter_types {
2169 DBG_BUS_FILTER_TYPE_OFF, 2250 DBG_BUS_FILTER_TYPE_OFF,
2170 DBG_BUS_FILTER_TYPE_PRE, 2251 DBG_BUS_FILTER_TYPE_PRE,
@@ -2181,6 +2262,7 @@ enum dbg_bus_frame_modes {
2181 MAX_DBG_BUS_FRAME_MODES 2262 MAX_DBG_BUS_FRAME_MODES
2182}; 2263};
2183 2264
2265/* Debug bus other engine mode */
2184enum dbg_bus_other_engine_modes { 2266enum dbg_bus_other_engine_modes {
2185 DBG_BUS_OTHER_ENGINE_MODE_NONE, 2267 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2186 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 2268 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
@@ -2190,12 +2272,14 @@ enum dbg_bus_other_engine_modes {
2190 MAX_DBG_BUS_OTHER_ENGINE_MODES 2272 MAX_DBG_BUS_OTHER_ENGINE_MODES
2191}; 2273};
2192 2274
2275/* Debug bus post-trigger recording types */
2193enum dbg_bus_post_trigger_types { 2276enum dbg_bus_post_trigger_types {
2194 DBG_BUS_POST_TRIGGER_RECORD, 2277 DBG_BUS_POST_TRIGGER_RECORD,
2195 DBG_BUS_POST_TRIGGER_DROP, 2278 DBG_BUS_POST_TRIGGER_DROP,
2196 MAX_DBG_BUS_POST_TRIGGER_TYPES 2279 MAX_DBG_BUS_POST_TRIGGER_TYPES
2197}; 2280};
2198 2281
2282/* Debug bus pre-trigger recording types */
2199enum dbg_bus_pre_trigger_types { 2283enum dbg_bus_pre_trigger_types {
2200 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO, 2284 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2201 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS, 2285 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
@@ -2203,11 +2287,10 @@ enum dbg_bus_pre_trigger_types {
2203 MAX_DBG_BUS_PRE_TRIGGER_TYPES 2287 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2204}; 2288};
2205 2289
2290/* Debug bus SEMI frame modes */
2206enum dbg_bus_semi_frame_modes { 2291enum dbg_bus_semi_frame_modes {
2207 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 2292 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2208 0, 2293 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2209 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =
2210 3,
2211 MAX_DBG_BUS_SEMI_FRAME_MODES 2294 MAX_DBG_BUS_SEMI_FRAME_MODES
2212}; 2295};
2213 2296
@@ -2220,6 +2303,7 @@ enum dbg_bus_states {
2220 MAX_DBG_BUS_STATES 2303 MAX_DBG_BUS_STATES
2221}; 2304};
2222 2305
2306/* Debug Bus Storm modes */
2223enum dbg_bus_storm_modes { 2307enum dbg_bus_storm_modes {
2224 DBG_BUS_STORM_MODE_PRINTF, 2308 DBG_BUS_STORM_MODE_PRINTF,
2225 DBG_BUS_STORM_MODE_PRAM_ADDR, 2309 DBG_BUS_STORM_MODE_PRAM_ADDR,
@@ -2406,6 +2490,7 @@ struct dbg_tools_data {
2406/* Number of VLAN priorities */ 2490/* Number of VLAN priorities */
2407#define NUM_OF_VLAN_PRIORITIES 8 2491#define NUM_OF_VLAN_PRIORITIES 8
2408 2492
2493/* BRB RAM init requirements */
2409struct init_brb_ram_req { 2494struct init_brb_ram_req {
2410 __le32 guranteed_per_tc; 2495 __le32 guranteed_per_tc;
2411 __le32 headroom_per_tc; 2496 __le32 headroom_per_tc;
@@ -2414,17 +2499,20 @@ struct init_brb_ram_req {
2414 u8 num_active_tcs[MAX_NUM_PORTS]; 2499 u8 num_active_tcs[MAX_NUM_PORTS];
2415}; 2500};
2416 2501
2502/* ETS per-TC init requirements */
2417struct init_ets_tc_req { 2503struct init_ets_tc_req {
2418 u8 use_sp; 2504 u8 use_sp;
2419 u8 use_wfq; 2505 u8 use_wfq;
2420 __le16 weight; 2506 __le16 weight;
2421}; 2507};
2422 2508
2509/* ETS init requirements */
2423struct init_ets_req { 2510struct init_ets_req {
2424 __le32 mtu; 2511 __le32 mtu;
2425 struct init_ets_tc_req tc_req[NUM_OF_TCS]; 2512 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2426}; 2513};
2427 2514
2515/* NIG LB RL init requirements */
2428struct init_nig_lb_rl_req { 2516struct init_nig_lb_rl_req {
2429 __le16 lb_mac_rate; 2517 __le16 lb_mac_rate;
2430 __le16 lb_rate; 2518 __le16 lb_rate;
@@ -2432,15 +2520,18 @@ struct init_nig_lb_rl_req {
2432 __le16 tc_rate[NUM_OF_PHYS_TCS]; 2520 __le16 tc_rate[NUM_OF_PHYS_TCS];
2433}; 2521};
2434 2522
2523/* NIG TC mapping for each priority */
2435struct init_nig_pri_tc_map_entry { 2524struct init_nig_pri_tc_map_entry {
2436 u8 tc_id; 2525 u8 tc_id;
2437 u8 valid; 2526 u8 valid;
2438}; 2527};
2439 2528
2529/* NIG priority to TC map init requirements */
2440struct init_nig_pri_tc_map_req { 2530struct init_nig_pri_tc_map_req {
2441 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; 2531 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2442}; 2532};
2443 2533
2534/* QM per-port init parameters */
2444struct init_qm_port_params { 2535struct init_qm_port_params {
2445 u8 active; 2536 u8 active;
2446 u8 active_phys_tcs; 2537 u8 active_phys_tcs;
@@ -2563,7 +2654,7 @@ struct bin_buffer_hdr {
2563 __le32 length; 2654 __le32 length;
2564}; 2655};
2565 2656
2566/* binary init buffer types */ 2657/* Binary init buffer types */
2567enum bin_init_buffer_type { 2658enum bin_init_buffer_type {
2568 BIN_BUF_INIT_FW_VER_INFO, 2659 BIN_BUF_INIT_FW_VER_INFO,
2569 BIN_BUF_INIT_CMD, 2660 BIN_BUF_INIT_CMD,
@@ -2793,6 +2884,7 @@ struct iro {
2793}; 2884};
2794 2885
2795/***************************** Public Functions *******************************/ 2886/***************************** Public Functions *******************************/
2887
2796/** 2888/**
2797 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug 2889 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2798 * arrays. 2890 * arrays.
@@ -3119,6 +3211,7 @@ enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3119#define MAX_NAME_LEN 16 3211#define MAX_NAME_LEN 16
3120 3212
3121/***************************** Public Functions *******************************/ 3213/***************************** Public Functions *******************************/
3214
3122/** 3215/**
3123 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with 3216 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3124 * debug arrays. 3217 * debug arrays.
@@ -3820,116 +3913,195 @@ void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3820 u16 pf_id, bool tcp, bool udp, 3913 u16 pf_id, bool tcp, bool udp,
3821 bool ipv4, bool ipv6); 3914 bool ipv4, bool ipv6);
3822 3915
3823#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) 3916/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
3824#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) 3917#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
3825#define TSTORM_PORT_STAT_OFFSET(port_id) \ 3918#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
3919
3920/* Tstorm port statistics */
3921#define TSTORM_PORT_STAT_OFFSET(port_id) \
3826 (IRO[1].base + ((port_id) * IRO[1].m1)) 3922 (IRO[1].base + ((port_id) * IRO[1].m1))
3827#define TSTORM_PORT_STAT_SIZE (IRO[1].size) 3923#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
3924
3925/* Tstorm ll2 port statistics */
3828#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \ 3926#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
3829 (IRO[2].base + ((port_id) * IRO[2].m1)) 3927 (IRO[2].base + ((port_id) * IRO[2].m1))
3830#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size) 3928#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
3831#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ 3929
3930/* Ustorm VF-PF Channel ready flag */
3931#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
3832 (IRO[3].base + ((vf_id) * IRO[3].m1)) 3932 (IRO[3].base + ((vf_id) * IRO[3].m1))
3833#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) 3933#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
3834#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ 3934
3835 (IRO[4].base + (pf_id) * IRO[4].m1) 3935/* Ustorm Final flr cleanup ack */
3836#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) 3936#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
3837#define USTORM_EQE_CONS_OFFSET(pf_id) \ 3937 (IRO[4].base + ((pf_id) * IRO[4].m1))
3938#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
3939
3940/* Ustorm Event ring consumer */
3941#define USTORM_EQE_CONS_OFFSET(pf_id) \
3838 (IRO[5].base + ((pf_id) * IRO[5].m1)) 3942 (IRO[5].base + ((pf_id) * IRO[5].m1))
3839#define USTORM_EQE_CONS_SIZE (IRO[5].size) 3943#define USTORM_EQE_CONS_SIZE (IRO[5].size)
3840#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \ 3944
3945/* Ustorm eth queue zone */
3946#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
3841 (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) 3947 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
3842#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size) 3948#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
3843#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \ 3949
3950/* Ustorm Common Queue ring consumer */
3951#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
3844 (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) 3952 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
3845#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size) 3953#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
3954
3955/* Tstorm producers */
3846#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \ 3956#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
3847 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1)) 3957 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
3848#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size) 3958#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
3959
3960/* Tstorm LightL2 queue statistics */
3849#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 3961#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3850 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1)) 3962 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
3851#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size) 3963#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
3964
3965/* Ustorm LiteL2 queue statistics */
3852#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 3966#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
3853 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1)) 3967 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
3854#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size) 3968#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
3969
3970/* Pstorm LiteL2 queue statistics */
3855#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \ 3971#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
3856 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1)) 3972 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
3857#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size) 3973#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size)
3858#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 3974
3975/* Mstorm queue statistics */
3976#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3859 (IRO[18].base + ((stat_counter_id) * IRO[18].m1)) 3977 (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
3860#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size) 3978#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
3861#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \ 3979
3980/* Mstorm ETH PF queues producers */
3981#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
3862 (IRO[19].base + ((queue_id) * IRO[19].m1)) 3982 (IRO[19].base + ((queue_id) * IRO[19].m1))
3863#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size) 3983#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
3984
3985/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
3986 * mode.
3987 */
3864#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \ 3988#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
3865 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2)) 3989 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
3866#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size) 3990#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
3867#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base) 3991
3868#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size) 3992/* TPA agregation timeout in us resolution (on ASIC) */
3869#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 3993#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
3994#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
3995
3996/* Mstorm pf statistics */
3997#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3870 (IRO[22].base + ((pf_id) * IRO[22].m1)) 3998 (IRO[22].base + ((pf_id) * IRO[22].m1))
3871#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size) 3999#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
3872#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 4000
4001/* Ustorm queue statistics */
4002#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3873 (IRO[23].base + ((stat_counter_id) * IRO[23].m1)) 4003 (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
3874#define USTORM_QUEUE_STAT_SIZE (IRO[23].size) 4004#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
3875#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \ 4005
4006/* Ustorm pf statistics */
4007#define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
3876 (IRO[24].base + ((pf_id) * IRO[24].m1)) 4008 (IRO[24].base + ((pf_id) * IRO[24].m1))
3877#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size) 4009#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
3878#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 4010
4011/* Pstorm queue statistics */
4012#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
3879 (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) 4013 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
3880#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size) 4014#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
3881#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 4015
4016/* Pstorm pf statistics */
4017#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
3882 (IRO[26].base + ((pf_id) * IRO[26].m1)) 4018 (IRO[26].base + ((pf_id) * IRO[26].m1))
3883#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size) 4019#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
3884#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \ 4020
3885 (IRO[27].base + ((ethtype) * IRO[27].m1)) 4021/* Control frame's EthType configuration for TX control frame security */
3886#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size) 4022#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
3887#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base) 4023 (IRO[27].base + ((eth_type_id) * IRO[27].m1))
3888#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size) 4024#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
3889#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \ 4025
4026/* Tstorm last parser message */
4027#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
4028#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
4029
4030/* Tstorm Eth limit Rx rate */
4031#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
3890 (IRO[29].base + ((pf_id) * IRO[29].m1)) 4032 (IRO[29].base + ((pf_id) * IRO[29].m1))
3891#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size) 4033#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
3892#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \ 4034
4035/* Xstorm queue zone */
4036#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
3893 (IRO[30].base + ((queue_id) * IRO[30].m1)) 4037 (IRO[30].base + ((queue_id) * IRO[30].m1))
3894#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size) 4038#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
4039
4040/* Tstorm cmdq-cons of given command queue-id */
3895#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \ 4041#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
3896 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1)) 4042 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
3897#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size) 4043#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
4044
4045/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4046 * BDqueue-id.
4047 */
3898#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ 4048#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3899 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2)) 4049 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
3900#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size) 4050#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
4051
4052/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
3901#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ 4053#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
3902 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) 4054 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
3903#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) 4055#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
4056
4057/* Tstorm iSCSI RX stats */
3904#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 4058#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3905 (IRO[37].base + ((pf_id) * IRO[37].m1)) 4059 (IRO[37].base + ((pf_id) * IRO[37].m1))
3906#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size) 4060#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
4061
4062/* Mstorm iSCSI RX stats */
3907#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 4063#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3908 (IRO[38].base + ((pf_id) * IRO[38].m1)) 4064 (IRO[38].base + ((pf_id) * IRO[38].m1))
3909#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) 4065#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
4066
4067/* Ustorm iSCSI RX stats */
3910#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 4068#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
3911 (IRO[39].base + ((pf_id) * IRO[39].m1)) 4069 (IRO[39].base + ((pf_id) * IRO[39].m1))
3912#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) 4070#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
4071
4072/* Xstorm iSCSI TX stats */
3913#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 4073#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3914 (IRO[40].base + ((pf_id) * IRO[40].m1)) 4074 (IRO[40].base + ((pf_id) * IRO[40].m1))
3915#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size) 4075#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
4076
4077/* Ystorm iSCSI TX stats */
3916#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 4078#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3917 (IRO[41].base + ((pf_id) * IRO[41].m1)) 4079 (IRO[41].base + ((pf_id) * IRO[41].m1))
3918#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) 4080#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
4081
4082/* Pstorm iSCSI TX stats */
3919#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 4083#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
3920 (IRO[42].base + ((pf_id) * IRO[42].m1)) 4084 (IRO[42].base + ((pf_id) * IRO[42].m1))
3921#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) 4085#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
3922#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ 4086
3923 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1)) 4087/* Tstorm FCoE RX stats */
3924#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
3925#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
3926 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
3927#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
3928#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \ 4088#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
3929 (IRO[43].base + ((pf_id) * IRO[43].m1)) 4089 (IRO[43].base + ((pf_id) * IRO[43].m1))
4090
4091/* Pstorm FCoE TX stats */
3930#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \ 4092#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
3931 (IRO[44].base + ((pf_id) * IRO[44].m1)) 4093 (IRO[44].base + ((pf_id) * IRO[44].m1))
3932 4094
4095/* Pstorm RDMA queue statistics */
4096#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4097 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
4098#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
4099
4100/* Tstorm RDMA queue statistics */
4101#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4102 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4103#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
4104
3933static const struct iro iro_arr[49] = { 4105static const struct iro iro_arr[49] = {
3934 {0x0, 0x0, 0x0, 0x0, 0x8}, 4106 {0x0, 0x0, 0x0, 0x0, 0x8},
3935 {0x4cb0, 0x80, 0x0, 0x0, 0x80}, 4107 {0x4cb0, 0x80, 0x0, 0x0, 0x80},
@@ -4475,31 +4647,31 @@ struct xstorm_eth_conn_ag_ctx {
4475#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 4647#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
4476 u8 flags2; 4648 u8 flags2;
4477#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4649#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4478#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 4650#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4479#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4651#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4480#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 4652#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4481#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4653#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4482#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 4654#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4483#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4655#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4484#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 4656#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
4485 u8 flags3; 4657 u8 flags3;
4486#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 4658#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4487#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 4659#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4488#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 4660#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4489#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 4661#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4490#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 4662#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4491#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 4663#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4492#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 4664#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4493#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 4665#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4494 u8 flags4; 4666 u8 flags4;
4495#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 4667#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4496#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 4668#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4497#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 4669#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4498#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 4670#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4499#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 4671#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4500#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 4672#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4501#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 4673#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4502#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 4674#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
4503 u8 flags5; 4675 u8 flags5;
4504#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 4676#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4505#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 4677#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
@@ -4547,39 +4719,39 @@ struct xstorm_eth_conn_ag_ctx {
4547#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 4719#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4548#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 4720#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
4549 u8 flags9; 4721 u8 flags9;
4550#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 4722#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4551#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 4723#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4552#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 4724#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4553#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 4725#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4554#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 4726#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4555#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 4727#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4556#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 4728#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4557#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 4729#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4558#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 4730#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4559#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 4731#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4560#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 4732#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4561#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 4733#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4562#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 4734#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4563#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 4735#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4564#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 4736#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4565#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 4737#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4566 u8 flags10; 4738 u8 flags10;
4567#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 4739#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4568#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 4740#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4569#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 4741#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4570#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 4742#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4571#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 4743#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4572#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 4744#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4573#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 4745#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4574#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 4746#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4575#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 4747#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4576#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 4748#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4577#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 4749#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4578#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 4750#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4579#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 4751#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4580#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 4752#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4581#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 4753#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4582#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 4754#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
4583 u8 flags11; 4755 u8 flags11;
4584#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 4756#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4585#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 4757#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
@@ -4632,20 +4804,20 @@ struct xstorm_eth_conn_ag_ctx {
4632#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 4804#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4633#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 4805#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
4634 u8 flags14; 4806 u8 flags14;
4635#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 4807#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4636#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 4808#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4637#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 4809#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4638#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 4810#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
4639#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 4811#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4640#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 4812#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
4641#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 4813#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4642#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 4814#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
4643#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 4815#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4644#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 4816#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
4645#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 4817#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4646#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 4818#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
4647#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 4819#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4648#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 4820#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
4649 u8 edpm_event_id; 4821 u8 edpm_event_id;
4650 __le16 physical_q0; 4822 __le16 physical_q0;
4651 __le16 ereserved1; 4823 __le16 ereserved1;
@@ -4752,85 +4924,85 @@ struct tstorm_eth_conn_ag_ctx {
4752 u8 byte0; 4924 u8 byte0;
4753 u8 byte1; 4925 u8 byte1;
4754 u8 flags0; 4926 u8 flags0;
4755#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 4927#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
4756#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 4928#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
4757#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4929#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4758#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4930#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
4759#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 4931#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
4760#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 4932#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
4761#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 4933#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
4762#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 4934#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
4763#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 4935#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
4764#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 4936#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
4765#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 4937#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
4766#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 4938#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
4767#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4939#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4768#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 4940#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
4769 u8 flags1; 4941 u8 flags1;
4770#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4942#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4771#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 4943#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
4772#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4944#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4773#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 4945#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
4774#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4946#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4775#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 4947#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
4776#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 4948#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4777#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 4949#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
4778 u8 flags2; 4950 u8 flags2;
4779#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 4951#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4780#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 4952#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
4781#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 4953#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4782#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 4954#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
4783#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 4955#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4784#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 4956#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
4785#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 4957#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4786#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 4958#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
4787 u8 flags3; 4959 u8 flags3;
4788#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 4960#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4789#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 4961#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
4790#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 4962#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4791#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 4963#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
4792#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 4964#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4793#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 4965#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
4794#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 4966#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4795#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 4967#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
4796#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4968#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4797#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 4969#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
4798#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 4970#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4799#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 4971#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
4800 u8 flags4; 4972 u8 flags4;
4801#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 4973#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4802#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 4974#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
4803#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 4975#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4804#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 4976#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
4805#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 4977#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4806#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 4978#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
4807#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 4979#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4808#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 4980#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
4809#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 4981#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4810#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 4982#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
4811#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 4983#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4812#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 4984#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
4813#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 4985#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4814#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 4986#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
4815#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4987#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4816#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 4988#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4817 u8 flags5; 4989 u8 flags5;
4818#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4990#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4819#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 4991#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4820#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4992#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4821#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 4993#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4822#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4994#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4823#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 4995#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4824#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4996#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4825#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 4997#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4826#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 4998#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4827#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 4999#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4828#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 5000#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
4829#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 5001#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
4830#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 5002#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4831#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 5003#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4832#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 5004#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4833#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 5005#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4834 __le32 reg0; 5006 __le32 reg0;
4835 __le32 reg1; 5007 __le32 reg1;
4836 __le32 reg2; 5008 __le32 reg2;
@@ -4867,14 +5039,14 @@ struct ustorm_eth_conn_ag_ctx {
4867#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5039#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4868#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 5040#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
4869 u8 flags1; 5041 u8 flags1;
4870#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 5042#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4871#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 5043#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
4872#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 5044#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
4873#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 5045#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
4874#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 5046#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
4875#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 5047#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
4876#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 5048#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4877#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 5049#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
4878 u8 flags2; 5050 u8 flags2;
4879#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 5051#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
4880#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 5052#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
@@ -4893,22 +5065,22 @@ struct ustorm_eth_conn_ag_ctx {
4893#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5065#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4894#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 5066#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
4895 u8 flags3; 5067 u8 flags3;
4896#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5068#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4897#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 5069#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
4898#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5070#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4899#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 5071#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
4900#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5072#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4901#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 5073#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
4902#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5074#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4903#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 5075#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
4904#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 5076#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
4905#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 5077#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
4906#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 5078#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
4907#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 5079#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
4908#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 5080#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
4909#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 5081#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
4910#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 5082#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
4911#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 5083#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
4912 u8 byte2; 5084 u8 byte2;
4913 u8 byte3; 5085 u8 byte3;
4914 __le16 word0; 5086 __le16 word0;
@@ -4946,6 +5118,7 @@ struct eth_conn_context {
4946 struct mstorm_eth_conn_st_ctx mstorm_st_context; 5118 struct mstorm_eth_conn_st_ctx mstorm_st_context;
4947}; 5119};
4948 5120
5121/* Ethernet filter types: mac/vlan/pair */
4949enum eth_error_code { 5122enum eth_error_code {
4950 ETH_OK = 0x00, 5123 ETH_OK = 0x00,
4951 ETH_FILTERS_MAC_ADD_FAIL_FULL, 5124 ETH_FILTERS_MAC_ADD_FAIL_FULL,
@@ -4972,6 +5145,7 @@ enum eth_error_code {
4972 MAX_ETH_ERROR_CODE 5145 MAX_ETH_ERROR_CODE
4973}; 5146};
4974 5147
5148/* Opcodes for the event ring */
4975enum eth_event_opcode { 5149enum eth_event_opcode {
4976 ETH_EVENT_UNUSED, 5150 ETH_EVENT_UNUSED,
4977 ETH_EVENT_VPORT_START, 5151 ETH_EVENT_VPORT_START,
@@ -5039,6 +5213,7 @@ enum eth_filter_type {
5039 MAX_ETH_FILTER_TYPE 5213 MAX_ETH_FILTER_TYPE
5040}; 5214};
5041 5215
5216/* Eth IPv4 Fragment Type */
5042enum eth_ipv4_frag_type { 5217enum eth_ipv4_frag_type {
5043 ETH_IPV4_NOT_FRAG, 5218 ETH_IPV4_NOT_FRAG,
5044 ETH_IPV4_FIRST_FRAG, 5219 ETH_IPV4_FIRST_FRAG,
@@ -5046,12 +5221,14 @@ enum eth_ipv4_frag_type {
5046 MAX_ETH_IPV4_FRAG_TYPE 5221 MAX_ETH_IPV4_FRAG_TYPE
5047}; 5222};
5048 5223
5224/* eth IPv4 Fragment Type */
5049enum eth_ip_type { 5225enum eth_ip_type {
5050 ETH_IPV4, 5226 ETH_IPV4,
5051 ETH_IPV6, 5227 ETH_IPV6,
5052 MAX_ETH_IP_TYPE 5228 MAX_ETH_IP_TYPE
5053}; 5229};
5054 5230
5231/* Ethernet Ramrod Command IDs */
5055enum eth_ramrod_cmd_id { 5232enum eth_ramrod_cmd_id {
5056 ETH_RAMROD_UNUSED, 5233 ETH_RAMROD_UNUSED,
5057 ETH_RAMROD_VPORT_START, 5234 ETH_RAMROD_VPORT_START,
@@ -5073,7 +5250,7 @@ enum eth_ramrod_cmd_id {
5073 MAX_ETH_RAMROD_CMD_ID 5250 MAX_ETH_RAMROD_CMD_ID
5074}; 5251};
5075 5252
5076/* return code from eth sp ramrods */ 5253/* Return code from eth sp ramrods */
5077struct eth_return_code { 5254struct eth_return_code {
5078 u8 value; 5255 u8 value;
5079#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F 5256#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
@@ -5209,6 +5386,7 @@ struct eth_vport_tx_mode {
5209 __le16 reserved2[3]; 5386 __le16 reserved2[3];
5210}; 5387};
5211 5388
5389/* GFT filter update action type */
5212enum gft_filter_update_action { 5390enum gft_filter_update_action {
5213 GFT_ADD_FILTER, 5391 GFT_ADD_FILTER,
5214 GFT_DELETE_FILTER, 5392 GFT_DELETE_FILTER,
@@ -5221,6 +5399,7 @@ enum gft_logic_filter_type {
5221 MAX_GFT_LOGIC_FILTER_TYPE 5399 MAX_GFT_LOGIC_FILTER_TYPE
5222}; 5400};
5223 5401
5402/* Ramrod data for rx add openflow filter */
5224struct rx_add_openflow_filter_data { 5403struct rx_add_openflow_filter_data {
5225 __le16 action_icid; 5404 __le16 action_icid;
5226 u8 priority; 5405 u8 priority;
@@ -5244,11 +5423,13 @@ struct rx_add_openflow_filter_data {
5244 __le16 l4_src_port; 5423 __le16 l4_src_port;
5245}; 5424};
5246 5425
5426/* Ramrod data for rx create gft action */
5247struct rx_create_gft_action_data { 5427struct rx_create_gft_action_data {
5248 u8 vport_id; 5428 u8 vport_id;
5249 u8 reserved[7]; 5429 u8 reserved[7];
5250}; 5430};
5251 5431
5432/* Ramrod data for rx create openflow action */
5252struct rx_create_openflow_action_data { 5433struct rx_create_openflow_action_data {
5253 u8 vport_id; 5434 u8 vport_id;
5254 u8 reserved[7]; 5435 u8 reserved[7];
@@ -5286,7 +5467,7 @@ struct rx_queue_start_ramrod_data {
5286 struct regpair reserved2; 5467 struct regpair reserved2;
5287}; 5468};
5288 5469
5289/* Ramrod data for rx queue start ramrod */ 5470/* Ramrod data for rx queue stop ramrod */
5290struct rx_queue_stop_ramrod_data { 5471struct rx_queue_stop_ramrod_data {
5291 __le16 rx_queue_id; 5472 __le16 rx_queue_id;
5292 u8 complete_cqe_flg; 5473 u8 complete_cqe_flg;
@@ -5324,6 +5505,9 @@ struct rx_udp_filter_data {
5324 __le32 tenant_id; 5505 __le32 tenant_id;
5325}; 5506};
5326 5507
5508/* Add or delete GFT filter - filter is packet header of type of packet wished
5509 * to pass certain FW flow.
5510 */
5327struct rx_update_gft_filter_data { 5511struct rx_update_gft_filter_data {
5328 struct regpair pkt_hdr_addr; 5512 struct regpair pkt_hdr_addr;
5329 __le16 pkt_hdr_length; 5513 __le16 pkt_hdr_length;
@@ -5481,212 +5665,212 @@ struct xstorm_eth_conn_agctxdq_ext_ldpart {
5481 u8 reserved0; 5665 u8 reserved0;
5482 u8 eth_state; 5666 u8 eth_state;
5483 u8 flags0; 5667 u8 flags0;
5484#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 5668#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5485#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 5669#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5486#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 5670#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5487#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 5671#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5488#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 5672#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5489#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 5673#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5490#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 5674#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5491#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 5675#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5492#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 5676#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5493#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 5677#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5494#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 5678#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5495#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 5679#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5496#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 5680#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5497#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 5681#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5498#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 5682#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5499#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 5683#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
5500 u8 flags1; 5684 u8 flags1;
5501#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 5685#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5502#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 5686#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5503#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 5687#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5504#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 5688#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5505#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 5689#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5506#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 5690#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5507#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 5691#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5508#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 5692#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5509#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 5693#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
5510#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 5694#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
5511#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 5695#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
5512#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 5696#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
5513#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 5697#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
5514#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 5698#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
5515#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 5699#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
5516#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 5700#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
5517 u8 flags2; 5701 u8 flags2;
5518#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 5702#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
5519#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 5703#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
5520#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 5704#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
5521#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 5705#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
5522#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 5706#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
5523#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 5707#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
5524#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 5708#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
5525#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 5709#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
5526 u8 flags3; 5710 u8 flags3;
5527#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 5711#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
5528#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 5712#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
5529#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 5713#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
5530#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 5714#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
5531#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 5715#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
5532#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 5716#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
5533#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 5717#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
5534#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 5718#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
5535 u8 flags4; 5719 u8 flags4;
5536#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 5720#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
5537#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 5721#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
5538#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 5722#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
5539#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 5723#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
5540#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 5724#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
5541#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 5725#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
5542#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 5726#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
5543#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 5727#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
5544 u8 flags5; 5728 u8 flags5;
5545#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 5729#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
5546#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 5730#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
5547#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 5731#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
5548#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 5732#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
5549#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 5733#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
5550#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 5734#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
5551#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 5735#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
5552#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 5736#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
5553 u8 flags6; 5737 u8 flags6;
5554#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 5738#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
5555#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 5739#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
5556#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 5740#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
5557#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 5741#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
5558#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 5742#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
5559#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 5743#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
5560#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 5744#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
5561#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 5745#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
5562 u8 flags7; 5746 u8 flags7;
5563#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 5747#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
5564#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 5748#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
5565#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 5749#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
5566#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 5750#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
5567#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 5751#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
5568#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 5752#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
5569#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 5753#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
5570#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 5754#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
5571#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 5755#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
5572#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 5756#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
5573 u8 flags8; 5757 u8 flags8;
5574#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 5758#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
5575#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 5759#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
5576#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 5760#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
5577#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 5761#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
5578#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 5762#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
5579#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 5763#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
5580#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 5764#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
5581#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 5765#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
5582#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 5766#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
5583#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 5767#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
5584#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 5768#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
5585#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 5769#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
5586#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 5770#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
5587#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 5771#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
5588#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 5772#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
5589#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 5773#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
5590 u8 flags9; 5774 u8 flags9;
5591#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 5775#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
5592#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 5776#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
5593#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 5777#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
5594#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 5778#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
5595#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 5779#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
5596#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 5780#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
5597#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 5781#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
5598#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 5782#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
5599#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 5783#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
5600#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 5784#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
5601#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 5785#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
5602#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 5786#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
5603#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 5787#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
5604#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 5788#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
5605#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 5789#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
5606#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 5790#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
5607 u8 flags10; 5791 u8 flags10;
5608#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 5792#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
5609#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 5793#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
5610#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 5794#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
5611#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 5795#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
5612#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 5796#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
5613#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 5797#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
5614#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 5798#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
5615#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 5799#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
5616#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 5800#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
5617#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 5801#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
5618#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 5802#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
5619#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 5803#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
5620#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 5804#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
5621#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 5805#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
5622#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 5806#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
5623#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 5807#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
5624 u8 flags11; 5808 u8 flags11;
5625#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 5809#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
5626#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 5810#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
5627#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 5811#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
5628#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 5812#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
5629#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 5813#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
5630#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 5814#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
5631#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 5815#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
5632#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 5816#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
5633#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 5817#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
5634#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 5818#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
5635#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 5819#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
5636#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 5820#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
5637#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 5821#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
5638#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 5822#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
5639#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 5823#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
5640#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 5824#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
5641 u8 flags12; 5825 u8 flags12;
5642#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 5826#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
5643#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 5827#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
5644#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 5828#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
5645#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 5829#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
5646#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 5830#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
5647#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 5831#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
5648#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 5832#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
5649#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 5833#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
5650#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 5834#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
5651#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 5835#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
5652#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 5836#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
5653#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 5837#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
5654#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 5838#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
5655#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 5839#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
5656#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 5840#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
5657#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 5841#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
5658 u8 flags13; 5842 u8 flags13;
5659#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 5843#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
5660#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 5844#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
5661#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 5845#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
5662#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 5846#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
5663#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 5847#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
5664#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 5848#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
5665#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 5849#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
5666#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 5850#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
5667#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 5851#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
5668#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 5852#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
5669#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 5853#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
5670#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 5854#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
5671#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 5855#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
5672#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 5856#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
5673#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 5857#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
5674#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 5858#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
5675 u8 flags14; 5859 u8 flags14;
5676#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 5860#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
5677#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 5861#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
5678#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 5862#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
5679#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 5863#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
5680#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 5864#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
5681#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 5865#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
5682#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 5866#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5683#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 5867#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5684#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 5868#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
5685#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 5869#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
5686#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 5870#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
5687#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 5871#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
5688#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 5872#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
5689#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 5873#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
5690 u8 edpm_event_id; 5874 u8 edpm_event_id;
5691 __le16 physical_q0; 5875 __le16 physical_q0;
5692 __le16 ereserved1; 5876 __le16 ereserved1;
@@ -5711,32 +5895,32 @@ struct mstorm_eth_conn_ag_ctx {
5711 u8 byte1; 5895 u8 byte1;
5712 u8 flags0; 5896 u8 flags0;
5713#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5897#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5714#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5898#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5715#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 5899#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5716#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 5900#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5717#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 5901#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5718#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 5902#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
5719#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 5903#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5720#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 5904#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
5721#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5905#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5722#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 5906#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5723 u8 flags1; 5907 u8 flags1;
5724#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 5908#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5725#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 5909#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
5726#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 5910#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5727#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 5911#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
5728#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5912#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5729#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 5913#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5730#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5914#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5731#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 5915#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5732#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5916#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5733#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 5917#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5734#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5918#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5735#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 5919#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5736#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5920#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5737#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 5921#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5738#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5922#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5739#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 5923#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5740 __le16 word0; 5924 __le16 word0;
5741 __le16 word1; 5925 __le16 word1;
5742 __le32 reg0; 5926 __le32 reg0;
@@ -5748,211 +5932,211 @@ struct xstorm_eth_hw_conn_ag_ctx {
5748 u8 eth_state; 5932 u8 eth_state;
5749 u8 flags0; 5933 u8 flags0;
5750#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5934#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5751#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5935#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5752#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 5936#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
5753#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 5937#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
5754#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 5938#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
5755#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 5939#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
5756#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 5940#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5757#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 5941#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5758#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 5942#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
5759#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 5943#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
5760#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 5944#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
5761#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 5945#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
5762#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 5946#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
5763#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 5947#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
5764#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 5948#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
5765#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 5949#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
5766 u8 flags1; 5950 u8 flags1;
5767#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 5951#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
5768#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 5952#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
5769#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 5953#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
5770#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 5954#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
5771#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 5955#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
5772#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 5956#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
5773#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 5957#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
5774#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 5958#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
5775#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1 5959#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
5776#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4 5960#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
5777#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1 5961#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
5778#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5 5962#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
5779#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 5963#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5780#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 5964#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5781#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 5965#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5782#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 5966#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
5783 u8 flags2; 5967 u8 flags2;
5784#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 5968#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
5785#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 5969#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
5786#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 5970#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
5787#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 5971#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
5788#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 5972#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
5789#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 5973#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
5790#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 5974#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
5791#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 5975#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
5792 u8 flags3; 5976 u8 flags3;
5793#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 5977#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
5794#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 5978#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
5795#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 5979#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
5796#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 5980#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
5797#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 5981#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
5798#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 5982#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
5799#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 5983#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
5800#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 5984#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
5801 u8 flags4; 5985 u8 flags4;
5802#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 5986#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
5803#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 5987#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
5804#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 5988#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
5805#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 5989#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
5806#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 5990#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
5807#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 5991#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
5808#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 5992#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
5809#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 5993#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
5810 u8 flags5; 5994 u8 flags5;
5811#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 5995#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
5812#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 5996#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
5813#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 5997#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
5814#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 5998#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
5815#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 5999#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
5816#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 6000#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
5817#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 6001#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
5818#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 6002#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
5819 u8 flags6; 6003 u8 flags6;
5820#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 6004#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
5821#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 6005#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
5822#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 6006#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
5823#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 6007#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
5824#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 6008#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
5825#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 6009#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
5826#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 6010#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
5827#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 6011#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
5828 u8 flags7; 6012 u8 flags7;
5829#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 6013#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5830#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 6014#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5831#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 6015#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
5832#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 6016#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
5833#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 6017#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5834#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 6018#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5835#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 6019#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
5836#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 6020#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
5837#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 6021#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
5838#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 6022#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
5839 u8 flags8; 6023 u8 flags8;
5840#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 6024#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
5841#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 6025#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
5842#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 6026#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
5843#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 6027#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
5844#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 6028#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
5845#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 6029#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
5846#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 6030#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
5847#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 6031#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
5848#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 6032#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
5849#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 6033#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
5850#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 6034#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
5851#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 6035#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
5852#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 6036#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
5853#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 6037#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
5854#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 6038#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
5855#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 6039#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
5856 u8 flags9; 6040 u8 flags9;
5857#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 6041#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
5858#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 6042#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
5859#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 6043#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
5860#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 6044#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
5861#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 6045#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
5862#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 6046#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
5863#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 6047#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
5864#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 6048#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
5865#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 6049#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
5866#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 6050#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
5867#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 6051#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
5868#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 6052#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
5869#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 6053#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
5870#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 6054#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
5871#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 6055#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
5872#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 6056#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
5873 u8 flags10; 6057 u8 flags10;
5874#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 6058#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5875#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 6059#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
5876#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 6060#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
5877#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 6061#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
5878#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 6062#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5879#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 6063#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5880#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 6064#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
5881#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 6065#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
5882#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 6066#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5883#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 6067#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5884#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 6068#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
5885#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 6069#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
5886#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 6070#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
5887#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 6071#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
5888#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 6072#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
5889#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 6073#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
5890 u8 flags11; 6074 u8 flags11;
5891#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 6075#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
5892#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 6076#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
5893#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 6077#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
5894#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 6078#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
5895#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 6079#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5896#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 6080#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5897#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 6081#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
5898#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 6082#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
5899#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 6083#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
5900#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 6084#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
5901#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 6085#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
5902#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 6086#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
5903#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 6087#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5904#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 6088#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5905#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 6089#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
5906#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 6090#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
5907 u8 flags12; 6091 u8 flags12;
5908#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 6092#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
5909#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 6093#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
5910#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 6094#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
5911#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 6095#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
5912#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 6096#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5913#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 6097#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5914#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 6098#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5915#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 6099#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5916#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 6100#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
5917#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 6101#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
5918#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 6102#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
5919#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 6103#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
5920#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 6104#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
5921#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 6105#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
5922#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 6106#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
5923#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 6107#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
5924 u8 flags13; 6108 u8 flags13;
5925#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 6109#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
5926#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 6110#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
5927#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 6111#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
5928#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 6112#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
5929#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 6113#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5930#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 6114#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5931#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 6115#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5932#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 6116#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5933#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 6117#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5934#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 6118#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5935#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 6119#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5936#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 6120#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5937#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 6121#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5938#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 6122#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5939#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 6123#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5940#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 6124#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5941 u8 flags14; 6125 u8 flags14;
5942#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 6126#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5943#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 6127#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5944#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 6128#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5945#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 6129#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5946#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 6130#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5947#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 6131#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5948#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 6132#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5949#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 6133#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5950#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 6134#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5951#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 6135#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5952#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 6136#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5953#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 6137#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5954#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 6138#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5955#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 6139#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5956 u8 edpm_event_id; 6140 u8 edpm_event_id;
5957 __le16 physical_q0; 6141 __le16 physical_q0;
5958 __le16 ereserved1; 6142 __le16 ereserved1;
@@ -5963,6 +6147,7 @@ struct xstorm_eth_hw_conn_ag_ctx {
5963 __le16 conn_dpi; 6147 __le16 conn_dpi;
5964}; 6148};
5965 6149
6150/* GFT CAM line struct */
5966struct gft_cam_line { 6151struct gft_cam_line {
5967 __le32 camline; 6152 __le32 camline;
5968#define GFT_CAM_LINE_VALID_MASK 0x1 6153#define GFT_CAM_LINE_VALID_MASK 0x1
@@ -5975,6 +6160,7 @@ struct gft_cam_line {
5975#define GFT_CAM_LINE_RESERVED1_SHIFT 29 6160#define GFT_CAM_LINE_RESERVED1_SHIFT 29
5976}; 6161};
5977 6162
6163/* GFT CAM line struct with fields breakout */
5978struct gft_cam_line_mapped { 6164struct gft_cam_line_mapped {
5979 __le32 camline; 6165 __le32 camline;
5980#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 6166#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
@@ -6008,28 +6194,31 @@ union gft_cam_line_union {
6008 struct gft_cam_line_mapped cam_line_mapped; 6194 struct gft_cam_line_mapped cam_line_mapped;
6009}; 6195};
6010 6196
6197/* Used in gft_profile_key: Indication for ip version */
6011enum gft_profile_ip_version { 6198enum gft_profile_ip_version {
6012 GFT_PROFILE_IPV4 = 0, 6199 GFT_PROFILE_IPV4 = 0,
6013 GFT_PROFILE_IPV6 = 1, 6200 GFT_PROFILE_IPV6 = 1,
6014 MAX_GFT_PROFILE_IP_VERSION 6201 MAX_GFT_PROFILE_IP_VERSION
6015}; 6202};
6016 6203
6204/* Profile key stucr fot GFT logic in Prs */
6017struct gft_profile_key { 6205struct gft_profile_key {
6018 __le16 profile_key; 6206 __le16 profile_key;
6019#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 6207#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6020#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 6208#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6021#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 6209#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6022#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 6210#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
6023#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 6211#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6024#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 6212#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
6025#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 6213#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6026#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 6214#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
6027#define GFT_PROFILE_KEY_PF_ID_MASK 0xF 6215#define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6028#define GFT_PROFILE_KEY_PF_ID_SHIFT 10 6216#define GFT_PROFILE_KEY_PF_ID_SHIFT 10
6029#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 6217#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6030#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 6218#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
6031}; 6219};
6032 6220
6221/* Used in gft_profile_key: Indication for tunnel type */
6033enum gft_profile_tunnel_type { 6222enum gft_profile_tunnel_type {
6034 GFT_PROFILE_NO_TUNNEL = 0, 6223 GFT_PROFILE_NO_TUNNEL = 0,
6035 GFT_PROFILE_VXLAN_TUNNEL = 1, 6224 GFT_PROFILE_VXLAN_TUNNEL = 1,
@@ -6040,6 +6229,7 @@ enum gft_profile_tunnel_type {
6040 MAX_GFT_PROFILE_TUNNEL_TYPE 6229 MAX_GFT_PROFILE_TUNNEL_TYPE
6041}; 6230};
6042 6231
6232/* Used in gft_profile_key: Indication for protocol type */
6043enum gft_profile_upper_protocol_type { 6233enum gft_profile_upper_protocol_type {
6044 GFT_PROFILE_ROCE_PROTOCOL = 0, 6234 GFT_PROFILE_ROCE_PROTOCOL = 0,
6045 GFT_PROFILE_RROCE_PROTOCOL = 1, 6235 GFT_PROFILE_RROCE_PROTOCOL = 1,
@@ -6060,6 +6250,7 @@ enum gft_profile_upper_protocol_type {
6060 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 6250 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6061}; 6251};
6062 6252
6253/* GFT RAM line struct */
6063struct gft_ram_line { 6254struct gft_ram_line {
6064 __le32 lo; 6255 __le32 lo;
6065#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 6256#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
@@ -6149,6 +6340,7 @@ struct gft_ram_line {
6149#define GFT_RAM_LINE_RESERVED1_SHIFT 10 6340#define GFT_RAM_LINE_RESERVED1_SHIFT 10
6150}; 6341};
6151 6342
6343/* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6152enum gft_vlan_select { 6344enum gft_vlan_select {
6153 INNER_PROVIDER_VLAN = 0, 6345 INNER_PROVIDER_VLAN = 0,
6154 INNER_VLAN = 1, 6346 INNER_VLAN = 1,
@@ -6157,10 +6349,205 @@ enum gft_vlan_select {
6157 MAX_GFT_VLAN_SELECT 6349 MAX_GFT_VLAN_SELECT
6158}; 6350};
6159 6351
6352/* The rdma task context of Mstorm */
6353struct ystorm_rdma_task_st_ctx {
6354 struct regpair temp[4];
6355};
6356
6357struct ystorm_rdma_task_ag_ctx {
6358 u8 reserved;
6359 u8 byte1;
6360 __le16 msem_ctx_upd_seq;
6361 u8 flags0;
6362#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6363#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6364#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6365#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6366#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6367#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6368#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6369#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
6370#define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6371#define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6372 u8 flags1;
6373#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6374#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6375#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6376#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6377#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6378#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
6379#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6380#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6381#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6382#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6383 u8 flags2;
6384#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6385#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6386#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6387#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6388#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6389#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6390#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6391#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6392#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6393#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6394#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6395#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6396#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6397#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6398#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6399#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6400 u8 key;
6401 __le32 mw_cnt;
6402 u8 ref_cnt_seq;
6403 u8 ctx_upd_seq;
6404 __le16 dif_flags;
6405 __le16 tx_ref_count;
6406 __le16 last_used_ltid;
6407 __le16 parent_mr_lo;
6408 __le16 parent_mr_hi;
6409 __le32 fbo_lo;
6410 __le32 fbo_hi;
6411};
6412
6413struct mstorm_rdma_task_ag_ctx {
6414 u8 reserved;
6415 u8 byte1;
6416 __le16 icid;
6417 u8 flags0;
6418#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6419#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6420#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6421#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6422#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6423#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6424#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6425#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6426#define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6427#define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6428 u8 flags1;
6429#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6430#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6431#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6432#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6433#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6434#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6435#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6436#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6437#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6438#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6439 u8 flags2;
6440#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6441#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6442#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6443#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6444#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6445#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6446#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6447#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6448#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6449#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6450#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6451#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6452#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6453#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6454#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6455#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6456 u8 key;
6457 __le32 mw_cnt;
6458 u8 ref_cnt_seq;
6459 u8 ctx_upd_seq;
6460 __le16 dif_flags;
6461 __le16 tx_ref_count;
6462 __le16 last_used_ltid;
6463 __le16 parent_mr_lo;
6464 __le16 parent_mr_hi;
6465 __le32 fbo_lo;
6466 __le32 fbo_hi;
6467};
6468
6469/* The roce task context of Mstorm */
6160struct mstorm_rdma_task_st_ctx { 6470struct mstorm_rdma_task_st_ctx {
6161 struct regpair temp[4]; 6471 struct regpair temp[4];
6162}; 6472};
6163 6473
6474/* The roce task context of Ustorm */
6475struct ustorm_rdma_task_st_ctx {
6476 struct regpair temp[2];
6477};
6478
6479struct ustorm_rdma_task_ag_ctx {
6480 u8 reserved;
6481 u8 byte1;
6482 __le16 icid;
6483 u8 flags0;
6484#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6485#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6486#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6487#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6488#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6489#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
6490#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6491#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6492 u8 flags1;
6493#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6494#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6495#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6496#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6497#define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6498#define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
6499#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6500#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
6501 u8 flags2;
6502#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6503#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6504#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6505#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6506#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6507#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6508#define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6509#define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
6510#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6511#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6512#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6513#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6514#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6515#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6516#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6517#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6518 u8 flags3;
6519#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6520#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6521#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6522#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6523#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6524#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6525#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6526#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6527#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6528#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6529 __le32 dif_err_intervals;
6530 __le32 dif_error_1st_interval;
6531 __le32 reg2;
6532 __le32 dif_runt_value;
6533 __le32 reg4;
6534 __le32 reg5;
6535};
6536
6537/* RDMA task context */
6538struct rdma_task_context {
6539 struct ystorm_rdma_task_st_ctx ystorm_st_context;
6540 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
6541 struct tdif_task_context tdif_context;
6542 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
6543 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6544 struct rdif_task_context rdif_context;
6545 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6546 struct regpair ustorm_st_padding[2];
6547 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
6548};
6549
6550/* rdma function init ramrod data */
6164struct rdma_close_func_ramrod_data { 6551struct rdma_close_func_ramrod_data {
6165 u8 cnq_start_offset; 6552 u8 cnq_start_offset;
6166 u8 num_cnqs; 6553 u8 num_cnqs;
@@ -6169,6 +6556,7 @@ struct rdma_close_func_ramrod_data {
6169 u8 reserved[4]; 6556 u8 reserved[4];
6170}; 6557};
6171 6558
6559/* rdma function init CNQ parameters */
6172struct rdma_cnq_params { 6560struct rdma_cnq_params {
6173 __le16 sb_num; 6561 __le16 sb_num;
6174 u8 sb_index; 6562 u8 sb_index;
@@ -6179,6 +6567,7 @@ struct rdma_cnq_params {
6179 u8 reserved1[6]; 6567 u8 reserved1[6];
6180}; 6568};
6181 6569
6570/* rdma create cq ramrod data */
6182struct rdma_create_cq_ramrod_data { 6571struct rdma_create_cq_ramrod_data {
6183 struct regpair cq_handle; 6572 struct regpair cq_handle;
6184 struct regpair pbl_addr; 6573 struct regpair pbl_addr;
@@ -6193,21 +6582,25 @@ struct rdma_create_cq_ramrod_data {
6193 __le16 reserved1; 6582 __le16 reserved1;
6194}; 6583};
6195 6584
6585/* rdma deregister tid ramrod data */
6196struct rdma_deregister_tid_ramrod_data { 6586struct rdma_deregister_tid_ramrod_data {
6197 __le32 itid; 6587 __le32 itid;
6198 __le32 reserved; 6588 __le32 reserved;
6199}; 6589};
6200 6590
6591/* rdma destroy cq output params */
6201struct rdma_destroy_cq_output_params { 6592struct rdma_destroy_cq_output_params {
6202 __le16 cnq_num; 6593 __le16 cnq_num;
6203 __le16 reserved0; 6594 __le16 reserved0;
6204 __le32 reserved1; 6595 __le32 reserved1;
6205}; 6596};
6206 6597
6598/* rdma destroy cq ramrod data */
6207struct rdma_destroy_cq_ramrod_data { 6599struct rdma_destroy_cq_ramrod_data {
6208 struct regpair output_params_addr; 6600 struct regpair output_params_addr;
6209}; 6601};
6210 6602
6603/* RDMA slow path EQ cmd IDs */
6211enum rdma_event_opcode { 6604enum rdma_event_opcode {
6212 RDMA_EVENT_UNUSED, 6605 RDMA_EVENT_UNUSED,
6213 RDMA_EVENT_FUNC_INIT, 6606 RDMA_EVENT_FUNC_INIT,
@@ -6223,6 +6616,7 @@ enum rdma_event_opcode {
6223 MAX_RDMA_EVENT_OPCODE 6616 MAX_RDMA_EVENT_OPCODE
6224}; 6617};
6225 6618
6619/* RDMA FW return code for slow path ramrods */
6226enum rdma_fw_return_code { 6620enum rdma_fw_return_code {
6227 RDMA_RETURN_OK = 0, 6621 RDMA_RETURN_OK = 0,
6228 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 6622 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
@@ -6232,6 +6626,7 @@ enum rdma_fw_return_code {
6232 MAX_RDMA_FW_RETURN_CODE 6626 MAX_RDMA_FW_RETURN_CODE
6233}; 6627};
6234 6628
6629/* rdma function init header */
6235struct rdma_init_func_hdr { 6630struct rdma_init_func_hdr {
6236 u8 cnq_start_offset; 6631 u8 cnq_start_offset;
6237 u8 num_cnqs; 6632 u8 num_cnqs;
@@ -6241,11 +6636,13 @@ struct rdma_init_func_hdr {
6241 u8 reserved[3]; 6636 u8 reserved[3];
6242}; 6637};
6243 6638
6639/* rdma function init ramrod data */
6244struct rdma_init_func_ramrod_data { 6640struct rdma_init_func_ramrod_data {
6245 struct rdma_init_func_hdr params_header; 6641 struct rdma_init_func_hdr params_header;
6246 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 6642 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6247}; 6643};
6248 6644
6645/* RDMA ramrod command IDs */
6249enum rdma_ramrod_cmd_id { 6646enum rdma_ramrod_cmd_id {
6250 RDMA_RAMROD_UNUSED, 6647 RDMA_RAMROD_UNUSED,
6251 RDMA_RAMROD_FUNC_INIT, 6648 RDMA_RAMROD_FUNC_INIT,
@@ -6261,42 +6658,43 @@ enum rdma_ramrod_cmd_id {
6261 MAX_RDMA_RAMROD_CMD_ID 6658 MAX_RDMA_RAMROD_CMD_ID
6262}; 6659};
6263 6660
6661/* rdma register tid ramrod data */
6264struct rdma_register_tid_ramrod_data { 6662struct rdma_register_tid_ramrod_data {
6265 __le16 flags; 6663 __le16 flags;
6266#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 6664#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6267#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 6665#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6268#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 6666#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6269#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 6667#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
6270#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 6668#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6271#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 6669#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
6272#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 6670#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6273#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 6671#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
6274#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 6672#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6275#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 6673#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
6276#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 6674#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6277#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 6675#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
6278#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 6676#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6279#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 6677#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
6280#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 6678#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6281#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 6679#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
6282#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 6680#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6283#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 6681#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
6284#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 6682#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6285#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 6683#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
6286#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 6684#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6287#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 6685#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
6288 u8 flags1; 6686 u8 flags1;
6289#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 6687#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6290#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 6688#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6291#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 6689#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6292#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 6690#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
6293 u8 flags2; 6691 u8 flags2;
6294#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 6692#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6295#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 6693#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6296#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 6694#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6297#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 6695#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
6298#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 6696#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6299#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 6697#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
6300 u8 key; 6698 u8 key;
6301 u8 length_hi; 6699 u8 length_hi;
6302 u8 vf_id; 6700 u8 vf_id;
@@ -6313,19 +6711,21 @@ struct rdma_register_tid_ramrod_data {
6313 __le32 reserved4[2]; 6711 __le32 reserved4[2];
6314}; 6712};
6315 6713
6714/* rdma resize cq output params */
6316struct rdma_resize_cq_output_params { 6715struct rdma_resize_cq_output_params {
6317 __le32 old_cq_cons; 6716 __le32 old_cq_cons;
6318 __le32 old_cq_prod; 6717 __le32 old_cq_prod;
6319}; 6718};
6320 6719
6720/* rdma resize cq ramrod data */
6321struct rdma_resize_cq_ramrod_data { 6721struct rdma_resize_cq_ramrod_data {
6322 u8 flags; 6722 u8 flags;
6323#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 6723#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6324#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 6724#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6325#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 6725#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6326#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 6726#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
6327#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 6727#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
6328#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 6728#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
6329 u8 pbl_log_page_size; 6729 u8 pbl_log_page_size;
6330 __le16 pbl_num_pages; 6730 __le16 pbl_num_pages;
6331 __le32 max_cqes; 6731 __le32 max_cqes;
@@ -6333,10 +6733,12 @@ struct rdma_resize_cq_ramrod_data {
6333 struct regpair output_params_addr; 6733 struct regpair output_params_addr;
6334}; 6734};
6335 6735
6736/* The rdma storm context of Mstorm */
6336struct rdma_srq_context { 6737struct rdma_srq_context {
6337 struct regpair temp[8]; 6738 struct regpair temp[8];
6338}; 6739};
6339 6740
6741/* rdma create qp requester ramrod data */
6340struct rdma_srq_create_ramrod_data { 6742struct rdma_srq_create_ramrod_data {
6341 struct regpair pbl_base_addr; 6743 struct regpair pbl_base_addr;
6342 __le16 pages_in_srq_pbl; 6744 __le16 pages_in_srq_pbl;
@@ -6348,206 +6750,19 @@ struct rdma_srq_create_ramrod_data {
6348 struct regpair producers_addr; 6750 struct regpair producers_addr;
6349}; 6751};
6350 6752
6753/* rdma create qp requester ramrod data */
6351struct rdma_srq_destroy_ramrod_data { 6754struct rdma_srq_destroy_ramrod_data {
6352 struct rdma_srq_id srq_id; 6755 struct rdma_srq_id srq_id;
6353 __le32 reserved; 6756 __le32 reserved;
6354}; 6757};
6355 6758
6759/* rdma create qp requester ramrod data */
6356struct rdma_srq_modify_ramrod_data { 6760struct rdma_srq_modify_ramrod_data {
6357 struct rdma_srq_id srq_id; 6761 struct rdma_srq_id srq_id;
6358 __le32 wqe_limit; 6762 __le32 wqe_limit;
6359}; 6763};
6360 6764
6361struct ystorm_rdma_task_st_ctx { 6765/* RDMA Tid type enumeration (for register_tid ramrod) */
6362 struct regpair temp[4];
6363};
6364
6365struct ystorm_rdma_task_ag_ctx {
6366 u8 reserved;
6367 u8 byte1;
6368 __le16 msem_ctx_upd_seq;
6369 u8 flags0;
6370#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6371#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6372#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6373#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6374#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6375#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6376#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6377#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
6378#define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6379#define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6380 u8 flags1;
6381#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6382#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6383#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6384#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6385#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6386#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
6387#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6388#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6389#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6390#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6391 u8 flags2;
6392#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6393#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6394#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6395#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6396#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6397#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6398#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6399#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6400#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6401#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6402#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6403#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6404#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6405#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6406#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6407#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6408 u8 key;
6409 __le32 mw_cnt;
6410 u8 ref_cnt_seq;
6411 u8 ctx_upd_seq;
6412 __le16 dif_flags;
6413 __le16 tx_ref_count;
6414 __le16 last_used_ltid;
6415 __le16 parent_mr_lo;
6416 __le16 parent_mr_hi;
6417 __le32 fbo_lo;
6418 __le32 fbo_hi;
6419};
6420
6421struct mstorm_rdma_task_ag_ctx {
6422 u8 reserved;
6423 u8 byte1;
6424 __le16 icid;
6425 u8 flags0;
6426#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6427#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6428#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6429#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6430#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6431#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6432#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6433#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6434#define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6435#define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6436 u8 flags1;
6437#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6438#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6439#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6440#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6441#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6442#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6443#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6444#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6445#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6446#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6447 u8 flags2;
6448#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6449#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6450#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6451#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6452#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6453#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6454#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6455#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6456#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6457#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6458#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6459#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6460#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6461#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6462#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6463#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6464 u8 key;
6465 __le32 mw_cnt;
6466 u8 ref_cnt_seq;
6467 u8 ctx_upd_seq;
6468 __le16 dif_flags;
6469 __le16 tx_ref_count;
6470 __le16 last_used_ltid;
6471 __le16 parent_mr_lo;
6472 __le16 parent_mr_hi;
6473 __le32 fbo_lo;
6474 __le32 fbo_hi;
6475};
6476
6477struct ustorm_rdma_task_st_ctx {
6478 struct regpair temp[2];
6479};
6480
6481struct ustorm_rdma_task_ag_ctx {
6482 u8 reserved;
6483 u8 byte1;
6484 __le16 icid;
6485 u8 flags0;
6486#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6487#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6488#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6489#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6490#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6491#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
6492#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6493#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6494 u8 flags1;
6495#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6496#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6497#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6498#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6499#define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6500#define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
6501#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6502#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
6503 u8 flags2;
6504#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6505#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6506#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6507#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6508#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6509#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6510#define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6511#define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
6512#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6513#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6514#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6515#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6516#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6517#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6518#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6519#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6520 u8 flags3;
6521#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6522#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6523#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6524#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6525#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6526#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6527#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6528#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6529#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6530#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6531 __le32 dif_err_intervals;
6532 __le32 dif_error_1st_interval;
6533 __le32 reg2;
6534 __le32 dif_runt_value;
6535 __le32 reg4;
6536 __le32 reg5;
6537};
6538
6539struct rdma_task_context {
6540 struct ystorm_rdma_task_st_ctx ystorm_st_context;
6541 struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
6542 struct tdif_task_context tdif_context;
6543 struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
6544 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6545 struct rdif_task_context rdif_context;
6546 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6547 struct regpair ustorm_st_padding[2];
6548 struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
6549};
6550
6551enum rdma_tid_type { 6766enum rdma_tid_type {
6552 RDMA_TID_REGISTERED_MR, 6767 RDMA_TID_REGISTERED_MR,
6553 RDMA_TID_FMR, 6768 RDMA_TID_FMR,
@@ -6560,210 +6775,210 @@ struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
6560 u8 reserved0; 6775 u8 reserved0;
6561 u8 state; 6776 u8 state;
6562 u8 flags0; 6777 u8 flags0;
6563#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 6778#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6564#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 6779#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6565#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 6780#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
6566#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 6781#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
6567#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 6782#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
6568#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 6783#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
6569#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 6784#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6570#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 6785#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6571#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 6786#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
6572#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 6787#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
6573#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 6788#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
6574#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 6789#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
6575#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 6790#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
6576#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 6791#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
6577#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 6792#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
6578#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 6793#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
6579 u8 flags1; 6794 u8 flags1;
6580#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 6795#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
6581#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 6796#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
6582#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 6797#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
6583#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 6798#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
6584#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 6799#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
6585#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 6800#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
6586#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 6801#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6587#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 6802#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6588#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 6803#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
6589#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 6804#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
6590#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 6805#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
6591#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 6806#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
6592#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 6807#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
6593#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 6808#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
6594#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 6809#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
6595#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 6810#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
6596 u8 flags2; 6811 u8 flags2;
6597#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 6812#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6598#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 6813#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6599#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 6814#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6600#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 6815#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6601#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 6816#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6602#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 6817#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6603#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 6818#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6604#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 6819#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6605 u8 flags3; 6820 u8 flags3;
6606#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 6821#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6607#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 6822#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6608#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 6823#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6609#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 6824#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6610#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 6825#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6611#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 6826#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6612#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 6827#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
6613#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 6828#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
6614 u8 flags4; 6829 u8 flags4;
6615#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 6830#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6616#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 6831#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6617#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 6832#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6618#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 6833#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6619#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 6834#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6620#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 6835#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6621#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 6836#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6622#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 6837#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6623 u8 flags5; 6838 u8 flags5;
6624#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 6839#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6625#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 6840#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6626#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 6841#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6627#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 6842#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6628#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 6843#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6629#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 6844#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6630#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 6845#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6631#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 6846#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6632 u8 flags6; 6847 u8 flags6;
6633#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 6848#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
6634#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 6849#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
6635#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 6850#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
6636#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 6851#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
6637#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 6852#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
6638#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 6853#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
6639#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 6854#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
6640#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 6855#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
6641 u8 flags7; 6856 u8 flags7;
6642#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 6857#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
6643#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 6858#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
6644#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 6859#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
6645#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 6860#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
6646#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 6861#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6647#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 6862#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6648#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 6863#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6649#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 6864#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6650#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 6865#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6651#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 6866#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6652 u8 flags8; 6867 u8 flags8;
6653#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 6868#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6654#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 6869#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6655#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 6870#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6656#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 6871#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6657#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 6872#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6658#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 6873#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6659#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 6874#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6660#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 6875#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6661#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 6876#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6662#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 6877#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6663#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 6878#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
6664#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 6879#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
6665#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 6880#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6666#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 6881#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6667#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 6882#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6668#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 6883#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6669 u8 flags9; 6884 u8 flags9;
6670#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 6885#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6671#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 6886#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6672#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 6887#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6673#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 6888#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6674#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 6889#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6675#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 6890#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6676#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 6891#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6677#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 6892#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6678#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 6893#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6679#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 6894#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6680#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 6895#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6681#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 6896#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6682#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 6897#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
6683#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 6898#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
6684#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 6899#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
6685#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 6900#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
6686 u8 flags10; 6901 u8 flags10;
6687#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 6902#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
6688#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 6903#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
6689#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 6904#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
6690#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 6905#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
6691#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 6906#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
6692#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 6907#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
6693#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 6908#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
6694#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 6909#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
6695#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 6910#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6696#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 6911#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6697#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 6912#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
6698#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 6913#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
6699#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 6914#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
6700#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 6915#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
6701#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 6916#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
6702#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 6917#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
6703 u8 flags11; 6918 u8 flags11;
6704#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 6919#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
6705#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 6920#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
6706#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 6921#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
6707#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 6922#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
6708#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 6923#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
6709#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 6924#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
6710#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 6925#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6711#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 6926#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6712#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 6927#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6713#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 6928#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6714#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 6929#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6715#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 6930#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6716#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 6931#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6717#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 6932#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6718#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 6933#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6719#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 6934#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6720 u8 flags12; 6935 u8 flags12;
6721#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 6936#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6722#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 6937#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6723#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 6938#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6724#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 6939#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6725#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 6940#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6726#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 6941#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6727#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 6942#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6728#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 6943#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6729#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 6944#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6730#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 6945#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6731#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 6946#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6732#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 6947#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6733#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 6948#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6734#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 6949#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6735#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 6950#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6736#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 6951#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6737 u8 flags13; 6952 u8 flags13;
6738#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 6953#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6739#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 6954#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6740#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 6955#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6741#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 6956#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6742#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 6957#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6743#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 6958#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6744#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 6959#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6745#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 6960#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6746#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 6961#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6747#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 6962#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6748#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 6963#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6749#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 6964#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6750#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 6965#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6751#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 6966#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6752#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 6967#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6753#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 6968#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6754 u8 flags14; 6969 u8 flags14;
6755#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 6970#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
6756#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 6971#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
6757#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 6972#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
6758#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 6973#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
6759#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 6974#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
6760#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 6975#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
6761#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 6976#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
6762#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 6977#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
6763#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 6978#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6764#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 6979#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6765#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 6980#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
6766#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 6981#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
6767 u8 byte2; 6982 u8 byte2;
6768 __le16 physical_q0; 6983 __le16 physical_q0;
6769 __le16 word1; 6984 __le16 word1;
@@ -6787,33 +7002,33 @@ struct mstorm_rdma_conn_ag_ctx {
6787 u8 byte0; 7002 u8 byte0;
6788 u8 byte1; 7003 u8 byte1;
6789 u8 flags0; 7004 u8 flags0;
6790#define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 7005#define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
6791#define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 7006#define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
6792#define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7007#define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6793#define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7008#define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6794#define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7009#define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6795#define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 7010#define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
6796#define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7011#define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6797#define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 7012#define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
6798#define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7013#define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6799#define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 7014#define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
6800 u8 flags1; 7015 u8 flags1;
6801#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7016#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6802#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 7017#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
6803#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7018#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6804#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 7019#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
6805#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7020#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6806#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 7021#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
6807#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7022#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6808#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 7023#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
6809#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7024#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6810#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 7025#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
6811#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7026#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6812#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 7027#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
6813#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7028#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6814#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 7029#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
6815#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7030#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6816#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 7031#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
6817 __le16 word0; 7032 __le16 word0;
6818 __le16 word1; 7033 __le16 word1;
6819 __le32 reg0; 7034 __le32 reg0;
@@ -6824,85 +7039,85 @@ struct tstorm_rdma_conn_ag_ctx {
6824 u8 reserved0; 7039 u8 reserved0;
6825 u8 byte1; 7040 u8 byte1;
6826 u8 flags0; 7041 u8 flags0;
6827#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7042#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6828#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7043#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6829#define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7044#define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
6830#define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7045#define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
6831#define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 7046#define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
6832#define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 7047#define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
6833#define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 7048#define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
6834#define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 7049#define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
6835#define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 7050#define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
6836#define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 7051#define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
6837#define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 7052#define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
6838#define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 7053#define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
6839#define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7054#define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
6840#define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 7055#define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
6841 u8 flags1; 7056 u8 flags1;
6842#define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7057#define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6843#define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 7058#define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
6844#define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7059#define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6845#define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 7060#define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
6846#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 7061#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6847#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 7062#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
6848#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7063#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6849#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7064#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
6850 u8 flags2; 7065 u8 flags2;
6851#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7066#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6852#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7067#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6853#define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 7068#define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6854#define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 7069#define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
6855#define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 7070#define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
6856#define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 7071#define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
6857#define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 7072#define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
6858#define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 7073#define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
6859 u8 flags3; 7074 u8 flags3;
6860#define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 7075#define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
6861#define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 7076#define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
6862#define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 7077#define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
6863#define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 7078#define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
6864#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7079#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
6865#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 7080#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
6866#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7081#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6867#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 7082#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
6868#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7083#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6869#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 7084#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
6870#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 7085#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6871#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 7086#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
6872 u8 flags4; 7087 u8 flags4;
6873#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7088#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6874#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7089#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6875#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7090#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6876#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 7091#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
6877#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7092#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6878#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 7093#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
6879#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 7094#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
6880#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 7095#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
6881#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 7096#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
6882#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 7097#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
6883#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 7098#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
6884#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 7099#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
6885#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 7100#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
6886#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 7101#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
6887#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7102#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
6888#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 7103#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
6889 u8 flags5; 7104 u8 flags5;
6890#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7105#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
6891#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 7106#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
6892#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7107#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6893#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 7108#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
6894#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7109#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6895#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 7110#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
6896#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7111#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6897#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 7112#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
6898#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7113#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6899#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 7114#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
6900#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7115#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6901#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 7116#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
6902#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7117#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6903#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 7118#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
6904#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 7119#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6905#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 7120#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
6906 __le32 reg0; 7121 __le32 reg0;
6907 __le32 reg1; 7122 __le32 reg1;
6908 __le32 reg2; 7123 __le32 reg2;
@@ -6929,68 +7144,68 @@ struct tstorm_rdma_task_ag_ctx {
6929 u8 byte1; 7144 u8 byte1;
6930 __le16 word0; 7145 __le16 word0;
6931 u8 flags0; 7146 u8 flags0;
6932#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF 7147#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6933#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 7148#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6934#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 7149#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6935#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 7150#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
6936#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 7151#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6937#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 7152#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6938#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 7153#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6939#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 7154#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6940#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 7155#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6941#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 7156#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
6942 u8 flags1; 7157 u8 flags1;
6943#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 7158#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6944#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 7159#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6945#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 7160#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6946#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 7161#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
6947#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 7162#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6948#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 7163#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
6949#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 7164#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6950#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 7165#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
6951#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 7166#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6952#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 7167#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
6953 u8 flags2; 7168 u8 flags2;
6954#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 7169#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6955#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 7170#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6956#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 7171#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6957#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 7172#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
6958#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 7173#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6959#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 7174#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
6960#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 7175#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6961#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 7176#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
6962 u8 flags3; 7177 u8 flags3;
6963#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 7178#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6964#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 7179#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6965#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 7180#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6966#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 7181#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
6967#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 7182#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6968#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 7183#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
6969#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 7184#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6970#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 7185#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
6971#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 7186#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6972#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 7187#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
6973#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 7188#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6974#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 7189#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
6975#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 7190#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6976#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 7191#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
6977 u8 flags4; 7192 u8 flags4;
6978#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 7193#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6979#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 7194#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6980#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 7195#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6981#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 7196#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
6982#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 7197#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6983#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 7198#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
6984#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 7199#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6985#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 7200#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
6986#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 7201#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6987#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 7202#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
6988#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 7203#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6989#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 7204#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
6990#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 7205#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6991#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 7206#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
6992#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 7207#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6993#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 7208#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
6994 u8 byte2; 7209 u8 byte2;
6995 __le16 word1; 7210 __le16 word1;
6996 __le32 reg0; 7211 __le32 reg0;
@@ -7007,59 +7222,59 @@ struct ustorm_rdma_conn_ag_ctx {
7007 u8 reserved; 7222 u8 reserved;
7008 u8 byte1; 7223 u8 byte1;
7009 u8 flags0; 7224 u8 flags0;
7010#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7225#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7011#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7226#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7012#define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7227#define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7013#define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7228#define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7014#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7229#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7015#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 7230#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
7016#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7231#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7017#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 7232#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7018#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7233#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7019#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 7234#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7020 u8 flags1; 7235 u8 flags1;
7021#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 7236#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7022#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 7237#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7023#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 7238#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7024#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 7239#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
7025#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 7240#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7026#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 7241#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
7027#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 7242#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7028#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 7243#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
7029 u8 flags2; 7244 u8 flags2;
7030#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7245#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7031#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7246#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7032#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7247#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7033#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 7248#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7034#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7249#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7035#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 7250#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7036#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 7251#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7037#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 7252#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
7038#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 7253#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7039#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 7254#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
7040#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 7255#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7041#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 7256#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
7042#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7257#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7043#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 7258#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
7044#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 7259#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7045#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 7260#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
7046 u8 flags3; 7261 u8 flags3;
7047#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 7262#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7048#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 7263#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7049#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7264#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7050#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 7265#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7051#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7266#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7052#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 7267#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7053#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7268#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7054#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 7269#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7055#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7270#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7056#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 7271#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7057#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7272#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7058#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 7273#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7059#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7274#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7060#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 7275#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7061#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 7276#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7062#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 7277#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
7063 u8 byte2; 7278 u8 byte2;
7064 u8 byte3; 7279 u8 byte3;
7065 __le16 conn_dpi; 7280 __le16 conn_dpi;
@@ -7076,210 +7291,210 @@ struct xstorm_rdma_conn_ag_ctx {
7076 u8 reserved0; 7291 u8 reserved0;
7077 u8 state; 7292 u8 state;
7078 u8 flags0; 7293 u8 flags0;
7079#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7294#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7080#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7295#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7081#define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7296#define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7082#define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7297#define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7083#define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 7298#define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
7084#define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 7299#define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
7085#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 7300#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7086#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 7301#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7087#define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 7302#define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
7088#define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 7303#define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
7089#define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 7304#define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
7090#define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 7305#define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
7091#define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 7306#define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
7092#define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 7307#define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
7093#define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 7308#define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
7094#define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 7309#define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
7095 u8 flags1; 7310 u8 flags1;
7096#define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 7311#define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
7097#define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 7312#define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
7098#define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 7313#define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
7099#define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 7314#define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
7100#define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 7315#define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
7101#define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 7316#define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
7102#define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 7317#define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
7103#define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 7318#define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
7104#define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 7319#define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
7105#define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 7320#define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
7106#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7321#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7107#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 7322#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
7108#define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 7323#define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
7109#define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 7324#define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
7110#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 7325#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7111#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 7326#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7112 u8 flags2; 7327 u8 flags2;
7113#define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7328#define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7114#define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 7329#define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
7115#define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7330#define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7116#define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 7331#define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
7117#define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7332#define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7118#define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 7333#define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
7119#define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 7334#define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7120#define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 7335#define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
7121 u8 flags3; 7336 u8 flags3;
7122#define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 7337#define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
7123#define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 7338#define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
7124#define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 7339#define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
7125#define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 7340#define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
7126#define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 7341#define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7127#define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 7342#define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
7128#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7343#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7129#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7344#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7130 u8 flags4; 7345 u8 flags4;
7131#define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 7346#define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
7132#define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 7347#define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
7133#define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 7348#define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
7134#define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 7349#define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
7135#define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 7350#define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
7136#define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 7351#define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
7137#define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 7352#define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
7138#define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 7353#define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
7139 u8 flags5; 7354 u8 flags5;
7140#define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 7355#define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
7141#define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 7356#define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
7142#define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 7357#define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
7143#define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 7358#define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
7144#define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 7359#define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
7145#define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 7360#define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
7146#define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 7361#define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
7147#define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 7362#define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
7148 u8 flags6; 7363 u8 flags6;
7149#define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 7364#define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
7150#define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 7365#define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
7151#define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 7366#define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
7152#define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 7367#define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
7153#define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 7368#define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
7154#define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 7369#define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
7155#define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 7370#define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
7156#define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 7371#define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
7157 u8 flags7; 7372 u8 flags7;
7158#define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 7373#define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
7159#define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 7374#define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
7160#define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 7375#define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
7161#define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 7376#define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
7162#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7377#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7163#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7378#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7164#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7379#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7165#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 7380#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
7166#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7381#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7167#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 7382#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
7168 u8 flags8; 7383 u8 flags8;
7169#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7384#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7170#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 7385#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
7171#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 7386#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7172#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 7387#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
7173#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 7388#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
7174#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 7389#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
7175#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 7390#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
7176#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 7391#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
7177#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7392#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7178#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 7393#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
7179#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7394#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7180#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 7395#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7181#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 7396#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
7182#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 7397#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
7183#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 7398#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
7184#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 7399#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
7185 u8 flags9; 7400 u8 flags9;
7186#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 7401#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
7187#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 7402#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
7188#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 7403#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
7189#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 7404#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
7190#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 7405#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
7191#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 7406#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
7192#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 7407#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
7193#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 7408#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
7194#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 7409#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
7195#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 7410#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
7196#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 7411#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
7197#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 7412#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
7198#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 7413#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
7199#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 7414#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
7200#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 7415#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
7201#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 7416#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
7202 u8 flags10; 7417 u8 flags10;
7203#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 7418#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
7204#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 7419#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
7205#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 7420#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
7206#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 7421#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
7207#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 7422#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
7208#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 7423#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
7209#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 7424#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
7210#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 7425#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
7211#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7426#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7212#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7427#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7213#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 7428#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
7214#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 7429#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
7215#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7430#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7216#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 7431#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
7217#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7432#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7218#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 7433#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
7219 u8 flags11; 7434 u8 flags11;
7220#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7435#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7221#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 7436#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
7222#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7437#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7223#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 7438#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
7224#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7439#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7225#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 7440#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
7226#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7441#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7227#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 7442#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
7228#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7443#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7229#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 7444#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
7230#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7445#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7231#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 7446#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
7232#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7447#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7233#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7448#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7234#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 7449#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
7235#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 7450#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
7236 u8 flags12; 7451 u8 flags12;
7237#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 7452#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
7238#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 7453#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
7239#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 7454#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
7240#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 7455#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
7241#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7456#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7242#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7457#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7243#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7458#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7244#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7459#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7245#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 7460#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
7246#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 7461#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
7247#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 7462#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
7248#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 7463#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
7249#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 7464#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
7250#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 7465#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
7251#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 7466#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
7252#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 7467#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
7253 u8 flags13; 7468 u8 flags13;
7254#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 7469#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
7255#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 7470#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
7256#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 7471#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
7257#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 7472#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
7258#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 7473#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7259#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 7474#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7260#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 7475#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7261#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 7476#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7262#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7477#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7263#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7478#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7264#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 7479#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7265#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 7480#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7266#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7481#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7267#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7482#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7268#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7483#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7269#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7484#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7270 u8 flags14; 7485 u8 flags14;
7271#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 7486#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
7272#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 7487#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
7273#define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 7488#define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
7274#define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 7489#define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
7275#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 7490#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7276#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 7491#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7277#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 7492#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
7278#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 7493#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
7279#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 7494#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7280#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 7495#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7281#define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 7496#define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
7282#define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 7497#define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
7283 u8 byte2; 7498 u8 byte2;
7284 __le16 physical_q0; 7499 __le16 physical_q0;
7285 __le16 word1; 7500 __le16 word1;
@@ -7305,33 +7520,33 @@ struct ystorm_rdma_conn_ag_ctx {
7305 u8 byte0; 7520 u8 byte0;
7306 u8 byte1; 7521 u8 byte1;
7307 u8 flags0; 7522 u8 flags0;
7308#define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 7523#define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
7309#define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 7524#define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
7310#define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7525#define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
7311#define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7526#define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
7312#define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7527#define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
7313#define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 7528#define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
7314#define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7529#define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7315#define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 7530#define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7316#define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7531#define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7317#define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 7532#define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7318 u8 flags1; 7533 u8 flags1;
7319#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7534#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
7320#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 7535#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
7321#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7536#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7322#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 7537#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7323#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7538#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7324#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 7539#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7325#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7540#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
7326#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 7541#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
7327#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7542#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
7328#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 7543#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
7329#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7544#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7330#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 7545#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
7331#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7546#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7332#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 7547#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
7333#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7548#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7334#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 7549#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
7335 u8 byte2; 7550 u8 byte2;
7336 u8 byte3; 7551 u8 byte3;
7337 __le16 word0; 7552 __le16 word0;
@@ -7345,30 +7560,37 @@ struct ystorm_rdma_conn_ag_ctx {
7345 __le32 reg3; 7560 __le32 reg3;
7346}; 7561};
7347 7562
7348struct mstorm_roce_conn_st_ctx { 7563/* The roce storm context of Ystorm */
7349 struct regpair temp[6]; 7564struct ystorm_roce_conn_st_ctx {
7565 struct regpair temp[2];
7350}; 7566};
7351 7567
7568/* The roce storm context of Mstorm */
7352struct pstorm_roce_conn_st_ctx { 7569struct pstorm_roce_conn_st_ctx {
7353 struct regpair temp[16]; 7570 struct regpair temp[16];
7354}; 7571};
7355 7572
7356struct ystorm_roce_conn_st_ctx { 7573/* The roce storm context of Xstorm */
7357 struct regpair temp[2];
7358};
7359
7360struct xstorm_roce_conn_st_ctx { 7574struct xstorm_roce_conn_st_ctx {
7361 struct regpair temp[24]; 7575 struct regpair temp[24];
7362}; 7576};
7363 7577
7578/* The roce storm context of Tstorm */
7364struct tstorm_roce_conn_st_ctx { 7579struct tstorm_roce_conn_st_ctx {
7365 struct regpair temp[30]; 7580 struct regpair temp[30];
7366}; 7581};
7367 7582
7583/* The roce storm context of Mstorm */
7584struct mstorm_roce_conn_st_ctx {
7585 struct regpair temp[6];
7586};
7587
7588/* The roce storm context of Ystorm */
7368struct ustorm_roce_conn_st_ctx { 7589struct ustorm_roce_conn_st_ctx {
7369 struct regpair temp[12]; 7590 struct regpair temp[12];
7370}; 7591};
7371 7592
7593/* roce connection context */
7372struct roce_conn_context { 7594struct roce_conn_context {
7373 struct ystorm_roce_conn_st_ctx ystorm_st_context; 7595 struct ystorm_roce_conn_st_ctx ystorm_st_context;
7374 struct regpair ystorm_st_padding[2]; 7596 struct regpair ystorm_st_padding[2];
@@ -7385,22 +7607,23 @@ struct roce_conn_context {
7385 struct regpair ustorm_st_padding[2]; 7607 struct regpair ustorm_st_padding[2];
7386}; 7608};
7387 7609
7610/* roce create qp requester ramrod data */
7388struct roce_create_qp_req_ramrod_data { 7611struct roce_create_qp_req_ramrod_data {
7389 __le16 flags; 7612 __le16 flags;
7390#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7613#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7391#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7614#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7392#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 7615#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
7393#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 7616#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
7394#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 7617#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
7395#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 7618#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
7396#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7619#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7397#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 7620#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
7398#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1 7621#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
7399#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7 7622#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
7400#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7623#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7401#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 7624#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
7402#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7625#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7403#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 7626#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
7404 u8 max_ord; 7627 u8 max_ord;
7405 u8 traffic_class; 7628 u8 traffic_class;
7406 u8 hop_limit; 7629 u8 hop_limit;
@@ -7431,26 +7654,27 @@ struct roce_create_qp_req_ramrod_data {
7431 __le16 dpi; 7654 __le16 dpi;
7432}; 7655};
7433 7656
7657/* roce create qp responder ramrod data */
7434struct roce_create_qp_resp_ramrod_data { 7658struct roce_create_qp_resp_ramrod_data {
7435 __le16 flags; 7659 __le16 flags;
7436#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7660#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7437#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7661#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7438#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7662#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7439#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 7663#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
7440#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7664#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7441#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 7665#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
7442#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7666#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7443#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 7667#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
7444#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 7668#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7445#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 7669#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
7446#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 7670#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7447#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 7671#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
7448#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 7672#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7449#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 7673#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
7450#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7674#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7451#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 7675#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
7452#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7676#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7453#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 7677#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
7454 u8 max_ird; 7678 u8 max_ird;
7455 u8 traffic_class; 7679 u8 traffic_class;
7456 u8 hop_limit; 7680 u8 hop_limit;
@@ -7482,24 +7706,29 @@ struct roce_create_qp_resp_ramrod_data {
7482 __le16 dpi; 7706 __le16 dpi;
7483}; 7707};
7484 7708
7709/* RoCE destroy qp requester output params */
7485struct roce_destroy_qp_req_output_params { 7710struct roce_destroy_qp_req_output_params {
7486 __le32 num_bound_mw; 7711 __le32 num_bound_mw;
7487 __le32 cq_prod; 7712 __le32 cq_prod;
7488}; 7713};
7489 7714
7715/* RoCE destroy qp requester ramrod data */
7490struct roce_destroy_qp_req_ramrod_data { 7716struct roce_destroy_qp_req_ramrod_data {
7491 struct regpair output_params_addr; 7717 struct regpair output_params_addr;
7492}; 7718};
7493 7719
7720/* RoCE destroy qp responder output params */
7494struct roce_destroy_qp_resp_output_params { 7721struct roce_destroy_qp_resp_output_params {
7495 __le32 num_invalidated_mw; 7722 __le32 num_invalidated_mw;
7496 __le32 cq_prod; 7723 __le32 cq_prod;
7497}; 7724};
7498 7725
7726/* RoCE destroy qp responder ramrod data */
7499struct roce_destroy_qp_resp_ramrod_data { 7727struct roce_destroy_qp_resp_ramrod_data {
7500 struct regpair output_params_addr; 7728 struct regpair output_params_addr;
7501}; 7729};
7502 7730
7731/* roce special events statistics */
7503struct roce_events_stats { 7732struct roce_events_stats {
7504 __le16 silent_drops; 7733 __le16 silent_drops;
7505 __le16 rnr_naks_sent; 7734 __le16 rnr_naks_sent;
@@ -7508,6 +7737,7 @@ struct roce_events_stats {
7508 __le32 reserved; 7737 __le32 reserved;
7509}; 7738};
7510 7739
7740/* ROCE slow path EQ cmd IDs */
7511enum roce_event_opcode { 7741enum roce_event_opcode {
7512 ROCE_EVENT_CREATE_QP = 11, 7742 ROCE_EVENT_CREATE_QP = 11,
7513 ROCE_EVENT_MODIFY_QP, 7743 ROCE_EVENT_MODIFY_QP,
@@ -7518,6 +7748,7 @@ enum roce_event_opcode {
7518 MAX_ROCE_EVENT_OPCODE 7748 MAX_ROCE_EVENT_OPCODE
7519}; 7749};
7520 7750
7751/* roce func init ramrod data */
7521struct roce_init_func_params { 7752struct roce_init_func_params {
7522 u8 ll2_queue_id; 7753 u8 ll2_queue_id;
7523 u8 cnp_vlan_priority; 7754 u8 cnp_vlan_priority;
@@ -7526,42 +7757,44 @@ struct roce_init_func_params {
7526 __le32 cnp_send_timeout; 7757 __le32 cnp_send_timeout;
7527}; 7758};
7528 7759
7760/* roce func init ramrod data */
7529struct roce_init_func_ramrod_data { 7761struct roce_init_func_ramrod_data {
7530 struct rdma_init_func_ramrod_data rdma; 7762 struct rdma_init_func_ramrod_data rdma;
7531 struct roce_init_func_params roce; 7763 struct roce_init_func_params roce;
7532}; 7764};
7533 7765
7766/* roce modify qp requester ramrod data */
7534struct roce_modify_qp_req_ramrod_data { 7767struct roce_modify_qp_req_ramrod_data {
7535 __le16 flags; 7768 __le16 flags;
7536#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7769#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7537#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7770#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7538#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 7771#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7539#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 7772#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7540#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 7773#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7541#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 7774#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7542#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7775#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7543#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 7776#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7544#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7777#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7545#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 7778#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7546#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 7779#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7547#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 7780#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7548#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 7781#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7549#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 7782#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7550#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 7783#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7551#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 7784#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7552#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 7785#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7553#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 7786#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7554#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 7787#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7555#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 7788#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7556#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7789#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7557#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 7790#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7558#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7 7791#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
7559#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13 7792#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
7560 u8 fields; 7793 u8 fields;
7561#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7794#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7562#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 7795#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7563#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7796#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7564#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 7797#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
7565 u8 max_ord; 7798 u8 max_ord;
7566 u8 traffic_class; 7799 u8 traffic_class;
7567 u8 hop_limit; 7800 u8 hop_limit;
@@ -7575,35 +7808,36 @@ struct roce_modify_qp_req_ramrod_data {
7575 __le32 dst_gid[4]; 7808 __le32 dst_gid[4];
7576}; 7809};
7577 7810
7811/* roce modify qp responder ramrod data */
7578struct roce_modify_qp_resp_ramrod_data { 7812struct roce_modify_qp_resp_ramrod_data {
7579 __le16 flags; 7813 __le16 flags;
7580#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7814#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7581#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7815#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7582#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7816#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7583#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 7817#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7584#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7818#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7585#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 7819#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7586#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7820#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7587#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 7821#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7588#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7822#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7589#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 7823#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7590#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7824#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7591#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 7825#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7592#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 7826#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7593#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 7827#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7594#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 7828#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7595#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 7829#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7596#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 7830#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7597#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 7831#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7598#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 7832#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7599#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 7833#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7600#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F 7834#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
7601#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10 7835#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
7602 u8 fields; 7836 u8 fields;
7603#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7837#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7604#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 7838#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7605#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7839#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7606#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 7840#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7607 u8 max_ird; 7841 u8 max_ird;
7608 u8 traffic_class; 7842 u8 traffic_class;
7609 u8 hop_limit; 7843 u8 hop_limit;
@@ -7615,21 +7849,24 @@ struct roce_modify_qp_resp_ramrod_data {
7615 __le32 dst_gid[4]; 7849 __le32 dst_gid[4];
7616}; 7850};
7617 7851
7852/* RoCE query qp requester output params */
7618struct roce_query_qp_req_output_params { 7853struct roce_query_qp_req_output_params {
7619 __le32 psn; 7854 __le32 psn;
7620 __le32 flags; 7855 __le32 flags;
7621#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 7856#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7622#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 7857#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7623#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 7858#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7624#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 7859#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7625#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 7860#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7626#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 7861#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7627}; 7862};
7628 7863
7864/* RoCE query qp requester ramrod data */
7629struct roce_query_qp_req_ramrod_data { 7865struct roce_query_qp_req_ramrod_data {
7630 struct regpair output_params_addr; 7866 struct regpair output_params_addr;
7631}; 7867};
7632 7868
7869/* RoCE query qp responder output params */
7633struct roce_query_qp_resp_output_params { 7870struct roce_query_qp_resp_output_params {
7634 __le32 psn; 7871 __le32 psn;
7635 __le32 err_flag; 7872 __le32 err_flag;
@@ -7639,10 +7876,12 @@ struct roce_query_qp_resp_output_params {
7639#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 7876#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7640}; 7877};
7641 7878
7879/* RoCE query qp responder ramrod data */
7642struct roce_query_qp_resp_ramrod_data { 7880struct roce_query_qp_resp_ramrod_data {
7643 struct regpair output_params_addr; 7881 struct regpair output_params_addr;
7644}; 7882};
7645 7883
7884/* ROCE ramrod command IDs */
7646enum roce_ramrod_cmd_id { 7885enum roce_ramrod_cmd_id {
7647 ROCE_RAMROD_CREATE_QP = 11, 7886 ROCE_RAMROD_CREATE_QP = 11,
7648 ROCE_RAMROD_MODIFY_QP, 7887 ROCE_RAMROD_MODIFY_QP,
@@ -7657,33 +7896,33 @@ struct mstorm_roce_req_conn_ag_ctx {
7657 u8 byte0; 7896 u8 byte0;
7658 u8 byte1; 7897 u8 byte1;
7659 u8 flags0; 7898 u8 flags0;
7660#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 7899#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7661#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 7900#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7662#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 7901#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7663#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 7902#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7664#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 7903#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7665#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 7904#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7666#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7905#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7667#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 7906#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7668#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 7907#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7669#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 7908#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7670 u8 flags1; 7909 u8 flags1;
7671#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7910#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7672#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 7911#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7673#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7912#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7674#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 7913#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7675#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7914#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7676#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 7915#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7677#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7916#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7678#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 7917#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
7679#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7918#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7680#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 7919#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
7681#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7920#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7682#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 7921#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
7683#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7922#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7684#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 7923#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
7685#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7924#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7686#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 7925#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
7687 __le16 word0; 7926 __le16 word0;
7688 __le16 word1; 7927 __le16 word1;
7689 __le32 reg0; 7928 __le32 reg0;
@@ -7694,33 +7933,33 @@ struct mstorm_roce_resp_conn_ag_ctx {
7694 u8 byte0; 7933 u8 byte0;
7695 u8 byte1; 7934 u8 byte1;
7696 u8 flags0; 7935 u8 flags0;
7697#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 7936#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7698#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 7937#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7699#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 7938#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7700#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 7939#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
7701#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7940#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7702#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 7941#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
7703#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7942#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7704#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 7943#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
7705#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7944#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7706#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 7945#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
7707 u8 flags1; 7946 u8 flags1;
7708#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7947#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7709#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 7948#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7710#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7949#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7711#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 7950#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
7712#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7951#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7713#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 7952#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
7714#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7953#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7715#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 7954#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
7716#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7955#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7717#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 7956#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
7718#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7957#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7719#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 7958#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
7720#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7959#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7721#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 7960#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
7722#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7961#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7723#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 7962#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
7724 __le16 word0; 7963 __le16 word0;
7725 __le16 word1; 7964 __le16 word1;
7726 __le32 reg0; 7965 __le32 reg0;
@@ -7731,85 +7970,85 @@ struct tstorm_roce_req_conn_ag_ctx {
7731 u8 reserved0; 7970 u8 reserved0;
7732 u8 state; 7971 u8 state;
7733 u8 flags0; 7972 u8 flags0;
7734#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7973#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7735#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7974#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7736#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 7975#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7737#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 7976#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
7738#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 7977#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7739#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 7978#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
7740#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 7979#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7741#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 7980#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
7742#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7981#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7743#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 7982#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7744#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 7983#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7745#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 7984#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
7746#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 7985#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7747#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 7986#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
7748 u8 flags1; 7987 u8 flags1;
7749#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7988#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7750#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 7989#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
7751#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 7990#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7752#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 7991#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
7753#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 7992#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7754#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 7993#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7755#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7994#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7756#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7995#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7757 u8 flags2; 7996 u8 flags2;
7758#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7997#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7759#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7998#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7760#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 7999#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7761#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 8000#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
7762#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 8001#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7763#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 8002#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
7764#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 8003#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7765#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 8004#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
7766 u8 flags3; 8005 u8 flags3;
7767#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 8006#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7768#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 8007#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7769#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 8008#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7770#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 8009#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
7771#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 8010#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7772#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 8011#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
7773#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8012#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7774#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 8013#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
7775#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 8014#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7776#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 8015#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
7777#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 8016#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7778#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 8017#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7779 u8 flags4; 8018 u8 flags4;
7780#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8019#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7781#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 8020#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7782#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 8021#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7783#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 8022#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7784#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 8023#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7785#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 8024#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
7786#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 8025#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7787#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 8026#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
7788#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 8027#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7789#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 8028#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
7790#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 8029#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7791#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 8030#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
7792#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 8031#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7793#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 8032#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
7794#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8033#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7795#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 8034#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7796 u8 flags5; 8035 u8 flags5;
7797#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8036#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7798#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 8037#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7799#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8038#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7800#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 8039#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7801#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8040#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7802#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 8041#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7803#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8042#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7804#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 8043#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7805#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8044#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7806#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 8045#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7807#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 8046#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7808#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 8047#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
7809#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 8048#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7810#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 8049#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7811#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 8050#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7812#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 8051#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7813 __le32 reg0; 8052 __le32 reg0;
7814 __le32 snd_nxt_psn; 8053 __le32 snd_nxt_psn;
7815 __le32 snd_max_psn; 8054 __le32 snd_max_psn;
@@ -7835,85 +8074,85 @@ struct tstorm_roce_resp_conn_ag_ctx {
7835 u8 byte0; 8074 u8 byte0;
7836 u8 state; 8075 u8 state;
7837 u8 flags0; 8076 u8 flags0;
7838#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8077#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7839#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8078#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7840#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 8079#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7841#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 8080#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
7842#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 8081#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7843#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 8082#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
7844#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 8083#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7845#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 8084#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
7846#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 8085#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7847#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 8086#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
7848#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 8087#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7849#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 8088#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
7850#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8089#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7851#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 8090#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
7852 u8 flags1; 8091 u8 flags1;
7853#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8092#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7854#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 8093#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7855#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 8094#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7856#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 8095#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
7857#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8096#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7858#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 8097#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
7859#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8098#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7860#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8099#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7861 u8 flags2; 8100 u8 flags2;
7862#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 8101#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7863#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 8102#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7864#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 8103#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7865#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 8104#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
7866#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 8105#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7867#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 8106#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
7868#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 8107#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7869#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 8108#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
7870 u8 flags3; 8109 u8 flags3;
7871#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 8110#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7872#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 8111#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7873#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 8112#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7874#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 8113#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
7875#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8114#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7876#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 8115#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
7877#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8116#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7878#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 8117#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
7879#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 8118#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7880#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 8119#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
7881#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8120#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7882#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 8121#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
7883 u8 flags4; 8122 u8 flags4;
7884#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8123#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7885#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 8124#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7886#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 8125#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7887#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 8126#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
7888#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8127#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7889#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 8128#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
7890#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 8129#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7891#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 8130#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
7892#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 8131#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7893#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 8132#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
7894#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 8133#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7895#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 8134#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
7896#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 8135#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7897#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 8136#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
7898#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8137#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7899#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 8138#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
7900 u8 flags5; 8139 u8 flags5;
7901#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8140#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7902#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8141#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7903#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8142#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7904#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8143#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
7905#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8144#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7906#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8145#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
7907#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8146#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7908#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8147#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
7909#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8148#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7910#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8149#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
7911#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 8150#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7912#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 8151#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
7913#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8152#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7914#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8153#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
7915#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8154#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
7916#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 8155#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
7917 __le32 psn_and_rxmit_id_echo; 8156 __le32 psn_and_rxmit_id_echo;
7918 __le32 reg1; 8157 __le32 reg1;
7919 __le32 reg2; 8158 __le32 reg2;
@@ -7939,59 +8178,59 @@ struct ustorm_roce_req_conn_ag_ctx {
7939 u8 byte0; 8178 u8 byte0;
7940 u8 byte1; 8179 u8 byte1;
7941 u8 flags0; 8180 u8 flags0;
7942#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8181#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7943#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8182#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7944#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8183#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7945#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8184#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
7946#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8185#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7947#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8186#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
7948#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8187#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7949#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8188#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
7950#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8189#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7951#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 8190#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
7952 u8 flags1; 8191 u8 flags1;
7953#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8192#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
7954#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 8193#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
7955#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 8194#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
7956#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 8195#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
7957#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 8196#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
7958#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 8197#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
7959#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 8198#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
7960#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 8199#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
7961 u8 flags2; 8200 u8 flags2;
7962#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8201#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7963#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8202#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7964#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8203#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7965#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8204#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
7966#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8205#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7967#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8206#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
7968#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8207#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
7969#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 8208#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
7970#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 8209#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
7971#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 8210#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
7972#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 8211#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
7973#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 8212#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
7974#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 8213#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
7975#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 8214#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
7976#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8215#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7977#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 8216#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
7978 u8 flags3; 8217 u8 flags3;
7979#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8218#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7980#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 8219#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7981#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8220#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7982#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 8221#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
7983#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8222#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7984#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 8223#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
7985#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8224#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7986#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 8225#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
7987#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8226#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7988#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 8227#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
7989#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8228#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
7990#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 8229#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
7991#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 8230#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7992#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 8231#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
7993#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 8232#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7994#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 8233#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
7995 u8 byte2; 8234 u8 byte2;
7996 u8 byte3; 8235 u8 byte3;
7997 __le16 word0; 8236 __le16 word0;
@@ -8008,59 +8247,59 @@ struct ustorm_roce_resp_conn_ag_ctx {
8008 u8 byte0; 8247 u8 byte0;
8009 u8 byte1; 8248 u8 byte1;
8010 u8 flags0; 8249 u8 flags0;
8011#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8250#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8012#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8251#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8013#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8252#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8014#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8253#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8015#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8254#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8016#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8255#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8017#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8256#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8018#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8257#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8019#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8258#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8020#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 8259#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8021 u8 flags1; 8260 u8 flags1;
8022#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8261#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8023#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 8262#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8024#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 8263#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8025#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 8264#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
8026#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 8265#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8027#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 8266#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
8028#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 8267#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8029#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 8268#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
8030 u8 flags2; 8269 u8 flags2;
8031#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8270#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8032#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8271#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8033#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8272#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8034#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8273#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8035#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8274#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8036#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8275#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8037#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8276#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8038#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 8277#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
8039#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 8278#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8040#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 8279#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
8041#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 8280#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8042#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 8281#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
8043#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8282#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8044#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 8283#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
8045#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8284#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8046#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 8285#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8047 u8 flags3; 8286 u8 flags3;
8048#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8287#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8049#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8288#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8050#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8289#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8051#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8290#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8052#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8291#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8053#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8292#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8054#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8293#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8055#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8294#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8056#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8295#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8057#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8296#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8058#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8297#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8059#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 8298#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
8060#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8299#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8061#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8300#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8062#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8301#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8063#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 8302#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8064 u8 byte2; 8303 u8 byte2;
8065 u8 byte3; 8304 u8 byte3;
8066 __le16 word0; 8305 __le16 word0;
@@ -8077,210 +8316,210 @@ struct xstorm_roce_req_conn_ag_ctx {
8077 u8 reserved0; 8316 u8 reserved0;
8078 u8 state; 8317 u8 state;
8079 u8 flags0; 8318 u8 flags0;
8080#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8319#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8081#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8320#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8082#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 8321#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8083#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 8322#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
8084#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 8323#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8085#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 8324#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
8086#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8325#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8087#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8326#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8088#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 8327#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8089#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 8328#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
8090#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 8329#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8091#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 8330#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
8092#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 8331#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8093#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 8332#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
8094#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 8333#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8095#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 8334#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
8096 u8 flags1; 8335 u8 flags1;
8097#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 8336#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8098#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 8337#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8099#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 8338#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8100#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 8339#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
8101#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 8340#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8102#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 8341#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8103#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 8342#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8104#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 8343#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8105#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 8344#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
8106#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 8345#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
8107#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 8346#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
8108#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 8347#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
8109#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8348#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8110#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8349#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8111#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8350#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8112#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 8351#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8113 u8 flags2; 8352 u8 flags2;
8114#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8353#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8115#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 8354#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8116#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8355#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8117#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 8356#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
8118#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8357#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8119#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 8358#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
8120#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8359#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8121#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 8360#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
8122 u8 flags3; 8361 u8 flags3;
8123#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8362#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8124#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 8363#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8125#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8364#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8126#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8365#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8127#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 8366#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8128#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 8367#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
8129#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8368#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8130#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8369#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8131 u8 flags4; 8370 u8 flags4;
8132#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 8371#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
8133#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 8372#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
8134#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 8373#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
8135#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 8374#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
8136#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 8375#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8137#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 8376#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
8138#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 8377#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8139#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 8378#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
8140 u8 flags5; 8379 u8 flags5;
8141#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 8380#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8142#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 8381#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8143#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 8382#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8144#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 8383#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
8145#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 8384#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8146#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 8385#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
8147#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 8386#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8148#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 8387#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
8149 u8 flags6; 8388 u8 flags6;
8150#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 8389#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8151#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 8390#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8152#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 8391#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8153#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 8392#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
8154#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 8393#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8155#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 8394#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
8156#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 8395#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8157#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 8396#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
8158 u8 flags7; 8397 u8 flags7;
8159#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 8398#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8160#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 8399#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8161#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 8400#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8162#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 8401#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
8163#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8402#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8164#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8403#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8165#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8404#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8166#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 8405#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
8167#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8406#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8168#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 8407#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
8169 u8 flags8; 8408 u8 flags8;
8170#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8409#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8171#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 8410#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8172#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8411#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8173#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 8412#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
8174#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8413#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8175#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 8414#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
8176#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8415#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8177#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8416#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8178#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 8417#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8179#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 8418#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
8180#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8419#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8181#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8420#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8182#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 8421#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
8183#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 8422#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
8184#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 8423#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
8185#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 8424#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
8186 u8 flags9; 8425 u8 flags9;
8187#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 8426#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8188#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 8427#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8189#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 8428#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8190#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 8429#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
8191#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 8430#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8192#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 8431#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
8193#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 8432#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8194#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 8433#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
8195#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 8434#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8196#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 8435#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
8197#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 8436#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8198#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 8437#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
8199#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 8438#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8200#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 8439#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
8201#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 8440#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8202#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 8441#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
8203 u8 flags10; 8442 u8 flags10;
8204#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 8443#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8205#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 8444#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8206#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 8445#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8207#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 8446#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
8208#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 8447#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8209#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 8448#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
8210#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 8449#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8211#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 8450#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
8212#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8451#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8213#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8452#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8214#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 8453#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8215#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 8454#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
8216#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8455#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8217#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 8456#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
8218#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8457#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8219#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 8458#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
8220 u8 flags11; 8459 u8 flags11;
8221#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8460#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8222#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 8461#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8223#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8462#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8224#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 8463#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
8225#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8464#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8226#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 8465#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
8227#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8466#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8228#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 8467#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
8229#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8468#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8230#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 8469#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
8231#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 8470#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8232#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 8471#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8233#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8472#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8234#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8473#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8235#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 8474#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8236#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 8475#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
8237 u8 flags12; 8476 u8 flags12;
8238#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 8477#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8239#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 8478#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8240#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 8479#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8241#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 8480#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
8242#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8481#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8243#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8482#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8244#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8483#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8245#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8484#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8246#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 8485#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8247#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 8486#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
8248#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 8487#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8249#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 8488#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
8250#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 8489#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8251#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 8490#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
8252#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 8491#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8253#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 8492#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
8254 u8 flags13; 8493 u8 flags13;
8255#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 8494#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8256#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 8495#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8257#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 8496#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8258#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 8497#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
8259#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8498#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8260#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8499#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8261#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8500#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8262#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8501#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8263#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8502#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8264#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8503#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8265#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8504#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8266#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8505#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8267#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8506#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8268#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8507#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8269#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8508#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8270#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8509#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8271 u8 flags14; 8510 u8 flags14;
8272#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 8511#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8273#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 8512#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8274#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 8513#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8275#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 8514#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
8276#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 8515#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8277#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 8516#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
8278#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 8517#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8279#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 8518#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
8280#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 8519#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8281#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 8520#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
8282#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 8521#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8283#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 8522#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
8284 u8 byte2; 8523 u8 byte2;
8285 __le16 physical_q0; 8524 __le16 physical_q0;
8286 __le16 word1; 8525 __le16 word1;
@@ -8306,212 +8545,212 @@ struct xstorm_roce_resp_conn_ag_ctx {
8306 u8 reserved0; 8545 u8 reserved0;
8307 u8 state; 8546 u8 state;
8308 u8 flags0; 8547 u8 flags0;
8309#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8548#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8310#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8549#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8311#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 8550#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8312#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 8551#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
8313#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 8552#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8314#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 8553#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
8315#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8554#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8316#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8555#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8317#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 8556#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8318#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 8557#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
8319#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 8558#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8320#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 8559#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
8321#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 8560#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8322#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 8561#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
8323#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 8562#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8324#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 8563#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
8325 u8 flags1; 8564 u8 flags1;
8326#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 8565#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8327#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 8566#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8328#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 8567#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8329#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 8568#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
8330#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 8569#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8331#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 8570#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
8332#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 8571#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8333#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 8572#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
8334#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 8573#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
8335#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 8574#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
8336#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 8575#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
8337#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 8576#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
8338#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8577#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8339#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8578#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8340#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8579#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8341#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 8580#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8342 u8 flags2; 8581 u8 flags2;
8343#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8582#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8344#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 8583#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8345#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8584#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8346#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 8585#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
8347#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8586#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8348#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 8587#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
8349#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8588#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8350#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 8589#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
8351 u8 flags3; 8590 u8 flags3;
8352#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 8591#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8353#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 8592#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8354#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8593#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8355#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8594#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8356#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 8595#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8357#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 8596#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
8358#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8597#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8359#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8598#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8360 u8 flags4; 8599 u8 flags4;
8361#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 8600#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8362#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 8601#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8363#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 8602#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8364#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 8603#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
8365#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 8604#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8366#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 8605#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
8367#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 8606#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8368#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 8607#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
8369 u8 flags5; 8608 u8 flags5;
8370#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 8609#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8371#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 8610#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8372#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 8611#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8373#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 8612#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
8374#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 8613#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8375#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 8614#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
8376#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 8615#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8377#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 8616#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
8378 u8 flags6; 8617 u8 flags6;
8379#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 8618#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8380#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 8619#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8381#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 8620#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8382#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 8621#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
8383#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 8622#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8384#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 8623#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
8385#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 8624#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8386#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 8625#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
8387 u8 flags7; 8626 u8 flags7;
8388#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 8627#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8389#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 8628#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8390#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 8629#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8391#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 8630#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
8392#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8631#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8393#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8632#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8394#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8633#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8395#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 8634#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
8396#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8635#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8397#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 8636#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
8398 u8 flags8; 8637 u8 flags8;
8399#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8638#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8400#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 8639#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8401#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8640#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8402#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 8641#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
8403#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 8642#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8404#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 8643#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
8405#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8644#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8406#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8645#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8407#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 8646#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8408#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 8647#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
8409#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8648#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8410#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8649#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8411#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 8650#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8412#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 8651#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
8413#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 8652#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8414#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 8653#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
8415 u8 flags9; 8654 u8 flags9;
8416#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 8655#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8417#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 8656#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8418#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 8657#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8419#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 8658#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
8420#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 8659#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8421#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 8660#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
8422#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 8661#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8423#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 8662#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
8424#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 8663#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8425#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 8664#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
8426#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 8665#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8427#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 8666#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
8428#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 8667#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8429#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 8668#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
8430#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 8669#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8431#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 8670#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
8432 u8 flags10; 8671 u8 flags10;
8433#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 8672#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8434#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 8673#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8435#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 8674#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8436#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 8675#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
8437#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 8676#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8438#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 8677#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
8439#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 8678#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8440#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 8679#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
8441#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8680#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8442#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8681#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8443#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 8682#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8444#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 8683#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
8445#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8684#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8446#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 8685#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
8447#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8686#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8448#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 8687#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
8449 u8 flags11; 8688 u8 flags11;
8450#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8689#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8451#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 8690#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8452#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8691#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8453#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 8692#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
8454#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8693#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8455#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 8694#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
8456#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8695#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8457#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 8696#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
8458#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8697#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8459#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 8698#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
8460#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8699#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8461#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 8700#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
8462#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8701#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8463#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8702#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8464#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 8703#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8465#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 8704#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
8466 u8 flags12; 8705 u8 flags12;
8467#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 8706#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8468#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 8707#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
8469#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 8708#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8470#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 8709#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
8471#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8710#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8472#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8711#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8473#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8712#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8474#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8713#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8475#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 8714#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8476#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 8715#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
8477#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 8716#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8478#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 8717#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
8479#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 8718#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8480#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 8719#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
8481#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 8720#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8482#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 8721#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
8483 u8 flags13; 8722 u8 flags13;
8484#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 8723#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8485#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 8724#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8486#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 8725#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8487#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 8726#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
8488#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8727#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8489#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8728#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8490#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8729#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8491#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8730#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8492#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8731#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8493#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8732#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8494#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8733#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8495#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8734#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8496#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8735#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8497#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8736#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8498#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8737#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8499#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8738#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8500 u8 flags14; 8739 u8 flags14;
8501#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 8740#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8502#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 8741#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8503#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 8742#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8504#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 8743#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
8505#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 8744#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8506#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 8745#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
8507#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 8746#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8508#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 8747#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
8509#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 8748#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8510#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 8749#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
8511#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 8750#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8512#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 8751#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
8513#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 8752#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8514#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 8753#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
8515 u8 byte2; 8754 u8 byte2;
8516 __le16 physical_q0; 8755 __le16 physical_q0;
8517 __le16 word1; 8756 __le16 word1;
@@ -8537,33 +8776,33 @@ struct ystorm_roce_req_conn_ag_ctx {
8537 u8 byte0; 8776 u8 byte0;
8538 u8 byte1; 8777 u8 byte1;
8539 u8 flags0; 8778 u8 flags0;
8540#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8779#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8541#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8780#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8542#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8781#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8543#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8782#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8544#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8783#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8545#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8784#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8546#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8785#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8547#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8786#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8548#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8787#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8549#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 8788#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8550 u8 flags1; 8789 u8 flags1;
8551#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8790#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8552#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8791#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8553#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8792#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8554#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8793#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8555#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8794#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8556#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8795#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8557#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8796#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8558#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 8797#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8559#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8798#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8560#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 8799#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8561#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8800#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8562#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 8801#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8563#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8802#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8564#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 8803#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8565#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8804#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8566#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 8805#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8567 u8 byte2; 8806 u8 byte2;
8568 u8 byte3; 8807 u8 byte3;
8569 __le16 word0; 8808 __le16 word0;
@@ -8581,33 +8820,33 @@ struct ystorm_roce_resp_conn_ag_ctx {
8581 u8 byte0; 8820 u8 byte0;
8582 u8 byte1; 8821 u8 byte1;
8583 u8 flags0; 8822 u8 flags0;
8584#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8823#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8585#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8824#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8586#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8825#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8587#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8826#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8588#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8827#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8589#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8828#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8590#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8829#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8591#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8830#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8592#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8831#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8593#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 8832#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8594 u8 flags1; 8833 u8 flags1;
8595#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8834#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8596#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8835#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8597#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8836#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8598#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8837#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8599#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8838#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8600#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8839#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8601#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8840#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8602#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 8841#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8603#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8842#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8604#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 8843#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8605#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8844#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8606#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 8845#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8607#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8846#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8608#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 8847#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8609#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8848#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8610#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 8849#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8611 u8 byte2; 8850 u8 byte2;
8612 u8 byte3; 8851 u8 byte3;
8613 __le16 word0; 8852 __le16 word0;
@@ -8621,6 +8860,7 @@ struct ystorm_roce_resp_conn_ag_ctx {
8621 __le32 reg3; 8860 __le32 reg3;
8622}; 8861};
8623 8862
8863/* Roce doorbell data */
8624enum roce_flavor { 8864enum roce_flavor {
8625 PLAIN_ROCE, 8865 PLAIN_ROCE,
8626 RROCE_IPV4, 8866 RROCE_IPV4,
@@ -8628,14 +8868,17 @@ enum roce_flavor {
8628 MAX_ROCE_FLAVOR 8868 MAX_ROCE_FLAVOR
8629}; 8869};
8630 8870
8871/* The iwarp storm context of Ystorm */
8631struct ystorm_iwarp_conn_st_ctx { 8872struct ystorm_iwarp_conn_st_ctx {
8632 __le32 reserved[4]; 8873 __le32 reserved[4];
8633}; 8874};
8634 8875
8876/* The iwarp storm context of Pstorm */
8635struct pstorm_iwarp_conn_st_ctx { 8877struct pstorm_iwarp_conn_st_ctx {
8636 __le32 reserved[36]; 8878 __le32 reserved[36];
8637}; 8879};
8638 8880
8881/* The iwarp storm context of Xstorm */
8639struct xstorm_iwarp_conn_st_ctx { 8882struct xstorm_iwarp_conn_st_ctx {
8640 __le32 reserved[44]; 8883 __le32 reserved[44];
8641}; 8884};
@@ -8652,38 +8895,38 @@ struct xstorm_iwarp_conn_ag_ctx {
8652#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 8895#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
8653#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8896#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8654#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8897#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8655#define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 8898#define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8656#define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 8899#define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8657#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 8900#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8658#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 8901#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
8659#define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 8902#define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8660#define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 8903#define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
8661#define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 8904#define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8662#define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 8905#define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
8663 u8 flags1; 8906 u8 flags1;
8664#define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 8907#define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8665#define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 8908#define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8666#define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 8909#define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8667#define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 8910#define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
8668#define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 8911#define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8669#define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 8912#define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
8670#define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 8913#define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8671#define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 8914#define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
8672#define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 8915#define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8673#define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 8916#define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
8674#define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 8917#define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8675#define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 8918#define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
8676#define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 8919#define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8677#define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 8920#define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
8678#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 8921#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8679#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 8922#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
8680 u8 flags2; 8923 u8 flags2;
8681#define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8924#define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8682#define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 8925#define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8683#define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8926#define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8684#define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 8927#define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
8685#define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8928#define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8686#define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 8929#define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
8687#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 8930#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8688#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 8931#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
8689 u8 flags3; 8932 u8 flags3;
@@ -8705,119 +8948,119 @@ struct xstorm_iwarp_conn_ag_ctx {
8705#define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 8948#define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8706#define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 8949#define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
8707 u8 flags5; 8950 u8 flags5;
8708#define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 8951#define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8709#define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 8952#define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8710#define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 8953#define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8711#define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 8954#define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
8712#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8955#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8713#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 8956#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
8714#define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 8957#define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8715#define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 8958#define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
8716 u8 flags6; 8959 u8 flags6;
8717#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 8960#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8718#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 8961#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8719#define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 8962#define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8720#define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 8963#define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
8721#define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 8964#define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8722#define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 8965#define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
8723#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 8966#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8724#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 8967#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
8725 u8 flags7; 8968 u8 flags7;
8726#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 8969#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8727#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 8970#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8728#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 8971#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8729#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 8972#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
8730#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8973#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8731#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8974#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8732#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8975#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8733#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 8976#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
8734#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8977#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8735#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 8978#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
8736 u8 flags8; 8979 u8 flags8;
8737#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8980#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8738#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 8981#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8739#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 8982#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8740#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 8983#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
8741#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 8984#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8742#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 8985#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
8743#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 8986#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8744#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 8987#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
8745#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 8988#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8746#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 8989#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
8747#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 8990#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8748#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 8991#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
8749#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 8992#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8750#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 8993#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
8751#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 8994#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8752#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 8995#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
8753 u8 flags9; 8996 u8 flags9;
8754#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 8997#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8755#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 8998#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8756#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 8999#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8757#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 9000#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
8758#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 9001#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8759#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 9002#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
8760#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 9003#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8761#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 9004#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
8762#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 9005#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8763#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 9006#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
8764#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 9007#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8765#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 9008#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
8766#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 9009#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8767#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 9010#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
8768#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 9011#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8769#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 9012#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
8770 u8 flags10; 9013 u8 flags10;
8771#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 9014#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8772#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 9015#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
8773#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 9016#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8774#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 9017#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
8775#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9018#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8776#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 9019#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
8777#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 9020#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8778#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 9021#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
8779#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9022#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8780#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9023#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8781#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 9024#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
8782#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 9025#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
8783#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9026#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8784#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 9027#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
8785#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 9028#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8786#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 9029#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
8787 u8 flags11; 9030 u8 flags11;
8788#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 9031#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8789#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 9032#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8790#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9033#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8791#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 9034#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
8792#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 9035#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8793#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 9036#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
8794#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9037#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8795#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 9038#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
8796#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 9039#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8797#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 9040#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
8798#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9041#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8799#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 9042#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
8800#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9043#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8801#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9044#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8802#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 9045#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8803#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 9046#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
8804 u8 flags12; 9047 u8 flags12;
8805#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 9048#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8806#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 9049#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
8807#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 9050#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8808#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 9051#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
8809#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9052#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8810#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9053#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8811#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9054#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8812#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9055#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8813#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 9056#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8814#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 9057#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
8815#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 9058#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8816#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 9059#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
8817#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 9060#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8818#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 9061#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
8819#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 9062#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8820#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 9063#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
8821 u8 flags13; 9064 u8 flags13;
8822#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 9065#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8823#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 9066#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
@@ -8825,31 +9068,31 @@ struct xstorm_iwarp_conn_ag_ctx {
8825#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 9068#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
8826#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 9069#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8827#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 9070#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
8828#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 9071#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8829#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 9072#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
8830#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9073#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8831#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9074#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8832#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 9075#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8833#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 9076#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
8834#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9077#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8835#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9078#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8836#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9079#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8837#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 9080#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8838 u8 flags14; 9081 u8 flags14;
8839#define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 9082#define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8840#define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 9083#define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
8841#define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 9084#define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8842#define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 9085#define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
8843#define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 9086#define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8844#define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 9087#define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
8845#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 9088#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8846#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 9089#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
8847#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 9090#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8848#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 9091#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
8849#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 9092#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8850#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 9093#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
8851#define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 9094#define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
8852#define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 9095#define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
8853 u8 byte2; 9096 u8 byte2;
8854 __le16 physical_q0; 9097 __le16 physical_q0;
8855 __le16 physical_q1; 9098 __le16 physical_q1;
@@ -8903,18 +9146,18 @@ struct tstorm_iwarp_conn_ag_ctx {
8903 u8 flags0; 9146 u8 flags0;
8904#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9147#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8905#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9148#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8906#define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9149#define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
8907#define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9150#define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
8908#define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 9151#define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
8909#define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 9152#define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
8910#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 9153#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8911#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 9154#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
8912#define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 9155#define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8913#define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 9156#define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
8914#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 9157#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8915#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 9158#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
8916#define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9159#define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8917#define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 9160#define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
8918 u8 flags1; 9161 u8 flags1;
8919#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 9162#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
8920#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 9163#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
@@ -8922,8 +9165,8 @@ struct tstorm_iwarp_conn_ag_ctx {
8922#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 9165#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
8923#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9166#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8924#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 9167#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
8925#define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 9168#define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8926#define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 9169#define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
8927 u8 flags2; 9170 u8 flags2;
8928#define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 9171#define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8929#define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 9172#define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
@@ -8934,52 +9177,52 @@ struct tstorm_iwarp_conn_ag_ctx {
8934#define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 9177#define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8935#define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 9178#define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
8936 u8 flags3; 9179 u8 flags3;
8937#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9180#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8938#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9181#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8939#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 9182#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
8940#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 9183#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
8941#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9184#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8942#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 9185#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
8943#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 9186#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
8944#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 9187#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
8945#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 9188#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
8946#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 9189#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
8947#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9190#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8948#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 9191#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
8949 u8 flags4; 9192 u8 flags4;
8950#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 9193#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8951#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 9194#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
8952#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 9195#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8953#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 9196#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
8954#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9197#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8955#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 9198#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
8956#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 9199#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8957#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 9200#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
8958#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 9201#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8959#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 9202#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
8960#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9203#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8961#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 9204#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
8962#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 9205#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
8963#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 9206#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
8964#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9207#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8965#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 9208#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
8966 u8 flags5; 9209 u8 flags5;
8967#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9210#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
8968#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 9211#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
8969#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9212#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
8970#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 9213#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
8971#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9214#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8972#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 9215#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
8973#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9216#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
8974#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 9217#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
8975#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9218#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8976#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 9219#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
8977#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 9220#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
8978#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 9221#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
8979#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9222#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8980#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 9223#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
8981#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 9224#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
8982#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 9225#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
8983 __le32 reg0; 9226 __le32 reg0;
8984 __le32 reg1; 9227 __le32 reg1;
8985 __le32 unaligned_nxt_seq; 9228 __le32 unaligned_nxt_seq;
@@ -9001,18 +9244,22 @@ struct tstorm_iwarp_conn_ag_ctx {
9001 __le32 last_hq_sequence; 9244 __le32 last_hq_sequence;
9002}; 9245};
9003 9246
9247/* The iwarp storm context of Tstorm */
9004struct tstorm_iwarp_conn_st_ctx { 9248struct tstorm_iwarp_conn_st_ctx {
9005 __le32 reserved[60]; 9249 __le32 reserved[60];
9006}; 9250};
9007 9251
9252/* The iwarp storm context of Mstorm */
9008struct mstorm_iwarp_conn_st_ctx { 9253struct mstorm_iwarp_conn_st_ctx {
9009 __le32 reserved[32]; 9254 __le32 reserved[32];
9010}; 9255};
9011 9256
9257/* The iwarp storm context of Ustorm */
9012struct ustorm_iwarp_conn_st_ctx { 9258struct ustorm_iwarp_conn_st_ctx {
9013 __le32 reserved[24]; 9259 __le32 reserved[24];
9014}; 9260};
9015 9261
9262/* iwarp connection context */
9016struct iwarp_conn_context { 9263struct iwarp_conn_context {
9017 struct ystorm_iwarp_conn_st_ctx ystorm_st_context; 9264 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9018 struct regpair ystorm_st_padding[2]; 9265 struct regpair ystorm_st_padding[2];
@@ -9030,22 +9277,23 @@ struct iwarp_conn_context {
9030 struct ustorm_iwarp_conn_st_ctx ustorm_st_context; 9277 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9031}; 9278};
9032 9279
9280/* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9033struct iwarp_create_qp_ramrod_data { 9281struct iwarp_create_qp_ramrod_data {
9034 u8 flags; 9282 u8 flags;
9035#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 9283#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9036#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 9284#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9037#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 9285#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9038#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 9286#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
9039#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9287#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9040#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 9288#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
9041#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9289#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9042#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 9290#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
9043#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9291#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9044#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 9292#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
9045#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 9293#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9046#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 9294#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
9047#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3 9295#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
9048#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6 9296#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
9049 u8 reserved1; 9297 u8 reserved1;
9050 __le16 pd; 9298 __le16 pd;
9051 __le16 sq_num_pages; 9299 __le16 sq_num_pages;
@@ -9061,6 +9309,7 @@ struct iwarp_create_qp_ramrod_data {
9061 u8 reserved2[6]; 9309 u8 reserved2[6];
9062}; 9310};
9063 9311
9312/* iWARP completion queue types */
9064enum iwarp_eqe_async_opcode { 9313enum iwarp_eqe_async_opcode {
9065 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, 9314 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9066 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, 9315 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
@@ -9083,6 +9332,7 @@ struct iwarp_eqe_data_tcp_async_completion {
9083 u8 reserved[5]; 9332 u8 reserved[5];
9084}; 9333};
9085 9334
9335/* iWARP completion queue types */
9086enum iwarp_eqe_sync_opcode { 9336enum iwarp_eqe_sync_opcode {
9087 IWARP_EVENT_TYPE_TCP_OFFLOAD = 9337 IWARP_EVENT_TYPE_TCP_OFFLOAD =
9088 11, 9338 11,
@@ -9095,6 +9345,7 @@ enum iwarp_eqe_sync_opcode {
9095 MAX_IWARP_EQE_SYNC_OPCODE 9345 MAX_IWARP_EQE_SYNC_OPCODE
9096}; 9346};
9097 9347
9348/* iWARP EQE completion status */
9098enum iwarp_fw_return_code { 9349enum iwarp_fw_return_code {
9099 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5, 9350 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9100 IWARP_CONN_ERROR_TCP_CONNECTION_RST, 9351 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
@@ -9125,54 +9376,60 @@ enum iwarp_fw_return_code {
9125 MAX_IWARP_FW_RETURN_CODE 9376 MAX_IWARP_FW_RETURN_CODE
9126}; 9377};
9127 9378
9379/* unaligned opaque data received from LL2 */
9128struct iwarp_init_func_params { 9380struct iwarp_init_func_params {
9129 u8 ll2_ooo_q_index; 9381 u8 ll2_ooo_q_index;
9130 u8 reserved1[7]; 9382 u8 reserved1[7];
9131}; 9383};
9132 9384
9385/* iwarp func init ramrod data */
9133struct iwarp_init_func_ramrod_data { 9386struct iwarp_init_func_ramrod_data {
9134 struct rdma_init_func_ramrod_data rdma; 9387 struct rdma_init_func_ramrod_data rdma;
9135 struct tcp_init_params tcp; 9388 struct tcp_init_params tcp;
9136 struct iwarp_init_func_params iwarp; 9389 struct iwarp_init_func_params iwarp;
9137}; 9390};
9138 9391
9392/* iWARP QP - possible states to transition to */
9139enum iwarp_modify_qp_new_state_type { 9393enum iwarp_modify_qp_new_state_type {
9140 IWARP_MODIFY_QP_STATE_CLOSING = 1, 9394 IWARP_MODIFY_QP_STATE_CLOSING = 1,
9141 IWARP_MODIFY_QP_STATE_ERROR = 9395 IWARP_MODIFY_QP_STATE_ERROR = 2,
9142 2,
9143 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 9396 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9144}; 9397};
9145 9398
9399/* iwarp modify qp responder ramrod data */
9146struct iwarp_modify_qp_ramrod_data { 9400struct iwarp_modify_qp_ramrod_data {
9147 __le16 transition_to_state; 9401 __le16 transition_to_state;
9148 __le16 flags; 9402 __le16 flags;
9149#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9403#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9150#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 9404#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9151#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9405#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9152#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 9406#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
9153#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9407#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9154#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 9408#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
9155#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 9409#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9156#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 9410#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
9157#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 9411#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9158#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 9412#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
9159#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF 9413#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
9160#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5 9414#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
9161 __le32 reserved3[3]; 9415 __le32 reserved3[3];
9162 __le32 reserved4[8]; 9416 __le32 reserved4[8];
9163}; 9417};
9164 9418
9419/* MPA params for Enhanced mode */
9165struct mpa_rq_params { 9420struct mpa_rq_params {
9166 __le32 ird; 9421 __le32 ird;
9167 __le32 ord; 9422 __le32 ord;
9168}; 9423};
9169 9424
9425/* MPA host Address-Len for private data */
9170struct mpa_ulp_buffer { 9426struct mpa_ulp_buffer {
9171 struct regpair addr; 9427 struct regpair addr;
9172 __le16 len; 9428 __le16 len;
9173 __le16 reserved[3]; 9429 __le16 reserved[3];
9174}; 9430};
9175 9431
9432/* iWARP MPA offload params common to Basic and Enhanced modes */
9176struct mpa_outgoing_params { 9433struct mpa_outgoing_params {
9177 u8 crc_needed; 9434 u8 crc_needed;
9178 u8 reject; 9435 u8 reject;
@@ -9181,6 +9438,9 @@ struct mpa_outgoing_params {
9181 struct mpa_ulp_buffer outgoing_ulp_buffer; 9438 struct mpa_ulp_buffer outgoing_ulp_buffer;
9182}; 9439};
9183 9440
9441/* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9442 * Ramrod.
9443 */
9184struct iwarp_mpa_offload_ramrod_data { 9444struct iwarp_mpa_offload_ramrod_data {
9185 struct mpa_outgoing_params common; 9445 struct mpa_outgoing_params common;
9186 __le32 tcp_cid; 9446 __le32 tcp_cid;
@@ -9188,9 +9448,9 @@ struct iwarp_mpa_offload_ramrod_data {
9188 u8 tcp_connect_side; 9448 u8 tcp_connect_side;
9189 u8 rtr_pref; 9449 u8 rtr_pref;
9190#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 9450#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9191#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 9451#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9192#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 9452#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9193#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 9453#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
9194 u8 reserved2; 9454 u8 reserved2;
9195 struct mpa_ulp_buffer incoming_ulp_buffer; 9455 struct mpa_ulp_buffer incoming_ulp_buffer;
9196 struct regpair async_eqe_output_buf; 9456 struct regpair async_eqe_output_buf;
@@ -9200,6 +9460,7 @@ struct iwarp_mpa_offload_ramrod_data {
9200 u8 reserved3[15]; 9460 u8 reserved3[15];
9201}; 9461};
9202 9462
9463/* iWARP TCP connection offload params passed by driver to FW */
9203struct iwarp_offload_params { 9464struct iwarp_offload_params {
9204 struct mpa_ulp_buffer incoming_ulp_buffer; 9465 struct mpa_ulp_buffer incoming_ulp_buffer;
9205 struct regpair async_eqe_output_buf; 9466 struct regpair async_eqe_output_buf;
@@ -9211,22 +9472,24 @@ struct iwarp_offload_params {
9211 u8 reserved[10]; 9472 u8 reserved[10];
9212}; 9473};
9213 9474
9475/* iWARP query QP output params */
9214struct iwarp_query_qp_output_params { 9476struct iwarp_query_qp_output_params {
9215 __le32 flags; 9477 __le32 flags;
9216#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 9478#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9217#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 9479#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9218#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 9480#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9219#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 9481#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
9220 u8 reserved1[4]; 9482 u8 reserved1[4];
9221}; 9483};
9222 9484
9485/* iWARP query QP ramrod data */
9223struct iwarp_query_qp_ramrod_data { 9486struct iwarp_query_qp_ramrod_data {
9224 struct regpair output_params_addr; 9487 struct regpair output_params_addr;
9225}; 9488};
9226 9489
9490/* iWARP Ramrod Command IDs */
9227enum iwarp_ramrod_cmd_id { 9491enum iwarp_ramrod_cmd_id {
9228 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 9492 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
9229 11,
9230 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, 9493 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9231 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 9494 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9232 IWARP_RAMROD_CMD_ID_CREATE_QP, 9495 IWARP_RAMROD_CMD_ID_CREATE_QP,
@@ -9236,22 +9499,28 @@ enum iwarp_ramrod_cmd_id {
9236 MAX_IWARP_RAMROD_CMD_ID 9499 MAX_IWARP_RAMROD_CMD_ID
9237}; 9500};
9238 9501
9502/* Per PF iWARP retransmit path statistics */
9239struct iwarp_rxmit_stats_drv { 9503struct iwarp_rxmit_stats_drv {
9240 struct regpair tx_go_to_slow_start_event_cnt; 9504 struct regpair tx_go_to_slow_start_event_cnt;
9241 struct regpair tx_fast_retransmit_event_cnt; 9505 struct regpair tx_fast_retransmit_event_cnt;
9242}; 9506};
9243 9507
9508/* iWARP and TCP connection offload params passed by driver to FW in iWARP
9509 * offload ramrod.
9510 */
9244struct iwarp_tcp_offload_ramrod_data { 9511struct iwarp_tcp_offload_ramrod_data {
9245 struct iwarp_offload_params iwarp; 9512 struct iwarp_offload_params iwarp;
9246 struct tcp_offload_params_opt2 tcp; 9513 struct tcp_offload_params_opt2 tcp;
9247}; 9514};
9248 9515
9516/* iWARP MPA negotiation types */
9249enum mpa_negotiation_mode { 9517enum mpa_negotiation_mode {
9250 MPA_NEGOTIATION_TYPE_BASIC = 1, 9518 MPA_NEGOTIATION_TYPE_BASIC = 1,
9251 MPA_NEGOTIATION_TYPE_ENHANCED = 2, 9519 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9252 MAX_MPA_NEGOTIATION_MODE 9520 MAX_MPA_NEGOTIATION_MODE
9253}; 9521};
9254 9522
9523/* iWARP MPA Enhanced mode RTR types */
9255enum mpa_rtr_type { 9524enum mpa_rtr_type {
9256 MPA_RTR_TYPE_NONE = 0, 9525 MPA_RTR_TYPE_NONE = 0,
9257 MPA_RTR_TYPE_ZERO_SEND = 1, 9526 MPA_RTR_TYPE_ZERO_SEND = 1,
@@ -9264,16 +9533,17 @@ enum mpa_rtr_type {
9264 MAX_MPA_RTR_TYPE 9533 MAX_MPA_RTR_TYPE
9265}; 9534};
9266 9535
9536/* unaligned opaque data received from LL2 */
9267struct unaligned_opaque_data { 9537struct unaligned_opaque_data {
9268 __le16 first_mpa_offset; 9538 __le16 first_mpa_offset;
9269 u8 tcp_payload_offset; 9539 u8 tcp_payload_offset;
9270 u8 flags; 9540 u8 flags;
9271#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 9541#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9272#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 9542#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9273#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 9543#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9274#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 9544#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
9275#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 9545#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9276#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 9546#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
9277 __le32 cid; 9547 __le32 cid;
9278}; 9548};
9279 9549
@@ -9283,31 +9553,31 @@ struct mstorm_iwarp_conn_ag_ctx {
9283 u8 flags0; 9553 u8 flags0;
9284#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9554#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9285#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9555#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9286#define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9556#define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9287#define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9557#define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9288#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 9558#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9289#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 9559#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
9290#define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9560#define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9291#define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9561#define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9292#define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9562#define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9293#define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 9563#define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9294 u8 flags1; 9564 u8 flags1;
9295#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 9565#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9296#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 9566#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9297#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9567#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9298#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9568#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9299#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9569#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9300#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9570#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9301#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9571#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9302#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9572#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9303#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9573#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9304#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9574#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9305#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9575#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9306#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9576#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9307#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 9577#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9308#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 9578#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
9309#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9579#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9310#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 9580#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9311 __le16 rcq_cons; 9581 __le16 rcq_cons;
9312 __le16 rcq_cons_th; 9582 __le16 rcq_cons_th;
9313 __le32 reg0; 9583 __le32 reg0;
@@ -9320,40 +9590,40 @@ struct ustorm_iwarp_conn_ag_ctx {
9320 u8 flags0; 9590 u8 flags0;
9321#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9591#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9322#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9592#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9323#define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9593#define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9324#define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9594#define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9325#define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9595#define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9326#define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 9596#define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
9327#define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9597#define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9328#define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9598#define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9329#define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9599#define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9330#define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 9600#define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9331 u8 flags1; 9601 u8 flags1;
9332#define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 9602#define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9333#define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 9603#define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9334#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 9604#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9335#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 9605#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
9336#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 9606#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9337#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 9607#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
9338#define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9608#define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9339#define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 9609#define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
9340 u8 flags2; 9610 u8 flags2;
9341#define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9611#define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9342#define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 9612#define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9343#define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9613#define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9344#define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9614#define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9345#define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9615#define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9346#define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9616#define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9347#define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 9617#define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9348#define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 9618#define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
9349#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 9619#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9350#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 9620#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
9351#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 9621#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9352#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 9622#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
9353#define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9623#define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9354#define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 9624#define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
9355#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 9625#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9356#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 9626#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
9357 u8 flags3; 9627 u8 flags3;
9358#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 9628#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9359#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 9629#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
@@ -9405,15 +9675,15 @@ struct ystorm_iwarp_conn_ag_ctx {
9405#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9675#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9406#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9676#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9407#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9677#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9408#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9678#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9409#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9679#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9410#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9680#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9411#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9681#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9412#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9682#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
9413#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9683#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9414#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 9684#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
9415#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9685#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9416#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 9686#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
9417 u8 byte2; 9687 u8 byte2;
9418 u8 byte3; 9688 u8 byte3;
9419 __le16 word0; 9689 __le16 word0;
@@ -9427,6 +9697,7 @@ struct ystorm_iwarp_conn_ag_ctx {
9427 __le32 reg3; 9697 __le32 reg3;
9428}; 9698};
9429 9699
9700/* The fcoe storm context of Ystorm */
9430struct ystorm_fcoe_conn_st_ctx { 9701struct ystorm_fcoe_conn_st_ctx {
9431 u8 func_mode; 9702 u8 func_mode;
9432 u8 cos; 9703 u8 cos;
@@ -9442,45 +9713,49 @@ struct ystorm_fcoe_conn_st_ctx {
9442 struct regpair reserved; 9713 struct regpair reserved;
9443 __le16 min_frame_size; 9714 __le16 min_frame_size;
9444 u8 protection_info_flags; 9715 u8 protection_info_flags;
9445#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 9716#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9446#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 9717#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9447#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 9718#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9448#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 9719#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
9449#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 9720#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9450#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 9721#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
9451 u8 dst_protection_per_mss; 9722 u8 dst_protection_per_mss;
9452 u8 src_protection_per_mss; 9723 u8 src_protection_per_mss;
9453 u8 ptu_log_page_size; 9724 u8 ptu_log_page_size;
9454 u8 flags; 9725 u8 flags;
9455#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9726#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9456#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 9727#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9457#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 9728#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9458#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 9729#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
9459#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 9730#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9460#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 9731#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
9461 u8 fcp_xfer_size; 9732 u8 fcp_xfer_size;
9462}; 9733};
9463 9734
9735/* FCoE 16-bits vlan structure */
9464struct fcoe_vlan_fields { 9736struct fcoe_vlan_fields {
9465 __le16 fields; 9737 __le16 fields;
9466#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 9738#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9467#define FCOE_VLAN_FIELDS_VID_SHIFT 0 9739#define FCOE_VLAN_FIELDS_VID_SHIFT 0
9468#define FCOE_VLAN_FIELDS_CLI_MASK 0x1 9740#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9469#define FCOE_VLAN_FIELDS_CLI_SHIFT 12 9741#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9470#define FCOE_VLAN_FIELDS_PRI_MASK 0x7 9742#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9471#define FCOE_VLAN_FIELDS_PRI_SHIFT 13 9743#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
9472}; 9744};
9473 9745
9746/* FCoE 16-bits vlan union */
9474union fcoe_vlan_field_union { 9747union fcoe_vlan_field_union {
9475 struct fcoe_vlan_fields fields; 9748 struct fcoe_vlan_fields fields;
9476 __le16 val; 9749 __le16 val;
9477}; 9750};
9478 9751
9752/* FCoE 16-bits vlan, vif union */
9479union fcoe_vlan_vif_field_union { 9753union fcoe_vlan_vif_field_union {
9480 union fcoe_vlan_field_union vlan; 9754 union fcoe_vlan_field_union vlan;
9481 __le16 vif; 9755 __le16 vif;
9482}; 9756};
9483 9757
9758/* Ethernet context section */
9484struct pstorm_fcoe_eth_context_section { 9759struct pstorm_fcoe_eth_context_section {
9485 u8 remote_addr_3; 9760 u8 remote_addr_3;
9486 u8 remote_addr_2; 9761 u8 remote_addr_2;
@@ -9500,6 +9775,7 @@ struct pstorm_fcoe_eth_context_section {
9500 __le16 inner_eth_type; 9775 __le16 inner_eth_type;
9501}; 9776};
9502 9777
9778/* The fcoe storm context of Pstorm */
9503struct pstorm_fcoe_conn_st_ctx { 9779struct pstorm_fcoe_conn_st_ctx {
9504 u8 func_mode; 9780 u8 func_mode;
9505 u8 cos; 9781 u8 cos;
@@ -9513,16 +9789,16 @@ struct pstorm_fcoe_conn_st_ctx {
9513 u8 sid_1; 9789 u8 sid_1;
9514 u8 sid_0; 9790 u8 sid_0;
9515 u8 flags; 9791 u8 flags;
9516#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 9792#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9517#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 9793#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9518#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 9794#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9519#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 9795#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
9520#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9796#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9521#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 9797#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
9522#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 9798#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9523#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 9799#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
9524#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF 9800#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
9525#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4 9801#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
9526 u8 did_2; 9802 u8 did_2;
9527 u8 did_1; 9803 u8 did_1;
9528 u8 did_0; 9804 u8 did_0;
@@ -9532,6 +9808,7 @@ struct pstorm_fcoe_conn_st_ctx {
9532 u8 reserved1; 9808 u8 reserved1;
9533}; 9809};
9534 9810
9811/* The fcoe storm context of Xstorm */
9535struct xstorm_fcoe_conn_st_ctx { 9812struct xstorm_fcoe_conn_st_ctx {
9536 u8 func_mode; 9813 u8 func_mode;
9537 u8 src_mac_index; 9814 u8 src_mac_index;
@@ -9539,16 +9816,16 @@ struct xstorm_fcoe_conn_st_ctx {
9539 u8 cached_wqes_avail; 9816 u8 cached_wqes_avail;
9540 __le16 stat_ram_addr; 9817 __le16 stat_ram_addr;
9541 u8 flags; 9818 u8 flags;
9542#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 9819#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9543#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 9820#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9544#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9821#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9545#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 9822#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
9546#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 9823#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9547#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 9824#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
9548#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 9825#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9549#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 9826#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
9550#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 9827#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9551#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 9828#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
9552 u8 cached_wqes_offset; 9829 u8 cached_wqes_offset;
9553 u8 reserved2; 9830 u8 reserved2;
9554 u8 eth_hdr_size; 9831 u8 eth_hdr_size;
@@ -9574,18 +9851,18 @@ struct xstorm_fcoe_conn_st_ctx {
9574 u8 fcp_cmd_byte_credit; 9851 u8 fcp_cmd_byte_credit;
9575 u8 fcp_rsp_byte_credit; 9852 u8 fcp_rsp_byte_credit;
9576 __le16 protection_info; 9853 __le16 protection_info;
9577#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 9854#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9578#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 9855#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9579#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 9856#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9580#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 9857#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
9581#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 9858#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9582#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 9859#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
9583#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 9860#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9584#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 9861#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
9585#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 9862#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9586#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 9863#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
9587#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF 9864#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9588#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 9865#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
9589 __le16 xferq_pbl_next_index; 9866 __le16 xferq_pbl_next_index;
9590 __le16 page_size; 9867 __le16 page_size;
9591 u8 mid_seq; 9868 u8 mid_seq;
@@ -9598,212 +9875,212 @@ struct xstorm_fcoe_conn_ag_ctx {
9598 u8 reserved0; 9875 u8 reserved0;
9599 u8 fcoe_state; 9876 u8 fcoe_state;
9600 u8 flags0; 9877 u8 flags0;
9601#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9878#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9602#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9879#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9603#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 9880#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9604#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 9881#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
9605#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 9882#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9606#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 9883#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
9607#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 9884#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9608#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 9885#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9609#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 9886#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9610#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 9887#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
9611#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 9888#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9612#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 9889#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
9613#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 9890#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9614#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 9891#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
9615#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 9892#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9616#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 9893#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
9617 u8 flags1; 9894 u8 flags1;
9618#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 9895#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9619#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 9896#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9620#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 9897#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9621#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 9898#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
9622#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 9899#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9623#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 9900#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
9624#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 9901#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9625#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 9902#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
9626#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 9903#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9627#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 9904#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
9628#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 9905#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9629#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 9906#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
9630#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 9907#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9631#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 9908#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
9632#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 9909#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9633#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 9910#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
9634 u8 flags2; 9911 u8 flags2;
9635#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9912#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9636#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 9913#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9637#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9914#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9638#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 9915#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
9639#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9916#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9640#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 9917#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
9641#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 9918#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9642#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 9919#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
9643 u8 flags3; 9920 u8 flags3;
9644#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 9921#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9645#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 9922#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9646#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 9923#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9647#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 9924#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
9648#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 9925#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9649#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 9926#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
9650#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 9927#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9651#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 9928#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
9652 u8 flags4; 9929 u8 flags4;
9653#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 9930#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9654#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 9931#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9655#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 9932#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9656#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 9933#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
9657#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 9934#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9658#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 9935#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
9659#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 9936#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9660#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 9937#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
9661 u8 flags5; 9938 u8 flags5;
9662#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 9939#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9663#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 9940#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9664#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 9941#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9665#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 9942#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
9666#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 9943#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9667#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 9944#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
9668#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 9945#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9669#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 9946#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
9670 u8 flags6; 9947 u8 flags6;
9671#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 9948#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9672#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 9949#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9673#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 9950#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9674#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 9951#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
9675#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 9952#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9676#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 9953#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
9677#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 9954#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9678#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 9955#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
9679 u8 flags7; 9956 u8 flags7;
9680#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9957#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9681#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9958#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9682#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 9959#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9683#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 9960#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
9684#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9961#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9685#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9962#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9686#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 9963#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9687#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 9964#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
9688#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 9965#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9689#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 9966#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
9690 u8 flags8; 9967 u8 flags8;
9691#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9968#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9692#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 9969#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9693#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 9970#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9694#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 9971#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
9695#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 9972#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9696#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 9973#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
9697#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 9974#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9698#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 9975#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
9699#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 9976#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9700#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 9977#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
9701#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 9978#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9702#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 9979#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
9703#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 9980#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9704#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 9981#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
9705#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 9982#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9706#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 9983#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
9707 u8 flags9; 9984 u8 flags9;
9708#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 9985#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9709#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 9986#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9710#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 9987#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9711#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 9988#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
9712#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 9989#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9713#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 9990#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
9714#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 9991#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9715#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 9992#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
9716#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 9993#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9717#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 9994#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
9718#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 9995#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9719#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 9996#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
9720#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 9997#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9721#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 9998#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
9722#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 9999#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9723#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 10000#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
9724 u8 flags10; 10001 u8 flags10;
9725#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 10002#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9726#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 10003#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
9727#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 10004#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9728#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 10005#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
9729#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 10006#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9730#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 10007#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9731#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 10008#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9732#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 10009#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
9733#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 10010#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9734#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 10011#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9735#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 10012#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9736#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 10013#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
9737#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 10014#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9738#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 10015#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
9739#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 10016#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9740#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 10017#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
9741 u8 flags11; 10018 u8 flags11;
9742#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 10019#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9743#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 10020#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
9744#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 10021#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9745#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 10022#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
9746#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 10023#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9747#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 10024#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
9748#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10025#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9749#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 10026#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
9750#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10027#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9751#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 10028#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
9752#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10029#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9753#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 10030#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
9754#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 10031#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9755#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 10032#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9756#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 10033#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9757#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 10034#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
9758 u8 flags12; 10035 u8 flags12;
9759#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 10036#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9760#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 10037#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
9761#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 10038#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9762#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 10039#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
9763#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 10040#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9764#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 10041#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9765#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 10042#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9766#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 10043#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9767#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 10044#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9768#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 10045#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
9769#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 10046#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9770#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 10047#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
9771#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 10048#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9772#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 10049#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
9773#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 10050#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9774#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 10051#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
9775 u8 flags13; 10052 u8 flags13;
9776#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 10053#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9777#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 10054#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
9778#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 10055#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9779#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 10056#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
9780#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 10057#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9781#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 10058#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9782#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 10059#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9783#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 10060#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9784#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 10061#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9785#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 10062#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9786#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 10063#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9787#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 10064#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9788#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 10065#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9789#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 10066#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9790#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 10067#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9791#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 10068#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9792 u8 flags14; 10069 u8 flags14;
9793#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 10070#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9794#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 10071#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
9795#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 10072#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9796#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 10073#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
9797#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 10074#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9798#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 10075#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
9799#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 10076#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9800#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 10077#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
9801#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 10078#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9802#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 10079#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
9803#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 10080#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9804#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 10081#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
9805#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 10082#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
9806#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 10083#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
9807 u8 byte2; 10084 u8 byte2;
9808 __le16 physical_q0; 10085 __le16 physical_q0;
9809 __le16 word1; 10086 __le16 word1;
@@ -9831,6 +10108,7 @@ struct xstorm_fcoe_conn_ag_ctx {
9831 __le32 reg8; 10108 __le32 reg8;
9832}; 10109};
9833 10110
10111/* The fcoe storm context of Ustorm */
9834struct ustorm_fcoe_conn_st_ctx { 10112struct ustorm_fcoe_conn_st_ctx {
9835 struct regpair respq_pbl_addr; 10113 struct regpair respq_pbl_addr;
9836 __le16 num_pages_in_pbl; 10114 __le16 num_pages_in_pbl;
@@ -9844,85 +10122,85 @@ struct tstorm_fcoe_conn_ag_ctx {
9844 u8 reserved0; 10122 u8 reserved0;
9845 u8 fcoe_state; 10123 u8 fcoe_state;
9846 u8 flags0; 10124 u8 flags0;
9847#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10125#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9848#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10126#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9849#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10127#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9850#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10128#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
9851#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 10129#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
9852#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 10130#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
9853#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 10131#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
9854#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 10132#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
9855#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 10133#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
9856#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 10134#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
9857#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 10135#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
9858#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 10136#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
9859#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 10137#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
9860#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 10138#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
9861 u8 flags1; 10139 u8 flags1;
9862#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 10140#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9863#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 10141#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
9864#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10142#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9865#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 10143#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
9866#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 10144#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
9867#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 10145#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
9868#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10146#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9869#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 10147#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
9870 u8 flags2; 10148 u8 flags2;
9871#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10149#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9872#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 10150#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
9873#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10151#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9874#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 10152#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
9875#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 10153#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9876#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 10154#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
9877#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 10155#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9878#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 10156#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
9879 u8 flags3; 10157 u8 flags3;
9880#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 10158#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9881#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 10159#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
9882#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 10160#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9883#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 10161#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
9884#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 10162#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
9885#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 10163#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
9886#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 10164#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9887#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 10165#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9888#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10166#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9889#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 10167#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
9890#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 10168#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
9891#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 10169#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
9892 u8 flags4; 10170 u8 flags4;
9893#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10171#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9894#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 10172#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
9895#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10173#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9896#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 10174#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
9897#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10175#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9898#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 10176#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
9899#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 10177#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9900#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 10178#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
9901#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 10179#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9902#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 10180#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
9903#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 10181#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9904#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 10182#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
9905#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 10183#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9906#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 10184#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
9907#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10185#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
9908#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 10186#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
9909 u8 flags5; 10187 u8 flags5;
9910#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10188#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
9911#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10189#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
9912#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10190#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
9913#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10191#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
9914#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10192#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
9915#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10193#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
9916#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10194#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
9917#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10195#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
9918#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10196#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9919#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10197#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
9920#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10198#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9921#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10199#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
9922#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10200#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9923#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10201#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
9924#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10202#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
9925#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 10203#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
9926 __le32 reg0; 10204 __le32 reg0;
9927 __le32 reg1; 10205 __le32 reg1;
9928}; 10206};
@@ -9931,59 +10209,59 @@ struct ustorm_fcoe_conn_ag_ctx {
9931 u8 byte0; 10209 u8 byte0;
9932 u8 byte1; 10210 u8 byte1;
9933 u8 flags0; 10211 u8 flags0;
9934#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10212#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
9935#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10213#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
9936#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10214#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
9937#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10215#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
9938#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10216#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9939#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10217#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
9940#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10218#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9941#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10219#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
9942#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10220#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9943#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10221#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
9944 u8 flags1; 10222 u8 flags1;
9945#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 10223#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9946#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 10224#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
9947#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10225#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9948#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 10226#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
9949#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10227#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9950#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 10228#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
9951#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10229#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9952#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 10230#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
9953 u8 flags2; 10231 u8 flags2;
9954#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10232#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9955#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10233#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
9956#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10234#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9957#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10235#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
9958#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10236#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9959#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10237#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
9960#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 10238#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9961#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 10239#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
9962#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10240#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9963#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 10241#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
9964#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10242#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9965#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 10243#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
9966#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10244#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9967#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 10245#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
9968#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10246#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
9969#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 10247#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
9970 u8 flags3; 10248 u8 flags3;
9971#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10249#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
9972#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10250#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
9973#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10251#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
9974#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10252#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
9975#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10253#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
9976#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10254#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
9977#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10255#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
9978#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10256#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
9979#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10257#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9980#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10258#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
9981#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10259#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9982#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10260#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
9983#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10261#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9984#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10262#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
9985#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10263#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
9986#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 10264#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
9987 u8 byte2; 10265 u8 byte2;
9988 u8 byte3; 10266 u8 byte3;
9989 __le16 word0; 10267 __le16 word0;
@@ -9996,28 +10274,29 @@ struct ustorm_fcoe_conn_ag_ctx {
9996 __le16 word3; 10274 __le16 word3;
9997}; 10275};
9998 10276
10277/* The fcoe storm context of Tstorm */
9999struct tstorm_fcoe_conn_st_ctx { 10278struct tstorm_fcoe_conn_st_ctx {
10000 __le16 stat_ram_addr; 10279 __le16 stat_ram_addr;
10001 __le16 rx_max_fc_payload_len; 10280 __le16 rx_max_fc_payload_len;
10002 __le16 e_d_tov_val; 10281 __le16 e_d_tov_val;
10003 u8 flags; 10282 u8 flags;
10004#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 10283#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10005#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 10284#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10006#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 10285#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10007#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 10286#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
10008#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F 10287#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10009#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 10288#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
10010 u8 timers_cleanup_invocation_cnt; 10289 u8 timers_cleanup_invocation_cnt;
10011 __le32 reserved1[2]; 10290 __le32 reserved1[2];
10012 __le32 dst_mac_address_bytes0to3; 10291 __le32 dst_mac_address_bytes_0_to_3;
10013 __le16 dst_mac_address_bytes4to5; 10292 __le16 dst_mac_address_bytes_4_to_5;
10014 __le16 ramrod_echo; 10293 __le16 ramrod_echo;
10015 u8 flags1; 10294 u8 flags1;
10016#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 10295#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10017#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 10296#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10018#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 10297#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10019#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 10298#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
10020 u8 q_relative_offset; 10299 u8 cq_relative_offset;
10021 u8 bdq_resource_id; 10300 u8 bdq_resource_id;
10022 u8 reserved0[5]; 10301 u8 reserved0[5];
10023}; 10302};
@@ -10026,39 +10305,40 @@ struct mstorm_fcoe_conn_ag_ctx {
10026 u8 byte0; 10305 u8 byte0;
10027 u8 byte1; 10306 u8 byte1;
10028 u8 flags0; 10307 u8 flags0;
10029#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10308#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10030#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10309#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10031#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10310#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10032#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10311#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10033#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10312#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10034#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10313#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10035#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10314#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10036#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10315#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10037#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10316#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10038#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10317#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10039 u8 flags1; 10318 u8 flags1;
10040#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10319#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10041#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10320#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10042#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10321#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10043#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10322#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10044#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10323#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10045#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10324#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10046#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10325#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10047#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10326#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10048#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10327#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10049#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10328#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10050#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10329#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10051#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10330#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10052#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10331#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10053#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10332#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10054#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10333#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10055#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10334#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10056 __le16 word0; 10335 __le16 word0;
10057 __le16 word1; 10336 __le16 word1;
10058 __le32 reg0; 10337 __le32 reg0;
10059 __le32 reg1; 10338 __le32 reg1;
10060}; 10339};
10061 10340
10341/* Fast path part of the fcoe storm context of Mstorm */
10062struct fcoe_mstorm_fcoe_conn_st_ctx_fp { 10342struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10063 __le16 xfer_prod; 10343 __le16 xfer_prod;
10064 __le16 reserved1; 10344 __le16 reserved1;
@@ -10073,6 +10353,7 @@ struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10073 u8 reserved2[2]; 10353 u8 reserved2[2];
10074}; 10354};
10075 10355
10356/* Non fast path part of the fcoe storm context of Mstorm */
10076struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { 10357struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10077 __le16 conn_id; 10358 __le16 conn_id;
10078 __le16 stat_ram_addr; 10359 __le16 stat_ram_addr;
@@ -10088,11 +10369,13 @@ struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10088 struct regpair reserved2[3]; 10369 struct regpair reserved2[3];
10089}; 10370};
10090 10371
10372/* The fcoe storm context of Mstorm */
10091struct mstorm_fcoe_conn_st_ctx { 10373struct mstorm_fcoe_conn_st_ctx {
10092 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; 10374 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10093 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; 10375 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10094}; 10376};
10095 10377
10378/* fcoe connection context */
10096struct fcoe_conn_context { 10379struct fcoe_conn_context {
10097 struct ystorm_fcoe_conn_st_ctx ystorm_st_context; 10380 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10098 struct pstorm_fcoe_conn_st_ctx pstorm_st_context; 10381 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
@@ -10111,14 +10394,21 @@ struct fcoe_conn_context {
10111 struct mstorm_fcoe_conn_st_ctx mstorm_st_context; 10394 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10112}; 10395};
10113 10396
10397/* FCoE connection offload params passed by driver to FW in FCoE offload
10398 * ramrod.
10399 */
10114struct fcoe_conn_offload_ramrod_params { 10400struct fcoe_conn_offload_ramrod_params {
10115 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 10401 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10116}; 10402};
10117 10403
10404/* FCoE connection terminate params passed by driver to FW in FCoE terminate
10405 * conn ramrod.
10406 */
10118struct fcoe_conn_terminate_ramrod_params { 10407struct fcoe_conn_terminate_ramrod_params {
10119 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 10408 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10120}; 10409};
10121 10410
10411/* FCoE event type */
10122enum fcoe_event_type { 10412enum fcoe_event_type {
10123 FCOE_EVENT_INIT_FUNC, 10413 FCOE_EVENT_INIT_FUNC,
10124 FCOE_EVENT_DESTROY_FUNC, 10414 FCOE_EVENT_DESTROY_FUNC,
@@ -10129,10 +10419,12 @@ enum fcoe_event_type {
10129 MAX_FCOE_EVENT_TYPE 10419 MAX_FCOE_EVENT_TYPE
10130}; 10420};
10131 10421
10422/* FCoE init params passed by driver to FW in FCoE init ramrod */
10132struct fcoe_init_ramrod_params { 10423struct fcoe_init_ramrod_params {
10133 struct fcoe_init_func_ramrod_data init_ramrod_data; 10424 struct fcoe_init_func_ramrod_data init_ramrod_data;
10134}; 10425};
10135 10426
10427/* FCoE ramrod Command IDs */
10136enum fcoe_ramrod_cmd_id { 10428enum fcoe_ramrod_cmd_id {
10137 FCOE_RAMROD_CMD_ID_INIT_FUNC, 10429 FCOE_RAMROD_CMD_ID_INIT_FUNC,
10138 FCOE_RAMROD_CMD_ID_DESTROY_FUNC, 10430 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
@@ -10142,6 +10434,9 @@ enum fcoe_ramrod_cmd_id {
10142 MAX_FCOE_RAMROD_CMD_ID 10434 MAX_FCOE_RAMROD_CMD_ID
10143}; 10435};
10144 10436
10437/* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10438 * ramrod.
10439 */
10145struct fcoe_stat_ramrod_params { 10440struct fcoe_stat_ramrod_params {
10146 struct fcoe_stat_ramrod_data stat_ramrod_data; 10441 struct fcoe_stat_ramrod_data stat_ramrod_data;
10147}; 10442};
@@ -10150,33 +10445,33 @@ struct ystorm_fcoe_conn_ag_ctx {
10150 u8 byte0; 10445 u8 byte0;
10151 u8 byte1; 10446 u8 byte1;
10152 u8 flags0; 10447 u8 flags0;
10153#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10448#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10154#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10449#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10155#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10450#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10156#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10451#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10157#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10452#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10158#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10453#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10159#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10454#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10160#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10455#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10161#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10456#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10162#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10457#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10163 u8 flags1; 10458 u8 flags1;
10164#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10459#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10165#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10460#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10166#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10461#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10167#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10462#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10168#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10463#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10169#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10464#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10170#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10465#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10171#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10466#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10172#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10467#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10173#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10468#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10174#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10469#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10175#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10470#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10176#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10471#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10177#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10472#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10178#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10473#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10179#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10474#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10180 u8 byte2; 10475 u8 byte2;
10181 u8 byte3; 10476 u8 byte3;
10182 __le16 word0; 10477 __le16 word0;
@@ -10190,15 +10485,18 @@ struct ystorm_fcoe_conn_ag_ctx {
10190 __le32 reg3; 10485 __le32 reg3;
10191}; 10486};
10192 10487
10488/* The iscsi storm connection context of Ystorm */
10193struct ystorm_iscsi_conn_st_ctx { 10489struct ystorm_iscsi_conn_st_ctx {
10194 __le32 reserved[4]; 10490 __le32 reserved[4];
10195}; 10491};
10196 10492
10493/* Combined iSCSI and TCP storm connection of Pstorm */
10197struct pstorm_iscsi_tcp_conn_st_ctx { 10494struct pstorm_iscsi_tcp_conn_st_ctx {
10198 __le32 tcp[32]; 10495 __le32 tcp[32];
10199 __le32 iscsi[4]; 10496 __le32 iscsi[4];
10200}; 10497};
10201 10498
10499/* The combined tcp and iscsi storm context of Xstorm */
10202struct xstorm_iscsi_tcp_conn_st_ctx { 10500struct xstorm_iscsi_tcp_conn_st_ctx {
10203 __le32 reserved_iscsi[40]; 10501 __le32 reserved_iscsi[40];
10204 __le32 reserved_tcp[4]; 10502 __le32 reserved_tcp[4];
@@ -10208,212 +10506,212 @@ struct xstorm_iscsi_conn_ag_ctx {
10208 u8 cdu_validation; 10506 u8 cdu_validation;
10209 u8 state; 10507 u8 state;
10210 u8 flags0; 10508 u8 flags0;
10211#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10509#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10212#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10510#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10213#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 10511#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10214#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 10512#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
10215#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 10513#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10216#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 10514#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
10217#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 10515#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10218#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 10516#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10219#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10517#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10220#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10518#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10221#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 10519#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10222#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 10520#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
10223#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 10521#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10224#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 10522#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
10225#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 10523#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10226#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 10524#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
10227 u8 flags1; 10525 u8 flags1;
10228#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 10526#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10229#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 10527#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10230#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 10528#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10231#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 10529#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
10232#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 10530#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10233#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 10531#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
10234#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 10532#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10235#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 10533#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
10236#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 10534#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10237#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 10535#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
10238#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 10536#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10239#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 10537#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
10240#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 10538#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10241#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 10539#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
10242#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 10540#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10243#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 10541#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
10244 u8 flags2; 10542 u8 flags2;
10245#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10543#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10246#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 10544#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10247#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10545#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10248#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 10546#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
10249#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10547#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10250#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 10548#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
10251#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10549#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10252#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 10550#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
10253 u8 flags3; 10551 u8 flags3;
10254#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10552#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10255#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 10553#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10256#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10554#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10257#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 10555#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
10258#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10556#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10259#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 10557#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
10260#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10558#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10261#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 10559#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
10262 u8 flags4; 10560 u8 flags4;
10263#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10561#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10264#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 10562#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10265#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 10563#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10266#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 10564#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
10267#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 10565#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10268#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 10566#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
10269#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 10567#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10270#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 10568#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
10271 u8 flags5; 10569 u8 flags5;
10272#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 10570#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10273#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 10571#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10274#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 10572#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10275#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 10573#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
10276#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 10574#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10277#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 10575#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
10278#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 10576#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10279#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 10577#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
10280 u8 flags6; 10578 u8 flags6;
10281#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 10579#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10282#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 10580#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10283#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 10581#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10284#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 10582#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
10285#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 10583#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10286#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 10584#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
10287#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 10585#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10288#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 10586#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
10289 u8 flags7; 10587 u8 flags7;
10290#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 10588#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10291#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 10589#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10292#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 10590#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10293#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 10591#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
10294#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 10592#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10295#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 10593#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10296#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10594#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10297#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 10595#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
10298#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10596#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10299#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 10597#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
10300 u8 flags8; 10598 u8 flags8;
10301#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10599#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10302#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 10600#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10303#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10601#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10304#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 10602#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
10305#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10603#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10306#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 10604#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
10307#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10605#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10308#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 10606#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
10309#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10607#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10310#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 10608#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
10311#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10609#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10312#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 10610#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
10313#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10611#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10314#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 10612#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
10315#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 10613#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10316#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 10614#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
10317 u8 flags9; 10615 u8 flags9;
10318#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 10616#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10319#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 10617#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10320#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 10618#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10321#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 10619#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
10322#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 10620#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10323#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 10621#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
10324#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 10622#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10325#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 10623#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
10326#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 10624#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10327#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 10625#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
10328#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 10626#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10329#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 10627#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
10330#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 10628#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10331#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 10629#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
10332#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 10630#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10333#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 10631#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
10334 u8 flags10; 10632 u8 flags10;
10335#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 10633#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10336#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 10634#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10337#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 10635#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10338#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 10636#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
10339#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 10637#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10340#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 10638#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
10341#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 10639#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10342#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 10640#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
10343#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 10641#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10344#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 10642#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10345#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 10643#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10346#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 10644#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
10347#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10645#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10348#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 10646#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
10349#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 10647#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10350#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 10648#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
10351 u8 flags11; 10649 u8 flags11;
10352#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 10650#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10353#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 10651#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10354#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10652#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10355#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 10653#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
10356#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 10654#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10357#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 10655#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
10358#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10656#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10359#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 10657#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
10360#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10658#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10361#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 10659#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
10362#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10660#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10363#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 10661#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
10364#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 10662#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10365#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 10663#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10366#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 10664#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10367#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 10665#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
10368 u8 flags12; 10666 u8 flags12;
10369#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 10667#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10370#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 10668#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10371#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 10669#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10372#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 10670#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
10373#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 10671#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10374#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 10672#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10375#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 10673#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10376#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 10674#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10377#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 10675#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10378#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 10676#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
10379#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 10677#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10380#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 10678#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
10381#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 10679#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10382#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 10680#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
10383#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 10681#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10384#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 10682#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
10385 u8 flags13; 10683 u8 flags13;
10386#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 10684#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10387#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 10685#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10388#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 10686#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10389#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 10687#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
10390#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 10688#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10391#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 10689#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10392#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 10690#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10393#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 10691#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10394#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 10692#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10395#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 10693#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10396#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 10694#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10397#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 10695#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10398#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 10696#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10399#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 10697#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10400#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 10698#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10401#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 10699#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
10402 u8 flags14; 10700 u8 flags14;
10403#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 10701#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10404#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 10702#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10405#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 10703#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10406#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 10704#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
10407#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 10705#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10408#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 10706#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
10409#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 10707#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10410#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 10708#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
10411#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 10709#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10412#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 10710#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
10413#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 10711#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10414#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 10712#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
10415#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 10713#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10416#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 10714#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
10417 u8 byte2; 10715 u8 byte2;
10418 __le16 physical_q0; 10716 __le16 physical_q0;
10419 __le16 physical_q1; 10717 __le16 physical_q1;
@@ -10465,85 +10763,85 @@ struct tstorm_iscsi_conn_ag_ctx {
10465 u8 reserved0; 10763 u8 reserved0;
10466 u8 state; 10764 u8 state;
10467 u8 flags0; 10765 u8 flags0;
10468#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10766#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10469#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10767#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10470#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10768#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10471#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10769#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10472#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 10770#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10473#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 10771#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
10474#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 10772#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10475#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 10773#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
10476#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10774#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10477#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10775#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10478#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 10776#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10479#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 10777#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
10480#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10778#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10481#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 10779#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
10482 u8 flags1; 10780 u8 flags1;
10483#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 10781#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10484#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 10782#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10485#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 10783#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10486#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 10784#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
10487#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10785#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10488#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 10786#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
10489#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10787#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10490#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 10788#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
10491 u8 flags2; 10789 u8 flags2;
10492#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10790#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10493#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 10791#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10494#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10792#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10495#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 10793#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
10496#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10794#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10497#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 10795#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
10498#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10796#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10499#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 10797#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
10500 u8 flags3; 10798 u8 flags3;
10501#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 10799#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10502#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 10800#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10503#define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 10801#define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10504#define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2 10802#define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
10505#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10803#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10506#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 10804#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
10507#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 10805#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10508#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 10806#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
10509#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 10807#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10510#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 10808#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
10511#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10809#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10512#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 10810#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
10513 u8 flags4; 10811 u8 flags4;
10514#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10812#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10515#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 10813#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10516#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10814#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10517#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 10815#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
10518#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10816#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10519#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 10817#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
10520#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10818#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10521#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 10819#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
10522#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10820#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10523#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 10821#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
10524#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 10822#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10525#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 10823#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
10526#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 10824#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10527#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6 10825#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
10528#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10826#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10529#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 10827#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10530 u8 flags5; 10828 u8 flags5;
10531#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10829#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10532#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10830#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10533#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10831#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10534#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10832#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10535#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10833#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10536#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10834#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10537#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10835#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10538#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10836#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10539#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10837#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10540#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10838#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10541#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10839#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10542#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10840#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10543#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10841#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10544#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10842#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10545#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10843#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10546#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 10844#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10547 __le32 reg0; 10845 __le32 reg0;
10548 __le32 reg1; 10846 __le32 reg1;
10549 __le32 reg2; 10847 __le32 reg2;
@@ -10562,59 +10860,59 @@ struct ustorm_iscsi_conn_ag_ctx {
10562 u8 byte0; 10860 u8 byte0;
10563 u8 byte1; 10861 u8 byte1;
10564 u8 flags0; 10862 u8 flags0;
10565#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10863#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10566#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10864#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10567#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10865#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10568#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10866#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10569#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10867#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10570#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10868#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10571#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10869#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10572#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10870#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10573#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10871#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10574#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 10872#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10575 u8 flags1; 10873 u8 flags1;
10576#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 10874#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10577#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 10875#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10578#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10876#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10579#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 10877#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
10580#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10878#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10581#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 10879#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
10582#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10880#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10583#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 10881#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
10584 u8 flags2; 10882 u8 flags2;
10585#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10883#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10586#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10884#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10587#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10885#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10588#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10886#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10589#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10887#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10590#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10888#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10591#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 10889#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10592#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 10890#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
10593#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10891#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10594#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 10892#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
10595#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10893#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10596#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 10894#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
10597#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10895#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10598#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 10896#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
10599#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10897#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10600#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 10898#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
10601 u8 flags3; 10899 u8 flags3;
10602#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10900#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10603#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10901#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10604#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10902#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10605#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10903#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
10606#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10904#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10607#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10905#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
10608#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10906#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10609#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10907#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
10610#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10908#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10611#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10909#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
10612#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10910#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10613#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10911#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
10614#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10912#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10615#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10913#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
10616#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10914#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10617#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 10915#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
10618 u8 byte2; 10916 u8 byte2;
10619 u8 byte3; 10917 u8 byte3;
10620 __le16 word0; 10918 __le16 word0;
@@ -10627,6 +10925,7 @@ struct ustorm_iscsi_conn_ag_ctx {
10627 __le16 word3; 10925 __le16 word3;
10628}; 10926};
10629 10927
10928/* The iscsi storm connection context of Tstorm */
10630struct tstorm_iscsi_conn_st_ctx { 10929struct tstorm_iscsi_conn_st_ctx {
10631 __le32 reserved[40]; 10930 __le32 reserved[40];
10632}; 10931};
@@ -10635,48 +10934,51 @@ struct mstorm_iscsi_conn_ag_ctx {
10635 u8 reserved; 10934 u8 reserved;
10636 u8 state; 10935 u8 state;
10637 u8 flags0; 10936 u8 flags0;
10638#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10937#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10639#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10938#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10640#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10939#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10641#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10940#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10642#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10941#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10643#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10942#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10644#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10943#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10645#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10944#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10646#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10945#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10647#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 10946#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10648 u8 flags1; 10947 u8 flags1;
10649#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10948#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10650#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10949#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10651#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10950#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10652#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10951#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10653#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10952#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10654#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10953#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10655#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10954#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10656#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 10955#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10657#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10956#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10658#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 10957#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10659#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10958#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10660#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 10959#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10661#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10960#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10662#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 10961#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10663#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10962#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10664#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 10963#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10665 __le16 word0; 10964 __le16 word0;
10666 __le16 word1; 10965 __le16 word1;
10667 __le32 reg0; 10966 __le32 reg0;
10668 __le32 reg1; 10967 __le32 reg1;
10669}; 10968};
10670 10969
10970/* Combined iSCSI and TCP storm connection of Mstorm */
10671struct mstorm_iscsi_tcp_conn_st_ctx { 10971struct mstorm_iscsi_tcp_conn_st_ctx {
10672 __le32 reserved_tcp[20]; 10972 __le32 reserved_tcp[20];
10673 __le32 reserved_iscsi[8]; 10973 __le32 reserved_iscsi[8];
10674}; 10974};
10675 10975
10976/* The iscsi storm context of Ustorm */
10676struct ustorm_iscsi_conn_st_ctx { 10977struct ustorm_iscsi_conn_st_ctx {
10677 __le32 reserved[52]; 10978 __le32 reserved[52];
10678}; 10979};
10679 10980
10981/* iscsi connection context */
10680struct iscsi_conn_context { 10982struct iscsi_conn_context {
10681 struct ystorm_iscsi_conn_st_ctx ystorm_st_context; 10983 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
10682 struct regpair ystorm_st_padding[2]; 10984 struct regpair ystorm_st_padding[2];
@@ -10698,6 +11000,7 @@ struct iscsi_conn_context {
10698 struct ustorm_iscsi_conn_st_ctx ustorm_st_context; 11000 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
10699}; 11001};
10700 11002
11003/* iSCSI init params passed by driver to FW in iSCSI init ramrod */
10701struct iscsi_init_ramrod_params { 11004struct iscsi_init_ramrod_params {
10702 struct iscsi_spe_func_init iscsi_init_spe; 11005 struct iscsi_spe_func_init iscsi_init_spe;
10703 struct tcp_init_params tcp_init; 11006 struct tcp_init_params tcp_init;
@@ -10707,33 +11010,33 @@ struct ystorm_iscsi_conn_ag_ctx {
10707 u8 byte0; 11010 u8 byte0;
10708 u8 byte1; 11011 u8 byte1;
10709 u8 flags0; 11012 u8 flags0;
10710#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 11013#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10711#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 11014#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10712#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 11015#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10713#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 11016#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
10714#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11017#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10715#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 11018#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
10716#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 11019#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10717#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 11020#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
10718#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 11021#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10719#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 11022#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
10720 u8 flags1; 11023 u8 flags1;
10721#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11024#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10722#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 11025#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10723#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 11026#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10724#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 11027#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
10725#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 11028#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10726#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 11029#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
10727#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11030#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10728#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 11031#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
10729#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 11032#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10730#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 11033#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
10731#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 11034#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10732#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 11035#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
10733#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11036#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10734#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 11037#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
10735#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 11038#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10736#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 11039#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
10737 u8 byte2; 11040 u8 byte2;
10738 u8 byte3; 11041 u8 byte3;
10739 __le16 word0; 11042 __le16 word0;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
index b069ad088269..e106e1b556ed 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
@@ -46,75 +46,110 @@
46 0x1000) : 0) 46 0x1000) : 0)
47#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \ 47#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \
48 0x100) - 1 : 0) 48 0x100) - 1 : 0)
49#define QM_INVALID_PQ_ID 0xffff 49#define QM_INVALID_PQ_ID 0xffff
50
50/* Feature enable */ 51/* Feature enable */
51#define QM_BYPASS_EN 1 52#define QM_BYPASS_EN 1
52#define QM_BYTE_CRD_EN 1 53#define QM_BYTE_CRD_EN 1
54
53/* Other PQ constants */ 55/* Other PQ constants */
54#define QM_OTHER_PQS_PER_PF 4 56#define QM_OTHER_PQS_PER_PF 4
57
55/* WFQ constants */ 58/* WFQ constants */
56#define QM_WFQ_UPPER_BOUND 62500000 59
57#define QM_WFQ_VP_PQ_VOQ_SHIFT 0 60/* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
58#define QM_WFQ_VP_PQ_PF_SHIFT 5 61#define QM_WFQ_UPPER_BOUND 62500000
59#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000) 62
60#define QM_WFQ_MAX_INC_VAL 43750000 63/* Bit of VOQ in WFQ VP PQ map */
64#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
65
66/* Bit of PF in WFQ VP PQ map */
67#define QM_WFQ_VP_PQ_PF_SHIFT 5
68
69/* 0x9000 = 4*9*1024 */
70#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
71
72/* Max WFQ increment value is 0.7 * upper bound */
73#define QM_WFQ_MAX_INC_VAL 43750000
61 74
62/* RL constants */ 75/* RL constants */
63#define QM_RL_UPPER_BOUND 62500000 76
64#define QM_RL_PERIOD 5 /* in us */ 77/* Period in us */
65#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD) 78#define QM_RL_PERIOD 5
66#define QM_RL_MAX_INC_VAL 43750000 79
80/* Period in 25MHz cycles */
81#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
82
83/* RL increment value - rate is specified in mbps */
67#define QM_RL_INC_VAL(rate) max_t(u32, \ 84#define QM_RL_INC_VAL(rate) max_t(u32, \
68 (u32)(((rate ? rate : \ 85 (u32)(((rate ? rate : \
69 1000000) * \ 86 1000000) * \
70 QM_RL_PERIOD * \ 87 QM_RL_PERIOD * \
71 101) / (8 * 100)), 1) 88 101) / (8 * 100)), 1)
89
90/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
91#define QM_RL_UPPER_BOUND 62500000
92
93/* Max PF RL increment value is 0.7 * upper bound */
94#define QM_RL_MAX_INC_VAL 43750000
95
72/* AFullOprtnstcCrdMask constants */ 96/* AFullOprtnstcCrdMask constants */
73#define QM_OPPOR_LINE_VOQ_DEF 1 97#define QM_OPPOR_LINE_VOQ_DEF 1
74#define QM_OPPOR_FW_STOP_DEF 0 98#define QM_OPPOR_FW_STOP_DEF 0
75#define QM_OPPOR_PQ_EMPTY_DEF 1 99#define QM_OPPOR_PQ_EMPTY_DEF 1
100
76/* Command Queue constants */ 101/* Command Queue constants */
77#define PBF_CMDQ_PURE_LB_LINES 150 102
78#define PBF_CMDQ_LINES_RT_OFFSET(voq) ( \ 103/* Pure LB CmdQ lines (+spare) */
79 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \ 104#define PBF_CMDQ_PURE_LB_LINES 150
80 (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \ 105
81 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET)) 106#define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
82#define PBF_BTB_GUARANTEED_RT_OFFSET(voq) ( \ 107 (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
83 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \ 108 (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
84 (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \ 109 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
85 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET)) 110
86#define QM_VOQ_LINE_CRD(pbf_cmd_lines) ((((pbf_cmd_lines) - \ 111#define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
87 4) * \ 112 (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
88 2) | QM_LINE_CRD_REG_SIGN_BIT) 113 (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
114 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
115
116#define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
117 ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
118
89/* BTB: blocks constants (block size = 256B) */ 119/* BTB: blocks constants (block size = 256B) */
90#define BTB_JUMBO_PKT_BLOCKS 38 120
91#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS 121/* 256B blocks in 9700B packet */
92#define BTB_PURE_LB_FACTOR 10 122#define BTB_JUMBO_PKT_BLOCKS 38
93#define BTB_PURE_LB_RATIO 7 123
124/* Headroom per-port */
125#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
126#define BTB_PURE_LB_FACTOR 10
127
128/* Factored (hence really 0.7) */
129#define BTB_PURE_LB_RATIO 7
130
94/* QM stop command constants */ 131/* QM stop command constants */
95#define QM_STOP_PQ_MASK_WIDTH 32 132#define QM_STOP_PQ_MASK_WIDTH 32
96#define QM_STOP_CMD_ADDR 2 133#define QM_STOP_CMD_ADDR 2
97#define QM_STOP_CMD_STRUCT_SIZE 2 134#define QM_STOP_CMD_STRUCT_SIZE 2
98#define QM_STOP_CMD_PAUSE_MASK_OFFSET 0 135#define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
99#define QM_STOP_CMD_PAUSE_MASK_SHIFT 0 136#define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
100#define QM_STOP_CMD_PAUSE_MASK_MASK -1 137#define QM_STOP_CMD_PAUSE_MASK_MASK -1
101#define QM_STOP_CMD_GROUP_ID_OFFSET 1 138#define QM_STOP_CMD_GROUP_ID_OFFSET 1
102#define QM_STOP_CMD_GROUP_ID_SHIFT 16 139#define QM_STOP_CMD_GROUP_ID_SHIFT 16
103#define QM_STOP_CMD_GROUP_ID_MASK 15 140#define QM_STOP_CMD_GROUP_ID_MASK 15
104#define QM_STOP_CMD_PQ_TYPE_OFFSET 1 141#define QM_STOP_CMD_PQ_TYPE_OFFSET 1
105#define QM_STOP_CMD_PQ_TYPE_SHIFT 24 142#define QM_STOP_CMD_PQ_TYPE_SHIFT 24
106#define QM_STOP_CMD_PQ_TYPE_MASK 1 143#define QM_STOP_CMD_PQ_TYPE_MASK 1
107#define QM_STOP_CMD_MAX_POLL_COUNT 100 144#define QM_STOP_CMD_MAX_POLL_COUNT 100
108#define QM_STOP_CMD_POLL_PERIOD_US 500 145#define QM_STOP_CMD_POLL_PERIOD_US 500
109 146
110/* QM command macros */ 147/* QM command macros */
111#define QM_CMD_STRUCT_SIZE(cmd) cmd ## \ 148#define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
112 _STRUCT_SIZE 149#define QM_CMD_SET_FIELD(var, cmd, field, value) \
113#define QM_CMD_SET_FIELD(var, cmd, field, \ 150 SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
114 value) SET_FIELD(var[cmd ## _ ## field ## \ 151 cmd ## _ ## field, \
115 _OFFSET], \ 152 value)
116 cmd ## _ ## field, \
117 value)
118/* QM: VOQ macros */ 153/* QM: VOQ macros */
119#define PHYS_VOQ(port, tc, max_phys_tcs_per_port) ((port) * \ 154#define PHYS_VOQ(port, tc, max_phys_tcs_per_port) ((port) * \
120 (max_phys_tcs_per_port) + \ 155 (max_phys_tcs_per_port) + \
@@ -128,6 +163,7 @@
128 max_phy_tcs_pr_port) \ 163 max_phy_tcs_pr_port) \
129 : LB_VOQ(port)) 164 : LB_VOQ(port))
130/******************** INTERNAL IMPLEMENTATION *********************/ 165/******************** INTERNAL IMPLEMENTATION *********************/
166
131/* Prepare PF RL enable/disable runtime init values */ 167/* Prepare PF RL enable/disable runtime init values */
132static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en) 168static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
133{ 169{
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c
index 719cdbfe1695..8b2d1410a098 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.c
@@ -59,10 +59,10 @@ struct qed_pi_info {
59}; 59};
60 60
61struct qed_sb_sp_info { 61struct qed_sb_sp_info {
62 struct qed_sb_info sb_info; 62 struct qed_sb_info sb_info;
63 63
64 /* per protocol index data */ 64 /* per protocol index data */
65 struct qed_pi_info pi_info_arr[PIS_PER_SB]; 65 struct qed_pi_info pi_info_arr[PIS_PER_SB];
66}; 66};
67 67
68enum qed_attention_type { 68enum qed_attention_type {
@@ -82,7 +82,7 @@ struct aeu_invert_reg_bit {
82#define ATTENTION_LENGTH_SHIFT (4) 82#define ATTENTION_LENGTH_SHIFT (4)
83#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 83#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
84 ATTENTION_LENGTH_SHIFT) 84 ATTENTION_LENGTH_SHIFT)
85#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 85#define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
86#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 86#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
87#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 87#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
88 ATTENTION_PARITY) 88 ATTENTION_PARITY)
diff --git a/drivers/net/ethernet/qlogic/qed/qed_iscsi.c b/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
index 813c77cc857f..0866516c0663 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
@@ -62,22 +62,6 @@
62#include "qed_sriov.h" 62#include "qed_sriov.h"
63#include "qed_reg_addr.h" 63#include "qed_reg_addr.h"
64 64
65static int
66qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
67 u8 fw_event_code,
68 u16 echo, union event_ring_data *data, u8 fw_return_code)
69{
70 if (p_hwfn->p_iscsi_info->event_cb) {
71 struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
72
73 return p_iscsi->event_cb(p_iscsi->event_context,
74 fw_event_code, data);
75 } else {
76 DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
77 return -EINVAL;
78 }
79}
80
81struct qed_iscsi_conn { 65struct qed_iscsi_conn {
82 struct list_head list_entry; 66 struct list_head list_entry;
83 bool free_on_delete; 67 bool free_on_delete;
@@ -162,6 +146,22 @@ struct qed_iscsi_conn {
162}; 146};
163 147
164static int 148static int
149qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
150 u8 fw_event_code,
151 u16 echo, union event_ring_data *data, u8 fw_return_code)
152{
153 if (p_hwfn->p_iscsi_info->event_cb) {
154 struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
155
156 return p_iscsi->event_cb(p_iscsi->event_context,
157 fw_event_code, data);
158 } else {
159 DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
160 return -EINVAL;
161 }
162}
163
164static int
165qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn, 165qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
166 enum spq_mode comp_mode, 166 enum spq_mode comp_mode,
167 struct qed_spq_comp_cb *p_comp_addr, 167 struct qed_spq_comp_cb *p_comp_addr,
@@ -276,7 +276,7 @@ qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
276 p_ramrod->tcp_init.two_msl_timer = cpu_to_le32(p_params->two_msl_timer); 276 p_ramrod->tcp_init.two_msl_timer = cpu_to_le32(p_params->two_msl_timer);
277 val = p_params->tx_sws_timer; 277 val = p_params->tx_sws_timer;
278 p_ramrod->tcp_init.tx_sws_timer = cpu_to_le16(val); 278 p_ramrod->tcp_init.tx_sws_timer = cpu_to_le16(val);
279 p_ramrod->tcp_init.maxfinrt = p_params->max_fin_rt; 279 p_ramrod->tcp_init.max_fin_rt = p_params->max_fin_rt;
280 280
281 p_hwfn->p_iscsi_info->event_context = event_context; 281 p_hwfn->p_iscsi_info->event_context = event_context;
282 p_hwfn->p_iscsi_info->event_cb = async_event_cb; 282 p_hwfn->p_iscsi_info->event_cb = async_event_cb;
@@ -304,8 +304,8 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
304 int rc = 0; 304 int rc = 0;
305 u32 dval; 305 u32 dval;
306 u16 wval; 306 u16 wval;
307 u8 i;
308 u16 *p; 307 u16 *p;
308 u8 i;
309 309
310 /* Get SPQ entry */ 310 /* Get SPQ entry */
311 memset(&init_data, 0, sizeof(init_data)); 311 memset(&init_data, 0, sizeof(init_data));
diff --git a/drivers/scsi/qedi/qedi_fw_api.c b/drivers/scsi/qedi/qedi_fw_api.c
index 7df32a68bd54..cf43b3f70e85 100644
--- a/drivers/scsi/qedi/qedi_fw_api.c
+++ b/drivers/scsi/qedi/qedi_fw_api.c
@@ -342,56 +342,57 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
342 cpu_to_le16(dif_task_params->application_tag_mask); 342 cpu_to_le16(dif_task_params->application_tag_mask);
343 SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_CRC_SEED, 343 SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_CRC_SEED,
344 dif_task_params->crc_seed ? 1 : 0); 344 dif_task_params->crc_seed ? 1 : 0);
345 SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_HOSTGUARDTYPE, 345 SET_FIELD(rdif_context->flags0,
346 RDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
346 dif_task_params->host_guard_type); 347 dif_task_params->host_guard_type);
347 SET_FIELD(rdif_context->flags0, 348 SET_FIELD(rdif_context->flags0,
348 RDIF_TASK_CONTEXT_PROTECTIONTYPE, 349 RDIF_TASK_CONTEXT_PROTECTION_TYPE,
349 dif_task_params->protection_type); 350 dif_task_params->protection_type);
350 SET_FIELD(rdif_context->flags0, 351 SET_FIELD(rdif_context->flags0,
351 RDIF_TASK_CONTEXT_INITIALREFTAGVALID, 1); 352 RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID, 1);
352 SET_FIELD(rdif_context->flags0, 353 SET_FIELD(rdif_context->flags0,
353 RDIF_TASK_CONTEXT_KEEPREFTAGCONST, 354 RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
354 dif_task_params->keep_ref_tag_const ? 1 : 0); 355 dif_task_params->keep_ref_tag_const ? 1 : 0);
355 SET_FIELD(rdif_context->flags1, 356 SET_FIELD(rdif_context->flags1,
356 RDIF_TASK_CONTEXT_VALIDATEAPPTAG, 357 RDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
357 (dif_task_params->validate_app_tag && 358 (dif_task_params->validate_app_tag &&
358 dif_task_params->dif_on_network) ? 1 : 0); 359 dif_task_params->dif_on_network) ? 1 : 0);
359 SET_FIELD(rdif_context->flags1, 360 SET_FIELD(rdif_context->flags1,
360 RDIF_TASK_CONTEXT_VALIDATEGUARD, 361 RDIF_TASK_CONTEXT_VALIDATE_GUARD,
361 (dif_task_params->validate_guard && 362 (dif_task_params->validate_guard &&
362 dif_task_params->dif_on_network) ? 1 : 0); 363 dif_task_params->dif_on_network) ? 1 : 0);
363 SET_FIELD(rdif_context->flags1, 364 SET_FIELD(rdif_context->flags1,
364 RDIF_TASK_CONTEXT_VALIDATEREFTAG, 365 RDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
365 (dif_task_params->validate_ref_tag && 366 (dif_task_params->validate_ref_tag &&
366 dif_task_params->dif_on_network) ? 1 : 0); 367 dif_task_params->dif_on_network) ? 1 : 0);
367 SET_FIELD(rdif_context->flags1, 368 SET_FIELD(rdif_context->flags1,
368 RDIF_TASK_CONTEXT_HOSTINTERFACE, 369 RDIF_TASK_CONTEXT_HOST_INTERFACE,
369 dif_task_params->dif_on_host ? 1 : 0); 370 dif_task_params->dif_on_host ? 1 : 0);
370 SET_FIELD(rdif_context->flags1, 371 SET_FIELD(rdif_context->flags1,
371 RDIF_TASK_CONTEXT_NETWORKINTERFACE, 372 RDIF_TASK_CONTEXT_NETWORK_INTERFACE,
372 dif_task_params->dif_on_network ? 1 : 0); 373 dif_task_params->dif_on_network ? 1 : 0);
373 SET_FIELD(rdif_context->flags1, 374 SET_FIELD(rdif_context->flags1,
374 RDIF_TASK_CONTEXT_FORWARDGUARD, 375 RDIF_TASK_CONTEXT_FORWARD_GUARD,
375 dif_task_params->forward_guard ? 1 : 0); 376 dif_task_params->forward_guard ? 1 : 0);
376 SET_FIELD(rdif_context->flags1, 377 SET_FIELD(rdif_context->flags1,
377 RDIF_TASK_CONTEXT_FORWARDAPPTAG, 378 RDIF_TASK_CONTEXT_FORWARD_APP_TAG,
378 dif_task_params->forward_app_tag ? 1 : 0); 379 dif_task_params->forward_app_tag ? 1 : 0);
379 SET_FIELD(rdif_context->flags1, 380 SET_FIELD(rdif_context->flags1,
380 RDIF_TASK_CONTEXT_FORWARDREFTAG, 381 RDIF_TASK_CONTEXT_FORWARD_REF_TAG,
381 dif_task_params->forward_ref_tag ? 1 : 0); 382 dif_task_params->forward_ref_tag ? 1 : 0);
382 SET_FIELD(rdif_context->flags1, 383 SET_FIELD(rdif_context->flags1,
383 RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK, 384 RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
384 dif_task_params->forward_app_tag_with_mask ? 1 : 0); 385 dif_task_params->forward_app_tag_with_mask ? 1 : 0);
385 SET_FIELD(rdif_context->flags1, 386 SET_FIELD(rdif_context->flags1,
386 RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK, 387 RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
387 dif_task_params->forward_ref_tag_with_mask ? 1 : 0); 388 dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
388 SET_FIELD(rdif_context->flags1, 389 SET_FIELD(rdif_context->flags1,
389 RDIF_TASK_CONTEXT_INTERVALSIZE, 390 RDIF_TASK_CONTEXT_INTERVAL_SIZE,
390 dif_task_params->dif_block_size_log - 9); 391 dif_task_params->dif_block_size_log - 9);
391 SET_FIELD(rdif_context->state, 392 SET_FIELD(rdif_context->state,
392 RDIF_TASK_CONTEXT_REFTAGMASK, 393 RDIF_TASK_CONTEXT_REF_TAG_MASK,
393 dif_task_params->ref_tag_mask); 394 dif_task_params->ref_tag_mask);
394 SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNOREAPPTAG, 395 SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNORE_APP_TAG,
395 dif_task_params->ignore_app_tag); 396 dif_task_params->ignore_app_tag);
396 } 397 }
397 398
@@ -399,7 +400,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
399 task_type == ISCSI_TASK_TYPE_INITIATOR_WRITE) { 400 task_type == ISCSI_TASK_TYPE_INITIATOR_WRITE) {
400 tdif_context->app_tag_value = 401 tdif_context->app_tag_value =
401 cpu_to_le16(dif_task_params->application_tag); 402 cpu_to_le16(dif_task_params->application_tag);
402 tdif_context->partial_crc_valueB = 403 tdif_context->partial_crc_value_b =
403 cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000); 404 cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
404 tdif_context->partial_crc_value_a = 405 tdif_context->partial_crc_value_a =
405 cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000); 406 cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
@@ -407,59 +408,63 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
407 dif_task_params->crc_seed ? 1 : 0); 408 dif_task_params->crc_seed ? 1 : 0);
408 409
409 SET_FIELD(tdif_context->flags0, 410 SET_FIELD(tdif_context->flags0,
410 TDIF_TASK_CONTEXT_SETERRORWITHEOP, 411 TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP,
411 dif_task_params->tx_dif_conn_err_en ? 1 : 0); 412 dif_task_params->tx_dif_conn_err_en ? 1 : 0);
412 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDGUARD, 413 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARD_GUARD,
413 dif_task_params->forward_guard ? 1 : 0); 414 dif_task_params->forward_guard ? 1 : 0);
414 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDAPPTAG, 415 SET_FIELD(tdif_context->flags1,
416 TDIF_TASK_CONTEXT_FORWARD_APP_TAG,
415 dif_task_params->forward_app_tag ? 1 : 0); 417 dif_task_params->forward_app_tag ? 1 : 0);
416 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDREFTAG, 418 SET_FIELD(tdif_context->flags1,
419 TDIF_TASK_CONTEXT_FORWARD_REF_TAG,
417 dif_task_params->forward_ref_tag ? 1 : 0); 420 dif_task_params->forward_ref_tag ? 1 : 0);
418 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVALSIZE, 421 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVAL_SIZE,
419 dif_task_params->dif_block_size_log - 9); 422 dif_task_params->dif_block_size_log - 9);
420 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_HOSTINTERFACE, 423 SET_FIELD(tdif_context->flags1,
424 TDIF_TASK_CONTEXT_HOST_INTERFACE,
421 dif_task_params->dif_on_host ? 1 : 0); 425 dif_task_params->dif_on_host ? 1 : 0);
422 SET_FIELD(tdif_context->flags1, 426 SET_FIELD(tdif_context->flags1,
423 TDIF_TASK_CONTEXT_NETWORKINTERFACE, 427 TDIF_TASK_CONTEXT_NETWORK_INTERFACE,
424 dif_task_params->dif_on_network ? 1 : 0); 428 dif_task_params->dif_on_network ? 1 : 0);
425 val = cpu_to_le32(dif_task_params->initial_ref_tag); 429 val = cpu_to_le32(dif_task_params->initial_ref_tag);
426 tdif_context->initial_ref_tag = val; 430 tdif_context->initial_ref_tag = val;
427 tdif_context->app_tag_mask = 431 tdif_context->app_tag_mask =
428 cpu_to_le16(dif_task_params->application_tag_mask); 432 cpu_to_le16(dif_task_params->application_tag_mask);
429 SET_FIELD(tdif_context->flags0, 433 SET_FIELD(tdif_context->flags0,
430 TDIF_TASK_CONTEXT_HOSTGUARDTYPE, 434 TDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
431 dif_task_params->host_guard_type); 435 dif_task_params->host_guard_type);
432 SET_FIELD(tdif_context->flags0, 436 SET_FIELD(tdif_context->flags0,
433 TDIF_TASK_CONTEXT_PROTECTIONTYPE, 437 TDIF_TASK_CONTEXT_PROTECTION_TYPE,
434 dif_task_params->protection_type); 438 dif_task_params->protection_type);
435 SET_FIELD(tdif_context->flags0, 439 SET_FIELD(tdif_context->flags0,
436 TDIF_TASK_CONTEXT_INITIALREFTAGVALID, 440 TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID,
437 dif_task_params->initial_ref_tag_is_valid ? 1 : 0); 441 dif_task_params->initial_ref_tag_is_valid ? 1 : 0);
438 SET_FIELD(tdif_context->flags0, 442 SET_FIELD(tdif_context->flags0,
439 TDIF_TASK_CONTEXT_KEEPREFTAGCONST, 443 TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
440 dif_task_params->keep_ref_tag_const ? 1 : 0); 444 dif_task_params->keep_ref_tag_const ? 1 : 0);
441 SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_VALIDATEGUARD, 445 SET_FIELD(tdif_context->flags1,
446 TDIF_TASK_CONTEXT_VALIDATE_GUARD,
442 (dif_task_params->validate_guard && 447 (dif_task_params->validate_guard &&
443 dif_task_params->dif_on_host) ? 1 : 0); 448 dif_task_params->dif_on_host) ? 1 : 0);
444 SET_FIELD(tdif_context->flags1, 449 SET_FIELD(tdif_context->flags1,
445 TDIF_TASK_CONTEXT_VALIDATEAPPTAG, 450 TDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
446 (dif_task_params->validate_app_tag && 451 (dif_task_params->validate_app_tag &&
447 dif_task_params->dif_on_host) ? 1 : 0); 452 dif_task_params->dif_on_host) ? 1 : 0);
448 SET_FIELD(tdif_context->flags1, 453 SET_FIELD(tdif_context->flags1,
449 TDIF_TASK_CONTEXT_VALIDATEREFTAG, 454 TDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
450 (dif_task_params->validate_ref_tag && 455 (dif_task_params->validate_ref_tag &&
451 dif_task_params->dif_on_host) ? 1 : 0); 456 dif_task_params->dif_on_host) ? 1 : 0);
452 SET_FIELD(tdif_context->flags1, 457 SET_FIELD(tdif_context->flags1,
453 TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK, 458 TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
454 dif_task_params->forward_app_tag_with_mask ? 1 : 0); 459 dif_task_params->forward_app_tag_with_mask ? 1 : 0);
455 SET_FIELD(tdif_context->flags1, 460 SET_FIELD(tdif_context->flags1,
456 TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK, 461 TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
457 dif_task_params->forward_ref_tag_with_mask ? 1 : 0); 462 dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
458 SET_FIELD(tdif_context->flags1, 463 SET_FIELD(tdif_context->flags1,
459 TDIF_TASK_CONTEXT_REFTAGMASK, 464 TDIF_TASK_CONTEXT_REF_TAG_MASK,
460 dif_task_params->ref_tag_mask); 465 dif_task_params->ref_tag_mask);
461 SET_FIELD(tdif_context->flags0, 466 SET_FIELD(tdif_context->flags0,
462 TDIF_TASK_CONTEXT_IGNOREAPPTAG, 467 TDIF_TASK_CONTEXT_IGNORE_APP_TAG,
463 dif_task_params->ignore_app_tag ? 1 : 0); 468 dif_task_params->ignore_app_tag ? 1 : 0);
464 } 469 }
465} 470}
diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h
index 39e2a2ac2471..4874c104144b 100644
--- a/include/linux/qed/common_hsi.h
+++ b/include/linux/qed/common_hsi.h
@@ -32,14 +32,15 @@
32 32
33#ifndef _COMMON_HSI_H 33#ifndef _COMMON_HSI_H
34#define _COMMON_HSI_H 34#define _COMMON_HSI_H
35
35#include <linux/types.h> 36#include <linux/types.h>
36#include <asm/byteorder.h> 37#include <asm/byteorder.h>
37#include <linux/bitops.h> 38#include <linux/bitops.h>
38#include <linux/slab.h> 39#include <linux/slab.h>
39 40
40/* dma_addr_t manip */ 41/* dma_addr_t manip */
41#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff)) 42#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
42#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16)) 43#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
43#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 44#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
44#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 45#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
45#define DMA_REGPAIR_LE(x, val) do { \ 46#define DMA_REGPAIR_LE(x, val) do { \
@@ -47,39 +48,45 @@
47 (x).lo = DMA_LO_LE((val)); \ 48 (x).lo = DMA_LO_LE((val)); \
48 } while (0) 49 } while (0)
49 50
50#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 51#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
51#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) 52#define HILO_64(hi, lo) \
52#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) 53 HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
54#define HILO_64_REGPAIR(regpair) ({ \
55 typeof(regpair) __regpair = (regpair); \
56 HILO_64(__regpair.hi, __regpair.lo); })
53#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 57#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
54 58
55#ifndef __COMMON_HSI__ 59#ifndef __COMMON_HSI__
56#define __COMMON_HSI__ 60#define __COMMON_HSI__
57 61
62/********************************/
63/* PROTOCOL COMMON FW CONSTANTS */
64/********************************/
58 65
59#define X_FINAL_CLEANUP_AGG_INT 1 66#define X_FINAL_CLEANUP_AGG_INT 1
60 67
61#define EVENT_RING_PAGE_SIZE_BYTES 4096 68#define EVENT_RING_PAGE_SIZE_BYTES 4096
62 69
63#define NUM_OF_GLOBAL_QUEUES 128 70#define NUM_OF_GLOBAL_QUEUES 128
64#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 71#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
65 72
66#define ISCSI_CDU_TASK_SEG_TYPE 0 73#define ISCSI_CDU_TASK_SEG_TYPE 0
67#define FCOE_CDU_TASK_SEG_TYPE 0 74#define FCOE_CDU_TASK_SEG_TYPE 0
68#define RDMA_CDU_TASK_SEG_TYPE 1 75#define RDMA_CDU_TASK_SEG_TYPE 1
69 76
70#define FW_ASSERT_GENERAL_ATTN_IDX 32 77#define FW_ASSERT_GENERAL_ATTN_IDX 32
71 78
72#define MAX_PINNED_CCFC 32 79#define MAX_PINNED_CCFC 32
73 80
74/* Queue Zone sizes in bytes */ 81/* Queue Zone sizes in bytes */
75#define TSTORM_QZONE_SIZE 8 82#define TSTORM_QZONE_SIZE 8
76#define MSTORM_QZONE_SIZE 16 83#define MSTORM_QZONE_SIZE 16
77#define USTORM_QZONE_SIZE 8 84#define USTORM_QZONE_SIZE 8
78#define XSTORM_QZONE_SIZE 8 85#define XSTORM_QZONE_SIZE 8
79#define YSTORM_QZONE_SIZE 0 86#define YSTORM_QZONE_SIZE 0
80#define PSTORM_QZONE_SIZE 0 87#define PSTORM_QZONE_SIZE 0
81 88
82#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 89#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
83#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 90#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
84#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 91#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
85#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 92#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
@@ -115,10 +122,10 @@
115#define MAX_NUM_PORTS_BB (2) 122#define MAX_NUM_PORTS_BB (2)
116#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 123#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
117 124
118#define MAX_NUM_PFS_K2 (16) 125#define MAX_NUM_PFS_K2 (16)
119#define MAX_NUM_PFS_BB (8) 126#define MAX_NUM_PFS_BB (8)
120#define MAX_NUM_PFS (MAX_NUM_PFS_K2) 127#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
121#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 128#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
122 129
123#define MAX_NUM_VFS_K2 (192) 130#define MAX_NUM_VFS_K2 (192)
124#define MAX_NUM_VFS_BB (120) 131#define MAX_NUM_VFS_BB (120)
@@ -147,9 +154,6 @@
147 154
148#define LB_TC (NUM_OF_PHYS_TCS) 155#define LB_TC (NUM_OF_PHYS_TCS)
149 156
150/* Num of possible traffic priority values */
151#define NUM_OF_PRIO (8)
152
153#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 157#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
154#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 158#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
155#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 159#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
@@ -157,13 +161,8 @@
157 161
158/* CIDs */ 162/* CIDs */
159#define NUM_OF_CONNECTION_TYPES (8) 163#define NUM_OF_CONNECTION_TYPES (8)
160#define NUM_OF_LCIDS (320) 164#define NUM_OF_LCIDS (320)
161#define NUM_OF_LTIDS (320) 165#define NUM_OF_LTIDS (320)
162
163/* Clock values */
164#define MASTER_CLK_FREQ_E4 (375e6)
165#define STORM_CLK_FREQ_E4 (1000e6)
166#define CLK25M_CLK_FREQ_E4 (25e6)
167 166
168/* Global PXP windows (GTT) */ 167/* Global PXP windows (GTT) */
169#define NUM_OF_GTT 19 168#define NUM_OF_GTT 19
@@ -172,17 +171,17 @@
172#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 171#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
173 172
174/* Tools Version */ 173/* Tools Version */
175#define TOOLS_VERSION 10 174#define TOOLS_VERSION 10
176 175
177/*****************/ 176/*****************/
178/* CDU CONSTANTS */ 177/* CDU CONSTANTS */
179/*****************/ 178/*****************/
180 179
181#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 180#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
182#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 181#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
183 182
184#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 183#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
185#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 184#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
186 185
187#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 186#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
188#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 187#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
@@ -201,45 +200,45 @@
201#define DQ_DEMS_TOE_LOCAL_ADV_WND 4 200#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
202#define DQ_DEMS_ROCE_CQ_CONS 7 201#define DQ_DEMS_ROCE_CQ_CONS 7
203 202
204/* XCM agg val selection */ 203/* XCM agg val selection (HW) */
205#define DQ_XCM_AGG_VAL_SEL_WORD2 0 204#define DQ_XCM_AGG_VAL_SEL_WORD2 0
206#define DQ_XCM_AGG_VAL_SEL_WORD3 1 205#define DQ_XCM_AGG_VAL_SEL_WORD3 1
207#define DQ_XCM_AGG_VAL_SEL_WORD4 2 206#define DQ_XCM_AGG_VAL_SEL_WORD4 2
208#define DQ_XCM_AGG_VAL_SEL_WORD5 3 207#define DQ_XCM_AGG_VAL_SEL_WORD5 3
209#define DQ_XCM_AGG_VAL_SEL_REG3 4 208#define DQ_XCM_AGG_VAL_SEL_REG3 4
210#define DQ_XCM_AGG_VAL_SEL_REG4 5 209#define DQ_XCM_AGG_VAL_SEL_REG4 5
211#define DQ_XCM_AGG_VAL_SEL_REG5 6 210#define DQ_XCM_AGG_VAL_SEL_REG5 6
212#define DQ_XCM_AGG_VAL_SEL_REG6 7 211#define DQ_XCM_AGG_VAL_SEL_REG6 7
213 212
214/* XCM agg val selection */ 213/* XCM agg val selection (FW) */
215#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 214#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
216#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 215#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
217#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 216#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
218#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 217#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
219#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 218#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
220#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 219#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
221#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 220#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
222#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 221#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
223#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 222#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
224#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 223#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
225#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 224#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
226#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 225#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
227#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 226#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
228#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 227#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
229#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 228#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
230#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 229#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
231#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 230#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
232#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 231#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
233 232
234/* UCM agg val selection (HW) */ 233/* UCM agg val selection (HW) */
235#define DQ_UCM_AGG_VAL_SEL_WORD0 0 234#define DQ_UCM_AGG_VAL_SEL_WORD0 0
236#define DQ_UCM_AGG_VAL_SEL_WORD1 1 235#define DQ_UCM_AGG_VAL_SEL_WORD1 1
237#define DQ_UCM_AGG_VAL_SEL_WORD2 2 236#define DQ_UCM_AGG_VAL_SEL_WORD2 2
238#define DQ_UCM_AGG_VAL_SEL_WORD3 3 237#define DQ_UCM_AGG_VAL_SEL_WORD3 3
239#define DQ_UCM_AGG_VAL_SEL_REG0 4 238#define DQ_UCM_AGG_VAL_SEL_REG0 4
240#define DQ_UCM_AGG_VAL_SEL_REG1 5 239#define DQ_UCM_AGG_VAL_SEL_REG1 5
241#define DQ_UCM_AGG_VAL_SEL_REG2 6 240#define DQ_UCM_AGG_VAL_SEL_REG2 6
242#define DQ_UCM_AGG_VAL_SEL_REG3 7 241#define DQ_UCM_AGG_VAL_SEL_REG3 7
243 242
244/* UCM agg val selection (FW) */ 243/* UCM agg val selection (FW) */
245#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 244#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
@@ -263,7 +262,7 @@
263#define DQ_TCM_ROCE_RQ_PROD_CMD \ 262#define DQ_TCM_ROCE_RQ_PROD_CMD \
264 DQ_TCM_AGG_VAL_SEL_WORD0 263 DQ_TCM_AGG_VAL_SEL_WORD0
265 264
266/* XCM agg counter flag selection */ 265/* XCM agg counter flag selection (HW) */
267#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 266#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
268#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 267#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
269#define DQ_XCM_AGG_FLG_SHIFT_CF12 2 268#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
@@ -273,20 +272,20 @@
273#define DQ_XCM_AGG_FLG_SHIFT_CF22 6 272#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
274#define DQ_XCM_AGG_FLG_SHIFT_CF23 7 273#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
275 274
276/* XCM agg counter flag selection */ 275/* XCM agg counter flag selection (FW) */
277#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 276#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
278#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 277#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
279#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 278#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
280#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 279#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
281#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 280#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
282#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 281#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
283#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 282#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
284#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 283#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
285#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 284#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
286#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 285#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
287#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 286#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
288#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 287#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
289#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 288#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
290 289
291/* UCM agg counter flag selection (HW) */ 290/* UCM agg counter flag selection (HW) */
292#define DQ_UCM_AGG_FLG_SHIFT_CF0 0 291#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -317,9 +316,9 @@
317#define DQ_TCM_AGG_FLG_SHIFT_CF6 6 316#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
318#define DQ_TCM_AGG_FLG_SHIFT_CF7 7 317#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
319/* TCM agg counter flag selection (FW) */ 318/* TCM agg counter flag selection (FW) */
320#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 319#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
321#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) 320#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
322#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 321#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
323#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 322#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
324#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 323#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
325#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 324#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
@@ -327,18 +326,18 @@
327#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 326#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
328 327
329/* PWM address mapping */ 328/* PWM address mapping */
330#define DQ_PWM_OFFSET_DPM_BASE 0x0 329#define DQ_PWM_OFFSET_DPM_BASE 0x0
331#define DQ_PWM_OFFSET_DPM_END 0x27 330#define DQ_PWM_OFFSET_DPM_END 0x27
332#define DQ_PWM_OFFSET_XCM16_BASE 0x40 331#define DQ_PWM_OFFSET_XCM16_BASE 0x40
333#define DQ_PWM_OFFSET_XCM32_BASE 0x44 332#define DQ_PWM_OFFSET_XCM32_BASE 0x44
334#define DQ_PWM_OFFSET_UCM16_BASE 0x48 333#define DQ_PWM_OFFSET_UCM16_BASE 0x48
335#define DQ_PWM_OFFSET_UCM32_BASE 0x4C 334#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
336#define DQ_PWM_OFFSET_UCM16_4 0x50 335#define DQ_PWM_OFFSET_UCM16_4 0x50
337#define DQ_PWM_OFFSET_TCM16_BASE 0x58 336#define DQ_PWM_OFFSET_TCM16_BASE 0x58
338#define DQ_PWM_OFFSET_TCM32_BASE 0x5C 337#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
339#define DQ_PWM_OFFSET_XCM_FLAGS 0x68 338#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
340#define DQ_PWM_OFFSET_UCM_FLAGS 0x69 339#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
341#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 340#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
342 341
343#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 342#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
344#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 343#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
@@ -347,10 +346,11 @@
347#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 346#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
348#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 347#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
349#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 348#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
350#define DQ_REGION_SHIFT (12) 349
350#define DQ_REGION_SHIFT (12)
351 351
352/* DPM */ 352/* DPM */
353#define DQ_DPM_WQE_BUFF_SIZE (320) 353#define DQ_DPM_WQE_BUFF_SIZE (320)
354 354
355/* Conn type ranges */ 355/* Conn type ranges */
356#define DQ_CONN_TYPE_RANGE_SHIFT (4) 356#define DQ_CONN_TYPE_RANGE_SHIFT (4)
@@ -359,29 +359,30 @@
359/* QM CONSTANTS */ 359/* QM CONSTANTS */
360/*****************/ 360/*****************/
361 361
362/* number of TX queues in the QM */ 362/* Number of TX queues in the QM */
363#define MAX_QM_TX_QUEUES_K2 512 363#define MAX_QM_TX_QUEUES_K2 512
364#define MAX_QM_TX_QUEUES_BB 448 364#define MAX_QM_TX_QUEUES_BB 448
365#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 365#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
366 366
367/* number of Other queues in the QM */ 367/* Number of Other queues in the QM */
368#define MAX_QM_OTHER_QUEUES_BB 64 368#define MAX_QM_OTHER_QUEUES_BB 64
369#define MAX_QM_OTHER_QUEUES_K2 128 369#define MAX_QM_OTHER_QUEUES_K2 128
370#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 370#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
371 371
372/* number of queues in a PF queue group */ 372/* Number of queues in a PF queue group */
373#define QM_PF_QUEUE_GROUP_SIZE 8 373#define QM_PF_QUEUE_GROUP_SIZE 8
374 374
375/* the size of a single queue element in bytes */ 375/* The size of a single queue element in bytes */
376#define QM_PQ_ELEMENT_SIZE 4 376#define QM_PQ_ELEMENT_SIZE 4
377 377
378/* base number of Tx PQs in the CM PQ representation. 378/* Base number of Tx PQs in the CM PQ representation.
379 * should be used when storing PQ IDs in CM PQ registers and context 379 * Should be used when storing PQ IDs in CM PQ registers and context.
380 */ 380 */
381#define CM_TX_PQ_BASE 0x200 381#define CM_TX_PQ_BASE 0x200
382 382
383/* number of global Vport/QCN rate limiters */ 383/* Number of global Vport/QCN rate limiters */
384#define MAX_QM_GLOBAL_RLS 256 384#define MAX_QM_GLOBAL_RLS 256
385
385/* QM registers data */ 386/* QM registers data */
386#define QM_LINE_CRD_REG_WIDTH 16 387#define QM_LINE_CRD_REG_WIDTH 16
387#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 388#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
@@ -432,8 +433,7 @@
432 433
433#define IGU_CMD_INT_ACK_BASE 0x0400 434#define IGU_CMD_INT_ACK_BASE 0x0400
434#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 435#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
435 MAX_TOT_SB_PER_PATH - \ 436 MAX_TOT_SB_PER_PATH - 1)
436 1)
437#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 437#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
438 438
439#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 439#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@@ -447,8 +447,7 @@
447 447
448#define IGU_CMD_PROD_UPD_BASE 0x0600 448#define IGU_CMD_PROD_UPD_BASE 0x0600
449#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 449#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
450 MAX_TOT_SB_PER_PATH - \ 450 MAX_TOT_SB_PER_PATH - 1)
451 1)
452#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 451#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
453 452
454/*****************/ 453/*****************/
@@ -514,129 +513,121 @@
514 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 513 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
515 514
516/* PF BAR */ 515/* PF BAR */
517#define PXP_BAR0_START_GRC 0x0000 516#define PXP_BAR0_START_GRC 0x0000
518#define PXP_BAR0_GRC_LENGTH 0x1C00000 517#define PXP_BAR0_GRC_LENGTH 0x1C00000
519#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 518#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
520 PXP_BAR0_GRC_LENGTH - 1) 519 PXP_BAR0_GRC_LENGTH - 1)
521 520
522#define PXP_BAR0_START_IGU 0x1C00000 521#define PXP_BAR0_START_IGU 0x1C00000
523#define PXP_BAR0_IGU_LENGTH 0x10000 522#define PXP_BAR0_IGU_LENGTH 0x10000
524#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 523#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
525 PXP_BAR0_IGU_LENGTH - 1) 524 PXP_BAR0_IGU_LENGTH - 1)
526 525
527#define PXP_BAR0_START_TSDM 0x1C80000 526#define PXP_BAR0_START_TSDM 0x1C80000
528#define PXP_BAR0_SDM_LENGTH 0x40000 527#define PXP_BAR0_SDM_LENGTH 0x40000
529#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 528#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
530#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 529#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
531 PXP_BAR0_SDM_LENGTH - 1) 530 PXP_BAR0_SDM_LENGTH - 1)
532 531
533#define PXP_BAR0_START_MSDM 0x1D00000 532#define PXP_BAR0_START_MSDM 0x1D00000
534#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 533#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
535 PXP_BAR0_SDM_LENGTH - 1) 534 PXP_BAR0_SDM_LENGTH - 1)
536 535
537#define PXP_BAR0_START_USDM 0x1D80000 536#define PXP_BAR0_START_USDM 0x1D80000
538#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 537#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
539 PXP_BAR0_SDM_LENGTH - 1) 538 PXP_BAR0_SDM_LENGTH - 1)
540 539
541#define PXP_BAR0_START_XSDM 0x1E00000 540#define PXP_BAR0_START_XSDM 0x1E00000
542#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 541#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
543 PXP_BAR0_SDM_LENGTH - 1) 542 PXP_BAR0_SDM_LENGTH - 1)
544 543
545#define PXP_BAR0_START_YSDM 0x1E80000 544#define PXP_BAR0_START_YSDM 0x1E80000
546#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 545#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
547 PXP_BAR0_SDM_LENGTH - 1) 546 PXP_BAR0_SDM_LENGTH - 1)
548 547
549#define PXP_BAR0_START_PSDM 0x1F00000 548#define PXP_BAR0_START_PSDM 0x1F00000
550#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 549#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
551 PXP_BAR0_SDM_LENGTH - 1) 550 PXP_BAR0_SDM_LENGTH - 1)
552 551
553#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 552#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
554 553
555/* VF BAR */ 554/* VF BAR */
556#define PXP_VF_BAR0 0 555#define PXP_VF_BAR0 0
557 556
558#define PXP_VF_BAR0_START_GRC 0x3E00 557#define PXP_VF_BAR0_START_IGU 0
559#define PXP_VF_BAR0_GRC_LENGTH 0x200 558#define PXP_VF_BAR0_IGU_LENGTH 0x3000
560#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 559#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
561 PXP_VF_BAR0_GRC_LENGTH - 1) 560 PXP_VF_BAR0_IGU_LENGTH - 1)
562 561
563#define PXP_VF_BAR0_START_IGU 0 562#define PXP_VF_BAR0_START_DQ 0x3000
564#define PXP_VF_BAR0_IGU_LENGTH 0x3000 563#define PXP_VF_BAR0_DQ_LENGTH 0x200
565#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 564#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
566 PXP_VF_BAR0_IGU_LENGTH - 1) 565#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
567 566 PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
568#define PXP_VF_BAR0_START_DQ 0x3000 567#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
569#define PXP_VF_BAR0_DQ_LENGTH 0x200 568 + 4)
570#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 569#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
571#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 570 PXP_VF_BAR0_DQ_LENGTH - 1)
572 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 571
573#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 572#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
574 + 4) 573#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
575#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 574#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
576 PXP_VF_BAR0_DQ_LENGTH - 1) 575 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
577 576
578#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 577#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
579#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 578#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
580#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 579 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
581 + \ 580
582 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 581#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
583 - 1) 582#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
584 583 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
585#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 584
586#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 585#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
587 + \ 586#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
588 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 587 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
589 - 1) 588
590 589#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
591#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 590#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
592#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 591 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
593 + \ 592
594 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 593#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
595 - 1) 594#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
596 595 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
597#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 596
598#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 597#define PXP_VF_BAR0_START_GRC 0x3E00
599 + \ 598#define PXP_VF_BAR0_GRC_LENGTH 0x200
600 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 599#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
601 - 1) 600 PXP_VF_BAR0_GRC_LENGTH - 1)
602 601
603#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 602#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
604#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 603#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
605 + \ 604
606 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 605#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
607 - 1) 606
608 607#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
609#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 608#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
610#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \
611 + \
612 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
613 - 1)
614
615#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
616#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
617
618#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
619
620#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
621#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
622 609
623/* ILT Records */ 610/* ILT Records */
624#define PXP_NUM_ILT_RECORDS_BB 7600 611#define PXP_NUM_ILT_RECORDS_BB 7600
625#define PXP_NUM_ILT_RECORDS_K2 11000 612#define PXP_NUM_ILT_RECORDS_K2 11000
626#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 613#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
627#define PXP_QUEUES_ZONE_MAX_NUM 320 614
615/* Host Interface */
616#define PXP_QUEUES_ZONE_MAX_NUM 320
617
628/*****************/ 618/*****************/
629/* PRM CONSTANTS */ 619/* PRM CONSTANTS */
630/*****************/ 620/*****************/
631#define PRM_DMA_PAD_BYTES_NUM 2 621#define PRM_DMA_PAD_BYTES_NUM 2
622
632/*****************/ 623/*****************/
633/* SDMs CONSTANTS */ 624/* SDMs CONSTANTS */
634/*****************/ 625/*****************/
635 626
636#define SDM_OP_GEN_TRIG_NONE 0 627#define SDM_OP_GEN_TRIG_NONE 0
637#define SDM_OP_GEN_TRIG_WAKE_THREAD 1 628#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
638#define SDM_OP_GEN_TRIG_AGG_INT 2 629#define SDM_OP_GEN_TRIG_AGG_INT 2
639#define SDM_OP_GEN_TRIG_LOADER 4 630#define SDM_OP_GEN_TRIG_LOADER 4
640#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 631#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
641#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 632#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
642 633
@@ -644,26 +635,26 @@
644/* Completion types */ 635/* Completion types */
645/********************/ 636/********************/
646 637
647#define SDM_COMP_TYPE_NONE 0 638#define SDM_COMP_TYPE_NONE 0
648#define SDM_COMP_TYPE_WAKE_THREAD 1 639#define SDM_COMP_TYPE_WAKE_THREAD 1
649#define SDM_COMP_TYPE_AGG_INT 2 640#define SDM_COMP_TYPE_AGG_INT 2
650#define SDM_COMP_TYPE_CM 3 641#define SDM_COMP_TYPE_CM 3
651#define SDM_COMP_TYPE_LOADER 4 642#define SDM_COMP_TYPE_LOADER 4
652#define SDM_COMP_TYPE_PXP 5 643#define SDM_COMP_TYPE_PXP 5
653#define SDM_COMP_TYPE_INDICATE_ERROR 6 644#define SDM_COMP_TYPE_INDICATE_ERROR 6
654#define SDM_COMP_TYPE_RELEASE_THREAD 7 645#define SDM_COMP_TYPE_RELEASE_THREAD 7
655#define SDM_COMP_TYPE_RAM 8 646#define SDM_COMP_TYPE_RAM 8
656#define SDM_COMP_TYPE_INC_ORDER_CNT 9 647#define SDM_COMP_TYPE_INC_ORDER_CNT 9
657 648
658/*****************/ 649/*****************/
659/* PBF Constants */ 650/* PBF CONSTANTS */
660/*****************/ 651/*****************/
661 652
662/* Number of PBF command queue lines. Each line is 32B. */ 653/* Number of PBF command queue lines. Each line is 32B. */
663#define PBF_MAX_CMD_LINES 3328 654#define PBF_MAX_CMD_LINES 3328
664 655
665/* Number of BTB blocks. Each block is 256B. */ 656/* Number of BTB blocks. Each block is 256B. */
666#define BTB_MAX_BLOCKS 1440 657#define BTB_MAX_BLOCKS 1440
667 658
668/*****************/ 659/*****************/
669/* PRS CONSTANTS */ 660/* PRS CONSTANTS */
@@ -679,6 +670,7 @@ struct async_data {
679 u8 fw_debug_param; 670 u8 fw_debug_param;
680}; 671};
681 672
673/* Interrupt coalescing TimeSet */
682struct coalescing_timeset { 674struct coalescing_timeset {
683 u8 value; 675 u8 value;
684#define COALESCING_TIMESET_TIMESET_MASK 0x7F 676#define COALESCING_TIMESET_TIMESET_MASK 0x7F
@@ -692,20 +684,12 @@ struct common_queue_zone {
692 __le16 reserved; 684 __le16 reserved;
693}; 685};
694 686
687/* ETH Rx producers data */
695struct eth_rx_prod_data { 688struct eth_rx_prod_data {
696 __le16 bd_prod; 689 __le16 bd_prod;
697 __le16 cqe_prod; 690 __le16 cqe_prod;
698}; 691};
699 692
700struct regpair {
701 __le32 lo;
702 __le32 hi;
703};
704
705struct vf_pf_channel_eqe_data {
706 struct regpair msg_addr;
707};
708
709struct iscsi_eqe_data { 693struct iscsi_eqe_data {
710 __le32 cid; 694 __le32 cid;
711 __le16 conn_id; 695 __le16 conn_id;
@@ -719,52 +703,6 @@ struct iscsi_eqe_data {
719#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 703#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
720}; 704};
721 705
722struct rdma_eqe_destroy_qp {
723 __le32 cid;
724 u8 reserved[4];
725};
726
727union rdma_eqe_data {
728 struct regpair async_handle;
729 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
730};
731
732struct malicious_vf_eqe_data {
733 u8 vf_id;
734 u8 err_id;
735 __le16 reserved[3];
736};
737
738struct initial_cleanup_eqe_data {
739 u8 vf_id;
740 u8 reserved[7];
741};
742
743/* Event Data Union */
744union event_ring_data {
745 u8 bytes[8];
746 struct vf_pf_channel_eqe_data vf_pf_channel;
747 struct iscsi_eqe_data iscsi_info;
748 union rdma_eqe_data rdma_data;
749 struct malicious_vf_eqe_data malicious_vf;
750 struct initial_cleanup_eqe_data vf_init_cleanup;
751};
752
753/* Event Ring Entry */
754struct event_ring_entry {
755 u8 protocol_id;
756 u8 opcode;
757 __le16 reserved0;
758 __le16 echo;
759 u8 fw_return_code;
760 u8 flags;
761#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
762#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
763#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
764#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
765 union event_ring_data data;
766};
767
768/* Multi function mode */ 706/* Multi function mode */
769enum mf_mode { 707enum mf_mode {
770 ERROR_MODE /* Unsupported mode */, 708 ERROR_MODE /* Unsupported mode */,
@@ -781,13 +719,31 @@ enum protocol_type {
781 PROTOCOLID_CORE, 719 PROTOCOLID_CORE,
782 PROTOCOLID_ETH, 720 PROTOCOLID_ETH,
783 PROTOCOLID_IWARP, 721 PROTOCOLID_IWARP,
784 PROTOCOLID_RESERVED5, 722 PROTOCOLID_RESERVED0,
785 PROTOCOLID_PREROCE, 723 PROTOCOLID_PREROCE,
786 PROTOCOLID_COMMON, 724 PROTOCOLID_COMMON,
787 PROTOCOLID_RESERVED6, 725 PROTOCOLID_RESERVED1,
788 MAX_PROTOCOL_TYPE 726 MAX_PROTOCOL_TYPE
789}; 727};
790 728
729struct regpair {
730 __le32 lo;
731 __le32 hi;
732};
733
734/* RoCE Destroy Event Data */
735struct rdma_eqe_destroy_qp {
736 __le32 cid;
737 u8 reserved[4];
738};
739
740/* RDMA Event Data Union */
741union rdma_eqe_data {
742 struct regpair async_handle;
743 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
744};
745
746/* Ustorm Queue Zone */
791struct ustorm_eth_queue_zone { 747struct ustorm_eth_queue_zone {
792 struct coalescing_timeset int_coalescing_timeset; 748 struct coalescing_timeset int_coalescing_timeset;
793 u8 reserved[3]; 749 u8 reserved[3];
@@ -798,62 +754,71 @@ struct ustorm_queue_zone {
798 struct common_queue_zone common; 754 struct common_queue_zone common;
799}; 755};
800 756
801/* status block structure */ 757/* Status block structure */
802struct cau_pi_entry { 758struct cau_pi_entry {
803 u32 prod; 759 u32 prod;
804#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 760#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
805#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 761#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
806#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 762#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
807#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 763#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
808#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 764#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
809#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 765#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
810#define CAU_PI_ENTRY_RESERVED_MASK 0xFF 766#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
811#define CAU_PI_ENTRY_RESERVED_SHIFT 24 767#define CAU_PI_ENTRY_RESERVED_SHIFT 24
812}; 768};
813 769
814/* status block structure */ 770/* Status block structure */
815struct cau_sb_entry { 771struct cau_sb_entry {
816 u32 data; 772 u32 data;
817#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 773#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
818#define CAU_SB_ENTRY_SB_PROD_SHIFT 0 774#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
819#define CAU_SB_ENTRY_STATE0_MASK 0xF 775#define CAU_SB_ENTRY_STATE0_MASK 0xF
820#define CAU_SB_ENTRY_STATE0_SHIFT 24 776#define CAU_SB_ENTRY_STATE0_SHIFT 24
821#define CAU_SB_ENTRY_STATE1_MASK 0xF 777#define CAU_SB_ENTRY_STATE1_MASK 0xF
822#define CAU_SB_ENTRY_STATE1_SHIFT 28 778#define CAU_SB_ENTRY_STATE1_SHIFT 28
823 u32 params; 779 u32 params;
824#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 780#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
825#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 781#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
826#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 782#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
827#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 783#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
828#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 784#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
829#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 785#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
830#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 786#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
831#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 787#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
832#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 788#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
833#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 789#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
834#define CAU_SB_ENTRY_VF_VALID_MASK 0x1 790#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
835#define CAU_SB_ENTRY_VF_VALID_SHIFT 26 791#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
836#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 792#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
837#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 793#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
838#define CAU_SB_ENTRY_TPH_MASK 0x1 794#define CAU_SB_ENTRY_TPH_MASK 0x1
839#define CAU_SB_ENTRY_TPH_SHIFT 31 795#define CAU_SB_ENTRY_TPH_SHIFT 31
796};
797
798/* Igu cleanup bit values to distinguish between clean or producer consumer
799 * update.
800 */
801enum command_type_bit {
802 IGU_COMMAND_TYPE_NOP = 0,
803 IGU_COMMAND_TYPE_SET = 1,
804 MAX_COMMAND_TYPE_BIT
840}; 805};
841 806
842/* core doorbell data */ 807/* Core doorbell data */
843struct core_db_data { 808struct core_db_data {
844 u8 params; 809 u8 params;
845#define CORE_DB_DATA_DEST_MASK 0x3 810#define CORE_DB_DATA_DEST_MASK 0x3
846#define CORE_DB_DATA_DEST_SHIFT 0 811#define CORE_DB_DATA_DEST_SHIFT 0
847#define CORE_DB_DATA_AGG_CMD_MASK 0x3 812#define CORE_DB_DATA_AGG_CMD_MASK 0x3
848#define CORE_DB_DATA_AGG_CMD_SHIFT 2 813#define CORE_DB_DATA_AGG_CMD_SHIFT 2
849#define CORE_DB_DATA_BYPASS_EN_MASK 0x1 814#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
850#define CORE_DB_DATA_BYPASS_EN_SHIFT 4 815#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
851#define CORE_DB_DATA_RESERVED_MASK 0x1 816#define CORE_DB_DATA_RESERVED_MASK 0x1
852#define CORE_DB_DATA_RESERVED_SHIFT 5 817#define CORE_DB_DATA_RESERVED_SHIFT 5
853#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 818#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
854#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 819#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
855 u8 agg_flags; 820 u8 agg_flags;
856 __le16 spq_prod; 821 __le16 spq_prod;
857}; 822};
858 823
859/* Enum of doorbell aggregative command selection */ 824/* Enum of doorbell aggregative command selection */
@@ -909,67 +874,69 @@ struct db_l2_dpm_sge {
909 struct regpair addr; 874 struct regpair addr;
910 __le16 nbytes; 875 __le16 nbytes;
911 __le16 bitfields; 876 __le16 bitfields;
912#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 877#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
913#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 878#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
914#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 879#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
915#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 880#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
916#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 881#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
917#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 882#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
918#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 883#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
919#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 884#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
920 __le32 reserved2; 885 __le32 reserved2;
921}; 886};
922 887
923/* Structure for doorbell address, in legacy mode */ 888/* Structure for doorbell address, in legacy mode */
924struct db_legacy_addr { 889struct db_legacy_addr {
925 __le32 addr; 890 __le32 addr;
926#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 891#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
927#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 892#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
928#define DB_LEGACY_ADDR_DEMS_MASK 0x7 893#define DB_LEGACY_ADDR_DEMS_MASK 0x7
929#define DB_LEGACY_ADDR_DEMS_SHIFT 2 894#define DB_LEGACY_ADDR_DEMS_SHIFT 2
930#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 895#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
931#define DB_LEGACY_ADDR_ICID_SHIFT 5 896#define DB_LEGACY_ADDR_ICID_SHIFT 5
932}; 897};
933 898
934/* Structure for doorbell address, in PWM mode */ 899/* Structure for doorbell address, in PWM mode */
935struct db_pwm_addr { 900struct db_pwm_addr {
936 __le32 addr; 901 __le32 addr;
937#define DB_PWM_ADDR_RESERVED0_MASK 0x7 902#define DB_PWM_ADDR_RESERVED0_MASK 0x7
938#define DB_PWM_ADDR_RESERVED0_SHIFT 0 903#define DB_PWM_ADDR_RESERVED0_SHIFT 0
939#define DB_PWM_ADDR_OFFSET_MASK 0x7F 904#define DB_PWM_ADDR_OFFSET_MASK 0x7F
940#define DB_PWM_ADDR_OFFSET_SHIFT 3 905#define DB_PWM_ADDR_OFFSET_SHIFT 3
941#define DB_PWM_ADDR_WID_MASK 0x3 906#define DB_PWM_ADDR_WID_MASK 0x3
942#define DB_PWM_ADDR_WID_SHIFT 10 907#define DB_PWM_ADDR_WID_SHIFT 10
943#define DB_PWM_ADDR_DPI_MASK 0xFFFF 908#define DB_PWM_ADDR_DPI_MASK 0xFFFF
944#define DB_PWM_ADDR_DPI_SHIFT 12 909#define DB_PWM_ADDR_DPI_SHIFT 12
945#define DB_PWM_ADDR_RESERVED1_MASK 0xF 910#define DB_PWM_ADDR_RESERVED1_MASK 0xF
946#define DB_PWM_ADDR_RESERVED1_SHIFT 28 911#define DB_PWM_ADDR_RESERVED1_SHIFT 28
947}; 912};
948 913
949/* Parameters to RoCE firmware, passed in EDPM doorbell */ 914/* Parameters to RDMA firmware, passed in EDPM doorbell */
950struct db_rdma_dpm_params { 915struct db_rdma_dpm_params {
951 __le32 params; 916 __le32 params;
952#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 917#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
953#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 918#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
954#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 919#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
955#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 920#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
956#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 921#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
957#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 922#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
958#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 923#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
959#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 924#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
960#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 925#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
961#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 926#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
962#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 927#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
963#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 928#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
964#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 929#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
965#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 930#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
966#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 931#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
967#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 932#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
968#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 933#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
969#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 934#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
970}; 935};
971 936
972/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ 937/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
938 * DPM burst.
939 */
973struct db_rdma_dpm_data { 940struct db_rdma_dpm_data {
974 __le16 icid; 941 __le16 icid;
975 __le16 prod_val; 942 __le16 prod_val;
@@ -988,20 +955,20 @@ enum igu_int_cmd {
988/* IGU producer or consumer update command */ 955/* IGU producer or consumer update command */
989struct igu_prod_cons_update { 956struct igu_prod_cons_update {
990 u32 sb_id_and_flags; 957 u32 sb_id_and_flags;
991#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 958#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
992#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 959#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
993#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 960#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
994#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 961#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
995#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 962#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
996#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 963#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
997#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 964#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
998#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 965#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
999#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 966#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1000#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 967#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
1001#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 968#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1002#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 969#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
1003#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 970#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1004#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 971#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
1005 u32 reserved1; 972 u32 reserved1;
1006}; 973};
1007 974
@@ -1014,36 +981,37 @@ enum igu_seg_access {
1014 981
1015struct parsing_and_err_flags { 982struct parsing_and_err_flags {
1016 __le16 flags; 983 __le16 flags;
1017#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 984#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1018#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 985#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1019#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 986#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1020#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 987#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1021#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 988#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1022#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 989#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1023#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 990#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1024#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 991#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1025#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 992#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1026#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 993#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1027#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 994#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1028#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 995#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1029#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 996#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1030#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 997#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1031#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 998#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1032#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 999#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1033#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1000#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1034#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1001#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1035#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1002#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1036#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1003#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1037#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1004#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1038#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1005#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1039#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1006#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1040#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1007#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1041#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1008#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1042#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1009#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1043#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1010#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1044#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1011#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1045}; 1012};
1046 1013
1014/* Parsing error flags bitmap */
1047struct parsing_err_flags { 1015struct parsing_err_flags {
1048 __le16 flags; 1016 __le16 flags;
1049#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1017#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
@@ -1080,168 +1048,160 @@ struct parsing_err_flags {
1080#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1048#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
1081}; 1049};
1082 1050
1051/* Pb context */
1083struct pb_context { 1052struct pb_context {
1084 __le32 crc[4]; 1053 __le32 crc[4];
1085}; 1054};
1086 1055
1056/* Concrete Function ID */
1087struct pxp_concrete_fid { 1057struct pxp_concrete_fid {
1088 __le16 fid; 1058 __le16 fid;
1089#define PXP_CONCRETE_FID_PFID_MASK 0xF 1059#define PXP_CONCRETE_FID_PFID_MASK 0xF
1090#define PXP_CONCRETE_FID_PFID_SHIFT 0 1060#define PXP_CONCRETE_FID_PFID_SHIFT 0
1091#define PXP_CONCRETE_FID_PORT_MASK 0x3 1061#define PXP_CONCRETE_FID_PORT_MASK 0x3
1092#define PXP_CONCRETE_FID_PORT_SHIFT 4 1062#define PXP_CONCRETE_FID_PORT_SHIFT 4
1093#define PXP_CONCRETE_FID_PATH_MASK 0x1 1063#define PXP_CONCRETE_FID_PATH_MASK 0x1
1094#define PXP_CONCRETE_FID_PATH_SHIFT 6 1064#define PXP_CONCRETE_FID_PATH_SHIFT 6
1095#define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1065#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1096#define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1066#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1097#define PXP_CONCRETE_FID_VFID_MASK 0xFF 1067#define PXP_CONCRETE_FID_VFID_MASK 0xFF
1098#define PXP_CONCRETE_FID_VFID_SHIFT 8 1068#define PXP_CONCRETE_FID_VFID_SHIFT 8
1099}; 1069};
1100 1070
1071/* Concrete Function ID */
1101struct pxp_pretend_concrete_fid { 1072struct pxp_pretend_concrete_fid {
1102 __le16 fid; 1073 __le16 fid;
1103#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1074#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1104#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1075#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1105#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1076#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1106#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1077#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1107#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1078#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1108#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1079#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1109#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1080#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1110#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1081#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1111}; 1082};
1112 1083
1084/* Function ID */
1113union pxp_pretend_fid { 1085union pxp_pretend_fid {
1114 struct pxp_pretend_concrete_fid concrete_fid; 1086 struct pxp_pretend_concrete_fid concrete_fid;
1115 __le16 opaque_fid; 1087 __le16 opaque_fid;
1116}; 1088};
1117 1089
1118/* Pxp Pretend Command Register. */ 1090/* Pxp Pretend Command Register */
1119struct pxp_pretend_cmd { 1091struct pxp_pretend_cmd {
1120 union pxp_pretend_fid fid; 1092 union pxp_pretend_fid fid;
1121 __le16 control; 1093 __le16 control;
1122#define PXP_PRETEND_CMD_PATH_MASK 0x1 1094#define PXP_PRETEND_CMD_PATH_MASK 0x1
1123#define PXP_PRETEND_CMD_PATH_SHIFT 0 1095#define PXP_PRETEND_CMD_PATH_SHIFT 0
1124#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1096#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1125#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1097#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1126#define PXP_PRETEND_CMD_PORT_MASK 0x3 1098#define PXP_PRETEND_CMD_PORT_MASK 0x3
1127#define PXP_PRETEND_CMD_PORT_SHIFT 2 1099#define PXP_PRETEND_CMD_PORT_SHIFT 2
1128#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1100#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1129#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1101#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1130#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1102#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1131#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1103#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1132#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1104#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1133#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1105#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1134#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1106#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1135#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1107#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1136#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1108#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1137#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1109#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1138#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1110#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1139#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1111#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1140}; 1112};
1141 1113
1142/* PTT Record in PXP Admin Window. */ 1114/* PTT Record in PXP Admin Window */
1143struct pxp_ptt_entry { 1115struct pxp_ptt_entry {
1144 __le32 offset; 1116 __le32 offset;
1145#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1117#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1146#define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1118#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1147#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1119#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1148#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1120#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1149 struct pxp_pretend_cmd pretend; 1121 struct pxp_pretend_cmd pretend;
1150}; 1122};
1151 1123
1152/* VF Zone A Permission Register. */ 1124/* VF Zone A Permission Register */
1153struct pxp_vf_zone_a_permission { 1125struct pxp_vf_zone_a_permission {
1154 __le32 control; 1126 __le32 control;
1155#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1127#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1156#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1128#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1157#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1129#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1158#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1130#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1159#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1131#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1160#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1132#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1161#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1133#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1162#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1134#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1163}; 1135};
1164 1136
1165/* RSS hash type */ 1137/* Rdif context */
1166struct rdif_task_context { 1138struct rdif_task_context {
1167 __le32 initial_ref_tag; 1139 __le32 initial_ref_tag;
1168 __le16 app_tag_value; 1140 __le16 app_tag_value;
1169 __le16 app_tag_mask; 1141 __le16 app_tag_mask;
1170 u8 flags0; 1142 u8 flags0;
1171#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1143#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1172#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1144#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1173#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1145#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1174#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1146#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1175#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1147#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1176#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1148#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1177#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1149#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1178#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1150#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1179#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1151#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1180#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1152#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1181#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1153#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1182#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1154#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1183#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1155#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1184#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1156#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
1185 u8 partial_dif_data[7]; 1157 u8 partial_dif_data[7];
1186 __le16 partial_crc_value; 1158 __le16 partial_crc_value;
1187 __le16 partial_checksum_value; 1159 __le16 partial_checksum_value;
1188 __le32 offset_in_io; 1160 __le32 offset_in_io;
1189 __le16 flags1; 1161 __le16 flags1;
1190#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1162#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1191#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1163#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1192#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1164#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1193#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1165#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1194#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1166#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1195#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1167#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1196#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1168#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1197#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1169#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1198#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1170#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1199#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1171#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1200#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1172#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1201#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1173#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1202#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1174#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1203#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1175#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1204#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1176#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1205#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1177#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1206#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1178#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1207#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1179#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1208#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1180#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1209#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1181#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1210#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1182#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1211#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1183#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1212#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1184#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1213#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1185#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
1214#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1186#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1215#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1187#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
1216 __le16 state; 1188 __le16 state;
1217#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1189#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1218#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1190#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1219#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1191#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1220#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1192#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
1221#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1193#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1222#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1194#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
1223#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1195#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1224#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1196#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
1225#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1197#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1226#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1198#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
1227#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1199#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1228#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1200#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1229 __le32 reserved2; 1201 __le32 reserved2;
1230}; 1202};
1231 1203
1232/* RSS hash type */ 1204/* Status block structure */
1233enum rss_hash_type {
1234 RSS_HASH_TYPE_DEFAULT = 0,
1235 RSS_HASH_TYPE_IPV4 = 1,
1236 RSS_HASH_TYPE_TCP_IPV4 = 2,
1237 RSS_HASH_TYPE_IPV6 = 3,
1238 RSS_HASH_TYPE_TCP_IPV6 = 4,
1239 RSS_HASH_TYPE_UDP_IPV4 = 5,
1240 RSS_HASH_TYPE_UDP_IPV6 = 6,
1241 MAX_RSS_HASH_TYPE
1242};
1243
1244/* status block structure */
1245struct status_block { 1205struct status_block {
1246 __le16 pi_array[PIS_PER_SB]; 1206 __le16 pi_array[PIS_PER_SB];
1247 __le32 sb_num; 1207 __le32 sb_num;
@@ -1258,88 +1218,90 @@ struct status_block {
1258#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1218#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
1259}; 1219};
1260 1220
1221/* Tdif context */
1261struct tdif_task_context { 1222struct tdif_task_context {
1262 __le32 initial_ref_tag; 1223 __le32 initial_ref_tag;
1263 __le16 app_tag_value; 1224 __le16 app_tag_value;
1264 __le16 app_tag_mask; 1225 __le16 app_tag_mask;
1265 __le16 partial_crc_valueB; 1226 __le16 partial_crc_value_b;
1266 __le16 partial_checksum_valueB; 1227 __le16 partial_checksum_value_b;
1267 __le16 stateB; 1228 __le16 stateB;
1268#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1229#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1269#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1230#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1270#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1231#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1271#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1232#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
1272#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1233#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1273#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1234#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
1274#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1235#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1275#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1236#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
1276#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1237#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1277#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1238#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1278 u8 reserved1; 1239 u8 reserved1;
1279 u8 flags0; 1240 u8 flags0;
1280#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1241#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1281#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1242#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1282#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1243#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1283#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1244#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1284#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1245#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1285#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1246#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1286#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1247#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1287#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1248#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1288#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1249#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1289#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1250#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1290#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1251#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1291#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1252#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1292#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1253#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1293#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1254#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1294 __le32 flags1; 1255 __le32 flags1;
1295#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1256#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1296#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1257#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1297#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1258#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1298#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1259#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1299#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1260#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1300#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1261#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1301#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1262#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1302#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1263#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1303#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1264#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1304#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1265#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1305#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1266#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1306#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1267#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1307#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1268#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1308#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1269#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1309#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1270#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1310#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1271#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1311#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1272#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1312#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1273#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1313#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1274#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1314#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1275#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1315#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1276#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1316#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1277#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1317#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1278#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1318#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1279#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
1319#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1280#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1320#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1281#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
1321#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1282#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1322#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1283#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
1323#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1284#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1324#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1285#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
1325#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1286#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1326#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1287#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
1327#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1288#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1328#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1289#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
1329#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1290#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1330#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1291#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
1331#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1292#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1332#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1293#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
1333#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1294#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1334#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1295#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1335 __le32 offset_in_iob; 1296 __le32 offset_in_io_b;
1336 __le16 partial_crc_value_a; 1297 __le16 partial_crc_value_a;
1337 __le16 partial_checksum_valuea_; 1298 __le16 partial_checksum_value_a;
1338 __le32 offset_in_ioa; 1299 __le32 offset_in_io_a;
1339 u8 partial_dif_data_a[8]; 1300 u8 partial_dif_data_a[8];
1340 u8 partial_dif_data_b[8]; 1301 u8 partial_dif_data_b[8];
1341}; 1302};
1342 1303
1304/* Timers context */
1343struct timers_context { 1305struct timers_context {
1344 __le32 logical_client_0; 1306 __le32 logical_client_0;
1345#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1307#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
@@ -1385,6 +1347,7 @@ struct timers_context {
1385#define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1347#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
1386}; 1348};
1387 1349
1350/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
1388enum tunnel_next_protocol { 1351enum tunnel_next_protocol {
1389 e_unknown = 0, 1352 e_unknown = 0,
1390 e_l2 = 1, 1353 e_l2 = 1,
diff --git a/include/linux/qed/eth_common.h b/include/linux/qed/eth_common.h
index cb06e6e368e1..f554f4b58dfe 100644
--- a/include/linux/qed/eth_common.h
+++ b/include/linux/qed/eth_common.h
@@ -36,139 +36,140 @@
36/********************/ 36/********************/
37/* ETH FW CONSTANTS */ 37/* ETH FW CONSTANTS */
38/********************/ 38/********************/
39#define ETH_HSI_VER_MAJOR 3 39
40#define ETH_HSI_VER_MINOR 10 40#define ETH_HSI_VER_MAJOR 3
41#define ETH_HSI_VER_MINOR 10
41 42
42#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5 43#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
43 44
44#define ETH_CACHE_LINE_SIZE 64 45#define ETH_CACHE_LINE_SIZE 64
45#define ETH_RX_CQE_GAP 32 46#define ETH_RX_CQE_GAP 32
46#define ETH_MAX_RAMROD_PER_CON 8 47#define ETH_MAX_RAMROD_PER_CON 8
47#define ETH_TX_BD_PAGE_SIZE_BYTES 4096 48#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
48#define ETH_RX_BD_PAGE_SIZE_BYTES 4096 49#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
49#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 50#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
50#define ETH_RX_NUM_NEXT_PAGE_BDS 2 51#define ETH_RX_NUM_NEXT_PAGE_BDS 2
51 52
52#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253 53#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
53#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251 54#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
54 55
55#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 56#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
56#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 57#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
57#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255 58#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
58#define ETH_TX_MAX_LSO_HDR_NBD 4 59#define ETH_TX_MAX_LSO_HDR_NBD 4
59#define ETH_TX_MIN_BDS_PER_LSO_PKT 3 60#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
60#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 61#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
61#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 62#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
62#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 63#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
63#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8)) 64#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
64#define ETH_TX_MAX_LSO_HDR_BYTES 510 65#define ETH_TX_MAX_LSO_HDR_BYTES 510
65#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1) 66#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
66#define ETH_TX_LSO_WINDOW_MIN_LEN 9700 67#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
67#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 68#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
68#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320 69#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
69#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF 70#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
70 71
71#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 72#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
72#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \ 73#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
73 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2) 74 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
74#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \ 75#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
75 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4) 76 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
76 77
77/* Maximum number of buffers, used for RX packet placement */ 78/* Maximum number of buffers, used for RX packet placement */
78#define ETH_RX_MAX_BUFF_PER_PKT 5 79#define ETH_RX_MAX_BUFF_PER_PKT 5
79#define ETH_RX_BD_THRESHOLD 12 80#define ETH_RX_BD_THRESHOLD 12
80 81
81/* num of MAC/VLAN filters */ 82/* Num of MAC/VLAN filters */
82#define ETH_NUM_MAC_FILTERS 512 83#define ETH_NUM_MAC_FILTERS 512
83#define ETH_NUM_VLAN_FILTERS 512 84#define ETH_NUM_VLAN_FILTERS 512
84 85
85/* approx. multicast constants */ 86/* Approx. multicast constants */
86#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 87#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
87#define ETH_MULTICAST_MAC_BINS 256 88#define ETH_MULTICAST_MAC_BINS 256
88#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 89#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
89 90
90/* ethernet vport update constants */ 91/* Ethernet vport update constants */
91#define ETH_FILTER_RULES_COUNT 10 92#define ETH_FILTER_RULES_COUNT 10
92#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 93#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
93#define ETH_RSS_KEY_SIZE_REGS 10 94#define ETH_RSS_KEY_SIZE_REGS 10
94#define ETH_RSS_ENGINE_NUM_K2 207 95#define ETH_RSS_ENGINE_NUM_K2 207
95#define ETH_RSS_ENGINE_NUM_BB 127 96#define ETH_RSS_ENGINE_NUM_BB 127
96 97
97/* TPA constants */ 98/* TPA constants */
98#define ETH_TPA_MAX_AGGS_NUM 64 99#define ETH_TPA_MAX_AGGS_NUM 64
99#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT 100#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
100#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 101#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
101#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 102#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
102 103
103/* Control frame check constants */ 104/* Control frame check constants */
104#define ETH_CTL_FRAME_ETH_TYPE_NUM 4 105#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
105 106
106struct eth_tx_1st_bd_flags { 107struct eth_tx_1st_bd_flags {
107 u8 bitfields; 108 u8 bitfields;
108#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 109#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
109#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 110#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
110#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 111#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
111#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 112#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
112#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 113#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
113#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 114#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
114#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 115#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
115#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 116#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
116#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 117#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
117#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 118#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
118#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 119#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
119#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 120#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
120#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 121#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
121#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 122#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
122#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 123#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
123#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 124#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
124}; 125};
125 126
126/* The parsing information data fo rthe first tx bd of a given packet. */ 127/* The parsing information data fo rthe first tx bd of a given packet */
127struct eth_tx_data_1st_bd { 128struct eth_tx_data_1st_bd {
128 __le16 vlan; 129 __le16 vlan;
129 u8 nbds; 130 u8 nbds;
130 struct eth_tx_1st_bd_flags bd_flags; 131 struct eth_tx_1st_bd_flags bd_flags;
131 __le16 bitfields; 132 __le16 bitfields;
132#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1 133#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
133#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0 134#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
134#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 135#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
135#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 136#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
136#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF 137#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
137#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2 138#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
138}; 139};
139 140
140/* The parsing information data for the second tx bd of a given packet. */ 141/* The parsing information data for the second tx bd of a given packet */
141struct eth_tx_data_2nd_bd { 142struct eth_tx_data_2nd_bd {
142 __le16 tunn_ip_size; 143 __le16 tunn_ip_size;
143 __le16 bitfields1; 144 __le16 bitfields1;
144#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 145#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
145#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 146#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
146#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 147#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
147#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 148#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
148#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3 149#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
149#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6 150#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
150#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 151#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
151#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 152#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
152#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 153#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
153#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 154#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
154#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 155#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
155#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 156#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
156#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 157#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
157#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 158#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
158#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 159#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
159#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 160#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
160#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 161#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
161#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 162#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
162#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 163#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
163#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 164#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
164 __le16 bitfields2; 165 __le16 bitfields2;
165#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 166#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
166#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 167#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
167#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 168#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
168#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 169#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
169}; 170};
170 171
171/* Firmware data for L2-EDPM packet. */ 172/* Firmware data for L2-EDPM packet */
172struct eth_edpm_fw_data { 173struct eth_edpm_fw_data {
173 struct eth_tx_data_1st_bd data_1st_bd; 174 struct eth_tx_data_1st_bd data_1st_bd;
174 struct eth_tx_data_2nd_bd data_2nd_bd; 175 struct eth_tx_data_2nd_bd data_2nd_bd;
@@ -179,7 +180,7 @@ struct eth_fast_path_cqe_fw_debug {
179 __le16 reserved2; 180 __le16 reserved2;
180}; 181};
181 182
182/* tunneling parsing flags */ 183/* Tunneling parsing flags */
183struct eth_tunnel_parsing_flags { 184struct eth_tunnel_parsing_flags {
184 u8 flags; 185 u8 flags;
185#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 186#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
@@ -199,24 +200,24 @@ struct eth_tunnel_parsing_flags {
199/* PMD flow control bits */ 200/* PMD flow control bits */
200struct eth_pmd_flow_flags { 201struct eth_pmd_flow_flags {
201 u8 flags; 202 u8 flags;
202#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 203#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
203#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0 204#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
204#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 205#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
205#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1 206#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
206#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F 207#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
207#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2 208#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
208}; 209};
209 210
210/* Regular ETH Rx FP CQE. */ 211/* Regular ETH Rx FP CQE */
211struct eth_fast_path_rx_reg_cqe { 212struct eth_fast_path_rx_reg_cqe {
212 u8 type; 213 u8 type;
213 u8 bitfields; 214 u8 bitfields;
214#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 215#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
215#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 216#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
216#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 217#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
217#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 218#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
218#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 219#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
219#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 220#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
220 __le16 pkt_len; 221 __le16 pkt_len;
221 struct parsing_and_err_flags pars_flags; 222 struct parsing_and_err_flags pars_flags;
222 __le16 vlan_tag; 223 __le16 vlan_tag;
@@ -231,7 +232,7 @@ struct eth_fast_path_rx_reg_cqe {
231 struct eth_pmd_flow_flags pmd_flags; 232 struct eth_pmd_flow_flags pmd_flags;
232}; 233};
233 234
234/* TPA-continue ETH Rx FP CQE. */ 235/* TPA-continue ETH Rx FP CQE */
235struct eth_fast_path_rx_tpa_cont_cqe { 236struct eth_fast_path_rx_tpa_cont_cqe {
236 u8 type; 237 u8 type;
237 u8 tpa_agg_index; 238 u8 tpa_agg_index;
@@ -243,7 +244,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
243 struct eth_pmd_flow_flags pmd_flags; 244 struct eth_pmd_flow_flags pmd_flags;
244}; 245};
245 246
246/* TPA-end ETH Rx FP CQE. */ 247/* TPA-end ETH Rx FP CQE */
247struct eth_fast_path_rx_tpa_end_cqe { 248struct eth_fast_path_rx_tpa_end_cqe {
248 u8 type; 249 u8 type;
249 u8 tpa_agg_index; 250 u8 tpa_agg_index;
@@ -259,16 +260,16 @@ struct eth_fast_path_rx_tpa_end_cqe {
259 struct eth_pmd_flow_flags pmd_flags; 260 struct eth_pmd_flow_flags pmd_flags;
260}; 261};
261 262
262/* TPA-start ETH Rx FP CQE. */ 263/* TPA-start ETH Rx FP CQE */
263struct eth_fast_path_rx_tpa_start_cqe { 264struct eth_fast_path_rx_tpa_start_cqe {
264 u8 type; 265 u8 type;
265 u8 bitfields; 266 u8 bitfields;
266#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 267#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
267#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 268#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
268#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 269#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
269#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 270#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
270#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 271#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
271#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 272#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
272 __le16 seg_len; 273 __le16 seg_len;
273 struct parsing_and_err_flags pars_flags; 274 struct parsing_and_err_flags pars_flags;
274 __le16 vlan_tag; 275 __le16 vlan_tag;
@@ -295,24 +296,24 @@ struct eth_rx_bd {
295 struct regpair addr; 296 struct regpair addr;
296}; 297};
297 298
298/* regular ETH Rx SP CQE */ 299/* Regular ETH Rx SP CQE */
299struct eth_slow_path_rx_cqe { 300struct eth_slow_path_rx_cqe {
300 u8 type; 301 u8 type;
301 u8 ramrod_cmd_id; 302 u8 ramrod_cmd_id;
302 u8 error_flag; 303 u8 error_flag;
303 u8 reserved[25]; 304 u8 reserved[25];
304 __le16 echo; 305 __le16 echo;
305 u8 reserved1; 306 u8 reserved1;
306 struct eth_pmd_flow_flags pmd_flags; 307 struct eth_pmd_flow_flags pmd_flags;
307}; 308};
308 309
309/* union for all ETH Rx CQE types */ 310/* Union for all ETH Rx CQE types */
310union eth_rx_cqe { 311union eth_rx_cqe {
311 struct eth_fast_path_rx_reg_cqe fast_path_regular; 312 struct eth_fast_path_rx_reg_cqe fast_path_regular;
312 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 313 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
313 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 314 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
314 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 315 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
315 struct eth_slow_path_rx_cqe slow_path; 316 struct eth_slow_path_rx_cqe slow_path;
316}; 317};
317 318
318/* ETH Rx CQE type */ 319/* ETH Rx CQE type */
@@ -339,7 +340,7 @@ enum eth_rx_tunn_type {
339 MAX_ETH_RX_TUNN_TYPE 340 MAX_ETH_RX_TUNN_TYPE
340}; 341};
341 342
342/* Aggregation end reason. */ 343/* Aggregation end reason. */
343enum eth_tpa_end_reason { 344enum eth_tpa_end_reason {
344 ETH_AGG_END_UNUSED, 345 ETH_AGG_END_UNUSED,
345 ETH_AGG_END_SP_UPDATE, 346 ETH_AGG_END_SP_UPDATE,
@@ -354,59 +355,59 @@ enum eth_tpa_end_reason {
354 355
355/* The first tx bd of a given packet */ 356/* The first tx bd of a given packet */
356struct eth_tx_1st_bd { 357struct eth_tx_1st_bd {
357 struct regpair addr; 358 struct regpair addr;
358 __le16 nbytes; 359 __le16 nbytes;
359 struct eth_tx_data_1st_bd data; 360 struct eth_tx_data_1st_bd data;
360}; 361};
361 362
362/* The second tx bd of a given packet */ 363/* The second tx bd of a given packet */
363struct eth_tx_2nd_bd { 364struct eth_tx_2nd_bd {
364 struct regpair addr; 365 struct regpair addr;
365 __le16 nbytes; 366 __le16 nbytes;
366 struct eth_tx_data_2nd_bd data; 367 struct eth_tx_data_2nd_bd data;
367}; 368};
368 369
369/* The parsing information data for the third tx bd of a given packet. */ 370/* The parsing information data for the third tx bd of a given packet */
370struct eth_tx_data_3rd_bd { 371struct eth_tx_data_3rd_bd {
371 __le16 lso_mss; 372 __le16 lso_mss;
372 __le16 bitfields; 373 __le16 bitfields;
373#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 374#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
374#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 375#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
375#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 376#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
376#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 377#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
377#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 378#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
378#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 379#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
379#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 380#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
380#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 381#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
381 u8 tunn_l4_hdr_start_offset_w; 382 u8 tunn_l4_hdr_start_offset_w;
382 u8 tunn_hdr_size_w; 383 u8 tunn_hdr_size_w;
383}; 384};
384 385
385/* The third tx bd of a given packet */ 386/* The third tx bd of a given packet */
386struct eth_tx_3rd_bd { 387struct eth_tx_3rd_bd {
387 struct regpair addr; 388 struct regpair addr;
388 __le16 nbytes; 389 __le16 nbytes;
389 struct eth_tx_data_3rd_bd data; 390 struct eth_tx_data_3rd_bd data;
390}; 391};
391 392
392/* Complementary information for the regular tx bd of a given packet. */ 393/* Complementary information for the regular tx bd of a given packet */
393struct eth_tx_data_bd { 394struct eth_tx_data_bd {
394 __le16 reserved0; 395 __le16 reserved0;
395 __le16 bitfields; 396 __le16 bitfields;
396#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 397#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
397#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 398#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
398#define ETH_TX_DATA_BD_START_BD_MASK 0x1 399#define ETH_TX_DATA_BD_START_BD_MASK 0x1
399#define ETH_TX_DATA_BD_START_BD_SHIFT 8 400#define ETH_TX_DATA_BD_START_BD_SHIFT 8
400#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 401#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
401#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 402#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
402 __le16 reserved3; 403 __le16 reserved3;
403}; 404};
404 405
405/* The common non-special TX BD ring element */ 406/* The common non-special TX BD ring element */
406struct eth_tx_bd { 407struct eth_tx_bd {
407 struct regpair addr; 408 struct regpair addr;
408 __le16 nbytes; 409 __le16 nbytes;
409 struct eth_tx_data_bd data; 410 struct eth_tx_data_bd data;
410}; 411};
411 412
412union eth_tx_bd_types { 413union eth_tx_bd_types {
@@ -434,18 +435,30 @@ struct xstorm_eth_queue_zone {
434/* ETH doorbell data */ 435/* ETH doorbell data */
435struct eth_db_data { 436struct eth_db_data {
436 u8 params; 437 u8 params;
437#define ETH_DB_DATA_DEST_MASK 0x3 438#define ETH_DB_DATA_DEST_MASK 0x3
438#define ETH_DB_DATA_DEST_SHIFT 0 439#define ETH_DB_DATA_DEST_SHIFT 0
439#define ETH_DB_DATA_AGG_CMD_MASK 0x3 440#define ETH_DB_DATA_AGG_CMD_MASK 0x3
440#define ETH_DB_DATA_AGG_CMD_SHIFT 2 441#define ETH_DB_DATA_AGG_CMD_SHIFT 2
441#define ETH_DB_DATA_BYPASS_EN_MASK 0x1 442#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
442#define ETH_DB_DATA_BYPASS_EN_SHIFT 4 443#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
443#define ETH_DB_DATA_RESERVED_MASK 0x1 444#define ETH_DB_DATA_RESERVED_MASK 0x1
444#define ETH_DB_DATA_RESERVED_SHIFT 5 445#define ETH_DB_DATA_RESERVED_SHIFT 5
445#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 446#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
446#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 447#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
447 u8 agg_flags; 448 u8 agg_flags;
448 __le16 bd_prod; 449 __le16 bd_prod;
449}; 450};
450 451
452/* RSS hash type */
453enum rss_hash_type {
454 RSS_HASH_TYPE_DEFAULT = 0,
455 RSS_HASH_TYPE_IPV4 = 1,
456 RSS_HASH_TYPE_TCP_IPV4 = 2,
457 RSS_HASH_TYPE_IPV6 = 3,
458 RSS_HASH_TYPE_TCP_IPV6 = 4,
459 RSS_HASH_TYPE_UDP_IPV4 = 5,
460 RSS_HASH_TYPE_UDP_IPV6 = 6,
461 MAX_RSS_HASH_TYPE
462};
463
451#endif /* __ETH_COMMON__ */ 464#endif /* __ETH_COMMON__ */
diff --git a/include/linux/qed/fcoe_common.h b/include/linux/qed/fcoe_common.h
index 12fc9e788eea..e720a7b37b0b 100644
--- a/include/linux/qed/fcoe_common.h
+++ b/include/linux/qed/fcoe_common.h
@@ -8,217 +8,78 @@
8 8
9#ifndef __FCOE_COMMON__ 9#ifndef __FCOE_COMMON__
10#define __FCOE_COMMON__ 10#define __FCOE_COMMON__
11
11/*********************/ 12/*********************/
12/* FCOE FW CONSTANTS */ 13/* FCOE FW CONSTANTS */
13/*********************/ 14/*********************/
14 15
15#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 16#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
16 17
17struct fcoe_abts_pkt { 18/* The fcoe storm task context protection-information of Ystorm */
18 __le32 abts_rsp_fc_payload_lo; 19struct protection_info_ctx {
19 __le16 abts_rsp_rx_id; 20 __le16 flags;
20 u8 abts_rsp_rctl; 21#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
21 u8 reserved2; 22#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
22}; 23#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
23 24#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
24/* FCoE additional WQE (Sq/XferQ) information */ 25#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
25union fcoe_additional_info_union { 26#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
26 __le32 previous_tid; 27#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
27 __le32 parent_tid; 28#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
28 __le32 burst_length; 29#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
29 __le32 seq_rec_updated_offset; 30#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
30}; 31#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
31 32#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
32struct fcoe_exp_ro { 33 u8 dix_block_size;
33 __le32 data_offset; 34 u8 dst_size;
34 __le32 reserved;
35};
36
37union fcoe_cleanup_addr_exp_ro_union {
38 struct regpair abts_rsp_fc_payload_hi;
39 struct fcoe_exp_ro exp_ro;
40};
41
42/* FCoE Ramrod Command IDs */
43enum fcoe_completion_status {
44 FCOE_COMPLETION_STATUS_SUCCESS,
45 FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
46 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
47 MAX_FCOE_COMPLETION_STATUS
48};
49
50struct fc_addr_nw {
51 u8 addr_lo;
52 u8 addr_mid;
53 u8 addr_hi;
54};
55
56/* FCoE connection offload */
57struct fcoe_conn_offload_ramrod_data {
58 struct regpair sq_pbl_addr;
59 struct regpair sq_curr_page_addr;
60 struct regpair sq_next_page_addr;
61 struct regpair xferq_pbl_addr;
62 struct regpair xferq_curr_page_addr;
63 struct regpair xferq_next_page_addr;
64 struct regpair respq_pbl_addr;
65 struct regpair respq_curr_page_addr;
66 struct regpair respq_next_page_addr;
67 __le16 dst_mac_addr_lo;
68 __le16 dst_mac_addr_mid;
69 __le16 dst_mac_addr_hi;
70 __le16 src_mac_addr_lo;
71 __le16 src_mac_addr_mid;
72 __le16 src_mac_addr_hi;
73 __le16 tx_max_fc_pay_len;
74 __le16 e_d_tov_timer_val;
75 __le16 rx_max_fc_pay_len;
76 __le16 vlan_tag;
77#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
78#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
79#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
80#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
81#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
82#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
83 __le16 physical_q0;
84 __le16 rec_rr_tov_timer_val;
85 struct fc_addr_nw s_id;
86 u8 max_conc_seqs_c3;
87 struct fc_addr_nw d_id;
88 u8 flags;
89#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
90#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
91#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
92#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
93#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
94#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
95#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
96#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
97#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
98#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
99#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
100#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
101 __le16 conn_id;
102 u8 def_q_idx;
103 u8 reserved[5];
104};
105
106/* FCoE terminate connection request */
107struct fcoe_conn_terminate_ramrod_data {
108 struct regpair terminate_params_addr;
109};
110
111struct fcoe_slow_sgl_ctx {
112 struct regpair base_sgl_addr;
113 __le16 curr_sge_off;
114 __le16 remainder_num_sges;
115 __le16 curr_sgl_index;
116 __le16 reserved;
117};
118
119union fcoe_dix_desc_ctx {
120 struct fcoe_slow_sgl_ctx dix_sgl;
121 struct scsi_sge cached_dix_sge;
122}; 35};
123 36
124struct fcoe_fast_sgl_ctx { 37/* The fcoe storm task context protection-information of Ystorm */
125 struct regpair sgl_start_addr; 38union protection_info_union_ctx {
126 __le32 sgl_byte_offset; 39 struct protection_info_ctx info;
127 __le16 task_reuse_cnt; 40 __le32 value;
128 __le16 init_offset_in_first_sge;
129}; 41};
130 42
43/* FCP CMD payload */
131struct fcoe_fcp_cmd_payload { 44struct fcoe_fcp_cmd_payload {
132 __le32 opaque[8]; 45 __le32 opaque[8];
133}; 46};
134 47
48/* FCP RSP payload */
135struct fcoe_fcp_rsp_payload { 49struct fcoe_fcp_rsp_payload {
136 __le32 opaque[6]; 50 __le32 opaque[6];
137}; 51};
138 52
139struct fcoe_fcp_xfer_payload { 53/* FCP RSP payload */
140 __le32 opaque[3];
141};
142
143/* FCoE firmware function init */
144struct fcoe_init_func_ramrod_data {
145 struct scsi_init_func_params func_params;
146 struct scsi_init_func_queues q_params;
147 __le16 mtu;
148 __le16 sq_num_pages_in_pbl;
149 __le32 reserved;
150};
151
152/* FCoE: Mode of the connection: Target or Initiator or both */
153enum fcoe_mode_type {
154 FCOE_INITIATOR_MODE = 0x0,
155 FCOE_TARGET_MODE = 0x1,
156 FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
157 MAX_FCOE_MODE_TYPE
158};
159
160struct fcoe_rx_stat {
161 struct regpair fcoe_rx_byte_cnt;
162 struct regpair fcoe_rx_data_pkt_cnt;
163 struct regpair fcoe_rx_xfer_pkt_cnt;
164 struct regpair fcoe_rx_other_pkt_cnt;
165 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
166 __le32 fcoe_silent_drop_pkt_rq_full_cnt;
167 __le32 fcoe_silent_drop_pkt_crc_error_cnt;
168 __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
169 __le32 fcoe_silent_drop_total_pkt_cnt;
170 __le32 rsrv;
171};
172
173struct fcoe_stat_ramrod_data {
174 struct regpair stat_params_addr;
175};
176
177struct protection_info_ctx {
178 __le16 flags;
179#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
180#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
181#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
182#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
183#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
184#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
185#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
186#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
187#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
188#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
189#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
190#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
191 u8 dix_block_size;
192 u8 dst_size;
193};
194
195union protection_info_union_ctx {
196 struct protection_info_ctx info;
197 __le32 value;
198};
199
200struct fcp_rsp_payload_padded { 54struct fcp_rsp_payload_padded {
201 struct fcoe_fcp_rsp_payload rsp_payload; 55 struct fcoe_fcp_rsp_payload rsp_payload;
202 __le32 reserved[2]; 56 __le32 reserved[2];
203}; 57};
204 58
59/* FCP RSP payload */
60struct fcoe_fcp_xfer_payload {
61 __le32 opaque[3];
62};
63
64/* FCP RSP payload */
205struct fcp_xfer_payload_padded { 65struct fcp_xfer_payload_padded {
206 struct fcoe_fcp_xfer_payload xfer_payload; 66 struct fcoe_fcp_xfer_payload xfer_payload;
207 __le32 reserved[5]; 67 __le32 reserved[5];
208}; 68};
209 69
70/* Task params */
210struct fcoe_tx_data_params { 71struct fcoe_tx_data_params {
211 __le32 data_offset; 72 __le32 data_offset;
212 __le32 offset_in_io; 73 __le32 offset_in_io;
213 u8 flags; 74 u8 flags;
214#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 75#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
215#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 76#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
216#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 77#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
217#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 78#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
218#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 79#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
219#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 80#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
220#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 81#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
221#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 82#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
222 u8 dif_residual; 83 u8 dif_residual;
223 __le16 seq_cnt; 84 __le16 seq_cnt;
224 __le16 single_sge_saved_offset; 85 __le16 single_sge_saved_offset;
@@ -227,6 +88,7 @@ struct fcoe_tx_data_params {
227 __le16 reserved3; 88 __le16 reserved3;
228}; 89};
229 90
91/* Middle path parameters: FC header fields provided by the driver */
230struct fcoe_tx_mid_path_params { 92struct fcoe_tx_mid_path_params {
231 __le32 parameter; 93 __le32 parameter;
232 u8 r_ctl; 94 u8 r_ctl;
@@ -237,11 +99,13 @@ struct fcoe_tx_mid_path_params {
237 __le16 ox_id; 99 __le16 ox_id;
238}; 100};
239 101
102/* Task params */
240struct fcoe_tx_params { 103struct fcoe_tx_params {
241 struct fcoe_tx_data_params data; 104 struct fcoe_tx_data_params data;
242 struct fcoe_tx_mid_path_params mid_path; 105 struct fcoe_tx_mid_path_params mid_path;
243}; 106};
244 107
108/* Union of FCP CMD payload \ TX params \ ABTS \ Cleanup */
245union fcoe_tx_info_union_ctx { 109union fcoe_tx_info_union_ctx {
246 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 110 struct fcoe_fcp_cmd_payload fcp_cmd_payload;
247 struct fcp_rsp_payload_padded fcp_rsp_payload; 111 struct fcp_rsp_payload_padded fcp_rsp_payload;
@@ -249,13 +113,29 @@ union fcoe_tx_info_union_ctx {
249 struct fcoe_tx_params tx_params; 113 struct fcoe_tx_params tx_params;
250}; 114};
251 115
116/* Data sgl */
117struct fcoe_slow_sgl_ctx {
118 struct regpair base_sgl_addr;
119 __le16 curr_sge_off;
120 __le16 remainder_num_sges;
121 __le16 curr_sgl_index;
122 __le16 reserved;
123};
124
125/* Union of DIX SGL \ cached DIX sges */
126union fcoe_dix_desc_ctx {
127 struct fcoe_slow_sgl_ctx dix_sgl;
128 struct scsi_sge cached_dix_sge;
129};
130
131/* The fcoe storm task context of Ystorm */
252struct ystorm_fcoe_task_st_ctx { 132struct ystorm_fcoe_task_st_ctx {
253 u8 task_type; 133 u8 task_type;
254 u8 sgl_mode; 134 u8 sgl_mode;
255#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 135#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
256#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 136#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
257#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 137#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
258#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 138#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
259 u8 cached_dix_sge; 139 u8 cached_dix_sge;
260 u8 expect_first_xfer; 140 u8 expect_first_xfer;
261 __le32 num_pbf_zero_write; 141 __le32 num_pbf_zero_write;
@@ -277,44 +157,44 @@ struct ystorm_fcoe_task_ag_ctx {
277 u8 byte1; 157 u8 byte1;
278 __le16 word0; 158 __le16 word0;
279 u8 flags0; 159 u8 flags0;
280#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF 160#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
281#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 161#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
282#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 162#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
283#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 163#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
284#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 164#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
285#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 165#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
286#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 166#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
287#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 167#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
288#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 168#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
289#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 169#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
290 u8 flags1; 170 u8 flags1;
291#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 171#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
292#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 172#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
293#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 173#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
294#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 174#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
295#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 175#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
296#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 176#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
297#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 177#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
298#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 178#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
299#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 179#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
300#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 180#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
301 u8 flags2; 181 u8 flags2;
302#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 182#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
303#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 183#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
304#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 184#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
305#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 185#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
306#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 186#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
307#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 187#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
308#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 188#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
309#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 189#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
310#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 190#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
311#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 191#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
312#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 192#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
313#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 193#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
314#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 194#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
315#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 195#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
316#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 196#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
317#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 197#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
318 u8 byte2; 198 u8 byte2;
319 __le32 reg0; 199 __le32 reg0;
320 u8 byte3; 200 u8 byte3;
@@ -333,68 +213,68 @@ struct tstorm_fcoe_task_ag_ctx {
333 u8 byte1; 213 u8 byte1;
334 __le16 icid; 214 __le16 icid;
335 u8 flags0; 215 u8 flags0;
336#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 216#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
337#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 217#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
338#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 218#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
339#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 219#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
340#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 220#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
341#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 221#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
342#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 222#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
343#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 223#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
344#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 224#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
345#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 225#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
346 u8 flags1; 226 u8 flags1;
347#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 227#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
348#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 228#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
349#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 229#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
350#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 230#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
351#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 231#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
352#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 232#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
353#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 233#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
354#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 234#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
355#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 235#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
356#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 236#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
357 u8 flags2; 237 u8 flags2;
358#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 238#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
359#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 239#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
360#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 240#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
361#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 241#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
362#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 242#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
363#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 243#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
364#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 244#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
365#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 245#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
366 u8 flags3; 246 u8 flags3;
367#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 247#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
368#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 248#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
369#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 249#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
370#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 250#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
371#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 251#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
372#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 252#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
373#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 253#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
374#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 254#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
375#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 255#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
376#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 256#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
377#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 257#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
378#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 258#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
379#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 259#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
380#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 260#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
381 u8 flags4; 261 u8 flags4;
382#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 262#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
383#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 263#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
384#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 264#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
385#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 265#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
386#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 266#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
387#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 267#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
388#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 268#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
389#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 269#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
390#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 270#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
391#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 271#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
392#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 272#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
393#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 273#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
394#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 274#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
395#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 275#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
396#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 276#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
397#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 277#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
398 u8 cleanup_state; 278 u8 cleanup_state;
399 __le16 last_sent_tid; 279 __le16 last_sent_tid;
400 __le32 rec_rr_tov_exp_timeout; 280 __le32 rec_rr_tov_exp_timeout;
@@ -407,25 +287,46 @@ struct tstorm_fcoe_task_ag_ctx {
407 __le32 data_offset_next; 287 __le32 data_offset_next;
408}; 288};
409 289
290/* Cached data sges */
291struct fcoe_exp_ro {
292 __le32 data_offset;
293 __le32 reserved;
294};
295
296/* Union of Cleanup address \ expected relative offsets */
297union fcoe_cleanup_addr_exp_ro_union {
298 struct regpair abts_rsp_fc_payload_hi;
299 struct fcoe_exp_ro exp_ro;
300};
301
302/* Fields coppied from ABTSrsp pckt */
303struct fcoe_abts_pkt {
304 __le32 abts_rsp_fc_payload_lo;
305 __le16 abts_rsp_rx_id;
306 u8 abts_rsp_rctl;
307 u8 reserved2;
308};
309
310/* FW read- write (modifyable) part The fcoe task storm context of Tstorm */
410struct fcoe_tstorm_fcoe_task_st_ctx_read_write { 311struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
411 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union; 312 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
412 __le16 flags; 313 __le16 flags;
413#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 314#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
414#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 315#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
415#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 316#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
416#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 317#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
417#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 318#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
418#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 319#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
419#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 320#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
420#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 321#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
421#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 322#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
422#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 323#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
423#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 324#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
424#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 325#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
425#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 326#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
426#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 327#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
427#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 328#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
428#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 329#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
429 __le16 seq_cnt; 330 __le16 seq_cnt;
430 u8 seq_id; 331 u8 seq_id;
431 u8 ooo_rx_seq_id; 332 u8 ooo_rx_seq_id;
@@ -436,6 +337,7 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
436 __le16 reserved1; 337 __le16 reserved1;
437}; 338};
438 339
340/* FW read only part The fcoe task storm context of Tstorm */
439struct fcoe_tstorm_fcoe_task_st_ctx_read_only { 341struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
440 u8 task_type; 342 u8 task_type;
441 u8 dev_type; 343 u8 dev_type;
@@ -446,6 +348,7 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
446 __le32 rsrv; 348 __le32 rsrv;
447}; 349};
448 350
351/** The fcoe task storm context of Tstorm */
449struct tstorm_fcoe_task_st_ctx { 352struct tstorm_fcoe_task_st_ctx {
450 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write; 353 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
451 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only; 354 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
@@ -456,44 +359,44 @@ struct mstorm_fcoe_task_ag_ctx {
456 u8 byte1; 359 u8 byte1;
457 __le16 icid; 360 __le16 icid;
458 u8 flags0; 361 u8 flags0;
459#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 362#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
460#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 363#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
461#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 364#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
462#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 365#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
463#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 366#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
464#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 367#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
465#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 368#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
466#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 369#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
467#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 370#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
468#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 371#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
469 u8 flags1; 372 u8 flags1;
470#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 373#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
471#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 374#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
472#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 375#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
473#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 376#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
474#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 377#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
475#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 378#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
476#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 379#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
477#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 380#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
478#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 381#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
479#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 382#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
480 u8 flags2; 383 u8 flags2;
481#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 384#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
482#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 385#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
483#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 386#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
484#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 387#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
485#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 388#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
486#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 389#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
487#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 390#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
488#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 391#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
489#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 392#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
490#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 393#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
491#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 394#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
492#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 395#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
493#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 396#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
494#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 397#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
495#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 398#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
496#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 399#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
497 u8 cleanup_state; 400 u8 cleanup_state;
498 __le32 received_bytes; 401 __le32 received_bytes;
499 u8 byte3; 402 u8 byte3;
@@ -507,6 +410,7 @@ struct mstorm_fcoe_task_ag_ctx {
507 __le32 reg2; 410 __le32 reg2;
508}; 411};
509 412
413/* The fcoe task storm context of Mstorm */
510struct mstorm_fcoe_task_st_ctx { 414struct mstorm_fcoe_task_st_ctx {
511 struct regpair rsp_buf_addr; 415 struct regpair rsp_buf_addr;
512 __le32 rsrv[2]; 416 __le32 rsrv[2];
@@ -515,26 +419,26 @@ struct mstorm_fcoe_task_st_ctx {
515 __le32 data_buffer_offset; 419 __le32 data_buffer_offset;
516 __le16 parent_id; 420 __le16 parent_id;
517 __le16 flags; 421 __le16 flags;
518#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF 422#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
519#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 423#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
520#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 424#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
521#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 425#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
522#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 426#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
523#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 427#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
524#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 428#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
525#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 429#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
526#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 430#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
527#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 431#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
528#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 432#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
529#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 433#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
530#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 434#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
531#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 435#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
532#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 436#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
533#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 437#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
534#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 438#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
535#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 439#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
536#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 440#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
537#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 441#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
538 struct scsi_cached_sges data_desc; 442 struct scsi_cached_sges data_desc;
539}; 443};
540 444
@@ -543,51 +447,51 @@ struct ustorm_fcoe_task_ag_ctx {
543 u8 byte1; 447 u8 byte1;
544 __le16 icid; 448 __le16 icid;
545 u8 flags0; 449 u8 flags0;
546#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 450#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
547#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 451#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
548#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 452#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
549#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 453#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
550#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 454#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
551#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 455#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
552#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 456#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
553#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 457#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
554 u8 flags1; 458 u8 flags1;
555#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 459#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
556#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 460#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
557#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 461#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
558#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 462#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
559#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 463#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
560#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 464#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
561#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 465#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
562#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 466#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
563 u8 flags2; 467 u8 flags2;
564#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 468#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
565#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 469#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
566#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 470#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
567#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 471#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
568#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 472#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
569#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 473#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
570#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 474#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
571#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 475#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
572#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 476#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
573#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 477#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
574#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 478#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
575#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 479#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
576#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 480#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
577#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 481#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
578#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 482#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
579#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 483#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
580 u8 flags3; 484 u8 flags3;
581#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 485#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
582#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 486#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
583#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 487#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
584#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 488#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
585#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 489#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
586#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 490#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
587#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 491#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
588#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 492#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
589#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 493#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
590#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 494#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
591 __le32 dif_err_intervals; 495 __le32 dif_err_intervals;
592 __le32 dif_error_1st_interval; 496 __le32 dif_error_1st_interval;
593 __le32 global_cq_num; 497 __le32 global_cq_num;
@@ -596,6 +500,7 @@ struct ustorm_fcoe_task_ag_ctx {
596 __le32 reg5; 500 __le32 reg5;
597}; 501};
598 502
503/* FCoE task context */
599struct fcoe_task_context { 504struct fcoe_task_context {
600 struct ystorm_fcoe_task_st_ctx ystorm_st_context; 505 struct ystorm_fcoe_task_st_ctx ystorm_st_context;
601 struct regpair ystorm_st_padding[2]; 506 struct regpair ystorm_st_padding[2];
@@ -611,6 +516,129 @@ struct fcoe_task_context {
611 struct rdif_task_context rdif_context; 516 struct rdif_task_context rdif_context;
612}; 517};
613 518
519/* FCoE additional WQE (Sq/XferQ) information */
520union fcoe_additional_info_union {
521 __le32 previous_tid;
522 __le32 parent_tid;
523 __le32 burst_length;
524 __le32 seq_rec_updated_offset;
525};
526
527/* FCoE Ramrod Command IDs */
528enum fcoe_completion_status {
529 FCOE_COMPLETION_STATUS_SUCCESS,
530 FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
531 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
532 MAX_FCOE_COMPLETION_STATUS
533};
534
535/* FC address (SID/DID) network presentation */
536struct fc_addr_nw {
537 u8 addr_lo;
538 u8 addr_mid;
539 u8 addr_hi;
540};
541
542/* FCoE connection offload */
543struct fcoe_conn_offload_ramrod_data {
544 struct regpair sq_pbl_addr;
545 struct regpair sq_curr_page_addr;
546 struct regpair sq_next_page_addr;
547 struct regpair xferq_pbl_addr;
548 struct regpair xferq_curr_page_addr;
549 struct regpair xferq_next_page_addr;
550 struct regpair respq_pbl_addr;
551 struct regpair respq_curr_page_addr;
552 struct regpair respq_next_page_addr;
553 __le16 dst_mac_addr_lo;
554 __le16 dst_mac_addr_mid;
555 __le16 dst_mac_addr_hi;
556 __le16 src_mac_addr_lo;
557 __le16 src_mac_addr_mid;
558 __le16 src_mac_addr_hi;
559 __le16 tx_max_fc_pay_len;
560 __le16 e_d_tov_timer_val;
561 __le16 rx_max_fc_pay_len;
562 __le16 vlan_tag;
563#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
564#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
565#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
566#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
567#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
568#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
569 __le16 physical_q0;
570 __le16 rec_rr_tov_timer_val;
571 struct fc_addr_nw s_id;
572 u8 max_conc_seqs_c3;
573 struct fc_addr_nw d_id;
574 u8 flags;
575#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
576#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
577#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
578#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
579#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
580#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
581#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
582#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
583#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
584#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
585#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
586#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
587 __le16 conn_id;
588 u8 def_q_idx;
589 u8 reserved[5];
590};
591
592/* FCoE terminate connection request */
593struct fcoe_conn_terminate_ramrod_data {
594 struct regpair terminate_params_addr;
595};
596
597/* Data sgl */
598struct fcoe_fast_sgl_ctx {
599 struct regpair sgl_start_addr;
600 __le32 sgl_byte_offset;
601 __le16 task_reuse_cnt;
602 __le16 init_offset_in_first_sge;
603};
604
605/* FCoE firmware function init */
606struct fcoe_init_func_ramrod_data {
607 struct scsi_init_func_params func_params;
608 struct scsi_init_func_queues q_params;
609 __le16 mtu;
610 __le16 sq_num_pages_in_pbl;
611 __le32 reserved;
612};
613
614/* FCoE: Mode of the connection: Target or Initiator or both */
615enum fcoe_mode_type {
616 FCOE_INITIATOR_MODE = 0x0,
617 FCOE_TARGET_MODE = 0x1,
618 FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
619 MAX_FCOE_MODE_TYPE
620};
621
622/* Per PF FCoE receive path statistics - tStorm RAM structure */
623struct fcoe_rx_stat {
624 struct regpair fcoe_rx_byte_cnt;
625 struct regpair fcoe_rx_data_pkt_cnt;
626 struct regpair fcoe_rx_xfer_pkt_cnt;
627 struct regpair fcoe_rx_other_pkt_cnt;
628 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
629 __le32 fcoe_silent_drop_pkt_rq_full_cnt;
630 __le32 fcoe_silent_drop_pkt_crc_error_cnt;
631 __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
632 __le32 fcoe_silent_drop_total_pkt_cnt;
633 __le32 rsrv;
634};
635
636/* FCoe statistics request */
637struct fcoe_stat_ramrod_data {
638 struct regpair stat_params_addr;
639};
640
641/* Per PF FCoE transmit path statistics - pStorm RAM structure */
614struct fcoe_tx_stat { 642struct fcoe_tx_stat {
615 struct regpair fcoe_tx_byte_cnt; 643 struct regpair fcoe_tx_byte_cnt;
616 struct regpair fcoe_tx_data_pkt_cnt; 644 struct regpair fcoe_tx_data_pkt_cnt;
@@ -618,51 +646,55 @@ struct fcoe_tx_stat {
618 struct regpair fcoe_tx_other_pkt_cnt; 646 struct regpair fcoe_tx_other_pkt_cnt;
619}; 647};
620 648
649/* FCoE SQ/XferQ element */
621struct fcoe_wqe { 650struct fcoe_wqe {
622 __le16 task_id; 651 __le16 task_id;
623 __le16 flags; 652 __le16 flags;
624#define FCOE_WQE_REQ_TYPE_MASK 0xF 653#define FCOE_WQE_REQ_TYPE_MASK 0xF
625#define FCOE_WQE_REQ_TYPE_SHIFT 0 654#define FCOE_WQE_REQ_TYPE_SHIFT 0
626#define FCOE_WQE_SGL_MODE_MASK 0x1 655#define FCOE_WQE_SGL_MODE_MASK 0x1
627#define FCOE_WQE_SGL_MODE_SHIFT 4 656#define FCOE_WQE_SGL_MODE_SHIFT 4
628#define FCOE_WQE_CONTINUATION_MASK 0x1 657#define FCOE_WQE_CONTINUATION_MASK 0x1
629#define FCOE_WQE_CONTINUATION_SHIFT 5 658#define FCOE_WQE_CONTINUATION_SHIFT 5
630#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 659#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
631#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 660#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
632#define FCOE_WQE_RESERVED_MASK 0x1 661#define FCOE_WQE_RESERVED_MASK 0x1
633#define FCOE_WQE_RESERVED_SHIFT 7 662#define FCOE_WQE_RESERVED_SHIFT 7
634#define FCOE_WQE_NUM_SGES_MASK 0xF 663#define FCOE_WQE_NUM_SGES_MASK 0xF
635#define FCOE_WQE_NUM_SGES_SHIFT 8 664#define FCOE_WQE_NUM_SGES_SHIFT 8
636#define FCOE_WQE_RESERVED1_MASK 0xF 665#define FCOE_WQE_RESERVED1_MASK 0xF
637#define FCOE_WQE_RESERVED1_SHIFT 12 666#define FCOE_WQE_RESERVED1_SHIFT 12
638 union fcoe_additional_info_union additional_info_union; 667 union fcoe_additional_info_union additional_info_union;
639}; 668};
640 669
670/* FCoE XFRQ element */
641struct xfrqe_prot_flags { 671struct xfrqe_prot_flags {
642 u8 flags; 672 u8 flags;
643#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF 673#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
644#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 674#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
645#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 675#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
646#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 676#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
647#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 677#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
648#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 678#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
649#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 679#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
650#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 680#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
651}; 681};
652 682
683/* FCoE doorbell data */
653struct fcoe_db_data { 684struct fcoe_db_data {
654 u8 params; 685 u8 params;
655#define FCOE_DB_DATA_DEST_MASK 0x3 686#define FCOE_DB_DATA_DEST_MASK 0x3
656#define FCOE_DB_DATA_DEST_SHIFT 0 687#define FCOE_DB_DATA_DEST_SHIFT 0
657#define FCOE_DB_DATA_AGG_CMD_MASK 0x3 688#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
658#define FCOE_DB_DATA_AGG_CMD_SHIFT 2 689#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
659#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 690#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
660#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 691#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
661#define FCOE_DB_DATA_RESERVED_MASK 0x1 692#define FCOE_DB_DATA_RESERVED_MASK 0x1
662#define FCOE_DB_DATA_RESERVED_SHIFT 5 693#define FCOE_DB_DATA_RESERVED_SHIFT 5
663#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 694#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
664#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 695#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
665 u8 agg_flags; 696 u8 agg_flags;
666 __le16 sq_prod; 697 __le16 sq_prod;
667}; 698};
699
668#endif /* __FCOE_COMMON__ */ 700#endif /* __FCOE_COMMON__ */
diff --git a/include/linux/qed/iscsi_common.h b/include/linux/qed/iscsi_common.h
index 85e086cba639..b8f83507f659 100644
--- a/include/linux/qed/iscsi_common.h
+++ b/include/linux/qed/iscsi_common.h
@@ -32,47 +32,48 @@
32 32
33#ifndef __ISCSI_COMMON__ 33#ifndef __ISCSI_COMMON__
34#define __ISCSI_COMMON__ 34#define __ISCSI_COMMON__
35
35/**********************/ 36/**********************/
36/* ISCSI FW CONSTANTS */ 37/* ISCSI FW CONSTANTS */
37/**********************/ 38/**********************/
38 39
39/* iSCSI HSI constants */ 40/* iSCSI HSI constants */
40#define ISCSI_DEFAULT_MTU (1500) 41#define ISCSI_DEFAULT_MTU (1500)
41 42
42/* KWQ (kernel work queue) layer codes */ 43/* KWQ (kernel work queue) layer codes */
43#define ISCSI_SLOW_PATH_LAYER_CODE (6) 44#define ISCSI_SLOW_PATH_LAYER_CODE (6)
44 45
45/* iSCSI parameter defaults */ 46/* iSCSI parameter defaults */
46#define ISCSI_DEFAULT_HEADER_DIGEST (0) 47#define ISCSI_DEFAULT_HEADER_DIGEST (0)
47#define ISCSI_DEFAULT_DATA_DIGEST (0) 48#define ISCSI_DEFAULT_DATA_DIGEST (0)
48#define ISCSI_DEFAULT_INITIAL_R2T (1) 49#define ISCSI_DEFAULT_INITIAL_R2T (1)
49#define ISCSI_DEFAULT_IMMEDIATE_DATA (1) 50#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
50#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000) 51#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
51#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000) 52#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
52#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000) 53#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
53#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1) 54#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
54 55
55/* iSCSI parameter limits */ 56/* iSCSI parameter limits */
56#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200) 57#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
57#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff) 58#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
58#define ISCSI_MIN_VAL_BURST_LENGTH (0x200) 59#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
59#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff) 60#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
60#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1) 61#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
61#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff) 62#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
62 63
63#define ISCSI_AHS_CNTL_SIZE 4 64#define ISCSI_AHS_CNTL_SIZE 4
64 65
65#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf) 66#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
66 67
67/* iSCSI reserved params */ 68/* iSCSI reserved params */
68#define ISCSI_ITT_ALL_ONES (0xffffffff) 69#define ISCSI_ITT_ALL_ONES (0xffffffff)
69#define ISCSI_TTT_ALL_ONES (0xffffffff) 70#define ISCSI_TTT_ALL_ONES (0xffffffff)
70 71
71#define ISCSI_OPTION_1_OFF_CHIP_TCP 1 72#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
72#define ISCSI_OPTION_2_ON_CHIP_TCP 2 73#define ISCSI_OPTION_2_ON_CHIP_TCP 2
73 74
74#define ISCSI_INITIATOR_MODE 0 75#define ISCSI_INITIATOR_MODE 0
75#define ISCSI_TARGET_MODE 1 76#define ISCSI_TARGET_MODE 1
76 77
77/* iSCSI request op codes */ 78/* iSCSI request op codes */
78#define ISCSI_OPCODE_NOP_OUT (0) 79#define ISCSI_OPCODE_NOP_OUT (0)
@@ -84,41 +85,42 @@
84#define ISCSI_OPCODE_LOGOUT_REQUEST (6) 85#define ISCSI_OPCODE_LOGOUT_REQUEST (6)
85 86
86/* iSCSI response/messages op codes */ 87/* iSCSI response/messages op codes */
87#define ISCSI_OPCODE_NOP_IN (0x20) 88#define ISCSI_OPCODE_NOP_IN (0x20)
88#define ISCSI_OPCODE_SCSI_RESPONSE (0x21) 89#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
89#define ISCSI_OPCODE_TMF_RESPONSE (0x22) 90#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
90#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23) 91#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
91#define ISCSI_OPCODE_TEXT_RESPONSE (0x24) 92#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
92#define ISCSI_OPCODE_DATA_IN (0x25) 93#define ISCSI_OPCODE_DATA_IN (0x25)
93#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26) 94#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
94#define ISCSI_OPCODE_R2T (0x31) 95#define ISCSI_OPCODE_R2T (0x31)
95#define ISCSI_OPCODE_ASYNC_MSG (0x32) 96#define ISCSI_OPCODE_ASYNC_MSG (0x32)
96#define ISCSI_OPCODE_REJECT (0x3f) 97#define ISCSI_OPCODE_REJECT (0x3f)
97 98
98/* iSCSI stages */ 99/* iSCSI stages */
99#define ISCSI_STAGE_SECURITY_NEGOTIATION (0) 100#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
100#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1) 101#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
101#define ISCSI_STAGE_FULL_FEATURE_PHASE (3) 102#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
102 103
103/* iSCSI CQE errors */ 104/* iSCSI CQE errors */
104#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08) 105#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
105#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10) 106#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
106#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20) 107#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
107 108
109/* ISCSI SGL entry */
108struct cqe_error_bitmap { 110struct cqe_error_bitmap {
109 u8 cqe_error_status_bits; 111 u8 cqe_error_status_bits;
110#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7 112#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
111#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0 113#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
112#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1 114#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
113#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3 115#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
114#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1 116#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
115#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4 117#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
116#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1 118#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
117#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5 119#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
118#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1 120#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
119#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6 121#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
120#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1 122#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
121#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7 123#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
122}; 124};
123 125
124union cqe_error_status { 126union cqe_error_status {
@@ -126,86 +128,72 @@ union cqe_error_status {
126 struct cqe_error_bitmap error_bits; 128 struct cqe_error_bitmap error_bits;
127}; 129};
128 130
131/* iSCSI Login Response PDU header */
129struct data_hdr { 132struct data_hdr {
130 __le32 data[12]; 133 __le32 data[12];
131}; 134};
132 135
133struct iscsi_async_msg_hdr { 136/* Union of data/r2t sequence number */
134 __le16 reserved0; 137union iscsi_seq_num {
135 u8 flags_attr; 138 __le16 data_sn;
136#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F 139 __le16 r2t_sn;
137#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
138#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
139#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
140 u8 opcode;
141 __le32 hdr_second_dword;
142#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
143#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
144#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
145#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
146 struct regpair lun;
147 __le32 all_ones;
148 __le32 reserved1;
149 __le32 stat_sn;
150 __le32 exp_cmd_sn;
151 __le32 max_cmd_sn;
152 __le16 param1_rsrv;
153 u8 async_vcode;
154 u8 async_event;
155 __le16 param3_rsrv;
156 __le16 param2_rsrv;
157 __le32 reserved7;
158}; 140};
159 141
160struct iscsi_cmd_hdr { 142/* iSCSI DIF flags */
161 __le16 reserved1; 143struct iscsi_dif_flags {
162 u8 flags_attr; 144 u8 flags;
163#define ISCSI_CMD_HDR_ATTR_MASK 0x7 145#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
164#define ISCSI_CMD_HDR_ATTR_SHIFT 0 146#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
165#define ISCSI_CMD_HDR_RSRV_MASK 0x3 147#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
166#define ISCSI_CMD_HDR_RSRV_SHIFT 3 148#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
167#define ISCSI_CMD_HDR_WRITE_MASK 0x1 149#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
168#define ISCSI_CMD_HDR_WRITE_SHIFT 5 150#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
169#define ISCSI_CMD_HDR_READ_MASK 0x1
170#define ISCSI_CMD_HDR_READ_SHIFT 6
171#define ISCSI_CMD_HDR_FINAL_MASK 0x1
172#define ISCSI_CMD_HDR_FINAL_SHIFT 7
173 u8 hdr_first_byte;
174#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
175#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
176#define ISCSI_CMD_HDR_IMM_MASK 0x1
177#define ISCSI_CMD_HDR_IMM_SHIFT 6
178#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
179#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
180 __le32 hdr_second_dword;
181#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
182#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
183#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
184#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
185 struct regpair lun;
186 __le32 itt;
187 __le32 expected_transfer_length;
188 __le32 cmd_sn;
189 __le32 exp_stat_sn;
190 __le32 cdb[4];
191}; 151};
192 152
153/* The iscsi storm task context of Ystorm */
154struct ystorm_iscsi_task_state {
155 struct scsi_cached_sges data_desc;
156 struct scsi_sgl_params sgl_params;
157 __le32 exp_r2t_sn;
158 __le32 buffer_offset;
159 union iscsi_seq_num seq_num;
160 struct iscsi_dif_flags dif_flags;
161 u8 flags;
162#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
163#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
164#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
165#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
166#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
167#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
168};
169
170/* The iscsi storm task context of Ystorm */
171struct ystorm_iscsi_task_rxmit_opt {
172 __le32 fast_rxmit_sge_offset;
173 __le32 scan_start_buffer_offset;
174 __le32 fast_rxmit_buffer_offset;
175 u8 scan_start_sgl_index;
176 u8 fast_rxmit_sgl_index;
177 __le16 reserved;
178};
179
180/* iSCSI Common PDU header */
193struct iscsi_common_hdr { 181struct iscsi_common_hdr {
194 u8 hdr_status; 182 u8 hdr_status;
195 u8 hdr_response; 183 u8 hdr_response;
196 u8 hdr_flags; 184 u8 hdr_flags;
197 u8 hdr_first_byte; 185 u8 hdr_first_byte;
198#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F 186#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
199#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0 187#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
200#define ISCSI_COMMON_HDR_IMM_MASK 0x1 188#define ISCSI_COMMON_HDR_IMM_MASK 0x1
201#define ISCSI_COMMON_HDR_IMM_SHIFT 6 189#define ISCSI_COMMON_HDR_IMM_SHIFT 6
202#define ISCSI_COMMON_HDR_RSRV_MASK 0x1 190#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
203#define ISCSI_COMMON_HDR_RSRV_SHIFT 7 191#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
204 __le32 hdr_second_dword; 192 __le32 hdr_second_dword;
205#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 193#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
206#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0 194#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
207#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF 195#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
208#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24 196#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
209 struct regpair lun_reserved; 197 struct regpair lun_reserved;
210 __le32 itt; 198 __le32 itt;
211 __le32 ttt; 199 __le32 ttt;
@@ -215,86 +203,60 @@ struct iscsi_common_hdr {
215 __le32 data[3]; 203 __le32 data[3];
216}; 204};
217 205
218struct iscsi_conn_offload_params { 206/* iSCSI Command PDU header */
219 struct regpair sq_pbl_addr; 207struct iscsi_cmd_hdr {
220 struct regpair r2tq_pbl_addr; 208 __le16 reserved1;
221 struct regpair xhq_pbl_addr; 209 u8 flags_attr;
222 struct regpair uhq_pbl_addr; 210#define ISCSI_CMD_HDR_ATTR_MASK 0x7
223 __le32 initial_ack; 211#define ISCSI_CMD_HDR_ATTR_SHIFT 0
224 __le16 physical_q0; 212#define ISCSI_CMD_HDR_RSRV_MASK 0x3
225 __le16 physical_q1; 213#define ISCSI_CMD_HDR_RSRV_SHIFT 3
226 u8 flags; 214#define ISCSI_CMD_HDR_WRITE_MASK 0x1
227#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1 215#define ISCSI_CMD_HDR_WRITE_SHIFT 5
228#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0 216#define ISCSI_CMD_HDR_READ_MASK 0x1
229#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1 217#define ISCSI_CMD_HDR_READ_SHIFT 6
230#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1 218#define ISCSI_CMD_HDR_FINAL_MASK 0x1
231#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1 219#define ISCSI_CMD_HDR_FINAL_SHIFT 7
232#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2 220 u8 hdr_first_byte;
233#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F 221#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
234#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3 222#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
235 u8 pbl_page_size_log; 223#define ISCSI_CMD_HDR_IMM_MASK 0x1
236 u8 pbe_page_size_log; 224#define ISCSI_CMD_HDR_IMM_SHIFT 6
237 u8 default_cq; 225#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
238 __le32 stat_sn; 226#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
239}; 227 __le32 hdr_second_dword;
240 228#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
241struct iscsi_slow_path_hdr { 229#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
242 u8 op_code; 230#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
243 u8 flags; 231#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
244#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF 232 struct regpair lun;
245#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0 233 __le32 itt;
246#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7 234 __le32 expected_transfer_length;
247#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4 235 __le32 cmd_sn;
248#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
249#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
250};
251
252struct iscsi_conn_update_ramrod_params {
253 struct iscsi_slow_path_hdr hdr;
254 __le16 conn_id;
255 __le32 fw_cid;
256 u8 flags;
257#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
258#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
259#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
260#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
261#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
262#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
263#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
264#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
265#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
266#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
267#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
268#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
269#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
270#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
271 u8 reserved0[3];
272 __le32 max_seq_size;
273 __le32 max_send_pdu_length;
274 __le32 max_recv_pdu_length;
275 __le32 first_seq_length;
276 __le32 exp_stat_sn; 236 __le32 exp_stat_sn;
237 __le32 cdb[4];
277}; 238};
278 239
240/* iSCSI Command PDU header with Extended CDB (Initiator Mode) */
279struct iscsi_ext_cdb_cmd_hdr { 241struct iscsi_ext_cdb_cmd_hdr {
280 __le16 reserved1; 242 __le16 reserved1;
281 u8 flags_attr; 243 u8 flags_attr;
282#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7 244#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
283#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0 245#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
284#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3 246#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
285#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3 247#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
286#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1 248#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
287#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5 249#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
288#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1 250#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
289#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6 251#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
290#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1 252#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
291#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7 253#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
292 u8 opcode; 254 u8 opcode;
293 __le32 hdr_second_dword; 255 __le32 hdr_second_dword;
294#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 256#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
295#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0 257#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
296#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF 258#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
297#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24 259#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
298 struct regpair lun; 260 struct regpair lun;
299 __le32 itt; 261 __le32 itt;
300 __le32 expected_transfer_length; 262 __le32 expected_transfer_length;
@@ -303,26 +265,27 @@ struct iscsi_ext_cdb_cmd_hdr {
303 struct scsi_sge cdb_sge; 265 struct scsi_sge cdb_sge;
304}; 266};
305 267
268/* iSCSI login request PDU header */
306struct iscsi_login_req_hdr { 269struct iscsi_login_req_hdr {
307 u8 version_min; 270 u8 version_min;
308 u8 version_max; 271 u8 version_max;
309 u8 flags_attr; 272 u8 flags_attr;
310#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3 273#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
311#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0 274#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
312#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3 275#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
313#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2 276#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
314#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3 277#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
315#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4 278#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
316#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1 279#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
317#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6 280#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
318#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1 281#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
319#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7 282#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
320 u8 opcode; 283 u8 opcode;
321 __le32 hdr_second_dword; 284 __le32 hdr_second_dword;
322#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 285#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
323#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0 286#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
324#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF 287#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
325#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24 288#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
326 __le32 isid_tabc; 289 __le32 isid_tabc;
327 __le16 tsih; 290 __le16 tsih;
328 __le16 isid_d; 291 __le16 isid_d;
@@ -334,6 +297,7 @@ struct iscsi_login_req_hdr {
334 __le32 reserved2[4]; 297 __le32 reserved2[4];
335}; 298};
336 299
300/* iSCSI logout request PDU header */
337struct iscsi_logout_req_hdr { 301struct iscsi_logout_req_hdr {
338 __le16 reserved0; 302 __le16 reserved0;
339 u8 reason_code; 303 u8 reason_code;
@@ -348,13 +312,14 @@ struct iscsi_logout_req_hdr {
348 __le32 reserved4[4]; 312 __le32 reserved4[4];
349}; 313};
350 314
315/* iSCSI Data-out PDU header */
351struct iscsi_data_out_hdr { 316struct iscsi_data_out_hdr {
352 __le16 reserved1; 317 __le16 reserved1;
353 u8 flags_attr; 318 u8 flags_attr;
354#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F 319#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
355#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0 320#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
356#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1 321#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
357#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7 322#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
358 u8 opcode; 323 u8 opcode;
359 __le32 reserved2; 324 __le32 reserved2;
360 struct regpair lun; 325 struct regpair lun;
@@ -368,22 +333,23 @@ struct iscsi_data_out_hdr {
368 __le32 reserved5; 333 __le32 reserved5;
369}; 334};
370 335
336/* iSCSI Data-in PDU header */
371struct iscsi_data_in_hdr { 337struct iscsi_data_in_hdr {
372 u8 status_rsvd; 338 u8 status_rsvd;
373 u8 reserved1; 339 u8 reserved1;
374 u8 flags; 340 u8 flags;
375#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1 341#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
376#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0 342#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
377#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1 343#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
378#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1 344#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
379#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1 345#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
380#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2 346#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
381#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7 347#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
382#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3 348#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
383#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1 349#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
384#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6 350#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
385#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1 351#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
386#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7 352#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
387 u8 opcode; 353 u8 opcode;
388 __le32 reserved2; 354 __le32 reserved2;
389 struct regpair lun; 355 struct regpair lun;
@@ -397,6 +363,7 @@ struct iscsi_data_in_hdr {
397 __le32 residual_count; 363 __le32 residual_count;
398}; 364};
399 365
366/* iSCSI R2T PDU header */
400struct iscsi_r2t_hdr { 367struct iscsi_r2t_hdr {
401 u8 reserved0[3]; 368 u8 reserved0[3];
402 u8 opcode; 369 u8 opcode;
@@ -412,13 +379,14 @@ struct iscsi_r2t_hdr {
412 __le32 desired_data_trns_len; 379 __le32 desired_data_trns_len;
413}; 380};
414 381
382/* iSCSI NOP-out PDU header */
415struct iscsi_nop_out_hdr { 383struct iscsi_nop_out_hdr {
416 __le16 reserved1; 384 __le16 reserved1;
417 u8 flags_attr; 385 u8 flags_attr;
418#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F 386#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
419#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0 387#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
420#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1 388#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
421#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7 389#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
422 u8 opcode; 390 u8 opcode;
423 __le32 reserved2; 391 __le32 reserved2;
424 struct regpair lun; 392 struct regpair lun;
@@ -432,19 +400,20 @@ struct iscsi_nop_out_hdr {
432 __le32 reserved6; 400 __le32 reserved6;
433}; 401};
434 402
403/* iSCSI NOP-in PDU header */
435struct iscsi_nop_in_hdr { 404struct iscsi_nop_in_hdr {
436 __le16 reserved0; 405 __le16 reserved0;
437 u8 flags_attr; 406 u8 flags_attr;
438#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F 407#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
439#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0 408#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
440#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1 409#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
441#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7 410#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
442 u8 opcode; 411 u8 opcode;
443 __le32 hdr_second_dword; 412 __le32 hdr_second_dword;
444#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 413#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
445#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0 414#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
446#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF 415#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
447#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24 416#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
448 struct regpair lun; 417 struct regpair lun;
449 __le32 itt; 418 __le32 itt;
450 __le32 ttt; 419 __le32 ttt;
@@ -456,26 +425,27 @@ struct iscsi_nop_in_hdr {
456 __le32 reserved7; 425 __le32 reserved7;
457}; 426};
458 427
428/* iSCSI Login Response PDU header */
459struct iscsi_login_response_hdr { 429struct iscsi_login_response_hdr {
460 u8 version_active; 430 u8 version_active;
461 u8 version_max; 431 u8 version_max;
462 u8 flags_attr; 432 u8 flags_attr;
463#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3 433#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
464#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0 434#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
465#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3 435#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
466#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2 436#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
467#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3 437#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
468#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4 438#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
469#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1 439#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
470#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6 440#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
471#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1 441#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
472#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7 442#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
473 u8 opcode; 443 u8 opcode;
474 __le32 hdr_second_dword; 444 __le32 hdr_second_dword;
475#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 445#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
476#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0 446#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
477#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF 447#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
478#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24 448#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
479 __le32 isid_tabc; 449 __le32 isid_tabc;
480 __le16 tsih; 450 __le16 tsih;
481 __le16 isid_d; 451 __le16 isid_d;
@@ -490,16 +460,17 @@ struct iscsi_login_response_hdr {
490 __le32 reserved4[2]; 460 __le32 reserved4[2];
491}; 461};
492 462
463/* iSCSI Logout Response PDU header */
493struct iscsi_logout_response_hdr { 464struct iscsi_logout_response_hdr {
494 u8 reserved1; 465 u8 reserved1;
495 u8 response; 466 u8 response;
496 u8 flags; 467 u8 flags;
497 u8 opcode; 468 u8 opcode;
498 __le32 hdr_second_dword; 469 __le32 hdr_second_dword;
499#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 470#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
500#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0 471#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
501#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF 472#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
502#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24 473#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
503 __le32 reserved2[2]; 474 __le32 reserved2[2];
504 __le32 itt; 475 __le32 itt;
505 __le32 reserved3; 476 __le32 reserved3;
@@ -512,21 +483,22 @@ struct iscsi_logout_response_hdr {
512 __le32 reserved5[1]; 483 __le32 reserved5[1];
513}; 484};
514 485
486/* iSCSI Text Request PDU header */
515struct iscsi_text_request_hdr { 487struct iscsi_text_request_hdr {
516 __le16 reserved0; 488 __le16 reserved0;
517 u8 flags_attr; 489 u8 flags_attr;
518#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F 490#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
519#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0 491#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
520#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1 492#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
521#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6 493#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
522#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1 494#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
523#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7 495#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
524 u8 opcode; 496 u8 opcode;
525 __le32 hdr_second_dword; 497 __le32 hdr_second_dword;
526#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 498#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
527#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0 499#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
528#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF 500#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
529#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24 501#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
530 struct regpair lun; 502 struct regpair lun;
531 __le32 itt; 503 __le32 itt;
532 __le32 ttt; 504 __le32 ttt;
@@ -535,21 +507,22 @@ struct iscsi_text_request_hdr {
535 __le32 reserved4[4]; 507 __le32 reserved4[4];
536}; 508};
537 509
510/* iSCSI Text Response PDU header */
538struct iscsi_text_response_hdr { 511struct iscsi_text_response_hdr {
539 __le16 reserved1; 512 __le16 reserved1;
540 u8 flags; 513 u8 flags;
541#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F 514#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
542#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0 515#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
543#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1 516#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
544#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6 517#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
545#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1 518#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
546#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7 519#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
547 u8 opcode; 520 u8 opcode;
548 __le32 hdr_second_dword; 521 __le32 hdr_second_dword;
549#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 522#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
550#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0 523#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
551#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF 524#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
552#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24 525#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
553 struct regpair lun; 526 struct regpair lun;
554 __le32 itt; 527 __le32 itt;
555 __le32 ttt; 528 __le32 ttt;
@@ -559,15 +532,16 @@ struct iscsi_text_response_hdr {
559 __le32 reserved4[3]; 532 __le32 reserved4[3];
560}; 533};
561 534
535/* iSCSI TMF Request PDU header */
562struct iscsi_tmf_request_hdr { 536struct iscsi_tmf_request_hdr {
563 __le16 reserved0; 537 __le16 reserved0;
564 u8 function; 538 u8 function;
565 u8 opcode; 539 u8 opcode;
566 __le32 hdr_second_dword; 540 __le32 hdr_second_dword;
567#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 541#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
568#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0 542#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
569#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF 543#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
570#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24 544#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
571 struct regpair lun; 545 struct regpair lun;
572 __le32 itt; 546 __le32 itt;
573 __le32 rtt; 547 __le32 rtt;
@@ -584,10 +558,10 @@ struct iscsi_tmf_response_hdr {
584 u8 hdr_flags; 558 u8 hdr_flags;
585 u8 opcode; 559 u8 opcode;
586 __le32 hdr_second_dword; 560 __le32 hdr_second_dword;
587#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 561#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
588#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0 562#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
589#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF 563#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
590#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24 564#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
591 struct regpair reserved0; 565 struct regpair reserved0;
592 __le32 itt; 566 __le32 itt;
593 __le32 reserved1; 567 __le32 reserved1;
@@ -597,16 +571,17 @@ struct iscsi_tmf_response_hdr {
597 __le32 reserved4[3]; 571 __le32 reserved4[3];
598}; 572};
599 573
574/* iSCSI Response PDU header */
600struct iscsi_response_hdr { 575struct iscsi_response_hdr {
601 u8 hdr_status; 576 u8 hdr_status;
602 u8 hdr_response; 577 u8 hdr_response;
603 u8 hdr_flags; 578 u8 hdr_flags;
604 u8 opcode; 579 u8 opcode;
605 __le32 hdr_second_dword; 580 __le32 hdr_second_dword;
606#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 581#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
607#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0 582#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
608#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF 583#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
609#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24 584#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
610 struct regpair lun; 585 struct regpair lun;
611 __le32 itt; 586 __le32 itt;
612 __le32 snack_tag; 587 __le32 snack_tag;
@@ -618,16 +593,17 @@ struct iscsi_response_hdr {
618 __le32 residual_count; 593 __le32 residual_count;
619}; 594};
620 595
596/* iSCSI Reject PDU header */
621struct iscsi_reject_hdr { 597struct iscsi_reject_hdr {
622 u8 reserved4; 598 u8 reserved4;
623 u8 hdr_reason; 599 u8 hdr_reason;
624 u8 hdr_flags; 600 u8 hdr_flags;
625 u8 opcode; 601 u8 opcode;
626 __le32 hdr_second_dword; 602 __le32 hdr_second_dword;
627#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF 603#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
628#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0 604#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
629#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF 605#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
630#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24 606#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
631 struct regpair reserved0; 607 struct regpair reserved0;
632 __le32 all_ones; 608 __le32 all_ones;
633 __le32 reserved2; 609 __le32 reserved2;
@@ -638,6 +614,35 @@ struct iscsi_reject_hdr {
638 __le32 reserved3[2]; 614 __le32 reserved3[2];
639}; 615};
640 616
617/* iSCSI Asynchronous Message PDU header */
618struct iscsi_async_msg_hdr {
619 __le16 reserved0;
620 u8 flags_attr;
621#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
622#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
623#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
624#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
625 u8 opcode;
626 __le32 hdr_second_dword;
627#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
628#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
629#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
630#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
631 struct regpair lun;
632 __le32 all_ones;
633 __le32 reserved1;
634 __le32 stat_sn;
635 __le32 exp_cmd_sn;
636 __le32 max_cmd_sn;
637 __le16 param1_rsrv;
638 u8 async_vcode;
639 u8 async_event;
640 __le16 param3_rsrv;
641 __le16 param2_rsrv;
642 __le32 reserved7;
643};
644
645/* PDU header part of Ystorm task context */
641union iscsi_task_hdr { 646union iscsi_task_hdr {
642 struct iscsi_common_hdr common; 647 struct iscsi_common_hdr common;
643 struct data_hdr data; 648 struct data_hdr data;
@@ -661,6 +666,329 @@ union iscsi_task_hdr {
661 struct iscsi_async_msg_hdr async_msg; 666 struct iscsi_async_msg_hdr async_msg;
662}; 667};
663 668
669/* The iscsi storm task context of Ystorm */
670struct ystorm_iscsi_task_st_ctx {
671 struct ystorm_iscsi_task_state state;
672 struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
673 union iscsi_task_hdr pdu_hdr;
674};
675
676struct ystorm_iscsi_task_ag_ctx {
677 u8 reserved;
678 u8 byte1;
679 __le16 word0;
680 u8 flags0;
681#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
682#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
683#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
684#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
685#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
686#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
687#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
688#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
689#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
690#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
691 u8 flags1;
692#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
693#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
694#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
695#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
696#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
697#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
698#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
699#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
700#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
701#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
702 u8 flags2;
703#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
704#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
705#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
706#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
707#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
708#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
709#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
710#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
711#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
712#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
713#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
714#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
715#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
716#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
717#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
718#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
719 u8 byte2;
720 __le32 TTT;
721 u8 byte3;
722 u8 byte4;
723 __le16 word1;
724};
725
726struct mstorm_iscsi_task_ag_ctx {
727 u8 cdu_validation;
728 u8 byte1;
729 __le16 task_cid;
730 u8 flags0;
731#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
732#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
733#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
734#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
735#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
736#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
737#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
738#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
739#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
740#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
741 u8 flags1;
742#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
743#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
744#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
745#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
746#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
747#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
748#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
749#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
750#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
751#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
752 u8 flags2;
753#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
754#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
755#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
756#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
757#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
758#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
759#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
760#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
761#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
762#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
763#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
764#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
765#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
766#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
767#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
768#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
769 u8 byte2;
770 __le32 reg0;
771 u8 byte3;
772 u8 byte4;
773 __le16 word1;
774};
775
776struct ustorm_iscsi_task_ag_ctx {
777 u8 reserved;
778 u8 state;
779 __le16 icid;
780 u8 flags0;
781#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
782#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
783#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
784#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
785#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
786#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
787#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
788#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
789 u8 flags1;
790#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
791#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
792#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
793#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
794#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
795#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
796#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
797#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
798 u8 flags2;
799#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
800#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
801#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
802#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
803#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
804#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
805#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
806#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
807#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
808#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
809#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
810#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
811#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
812#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
813#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
814#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
815 u8 flags3;
816#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
817#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
818#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
819#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
820#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
821#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
822#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
823#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
824#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
825#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
826 __le32 dif_err_intervals;
827 __le32 dif_error_1st_interval;
828 __le32 rcv_cont_len;
829 __le32 exp_cont_len;
830 __le32 total_data_acked;
831 __le32 exp_data_acked;
832 u8 next_tid_valid;
833 u8 byte3;
834 __le16 word1;
835 __le16 next_tid;
836 __le16 word3;
837 __le32 hdr_residual_count;
838 __le32 exp_r2t_sn;
839};
840
841/* The iscsi storm task context of Mstorm */
842struct mstorm_iscsi_task_st_ctx {
843 struct scsi_cached_sges data_desc;
844 struct scsi_sgl_params sgl_params;
845 __le32 rem_task_size;
846 __le32 data_buffer_offset;
847 u8 task_type;
848 struct iscsi_dif_flags dif_flags;
849 u8 reserved0[2];
850 struct regpair sense_db;
851 __le32 expected_itt;
852 __le32 reserved1;
853};
854
855struct iscsi_reg1 {
856 __le32 reg1_map;
857#define ISCSI_REG1_NUM_SGES_MASK 0xF
858#define ISCSI_REG1_NUM_SGES_SHIFT 0
859#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
860#define ISCSI_REG1_RESERVED1_SHIFT 4
861};
862
863/* The iscsi storm task context of Ustorm */
864struct ustorm_iscsi_task_st_ctx {
865 __le32 rem_rcv_len;
866 __le32 exp_data_transfer_len;
867 __le32 exp_data_sn;
868 struct regpair lun;
869 struct iscsi_reg1 reg1;
870 u8 flags2;
871#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
872#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
873#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
874#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
875 struct iscsi_dif_flags dif_flags;
876 __le16 reserved3;
877 __le32 reserved4;
878 __le32 reserved5;
879 __le32 reserved6;
880 __le32 reserved7;
881 u8 task_type;
882 u8 error_flags;
883#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
884#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
885#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
886#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
887#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
888#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
889#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
890#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
891 u8 flags;
892#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
893#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
894#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
895#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
896#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
897#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
898#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
899#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
900#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
901#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
902#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
903#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
904#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
905#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
906 u8 cq_rss_number;
907};
908
909/* iscsi task context */
910struct iscsi_task_context {
911 struct ystorm_iscsi_task_st_ctx ystorm_st_context;
912 struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
913 struct regpair ystorm_ag_padding[2];
914 struct tdif_task_context tdif_context;
915 struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
916 struct regpair mstorm_ag_padding[2];
917 struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
918 struct mstorm_iscsi_task_st_ctx mstorm_st_context;
919 struct ustorm_iscsi_task_st_ctx ustorm_st_context;
920 struct rdif_task_context rdif_context;
921};
922
923/* iSCSI connection offload params passed by driver to FW in ISCSI offload
924 * ramrod.
925 */
926struct iscsi_conn_offload_params {
927 struct regpair sq_pbl_addr;
928 struct regpair r2tq_pbl_addr;
929 struct regpair xhq_pbl_addr;
930 struct regpair uhq_pbl_addr;
931 __le32 initial_ack;
932 __le16 physical_q0;
933 __le16 physical_q1;
934 u8 flags;
935#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
936#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
937#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
938#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
939#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
940#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
941#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
942#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
943 u8 pbl_page_size_log;
944 u8 pbe_page_size_log;
945 u8 default_cq;
946 __le32 stat_sn;
947};
948
949/* spe message header */
950struct iscsi_slow_path_hdr {
951 u8 op_code;
952 u8 flags;
953#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
954#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
955#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
956#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
957#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
958#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
959};
960
961/* iSCSI connection update params passed by driver to FW in ISCSI update
962 *ramrod.
963 */
964struct iscsi_conn_update_ramrod_params {
965 struct iscsi_slow_path_hdr hdr;
966 __le16 conn_id;
967 __le32 fw_cid;
968 u8 flags;
969#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
970#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
971#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
972#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
973#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
974#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
975#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
976#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
977#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
978#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
979#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
980#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
981#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
982#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
983 u8 reserved0[3];
984 __le32 max_seq_size;
985 __le32 max_send_pdu_length;
986 __le32 max_recv_pdu_length;
987 __le32 first_seq_length;
988 __le32 exp_stat_sn;
989};
990
991/* iSCSI CQ element */
664struct iscsi_cqe_common { 992struct iscsi_cqe_common {
665 __le16 conn_id; 993 __le16 conn_id;
666 u8 cqe_type; 994 u8 cqe_type;
@@ -669,6 +997,7 @@ struct iscsi_cqe_common {
669 union iscsi_task_hdr iscsi_hdr; 997 union iscsi_task_hdr iscsi_hdr;
670}; 998};
671 999
1000/* iSCSI CQ element */
672struct iscsi_cqe_solicited { 1001struct iscsi_cqe_solicited {
673 __le16 conn_id; 1002 __le16 conn_id;
674 u8 cqe_type; 1003 u8 cqe_type;
@@ -682,6 +1011,7 @@ struct iscsi_cqe_solicited {
682 union iscsi_task_hdr iscsi_hdr; 1011 union iscsi_task_hdr iscsi_hdr;
683}; 1012};
684 1013
1014/* iSCSI CQ element */
685struct iscsi_cqe_unsolicited { 1015struct iscsi_cqe_unsolicited {
686 __le16 conn_id; 1016 __le16 conn_id;
687 u8 cqe_type; 1017 u8 cqe_type;
@@ -693,12 +1023,14 @@ struct iscsi_cqe_unsolicited {
693 union iscsi_task_hdr iscsi_hdr; 1023 union iscsi_task_hdr iscsi_hdr;
694}; 1024};
695 1025
1026/* iSCSI CQ element */
696union iscsi_cqe { 1027union iscsi_cqe {
697 struct iscsi_cqe_common cqe_common; 1028 struct iscsi_cqe_common cqe_common;
698 struct iscsi_cqe_solicited cqe_solicited; 1029 struct iscsi_cqe_solicited cqe_solicited;
699 struct iscsi_cqe_unsolicited cqe_unsolicited; 1030 struct iscsi_cqe_unsolicited cqe_unsolicited;
700}; 1031};
701 1032
1033/* iSCSI CQE type */
702enum iscsi_cqes_type { 1034enum iscsi_cqes_type {
703 ISCSI_CQE_TYPE_SOLICITED = 1, 1035 ISCSI_CQE_TYPE_SOLICITED = 1,
704 ISCSI_CQE_TYPE_UNSOLICITED, 1036 ISCSI_CQE_TYPE_UNSOLICITED,
@@ -708,6 +1040,7 @@ enum iscsi_cqes_type {
708 MAX_ISCSI_CQES_TYPE 1040 MAX_ISCSI_CQES_TYPE
709}; 1041};
710 1042
1043/* iSCSI CQE type */
711enum iscsi_cqe_unsolicited_type { 1044enum iscsi_cqe_unsolicited_type {
712 ISCSI_CQE_UNSOLICITED_NONE, 1045 ISCSI_CQE_UNSOLICITED_NONE,
713 ISCSI_CQE_UNSOLICITED_SINGLE, 1046 ISCSI_CQE_UNSOLICITED_SINGLE,
@@ -717,37 +1050,28 @@ enum iscsi_cqe_unsolicited_type {
717 MAX_ISCSI_CQE_UNSOLICITED_TYPE 1050 MAX_ISCSI_CQE_UNSOLICITED_TYPE
718}; 1051};
719 1052
720 1053/* iscsi debug modes */
721struct iscsi_debug_modes { 1054struct iscsi_debug_modes {
722 u8 flags; 1055 u8 flags;
723#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1 1056#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
724#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0 1057#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
725#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1 1058#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
726#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1 1059#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
727#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1 1060#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
728#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2 1061#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
729#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1 1062#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
730#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3 1063#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
731#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1 1064#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
732#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4 1065#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
733#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1 1066#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
734#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5 1067#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
735#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1 1068#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1
736#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6 1069#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6
737#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1 1070#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1
738#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7 1071#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7
739}; 1072};
740 1073
741struct iscsi_dif_flags { 1074/* iSCSI kernel completion queue IDs */
742 u8 flags;
743#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
744#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
745#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
746#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
747#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
748#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
749};
750
751enum iscsi_eqe_opcode { 1075enum iscsi_eqe_opcode {
752 ISCSI_EVENT_TYPE_INIT_FUNC = 0, 1076 ISCSI_EVENT_TYPE_INIT_FUNC = 0,
753 ISCSI_EVENT_TYPE_DESTROY_FUNC, 1077 ISCSI_EVENT_TYPE_DESTROY_FUNC,
@@ -772,6 +1096,7 @@ enum iscsi_eqe_opcode {
772 MAX_ISCSI_EQE_OPCODE 1096 MAX_ISCSI_EQE_OPCODE
773}; 1097};
774 1098
1099/* iSCSI EQE and CQE completion status */
775enum iscsi_error_types { 1100enum iscsi_error_types {
776 ISCSI_STATUS_NONE = 0, 1101 ISCSI_STATUS_NONE = 0,
777 ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN = 1, 1102 ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN = 1,
@@ -823,7 +1148,7 @@ enum iscsi_error_types {
823 MAX_ISCSI_ERROR_TYPES 1148 MAX_ISCSI_ERROR_TYPES
824}; 1149};
825 1150
826 1151/* iSCSI Ramrod Command IDs */
827enum iscsi_ramrod_cmd_id { 1152enum iscsi_ramrod_cmd_id {
828 ISCSI_RAMROD_CMD_ID_UNUSED = 0, 1153 ISCSI_RAMROD_CMD_ID_UNUSED = 0,
829 ISCSI_RAMROD_CMD_ID_INIT_FUNC = 1, 1154 ISCSI_RAMROD_CMD_ID_INIT_FUNC = 1,
@@ -836,19 +1161,7 @@ enum iscsi_ramrod_cmd_id {
836 MAX_ISCSI_RAMROD_CMD_ID 1161 MAX_ISCSI_RAMROD_CMD_ID
837}; 1162};
838 1163
839struct iscsi_reg1 { 1164/* iSCSI connection termination request */
840 __le32 reg1_map;
841#define ISCSI_REG1_NUM_SGES_MASK 0xF
842#define ISCSI_REG1_NUM_SGES_SHIFT 0
843#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
844#define ISCSI_REG1_RESERVED1_SHIFT 4
845};
846
847union iscsi_seq_num {
848 __le16 data_sn;
849 __le16 r2t_sn;
850};
851
852struct iscsi_spe_conn_mac_update { 1165struct iscsi_spe_conn_mac_update {
853 struct iscsi_slow_path_hdr hdr; 1166 struct iscsi_slow_path_hdr hdr;
854 __le16 conn_id; 1167 __le16 conn_id;
@@ -859,6 +1172,9 @@ struct iscsi_spe_conn_mac_update {
859 u8 reserved0[2]; 1172 u8 reserved0[2];
860}; 1173};
861 1174
1175/* iSCSI and TCP connection (Option 1) offload params passed by driver to FW in
1176 * iSCSI offload ramrod.
1177 */
862struct iscsi_spe_conn_offload { 1178struct iscsi_spe_conn_offload {
863 struct iscsi_slow_path_hdr hdr; 1179 struct iscsi_slow_path_hdr hdr;
864 __le16 conn_id; 1180 __le16 conn_id;
@@ -867,6 +1183,9 @@ struct iscsi_spe_conn_offload {
867 struct tcp_offload_params tcp; 1183 struct tcp_offload_params tcp;
868}; 1184};
869 1185
1186/* iSCSI and TCP connection(Option 2) offload params passed by driver to FW in
1187 * iSCSI offload ramrod.
1188 */
870struct iscsi_spe_conn_offload_option2 { 1189struct iscsi_spe_conn_offload_option2 {
871 struct iscsi_slow_path_hdr hdr; 1190 struct iscsi_slow_path_hdr hdr;
872 __le16 conn_id; 1191 __le16 conn_id;
@@ -875,6 +1194,7 @@ struct iscsi_spe_conn_offload_option2 {
875 struct tcp_offload_params_opt2 tcp; 1194 struct tcp_offload_params_opt2 tcp;
876}; 1195};
877 1196
1197/* iSCSI connection termination request */
878struct iscsi_spe_conn_termination { 1198struct iscsi_spe_conn_termination {
879 struct iscsi_slow_path_hdr hdr; 1199 struct iscsi_slow_path_hdr hdr;
880 __le16 conn_id; 1200 __le16 conn_id;
@@ -885,12 +1205,14 @@ struct iscsi_spe_conn_termination {
885 struct regpair query_params_addr; 1205 struct regpair query_params_addr;
886}; 1206};
887 1207
1208/* iSCSI firmware function destroy parameters */
888struct iscsi_spe_func_dstry { 1209struct iscsi_spe_func_dstry {
889 struct iscsi_slow_path_hdr hdr; 1210 struct iscsi_slow_path_hdr hdr;
890 __le16 reserved0; 1211 __le16 reserved0;
891 __le32 reserved1; 1212 __le32 reserved1;
892}; 1213};
893 1214
1215/* iSCSI firmware function init parameters */
894struct iscsi_spe_func_init { 1216struct iscsi_spe_func_init {
895 struct iscsi_slow_path_hdr hdr; 1217 struct iscsi_slow_path_hdr hdr;
896 __le16 half_way_close_timeout; 1218 __le16 half_way_close_timeout;
@@ -908,273 +1230,7 @@ struct iscsi_spe_func_init {
908 struct scsi_init_func_queues q_params; 1230 struct scsi_init_func_queues q_params;
909}; 1231};
910 1232
911struct ystorm_iscsi_task_state { 1233/* iSCSI task type */
912 struct scsi_cached_sges data_desc;
913 struct scsi_sgl_params sgl_params;
914 __le32 exp_r2t_sn;
915 __le32 buffer_offset;
916 union iscsi_seq_num seq_num;
917 struct iscsi_dif_flags dif_flags;
918 u8 flags;
919#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
920#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
921#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
922#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
923#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
924#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
925};
926
927struct ystorm_iscsi_task_rxmit_opt {
928 __le32 fast_rxmit_sge_offset;
929 __le32 scan_start_buffer_offset;
930 __le32 fast_rxmit_buffer_offset;
931 u8 scan_start_sgl_index;
932 u8 fast_rxmit_sgl_index;
933 __le16 reserved;
934};
935
936struct ystorm_iscsi_task_st_ctx {
937 struct ystorm_iscsi_task_state state;
938 struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
939 union iscsi_task_hdr pdu_hdr;
940};
941
942struct ystorm_iscsi_task_ag_ctx {
943 u8 reserved;
944 u8 byte1;
945 __le16 word0;
946 u8 flags0;
947#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
948#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
949#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
950#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
951#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
952#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
953#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
954#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
955#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
956#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
957 u8 flags1;
958#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
959#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
960#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
961#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
962#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
963#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
964#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
965#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
966#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
967#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
968 u8 flags2;
969#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
970#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
971#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
972#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
973#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
974#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
975#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
976#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
977#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
978#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
979#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
980#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
981#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
982#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
983#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
984#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
985 u8 byte2;
986 __le32 TTT;
987 u8 byte3;
988 u8 byte4;
989 __le16 word1;
990};
991
992struct mstorm_iscsi_task_ag_ctx {
993 u8 cdu_validation;
994 u8 byte1;
995 __le16 task_cid;
996 u8 flags0;
997#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
998#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
999#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
1000#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
1001#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
1002#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
1003#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
1004#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
1005#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
1006#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
1007 u8 flags1;
1008#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
1009#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
1010#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
1011#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
1012#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
1013#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
1014#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
1015#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
1016#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
1017#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
1018 u8 flags2;
1019#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
1020#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
1021#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
1022#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
1023#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
1024#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
1025#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
1026#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
1027#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
1028#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
1029#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
1030#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
1031#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
1032#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
1033#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
1034#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
1035 u8 byte2;
1036 __le32 reg0;
1037 u8 byte3;
1038 u8 byte4;
1039 __le16 word1;
1040};
1041
1042struct ustorm_iscsi_task_ag_ctx {
1043 u8 reserved;
1044 u8 state;
1045 __le16 icid;
1046 u8 flags0;
1047#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
1048#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
1049#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
1050#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
1051#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
1052#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
1053#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
1054#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
1055 u8 flags1;
1056#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
1057#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
1058#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
1059#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
1060#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
1061#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
1062#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
1063#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
1064 u8 flags2;
1065#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
1066#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
1067#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
1068#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
1069#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
1070#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
1071#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
1072#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
1073#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
1074#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
1075#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
1076#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
1077#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
1078#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
1079#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
1080#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
1081 u8 flags3;
1082#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
1083#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
1084#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
1085#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
1086#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
1087#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
1088#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
1089#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
1090#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
1091#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
1092 __le32 dif_err_intervals;
1093 __le32 dif_error_1st_interval;
1094 __le32 rcv_cont_len;
1095 __le32 exp_cont_len;
1096 __le32 total_data_acked;
1097 __le32 exp_data_acked;
1098 u8 next_tid_valid;
1099 u8 byte3;
1100 __le16 word1;
1101 __le16 next_tid;
1102 __le16 word3;
1103 __le32 hdr_residual_count;
1104 __le32 exp_r2t_sn;
1105};
1106
1107struct mstorm_iscsi_task_st_ctx {
1108 struct scsi_cached_sges data_desc;
1109 struct scsi_sgl_params sgl_params;
1110 __le32 rem_task_size;
1111 __le32 data_buffer_offset;
1112 u8 task_type;
1113 struct iscsi_dif_flags dif_flags;
1114 u8 reserved0[2];
1115 struct regpair sense_db;
1116 __le32 expected_itt;
1117 __le32 reserved1;
1118};
1119
1120struct ustorm_iscsi_task_st_ctx {
1121 __le32 rem_rcv_len;
1122 __le32 exp_data_transfer_len;
1123 __le32 exp_data_sn;
1124 struct regpair lun;
1125 struct iscsi_reg1 reg1;
1126 u8 flags2;
1127#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
1128#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
1129#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
1130#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
1131 struct iscsi_dif_flags dif_flags;
1132 __le16 reserved3;
1133 __le32 reserved4;
1134 __le32 reserved5;
1135 __le32 reserved6;
1136 __le32 reserved7;
1137 u8 task_type;
1138 u8 error_flags;
1139#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
1140#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
1141#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
1142#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
1143#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
1144#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
1145#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
1146#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
1147 u8 flags;
1148#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
1149#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
1150#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
1151#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
1152#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
1153#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
1154#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
1155#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
1156#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
1157#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
1158#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
1159#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
1160#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
1161#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
1162 u8 cq_rss_number;
1163};
1164
1165struct iscsi_task_context {
1166 struct ystorm_iscsi_task_st_ctx ystorm_st_context;
1167 struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
1168 struct regpair ystorm_ag_padding[2];
1169 struct tdif_task_context tdif_context;
1170 struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
1171 struct regpair mstorm_ag_padding[2];
1172 struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
1173 struct mstorm_iscsi_task_st_ctx mstorm_st_context;
1174 struct ustorm_iscsi_task_st_ctx ustorm_st_context;
1175 struct rdif_task_context rdif_context;
1176};
1177
1178enum iscsi_task_type { 1234enum iscsi_task_type {
1179 ISCSI_TASK_TYPE_INITIATOR_WRITE, 1235 ISCSI_TASK_TYPE_INITIATOR_WRITE,
1180 ISCSI_TASK_TYPE_INITIATOR_READ, 1236 ISCSI_TASK_TYPE_INITIATOR_READ,
@@ -1189,50 +1245,53 @@ enum iscsi_task_type {
1189 MAX_ISCSI_TASK_TYPE 1245 MAX_ISCSI_TASK_TYPE
1190}; 1246};
1191 1247
1248/* iSCSI DesiredDataTransferLength/ttt union */
1192union iscsi_ttt_txlen_union { 1249union iscsi_ttt_txlen_union {
1193 __le32 desired_tx_len; 1250 __le32 desired_tx_len;
1194 __le32 ttt; 1251 __le32 ttt;
1195}; 1252};
1196 1253
1254/* iSCSI uHQ element */
1197struct iscsi_uhqe { 1255struct iscsi_uhqe {
1198 __le32 reg1; 1256 __le32 reg1;
1199#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF 1257#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
1200#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0 1258#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
1201#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1 1259#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
1202#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20 1260#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
1203#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1 1261#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
1204#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21 1262#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
1205#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1 1263#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
1206#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22 1264#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
1207#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1 1265#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
1208#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23 1266#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
1209#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF 1267#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
1210#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24 1268#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
1211 __le32 reg2; 1269 __le32 reg2;
1212#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF 1270#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
1213#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0 1271#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
1214#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF 1272#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
1215#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24 1273#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
1216}; 1274};
1217 1275
1218 1276/* iSCSI WQ element */
1219struct iscsi_wqe { 1277struct iscsi_wqe {
1220 __le16 task_id; 1278 __le16 task_id;
1221 u8 flags; 1279 u8 flags;
1222#define ISCSI_WQE_WQE_TYPE_MASK 0x7 1280#define ISCSI_WQE_WQE_TYPE_MASK 0x7
1223#define ISCSI_WQE_WQE_TYPE_SHIFT 0 1281#define ISCSI_WQE_WQE_TYPE_SHIFT 0
1224#define ISCSI_WQE_NUM_SGES_MASK 0xF 1282#define ISCSI_WQE_NUM_SGES_MASK 0xF
1225#define ISCSI_WQE_NUM_SGES_SHIFT 3 1283#define ISCSI_WQE_NUM_SGES_SHIFT 3
1226#define ISCSI_WQE_RESPONSE_MASK 0x1 1284#define ISCSI_WQE_RESPONSE_MASK 0x1
1227#define ISCSI_WQE_RESPONSE_SHIFT 7 1285#define ISCSI_WQE_RESPONSE_SHIFT 7
1228 struct iscsi_dif_flags prot_flags; 1286 struct iscsi_dif_flags prot_flags;
1229 __le32 contlen_cdbsize; 1287 __le32 contlen_cdbsize;
1230#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF 1288#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
1231#define ISCSI_WQE_CONT_LEN_SHIFT 0 1289#define ISCSI_WQE_CONT_LEN_SHIFT 0
1232#define ISCSI_WQE_CDB_SIZE_MASK 0xFF 1290#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
1233#define ISCSI_WQE_CDB_SIZE_SHIFT 24 1291#define ISCSI_WQE_CDB_SIZE_SHIFT 24
1234}; 1292};
1235 1293
1294/* iSCSI wqe type */
1236enum iscsi_wqe_type { 1295enum iscsi_wqe_type {
1237 ISCSI_WQE_TYPE_NORMAL, 1296 ISCSI_WQE_TYPE_NORMAL,
1238 ISCSI_WQE_TYPE_TASK_CLEANUP, 1297 ISCSI_WQE_TYPE_TASK_CLEANUP,
@@ -1244,6 +1303,7 @@ enum iscsi_wqe_type {
1244 MAX_ISCSI_WQE_TYPE 1303 MAX_ISCSI_WQE_TYPE
1245}; 1304};
1246 1305
1306/* iSCSI xHQ element */
1247struct iscsi_xhqe { 1307struct iscsi_xhqe {
1248 union iscsi_ttt_txlen_union ttt_or_txlen; 1308 union iscsi_ttt_txlen_union ttt_or_txlen;
1249 __le32 exp_stat_sn; 1309 __le32 exp_stat_sn;
@@ -1251,27 +1311,30 @@ struct iscsi_xhqe {
1251 u8 total_ahs_length; 1311 u8 total_ahs_length;
1252 u8 opcode; 1312 u8 opcode;
1253 u8 flags; 1313 u8 flags;
1254#define ISCSI_XHQE_FINAL_MASK 0x1 1314#define ISCSI_XHQE_FINAL_MASK 0x1
1255#define ISCSI_XHQE_FINAL_SHIFT 0 1315#define ISCSI_XHQE_FINAL_SHIFT 0
1256#define ISCSI_XHQE_STATUS_BIT_MASK 0x1 1316#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
1257#define ISCSI_XHQE_STATUS_BIT_SHIFT 1 1317#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
1258#define ISCSI_XHQE_NUM_SGES_MASK 0xF 1318#define ISCSI_XHQE_NUM_SGES_MASK 0xF
1259#define ISCSI_XHQE_NUM_SGES_SHIFT 2 1319#define ISCSI_XHQE_NUM_SGES_SHIFT 2
1260#define ISCSI_XHQE_RESERVED0_MASK 0x3 1320#define ISCSI_XHQE_RESERVED0_MASK 0x3
1261#define ISCSI_XHQE_RESERVED0_SHIFT 6 1321#define ISCSI_XHQE_RESERVED0_SHIFT 6
1262 union iscsi_seq_num seq_num; 1322 union iscsi_seq_num seq_num;
1263 __le16 reserved1; 1323 __le16 reserved1;
1264}; 1324};
1265 1325
1326/* Per PF iSCSI receive path statistics - mStorm RAM structure */
1266struct mstorm_iscsi_stats_drv { 1327struct mstorm_iscsi_stats_drv {
1267 struct regpair iscsi_rx_dropped_pdus_task_not_valid; 1328 struct regpair iscsi_rx_dropped_pdus_task_not_valid;
1268}; 1329};
1269 1330
1331/* Per PF iSCSI transmit path statistics - pStorm RAM structure */
1270struct pstorm_iscsi_stats_drv { 1332struct pstorm_iscsi_stats_drv {
1271 struct regpair iscsi_tx_bytes_cnt; 1333 struct regpair iscsi_tx_bytes_cnt;
1272 struct regpair iscsi_tx_packet_cnt; 1334 struct regpair iscsi_tx_packet_cnt;
1273}; 1335};
1274 1336
1337/* Per PF iSCSI receive path statistics - tStorm RAM structure */
1275struct tstorm_iscsi_stats_drv { 1338struct tstorm_iscsi_stats_drv {
1276 struct regpair iscsi_rx_bytes_cnt; 1339 struct regpair iscsi_rx_bytes_cnt;
1277 struct regpair iscsi_rx_packet_cnt; 1340 struct regpair iscsi_rx_packet_cnt;
@@ -1281,17 +1344,20 @@ struct tstorm_iscsi_stats_drv {
1281 __le32 iscsi_immq_threshold_cnt; 1344 __le32 iscsi_immq_threshold_cnt;
1282}; 1345};
1283 1346
1347/* Per PF iSCSI receive path statistics - uStorm RAM structure */
1284struct ustorm_iscsi_stats_drv { 1348struct ustorm_iscsi_stats_drv {
1285 struct regpair iscsi_rx_data_pdu_cnt; 1349 struct regpair iscsi_rx_data_pdu_cnt;
1286 struct regpair iscsi_rx_r2t_pdu_cnt; 1350 struct regpair iscsi_rx_r2t_pdu_cnt;
1287 struct regpair iscsi_rx_total_pdu_cnt; 1351 struct regpair iscsi_rx_total_pdu_cnt;
1288}; 1352};
1289 1353
1354/* Per PF iSCSI transmit path statistics - xStorm RAM structure */
1290struct xstorm_iscsi_stats_drv { 1355struct xstorm_iscsi_stats_drv {
1291 struct regpair iscsi_tx_go_to_slow_start_event_cnt; 1356 struct regpair iscsi_tx_go_to_slow_start_event_cnt;
1292 struct regpair iscsi_tx_fast_retransmit_event_cnt; 1357 struct regpair iscsi_tx_fast_retransmit_event_cnt;
1293}; 1358};
1294 1359
1360/* Per PF iSCSI transmit path statistics - yStorm RAM structure */
1295struct ystorm_iscsi_stats_drv { 1361struct ystorm_iscsi_stats_drv {
1296 struct regpair iscsi_tx_data_pdu_cnt; 1362 struct regpair iscsi_tx_data_pdu_cnt;
1297 struct regpair iscsi_tx_r2t_pdu_cnt; 1363 struct regpair iscsi_tx_r2t_pdu_cnt;
@@ -1303,68 +1369,68 @@ struct tstorm_iscsi_task_ag_ctx {
1303 u8 byte1; 1369 u8 byte1;
1304 __le16 word0; 1370 __le16 word0;
1305 u8 flags0; 1371 u8 flags0;
1306#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF 1372#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
1307#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0 1373#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
1308#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1 1374#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
1309#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4 1375#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
1310#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1 1376#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
1311#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5 1377#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
1312#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1 1378#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
1313#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6 1379#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
1314#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1 1380#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
1315#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7 1381#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
1316 u8 flags1; 1382 u8 flags1;
1317#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1 1383#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
1318#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0 1384#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
1319#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1 1385#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
1320#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1 1386#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
1321#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3 1387#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
1322#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2 1388#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
1323#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3 1389#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
1324#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4 1390#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
1325#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3 1391#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
1326#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6 1392#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
1327 u8 flags2; 1393 u8 flags2;
1328#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3 1394#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
1329#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0 1395#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
1330#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3 1396#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
1331#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2 1397#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
1332#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3 1398#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
1333#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4 1399#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
1334#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3 1400#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
1335#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6 1401#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
1336 u8 flags3; 1402 u8 flags3;
1337#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3 1403#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
1338#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0 1404#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
1339#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1 1405#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
1340#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2 1406#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
1341#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1 1407#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
1342#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3 1408#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
1343#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1 1409#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
1344#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4 1410#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
1345#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1 1411#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
1346#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5 1412#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
1347#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1 1413#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
1348#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6 1414#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
1349#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1 1415#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
1350#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7 1416#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
1351 u8 flags4; 1417 u8 flags4;
1352#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1 1418#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
1353#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0 1419#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
1354#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1 1420#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
1355#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1 1421#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
1356#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1 1422#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
1357#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2 1423#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
1358#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1 1424#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
1359#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3 1425#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
1360#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1 1426#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
1361#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4 1427#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
1362#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1 1428#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
1363#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5 1429#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
1364#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1 1430#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
1365#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6 1431#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
1366#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1 1432#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
1367#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7 1433#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
1368 u8 byte2; 1434 u8 byte2;
1369 __le16 word1; 1435 __le16 word1;
1370 __le32 reg0; 1436 __le32 reg0;
@@ -1376,18 +1442,20 @@ struct tstorm_iscsi_task_ag_ctx {
1376 __le32 reg1; 1442 __le32 reg1;
1377 __le32 reg2; 1443 __le32 reg2;
1378}; 1444};
1445
1446/* iSCSI doorbell data */
1379struct iscsi_db_data { 1447struct iscsi_db_data {
1380 u8 params; 1448 u8 params;
1381#define ISCSI_DB_DATA_DEST_MASK 0x3 1449#define ISCSI_DB_DATA_DEST_MASK 0x3
1382#define ISCSI_DB_DATA_DEST_SHIFT 0 1450#define ISCSI_DB_DATA_DEST_SHIFT 0
1383#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3 1451#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
1384#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2 1452#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
1385#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1 1453#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
1386#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4 1454#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
1387#define ISCSI_DB_DATA_RESERVED_MASK 0x1 1455#define ISCSI_DB_DATA_RESERVED_MASK 0x1
1388#define ISCSI_DB_DATA_RESERVED_SHIFT 5 1456#define ISCSI_DB_DATA_RESERVED_SHIFT 5
1389#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3 1457#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
1390#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6 1458#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
1391 u8 agg_flags; 1459 u8 agg_flags;
1392 __le16 sq_prod; 1460 __le16 sq_prod;
1393}; 1461};
diff --git a/include/linux/qed/iwarp_common.h b/include/linux/qed/iwarp_common.h
index b8b3e1cfae90..c6cfd39cd910 100644
--- a/include/linux/qed/iwarp_common.h
+++ b/include/linux/qed/iwarp_common.h
@@ -29,9 +29,12 @@
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31 */
32
32#ifndef __IWARP_COMMON__ 33#ifndef __IWARP_COMMON__
33#define __IWARP_COMMON__ 34#define __IWARP_COMMON__
35
34#include <linux/qed/rdma_common.h> 36#include <linux/qed/rdma_common.h>
37
35/************************/ 38/************************/
36/* IWARP FW CONSTANTS */ 39/* IWARP FW CONSTANTS */
37/************************/ 40/************************/
@@ -40,14 +43,14 @@
40#define IWARP_PASSIVE_MODE 1 43#define IWARP_PASSIVE_MODE 1
41 44
42#define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000) 45#define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000)
43#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000) 46#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
44#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000) 47#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
45#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000) 48#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
46#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000) 49#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
47 50
48#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128) 51#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128)
49#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176) 52#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176)
50 53
51#define IWARP_MAX_QPS (64 * 1024) 54#define IWARP_MAX_QPS (64 * 1024)
52 55
53#endif /* __IWARP_COMMON__ */ 56#endif /* __IWARP_COMMON__ */
diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h
index cc646ca97974..0301499b59ae 100644
--- a/include/linux/qed/qed_if.h
+++ b/include/linux/qed/qed_if.h
@@ -316,16 +316,16 @@ enum qed_int_mode {
316}; 316};
317 317
318struct qed_sb_info { 318struct qed_sb_info {
319 struct status_block *sb_virt; 319 struct status_block *sb_virt;
320 dma_addr_t sb_phys; 320 dma_addr_t sb_phys;
321 u32 sb_ack; /* Last given ack */ 321 u32 sb_ack; /* Last given ack */
322 u16 igu_sb_id; 322 u16 igu_sb_id;
323 void __iomem *igu_addr; 323 void __iomem *igu_addr;
324 u8 flags; 324 u8 flags;
325#define QED_SB_INFO_INIT 0x1 325#define QED_SB_INFO_INIT 0x1
326#define QED_SB_INFO_SETUP 0x2 326#define QED_SB_INFO_SETUP 0x2
327 327
328 struct qed_dev *cdev; 328 struct qed_dev *cdev;
329}; 329};
330 330
331enum qed_dev_type { 331enum qed_dev_type {
diff --git a/include/linux/qed/rdma_common.h b/include/linux/qed/rdma_common.h
index a9b3050f469c..c1a446ebe362 100644
--- a/include/linux/qed/rdma_common.h
+++ b/include/linux/qed/rdma_common.h
@@ -32,28 +32,29 @@
32 32
33#ifndef __RDMA_COMMON__ 33#ifndef __RDMA_COMMON__
34#define __RDMA_COMMON__ 34#define __RDMA_COMMON__
35
35/************************/ 36/************************/
36/* RDMA FW CONSTANTS */ 37/* RDMA FW CONSTANTS */
37/************************/ 38/************************/
38 39
39#define RDMA_RESERVED_LKEY (0) 40#define RDMA_RESERVED_LKEY (0)
40#define RDMA_RING_PAGE_SIZE (0x1000) 41#define RDMA_RING_PAGE_SIZE (0x1000)
41 42
42#define RDMA_MAX_SGE_PER_SQ_WQE (4) 43#define RDMA_MAX_SGE_PER_SQ_WQE (4)
43#define RDMA_MAX_SGE_PER_RQ_WQE (4) 44#define RDMA_MAX_SGE_PER_RQ_WQE (4)
44 45
45#define RDMA_MAX_DATA_SIZE_IN_WQE (0x80000000) 46#define RDMA_MAX_DATA_SIZE_IN_WQE (0x80000000)
46 47
47#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50) 48#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
48#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20) 49#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
49 50
50#define RDMA_MAX_CQS (64 * 1024) 51#define RDMA_MAX_CQS (64 * 1024)
51#define RDMA_MAX_TIDS (128 * 1024 - 1) 52#define RDMA_MAX_TIDS (128 * 1024 - 1)
52#define RDMA_MAX_PDS (64 * 1024) 53#define RDMA_MAX_PDS (64 * 1024)
53 54
54#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 55#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
55#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2 56#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
56#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB 57#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
57 58
58#define RDMA_TASK_TYPE (PROTOCOLID_ROCE) 59#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)
59 60
diff --git a/include/linux/qed/roce_common.h b/include/linux/qed/roce_common.h
index fe6a33e45977..e15e0da71240 100644
--- a/include/linux/qed/roce_common.h
+++ b/include/linux/qed/roce_common.h
@@ -33,13 +33,18 @@
33#ifndef __ROCE_COMMON__ 33#ifndef __ROCE_COMMON__
34#define __ROCE_COMMON__ 34#define __ROCE_COMMON__
35 35
36#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256) 36/************************/
37#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288) 37/* ROCE FW CONSTANTS */
38/************************/
38 39
39#define ROCE_MAX_QPS (32 * 1024) 40#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
40#define ROCE_DCQCN_NP_MAX_QPS (64) 41#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
41#define ROCE_DCQCN_RP_MAX_QPS (64)
42 42
43#define ROCE_MAX_QPS (32 * 1024)
44#define ROCE_DCQCN_NP_MAX_QPS (64)
45#define ROCE_DCQCN_RP_MAX_QPS (64)
46
47/* Affiliated asynchronous events / errors enumeration */
43enum roce_async_events_type { 48enum roce_async_events_type {
44 ROCE_ASYNC_EVENT_NONE = 0, 49 ROCE_ASYNC_EVENT_NONE = 0,
45 ROCE_ASYNC_EVENT_COMM_EST = 1, 50 ROCE_ASYNC_EVENT_COMM_EST = 1,
diff --git a/include/linux/qed/storage_common.h b/include/linux/qed/storage_common.h
index 08df82a096b6..f8c7b408e842 100644
--- a/include/linux/qed/storage_common.h
+++ b/include/linux/qed/storage_common.h
@@ -33,43 +33,53 @@
33#ifndef __STORAGE_COMMON__ 33#ifndef __STORAGE_COMMON__
34#define __STORAGE_COMMON__ 34#define __STORAGE_COMMON__
35 35
36#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2) 36/*********************/
37#define BDQ_NUM_RESOURCES (4) 37/* SCSI CONSTANTS */
38/*********************/
38 39
39#define BDQ_ID_RQ (0) 40#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
40#define BDQ_ID_IMM_DATA (1) 41#define BDQ_NUM_RESOURCES (4)
41#define BDQ_NUM_IDS (2)
42 42
43#define SCSI_NUM_SGES_SLOW_SGL_THR 8 43#define BDQ_ID_RQ (0)
44#define BDQ_ID_IMM_DATA (1)
45#define BDQ_NUM_IDS (2)
44 46
45#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15) 47#define SCSI_NUM_SGES_SLOW_SGL_THR 8
46 48
49#define BDQ_MAX_EXTERNAL_RING_SIZE BIT(15)
50
51/* SCSI buffer descriptor */
47struct scsi_bd { 52struct scsi_bd {
48 struct regpair address; 53 struct regpair address;
49 struct regpair opaque; 54 struct regpair opaque;
50}; 55};
51 56
57/* Scsi Drv BDQ struct */
52struct scsi_bdq_ram_drv_data { 58struct scsi_bdq_ram_drv_data {
53 __le16 external_producer; 59 __le16 external_producer;
54 __le16 reserved0[3]; 60 __le16 reserved0[3];
55}; 61};
56 62
63/* SCSI SGE entry */
57struct scsi_sge { 64struct scsi_sge {
58 struct regpair sge_addr; 65 struct regpair sge_addr;
59 __le32 sge_len; 66 __le32 sge_len;
60 __le32 reserved; 67 __le32 reserved;
61}; 68};
62 69
70/* Cached SGEs section */
63struct scsi_cached_sges { 71struct scsi_cached_sges {
64 struct scsi_sge sge[4]; 72 struct scsi_sge sge[4];
65}; 73};
66 74
75/* Scsi Drv CMDQ struct */
67struct scsi_drv_cmdq { 76struct scsi_drv_cmdq {
68 __le16 cmdq_cons; 77 __le16 cmdq_cons;
69 __le16 reserved0; 78 __le16 reserved0;
70 __le32 reserved1; 79 __le32 reserved1;
71}; 80};
72 81
82/* Common SCSI init params passed by driver to FW in function init ramrod */
73struct scsi_init_func_params { 83struct scsi_init_func_params {
74 __le16 num_tasks; 84 __le16 num_tasks;
75 u8 log_page_size; 85 u8 log_page_size;
@@ -77,6 +87,7 @@ struct scsi_init_func_params {
77 u8 reserved2[12]; 87 u8 reserved2[12];
78}; 88};
79 89
90/* SCSI RQ/CQ/CMDQ firmware function init parameters */
80struct scsi_init_func_queues { 91struct scsi_init_func_queues {
81 struct regpair glbl_q_params_addr; 92 struct regpair glbl_q_params_addr;
82 __le16 rq_buffer_size; 93 __le16 rq_buffer_size;
@@ -84,14 +95,14 @@ struct scsi_init_func_queues {
84 __le16 cmdq_num_entries; 95 __le16 cmdq_num_entries;
85 u8 bdq_resource_id; 96 u8 bdq_resource_id;
86 u8 q_validity; 97 u8 q_validity;
87#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1 98#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
88#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0 99#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
89#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1 100#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
90#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1 101#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
91#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1 102#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
92#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2 103#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
93#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F 104#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
94#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3 105#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
95 u8 num_queues; 106 u8 num_queues;
96 u8 queue_relative_offset; 107 u8 queue_relative_offset;
97 u8 cq_sb_pi; 108 u8 cq_sb_pi;
@@ -107,16 +118,19 @@ struct scsi_init_func_queues {
107 __le32 reserved1; 118 __le32 reserved1;
108}; 119};
109 120
121/* Scsi Drv BDQ Data struct (2 BDQ IDs: 0 - RQ, 1 - Immediate Data) */
110struct scsi_ram_per_bdq_resource_drv_data { 122struct scsi_ram_per_bdq_resource_drv_data {
111 struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS]; 123 struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
112}; 124};
113 125
126/* SCSI SGL types */
114enum scsi_sgl_mode { 127enum scsi_sgl_mode {
115 SCSI_TX_SLOW_SGL, 128 SCSI_TX_SLOW_SGL,
116 SCSI_FAST_SGL, 129 SCSI_FAST_SGL,
117 MAX_SCSI_SGL_MODE 130 MAX_SCSI_SGL_MODE
118}; 131};
119 132
133/* SCSI SGL parameters */
120struct scsi_sgl_params { 134struct scsi_sgl_params {
121 struct regpair sgl_addr; 135 struct regpair sgl_addr;
122 __le32 sgl_total_length; 136 __le32 sgl_total_length;
@@ -126,6 +140,7 @@ struct scsi_sgl_params {
126 u8 reserved; 140 u8 reserved;
127}; 141};
128 142
143/* SCSI terminate connection params */
129struct scsi_terminate_extra_params { 144struct scsi_terminate_extra_params {
130 __le16 unsolicited_cq_count; 145 __le16 unsolicited_cq_count;
131 __le16 cmdq_count; 146 __le16 cmdq_count;
diff --git a/include/linux/qed/tcp_common.h b/include/linux/qed/tcp_common.h
index dbf7a43c3e1f..65b95fd25101 100644
--- a/include/linux/qed/tcp_common.h
+++ b/include/linux/qed/tcp_common.h
@@ -33,8 +33,13 @@
33#ifndef __TCP_COMMON__ 33#ifndef __TCP_COMMON__
34#define __TCP_COMMON__ 34#define __TCP_COMMON__
35 35
36#define TCP_INVALID_TIMEOUT_VAL -1 36/********************/
37/* TCP FW CONSTANTS */
38/********************/
37 39
40#define TCP_INVALID_TIMEOUT_VAL -1
41
42/* OOO opaque data received from LL2 */
38struct ooo_opaque { 43struct ooo_opaque {
39 __le32 cid; 44 __le32 cid;
40 u8 drop_isle; 45 u8 drop_isle;
@@ -43,25 +48,29 @@ struct ooo_opaque {
43 u8 ooo_isle; 48 u8 ooo_isle;
44}; 49};
45 50
51/* tcp connect mode enum */
46enum tcp_connect_mode { 52enum tcp_connect_mode {
47 TCP_CONNECT_ACTIVE, 53 TCP_CONNECT_ACTIVE,
48 TCP_CONNECT_PASSIVE, 54 TCP_CONNECT_PASSIVE,
49 MAX_TCP_CONNECT_MODE 55 MAX_TCP_CONNECT_MODE
50}; 56};
51 57
58/* tcp function init parameters */
52struct tcp_init_params { 59struct tcp_init_params {
53 __le32 two_msl_timer; 60 __le32 two_msl_timer;
54 __le16 tx_sws_timer; 61 __le16 tx_sws_timer;
55 u8 maxfinrt; 62 u8 max_fin_rt;
56 u8 reserved[9]; 63 u8 reserved[9];
57}; 64};
58 65
66/* tcp IPv4/IPv6 enum */
59enum tcp_ip_version { 67enum tcp_ip_version {
60 TCP_IPV4, 68 TCP_IPV4,
61 TCP_IPV6, 69 TCP_IPV6,
62 MAX_TCP_IP_VERSION 70 MAX_TCP_IP_VERSION
63}; 71};
64 72
73/* tcp offload parameters */
65struct tcp_offload_params { 74struct tcp_offload_params {
66 __le16 local_mac_addr_lo; 75 __le16 local_mac_addr_lo;
67 __le16 local_mac_addr_mid; 76 __le16 local_mac_addr_mid;
@@ -71,22 +80,22 @@ struct tcp_offload_params {
71 __le16 remote_mac_addr_hi; 80 __le16 remote_mac_addr_hi;
72 __le16 vlan_id; 81 __le16 vlan_id;
73 u8 flags; 82 u8 flags;
74#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1 83#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
75#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0 84#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
76#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1 85#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
77#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1 86#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
78#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1 87#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
79#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2 88#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
80#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1 89#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
81#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3 90#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
82#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1 91#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
83#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4 92#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
84#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1 93#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
85#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5 94#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
86#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1 95#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
87#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6 96#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
88#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1 97#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
89#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7 98#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
90 u8 ip_version; 99 u8 ip_version;
91 __le32 remote_ip[4]; 100 __le32 remote_ip[4];
92 __le32 local_ip[4]; 101 __le32 local_ip[4];
@@ -132,6 +141,7 @@ struct tcp_offload_params {
132 __le32 reserved3[2]; 141 __le32 reserved3[2];
133}; 142};
134 143
144/* tcp offload parameters */
135struct tcp_offload_params_opt2 { 145struct tcp_offload_params_opt2 {
136 __le16 local_mac_addr_lo; 146 __le16 local_mac_addr_lo;
137 __le16 local_mac_addr_mid; 147 __le16 local_mac_addr_mid;
@@ -141,14 +151,14 @@ struct tcp_offload_params_opt2 {
141 __le16 remote_mac_addr_hi; 151 __le16 remote_mac_addr_hi;
142 __le16 vlan_id; 152 __le16 vlan_id;
143 u8 flags; 153 u8 flags;
144#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1 154#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
145#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0 155#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
146#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1 156#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
147#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1 157#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
148#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1 158#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
149#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2 159#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
150#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F 160#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
151#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3 161#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
152 u8 ip_version; 162 u8 ip_version;
153 __le32 remote_ip[4]; 163 __le32 remote_ip[4];
154 __le32 local_ip[4]; 164 __le32 local_ip[4];
@@ -166,6 +176,7 @@ struct tcp_offload_params_opt2 {
166 __le32 reserved1[22]; 176 __le32 reserved1[22];
167}; 177};
168 178
179/* tcp IPv4/IPv6 enum */
169enum tcp_seg_placement_event { 180enum tcp_seg_placement_event {
170 TCP_EVENT_ADD_PEN, 181 TCP_EVENT_ADD_PEN,
171 TCP_EVENT_ADD_NEW_ISLE, 182 TCP_EVENT_ADD_NEW_ISLE,
@@ -177,40 +188,41 @@ enum tcp_seg_placement_event {
177 MAX_TCP_SEG_PLACEMENT_EVENT 188 MAX_TCP_SEG_PLACEMENT_EVENT
178}; 189};
179 190
191/* tcp init parameters */
180struct tcp_update_params { 192struct tcp_update_params {
181 __le16 flags; 193 __le16 flags;
182#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1 194#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
183#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0 195#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
184#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1 196#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
185#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1 197#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
186#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1 198#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
187#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2 199#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
188#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1 200#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
189#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3 201#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
190#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1 202#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
191#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4 203#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
192#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1 204#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
193#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5 205#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
194#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1 206#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
195#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6 207#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
196#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1 208#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
197#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7 209#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
198#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1 210#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
199#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8 211#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
200#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1 212#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
201#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9 213#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
202#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1 214#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
203#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10 215#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
204#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1 216#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
205#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11 217#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
206#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1 218#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
207#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12 219#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
208#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1 220#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
209#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13 221#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
210#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1 222#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
211#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14 223#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
212#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1 224#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
213#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15 225#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
214 __le16 remote_mac_addr_lo; 226 __le16 remote_mac_addr_lo;
215 __le16 remote_mac_addr_mid; 227 __le16 remote_mac_addr_mid;
216 __le16 remote_mac_addr_hi; 228 __le16 remote_mac_addr_hi;
@@ -226,6 +238,7 @@ struct tcp_update_params {
226 u8 reserved1[7]; 238 u8 reserved1[7];
227}; 239};
228 240
241/* toe upload parameters */
229struct tcp_upload_params { 242struct tcp_upload_params {
230 __le32 rcv_next; 243 __le32 rcv_next;
231 __le32 snd_una; 244 __le32 snd_una;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 11:54:41 -0500