diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2014-03-24 06:19:35 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 12:17:13 -0400 |
| commit | 9a1724c7506bfa7d3d9dcab13f83e9e6446929f9 (patch) | |
| tree | ed3ead9dc65f967f2afd0ed9683cfdfbcc407f08 | |
| parent | cd217546602dbfe96c3f8e8025eb750fadf1ab4f (diff) | |
MIPS: CPC: Use __raw_ memory access functions
The CPC registers use native endianness, so using plain readl & writel
will produce incorrect results on big endian systems.
Reported-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Reported-by: Keng Koh <keng.koh@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6657/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/mips-cpc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h index fb78935010a3..988507e46d42 100644 --- a/arch/mips/include/asm/mips-cpc.h +++ b/arch/mips/include/asm/mips-cpc.h | |||
| @@ -75,13 +75,13 @@ static inline bool mips_cpc_present(void) | |||
| 75 | #define BUILD_CPC_R_(name, off) \ | 75 | #define BUILD_CPC_R_(name, off) \ |
| 76 | static inline u32 read_cpc_##name(void) \ | 76 | static inline u32 read_cpc_##name(void) \ |
| 77 | { \ | 77 | { \ |
| 78 | return readl(mips_cpc_base + (off)); \ | 78 | return __raw_readl(mips_cpc_base + (off)); \ |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | #define BUILD_CPC__W(name, off) \ | 81 | #define BUILD_CPC__W(name, off) \ |
| 82 | static inline void write_cpc_##name(u32 value) \ | 82 | static inline void write_cpc_##name(u32 value) \ |
| 83 | { \ | 83 | { \ |
| 84 | writel(value, mips_cpc_base + (off)); \ | 84 | __raw_writel(value, mips_cpc_base + (off)); \ |
| 85 | } | 85 | } |
| 86 | 86 | ||
| 87 | #define BUILD_CPC_RW(name, off) \ | 87 | #define BUILD_CPC_RW(name, off) \ |
