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authorMattias Nilsson <mattias.i.nilsson@stericsson.com>2011-08-12 04:28:10 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2011-10-24 08:09:18 -0400
commit73180f85f4ffbb66843f8248811b2ade29b22df2 (patch)
tree26b48bd3369e2f38d741bae92ceef25e8da35948
parentfea799e3d3ab84ac675de7e48a13a79fb76b6e63 (diff)
mfd: Move to the new db500 PRCMU API
Now that we have a shared API between the DB8500 and DB5500 PRCMU's, switch to using this neutral API instead. We delete the parts of db8500-prcmu.h that is now PRCMU-neutral, and calls will be diverted to respective driver. Common registers are in dbx500-prcmu-regs.h and common accessors and defines in <linux/mfd/dbx500-prcmu.h> This way we get a a lot more abstraction and code reuse. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat
-rw-r--r--arch/arm/mach-ux500/cpu.c2
-rw-r--r--drivers/cpufreq/db8500-cpufreq.c2
-rw-r--r--drivers/mfd/db5500-prcmu-regs.h115
-rw-r--r--drivers/mfd/db5500-prcmu.c22
-rw-r--r--drivers/mfd/db8500-prcmu.c46
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h (renamed from drivers/mfd/db8500-prcmu-regs.h)0
-rw-r--r--drivers/regulator/db8500-prcmu.c2
-rw-r--r--include/linux/mfd/db5500-prcmu.h102
-rw-r--r--include/linux/mfd/db8500-prcmu.h368
-rw-r--r--include/linux/mfd/dbx500-prcmu.h8
10 files changed, 211 insertions, 456 deletions
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1da23bb87c16..bb5653993ca2 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -53,7 +53,7 @@ void __init ux500_init_irq(void)
53 if (cpu_is_u5500()) 53 if (cpu_is_u5500())
54 db5500_prcmu_early_init(); 54 db5500_prcmu_early_init();
55 if (cpu_is_u8500()) 55 if (cpu_is_u8500())
56 prcmu_early_init(); 56 db8500_prcmu_early_init();
57 clk_init(); 57 clk_init();
58} 58}
59 59
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
index d90456a809f9..8e89dcf9d94d 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -12,7 +12,7 @@
12#include <linux/cpufreq.h> 12#include <linux/cpufreq.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/mfd/db8500-prcmu.h> 15#include <linux/mfd/dbx500-prcmu.h>
16#include <mach/id.h> 16#include <mach/id.h>
17 17
18static struct cpufreq_frequency_table freq_table[] = { 18static struct cpufreq_frequency_table freq_table[] = {
diff --git a/drivers/mfd/db5500-prcmu-regs.h b/drivers/mfd/db5500-prcmu-regs.h
deleted file mode 100644
index 9a8e9e4ddd33..000000000000
--- a/drivers/mfd/db5500-prcmu-regs.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * License Terms: GNU General Public License v2
9 *
10 * PRCM Unit registers
11 */
12
13#ifndef __MACH_PRCMU_REGS_H
14#define __MACH_PRCMU_REGS_H
15
16#include <mach/hardware.h>
17
18#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
19#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
20#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
21
22#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8)
23#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
24
25#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
26#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1
27
28#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
29#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
30#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
31
32#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
33#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
34#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
35#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
36#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
37
38/* ARM WFI Standby signal register */
39#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
40#define PRCM_IOCR (_PRCMU_BASE + 0x310)
41#define PRCM_IOCR_IOFORCE 0x1
42
43/* CPU mailbox registers */
44#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
45#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
46#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
47
48/* Dual A9 core interrupt management unit registers */
49#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
50#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
51
52#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
53#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
54#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
55#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
56#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
57#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
58#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
59#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
60#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
61#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
62
63#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
64#define ARM_WAKEUP_MODEM 0x1
65
66#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
67#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
68#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
69
70#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
71#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
72#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
73#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
74#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
75#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
76#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
77#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
78
79/* System reset register */
80#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
81
82/* Level shifter and clamp control registers */
83#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
84#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
85
86/* PRCMU clock/PLL/reset registers */
87#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
88#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
89#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
90#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
91#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
92#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
93#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
94#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
95#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
96#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
97#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
98#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
99#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC)
100
101/* ePOD and memory power signal control registers */
102#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
103#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
104
105/* Debug power control unit registers */
106#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
107
108/* Miscellaneous unit registers */
109#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
110#define PRCM_GPIOCR (_PRCMU_BASE + 0x138)
111#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
112#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
113
114
115#endif /* __MACH_PRCMU__REGS_H */
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
index 9dbb3cab4a6f..dc215878835a 100644
--- a/drivers/mfd/db5500-prcmu.c
+++ b/drivers/mfd/db5500-prcmu.c
@@ -20,11 +20,11 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/bitops.h> 21#include <linux/bitops.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/mfd/db5500-prcmu.h> 23#include <linux/mfd/dbx500-prcmu.h>
24#include <mach/hardware.h> 24#include <mach/hardware.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
26#include <mach/db5500-regs.h> 26#include <mach/db5500-regs.h>
27#include "db5500-prcmu-regs.h" 27#include "dbx500-prcmu-regs.h"
28 28
29#define _PRCM_MB_HEADER (tcdm_base + 0xFE8) 29#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
30#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0) 30#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
@@ -315,31 +315,31 @@ static bool read_mailbox_0(void)
315 r = false; 315 r = false;
316 break; 316 break;
317 } 317 }
318 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); 318 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
319 return r; 319 return r;
320} 320}
321 321
322static bool read_mailbox_1(void) 322static bool read_mailbox_1(void)
323{ 323{
324 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); 324 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
325 return false; 325 return false;
326} 326}
327 327
328static bool read_mailbox_2(void) 328static bool read_mailbox_2(void)
329{ 329{
330 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR); 330 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
331 return false; 331 return false;
332} 332}
333 333
334static bool read_mailbox_3(void) 334static bool read_mailbox_3(void)
335{ 335{
336 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR); 336 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
337 return false; 337 return false;
338} 338}
339 339
340static bool read_mailbox_4(void) 340static bool read_mailbox_4(void)
341{ 341{
342 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR); 342 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
343 return false; 343 return false;
344} 344}
345 345
@@ -360,19 +360,19 @@ static bool read_mailbox_5(void)
360 print_unknown_header_warning(5, header); 360 print_unknown_header_warning(5, header);
361 break; 361 break;
362 } 362 }
363 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR); 363 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
364 return false; 364 return false;
365} 365}
366 366
367static bool read_mailbox_6(void) 367static bool read_mailbox_6(void)
368{ 368{
369 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR); 369 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
370 return false; 370 return false;
371} 371}
372 372
373static bool read_mailbox_7(void) 373static bool read_mailbox_7(void)
374{ 374{
375 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR); 375 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
376 return false; 376 return false;
377} 377}
378 378
@@ -434,7 +434,7 @@ int __init db5500_prcmu_init(void)
434 return -ENODEV; 434 return -ENODEV;
435 435
436 /* Clean up the mailbox interrupts after pre-kernel code. */ 436 /* Clean up the mailbox interrupts after pre-kernel code. */
437 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR); 437 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
438 438
439 r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler, 439 r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
440 prcmu_irq_thread_fn, 0, "prcmu", NULL); 440 prcmu_irq_thread_fn, 0, "prcmu", NULL);
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index e2c4a26a9eb1..cea814509a6f 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -27,14 +27,14 @@
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/uaccess.h> 28#include <linux/uaccess.h>
29#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
30#include <linux/mfd/db8500-prcmu.h> 30#include <linux/mfd/dbx500-prcmu.h>
31#include <linux/regulator/db8500-prcmu.h> 31#include <linux/regulator/db8500-prcmu.h>
32#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/irqs.h> 34#include <mach/irqs.h>
35#include <mach/db8500-regs.h> 35#include <mach/db8500-regs.h>
36#include <mach/id.h> 36#include <mach/id.h>
37#include "db8500-prcmu-regs.h" 37#include "dbx500-prcmu-regs.h"
38 38
39/* Offset for the firmware version within the TCPM */ 39/* Offset for the firmware version within the TCPM */
40#define PRCMU_FW_VERSION_OFFSET 0xA4 40#define PRCMU_FW_VERSION_OFFSET 0xA4
@@ -507,7 +507,7 @@ static struct {
507} prcmu_version; 507} prcmu_version;
508 508
509 509
510int prcmu_enable_dsipll(void) 510int db8500_prcmu_enable_dsipll(void)
511{ 511{
512 int i; 512 int i;
513 unsigned int plldsifreq; 513 unsigned int plldsifreq;
@@ -542,7 +542,7 @@ int prcmu_enable_dsipll(void)
542 return 0; 542 return 0;
543} 543}
544 544
545int prcmu_disable_dsipll(void) 545int db8500_prcmu_disable_dsipll(void)
546{ 546{
547 /* Disable dsi pll */ 547 /* Disable dsi pll */
548 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); 548 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
@@ -551,7 +551,7 @@ int prcmu_disable_dsipll(void)
551 return 0; 551 return 0;
552} 552}
553 553
554int prcmu_set_display_clocks(void) 554int db8500_prcmu_set_display_clocks(void)
555{ 555{
556 unsigned long flags; 556 unsigned long flags;
557 unsigned int dsiclk; 557 unsigned int dsiclk;
@@ -734,7 +734,7 @@ unlock_and_return:
734 return r; 734 return r;
735} 735}
736 736
737int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) 737int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
738{ 738{
739 unsigned long flags; 739 unsigned long flags;
740 740
@@ -791,7 +791,7 @@ static void config_wakeups(void)
791 last_abb_events = abb_events; 791 last_abb_events = abb_events;
792} 792}
793 793
794void prcmu_enable_wakeups(u32 wakeups) 794void db8500_prcmu_enable_wakeups(u32 wakeups)
795{ 795{
796 unsigned long flags; 796 unsigned long flags;
797 u32 bits; 797 u32 bits;
@@ -812,7 +812,7 @@ void prcmu_enable_wakeups(u32 wakeups)
812 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 812 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
813} 813}
814 814
815void prcmu_config_abb_event_readout(u32 abb_events) 815void db8500_prcmu_config_abb_event_readout(u32 abb_events)
816{ 816{
817 unsigned long flags; 817 unsigned long flags;
818 818
@@ -824,7 +824,7 @@ void prcmu_config_abb_event_readout(u32 abb_events)
824 spin_unlock_irqrestore(&mb0_transfer.lock, flags); 824 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
825} 825}
826 826
827void prcmu_get_abb_event_buffer(void __iomem **buf) 827void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
828{ 828{
829 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) 829 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
830 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); 830 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
@@ -833,13 +833,13 @@ void prcmu_get_abb_event_buffer(void __iomem **buf)
833} 833}
834 834
835/** 835/**
836 * prcmu_set_arm_opp - set the appropriate ARM OPP 836 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
837 * @opp: The new ARM operating point to which transition is to be made 837 * @opp: The new ARM operating point to which transition is to be made
838 * Returns: 0 on success, non-zero on failure 838 * Returns: 0 on success, non-zero on failure
839 * 839 *
840 * This function sets the the operating point of the ARM. 840 * This function sets the the operating point of the ARM.
841 */ 841 */
842int prcmu_set_arm_opp(u8 opp) 842int db8500_prcmu_set_arm_opp(u8 opp)
843{ 843{
844 int r; 844 int r;
845 845
@@ -870,11 +870,11 @@ int prcmu_set_arm_opp(u8 opp)
870} 870}
871 871
872/** 872/**
873 * prcmu_get_arm_opp - get the current ARM OPP 873 * db8500_prcmu_get_arm_opp - get the current ARM OPP
874 * 874 *
875 * Returns: the current ARM OPP 875 * Returns: the current ARM OPP
876 */ 876 */
877int prcmu_get_arm_opp(void) 877int db8500_prcmu_get_arm_opp(void)
878{ 878{
879 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); 879 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
880} 880}
@@ -1024,14 +1024,14 @@ int prcmu_release_usb_wakeup_state(void)
1024} 1024}
1025 1025
1026/** 1026/**
1027 * prcmu_set_epod - set the state of a EPOD (power domain) 1027 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1028 * @epod_id: The EPOD to set 1028 * @epod_id: The EPOD to set
1029 * @epod_state: The new EPOD state 1029 * @epod_state: The new EPOD state
1030 * 1030 *
1031 * This function sets the state of a EPOD (power domain). It may not be called 1031 * This function sets the state of a EPOD (power domain). It may not be called
1032 * from interrupt context. 1032 * from interrupt context.
1033 */ 1033 */
1034int prcmu_set_epod(u16 epod_id, u8 epod_state) 1034int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1035{ 1035{
1036 int r = 0; 1036 int r = 0;
1037 bool ram_retention = false; 1037 bool ram_retention = false;
@@ -1221,14 +1221,14 @@ static int request_reg_clock(u8 clock, bool enable)
1221} 1221}
1222 1222
1223/** 1223/**
1224 * prcmu_request_clock() - Request for a clock to be enabled or disabled. 1224 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1225 * @clock: The clock for which the request is made. 1225 * @clock: The clock for which the request is made.
1226 * @enable: Whether the clock should be enabled (true) or disabled (false). 1226 * @enable: Whether the clock should be enabled (true) or disabled (false).
1227 * 1227 *
1228 * This function should only be used by the clock implementation. 1228 * This function should only be used by the clock implementation.
1229 * Do not use it from any other place! 1229 * Do not use it from any other place!
1230 */ 1230 */
1231int prcmu_request_clock(u8 clock, bool enable) 1231int db8500_prcmu_request_clock(u8 clock, bool enable)
1232{ 1232{
1233 if (clock < PRCMU_NUM_REG_CLOCKS) 1233 if (clock < PRCMU_NUM_REG_CLOCKS)
1234 return request_reg_clock(clock, enable); 1234 return request_reg_clock(clock, enable);
@@ -1240,7 +1240,7 @@ int prcmu_request_clock(u8 clock, bool enable)
1240 return -EINVAL; 1240 return -EINVAL;
1241} 1241}
1242 1242
1243int prcmu_config_esram0_deep_sleep(u8 state) 1243int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1244{ 1244{
1245 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || 1245 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1246 (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) 1246 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
@@ -1515,18 +1515,18 @@ unlock_and_return:
1515 mutex_unlock(&mb0_transfer.ac_wake_lock); 1515 mutex_unlock(&mb0_transfer.ac_wake_lock);
1516} 1516}
1517 1517
1518bool prcmu_is_ac_wake_requested(void) 1518bool db8500_prcmu_is_ac_wake_requested(void)
1519{ 1519{
1520 return (atomic_read(&ac_wake_req_state) != 0); 1520 return (atomic_read(&ac_wake_req_state) != 0);
1521} 1521}
1522 1522
1523/** 1523/**
1524 * prcmu_system_reset - System reset 1524 * db8500_prcmu_system_reset - System reset
1525 * 1525 *
1526 * Saves the reset reason code and then sets the APE_SOFRST register which 1526 * Saves the reset reason code and then sets the APE_SOFTRST register which
1527 * fires interrupt to fw 1527 * fires interrupt to fw
1528 */ 1528 */
1529void prcmu_system_reset(u16 reset_code) 1529void db8500_prcmu_system_reset(u16 reset_code)
1530{ 1530{
1531 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); 1531 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
1532 writel(1, PRCM_APE_SOFTRST); 1532 writel(1, PRCM_APE_SOFTRST);
@@ -1782,7 +1782,7 @@ static struct irq_chip prcmu_irq_chip = {
1782 .irq_unmask = prcmu_irq_unmask, 1782 .irq_unmask = prcmu_irq_unmask,
1783}; 1783};
1784 1784
1785void __init prcmu_early_init(void) 1785void __init db8500_prcmu_early_init(void)
1786{ 1786{
1787 unsigned int i; 1787 unsigned int i;
1788 1788
diff --git a/drivers/mfd/db8500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index ec22e9f15d32..ec22e9f15d32 100644
--- a/drivers/mfd/db8500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
diff --git a/drivers/regulator/db8500-prcmu.c b/drivers/regulator/db8500-prcmu.c
index 2bb8f451cc06..2d014a144365 100644
--- a/drivers/regulator/db8500-prcmu.c
+++ b/drivers/regulator/db8500-prcmu.c
@@ -13,7 +13,7 @@
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/mfd/db8500-prcmu.h> 16#include <linux/mfd/dbx500-prcmu.h>
17#include <linux/regulator/driver.h> 17#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
19#include <linux/regulator/db8500-prcmu.h> 19#include <linux/regulator/db8500-prcmu.h>
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
index f0977986402c..9890687f582d 100644
--- a/include/linux/mfd/db5500-prcmu.h
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -5,21 +5,35 @@
5 * 5 *
6 * U5500 PRCMU API. 6 * U5500 PRCMU API.
7 */ 7 */
8#ifndef __MACH_PRCMU_U5500_H 8#ifndef __MFD_DB5500_PRCMU_H
9#define __MACH_PRCMU_U5500_H 9#define __MFD_DB5500_PRCMU_H
10 10
11#ifdef CONFIG_UX500_SOC_DB5500 11#ifdef CONFIG_MFD_DB5500_PRCMU
12 12
13void db5500_prcmu_early_init(void); 13void db5500_prcmu_early_init(void);
14 14int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state);
15int db5500_prcmu_set_display_clocks(void);
16int db5500_prcmu_disable_dsipll(void);
17int db5500_prcmu_enable_dsipll(void);
15int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 18int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
16int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 19int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
20void db5500_prcmu_enable_wakeups(u32 wakeups);
21int db5500_prcmu_request_clock(u8 clock, bool enable);
22void db5500_prcmu_config_abb_event_readout(u32 abb_events);
23void db5500_prcmu_get_abb_event_buffer(void __iomem **buf);
24int prcmu_resetout(u8 resoutn, u8 state);
25int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
26 bool keep_ap_pll);
27int db5500_prcmu_config_esram0_deep_sleep(u8 state);
28void db5500_prcmu_system_reset(u16 reset_code);
29u16 db5500_prcmu_get_reset_code(void);
30bool db5500_prcmu_is_ac_wake_requested(void);
31int db5500_prcmu_set_arm_opp(u8 opp);
32int db5500_prcmu_get_arm_opp(void);
17 33
18#else /* !CONFIG_UX500_SOC_DB5500 */ 34#else /* !CONFIG_UX500_SOC_DB5500 */
19 35
20static inline void db5500_prcmu_early_init(void) 36static inline void db5500_prcmu_early_init(void) {}
21{
22}
23 37
24static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 38static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
25{ 39{
@@ -31,15 +45,75 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
31 return -ENOSYS; 45 return -ENOSYS;
32} 46}
33 47
34#endif /* CONFIG_UX500_SOC_DB5500 */ 48static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
49{
50 return 0;
51}
52
53static inline int db5500_prcmu_set_display_clocks(void)
54{
55 return 0;
56}
57
58static inline int db5500_prcmu_disable_dsipll(void)
59{
60 return 0;
61}
62
63static inline int db5500_prcmu_enable_dsipll(void)
64{
65 return 0;
66}
35 67
36static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events) 68static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
37{ 69{
38#ifdef CONFIG_MACH_U5500_SIMULATOR
39 return 0; 70 return 0;
40#else
41 return -1;
42#endif
43} 71}
44 72
45#endif /* __MACH_PRCMU_U5500_H */ 73static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
74
75static inline int prcmu_resetout(u8 resoutn, u8 state)
76{
77 return 0;
78}
79
80static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
81{
82 return 0;
83}
84
85static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
86static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
87
88static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
89 bool keep_ap_pll)
90{
91 return 0;
92}
93
94static inline void db5500_prcmu_system_reset(u16 reset_code) {}
95
96static inline u16 db5500_prcmu_get_reset_code(void)
97{
98 return 0;
99}
100
101static inline bool db5500_prcmu_is_ac_wake_requested(void)
102{
103 return 0;
104}
105
106static inline int db5500_prcmu_set_arm_opp(u8 opp)
107{
108 return 0;
109}
110
111static inline int db5500_prcmu_get_arm_opp(void)
112{
113 return 0;
114}
115
116
117#endif /* CONFIG_MFD_DB5500_PRCMU */
118
119#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 917dbcab701c..60d27f7bfc1f 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -11,7 +11,6 @@
11#define __MFD_DB8500_PRCMU_H 11#define __MFD_DB8500_PRCMU_H
12 12
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/notifier.h>
15 14
16/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ 15/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
17 16
@@ -133,7 +132,7 @@ enum ap_pwrst {
133 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle 132 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
134 */ 133 */
135enum ap_pwrst_trans { 134enum ap_pwrst_trans {
136 NO_TRANSITION = 0x00, 135 PRCMU_AP_NO_CHANGE = 0x00,
137 APEXECUTE_TO_APSLEEP = 0x01, 136 APEXECUTE_TO_APSLEEP = 0x01,
138 APIDLE_TO_APSLEEP = 0x02, /* To be removed */ 137 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
139 PRCMU_AP_SLEEP = 0x01, 138 PRCMU_AP_SLEEP = 0x01,
@@ -146,54 +145,6 @@ enum ap_pwrst_trans {
146}; 145};
147 146
148/** 147/**
149 * enum ddr_pwrst - DDR power states definition
150 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
151 * @DDR_PWR_STATE_ON:
152 * @DDR_PWR_STATE_OFFLOWLAT:
153 * @DDR_PWR_STATE_OFFHIGHLAT:
154 */
155enum ddr_pwrst {
156 DDR_PWR_STATE_UNCHANGED = 0x00,
157 DDR_PWR_STATE_ON = 0x01,
158 DDR_PWR_STATE_OFFLOWLAT = 0x02,
159 DDR_PWR_STATE_OFFHIGHLAT = 0x03
160};
161
162/**
163 * enum arm_opp - ARM OPP states definition
164 * @ARM_OPP_INIT:
165 * @ARM_NO_CHANGE: The ARM operating point is unchanged
166 * @ARM_100_OPP: The new ARM operating point is arm100opp
167 * @ARM_50_OPP: The new ARM operating point is arm50opp
168 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
169 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
170 * @ARM_EXTCLK: The new ARM operating point is armExtClk
171 */
172enum arm_opp {
173 ARM_OPP_INIT = 0x00,
174 ARM_NO_CHANGE = 0x01,
175 ARM_100_OPP = 0x02,
176 ARM_50_OPP = 0x03,
177 ARM_MAX_OPP = 0x04,
178 ARM_MAX_FREQ100OPP = 0x05,
179 ARM_EXTCLK = 0x07
180};
181
182/**
183 * enum ape_opp - APE OPP states definition
184 * @APE_OPP_INIT:
185 * @APE_NO_CHANGE: The APE operating point is unchanged
186 * @APE_100_OPP: The new APE operating point is ape100opp
187 * @APE_50_OPP: 50%
188 */
189enum ape_opp {
190 APE_OPP_INIT = 0x00,
191 APE_NO_CHANGE = 0x01,
192 APE_100_OPP = 0x02,
193 APE_50_OPP = 0x03
194};
195
196/**
197 * enum hw_acc_state - State definition for hardware accelerator 148 * enum hw_acc_state - State definition for hardware accelerator
198 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged 149 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
199 * @HW_OFF: The hardware accelerator must be switched off 150 * @HW_OFF: The hardware accelerator must be switched off
@@ -469,26 +420,6 @@ enum auto_enable {
469 420
470/* End of file previously known as prcmu-fw-defs_v1.h */ 421/* End of file previously known as prcmu-fw-defs_v1.h */
471 422
472/* PRCMU Wakeup defines */
473enum prcmu_wakeup_index {
474 PRCMU_WAKEUP_INDEX_RTC,
475 PRCMU_WAKEUP_INDEX_RTT0,
476 PRCMU_WAKEUP_INDEX_RTT1,
477 PRCMU_WAKEUP_INDEX_HSI0,
478 PRCMU_WAKEUP_INDEX_HSI1,
479 PRCMU_WAKEUP_INDEX_USB,
480 PRCMU_WAKEUP_INDEX_ABB,
481 PRCMU_WAKEUP_INDEX_ABB_FIFO,
482 PRCMU_WAKEUP_INDEX_ARM,
483 NUM_PRCMU_WAKEUP_INDICES
484};
485#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
486
487/* PRCMU QoS APE OPP class */
488#define PRCMU_QOS_APE_OPP 1
489#define PRCMU_QOS_DDR_OPP 2
490#define PRCMU_QOS_DEFAULT_VALUE -1
491
492/** 423/**
493 * enum hw_acc_dev - enum for hw accelerators 424 * enum hw_acc_dev - enum for hw accelerators
494 * @HW_ACC_SVAMMDSP: for SVAMMDSP 425 * @HW_ACC_SVAMMDSP: for SVAMMDSP
@@ -527,64 +458,6 @@ enum hw_acc_dev {
527}; 458};
528 459
529/* 460/*
530 * Ids for all EPODs (power domains)
531 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
532 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
533 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
534 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
535 * - EPOD_ID_SGA: power domain for SGA
536 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
537 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
538 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
539 * - NUM_EPOD_ID: number of power domains
540 */
541#define EPOD_ID_SVAMMDSP 0
542#define EPOD_ID_SVAPIPE 1
543#define EPOD_ID_SIAMMDSP 2
544#define EPOD_ID_SIAPIPE 3
545#define EPOD_ID_SGA 4
546#define EPOD_ID_B2R2_MCDE 5
547#define EPOD_ID_ESRAM12 6
548#define EPOD_ID_ESRAM34 7
549#define NUM_EPOD_ID 8
550
551/*
552 * state definition for EPOD (power domain)
553 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
554 * - EPOD_STATE_OFF: The EPOD is switched off
555 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
556 * retention
557 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
558 * - EPOD_STATE_ON: Same as above, but with clock enabled
559 */
560#define EPOD_STATE_NO_CHANGE 0x00
561#define EPOD_STATE_OFF 0x01
562#define EPOD_STATE_RAMRET 0x02
563#define EPOD_STATE_ON_CLK_OFF 0x03
564#define EPOD_STATE_ON 0x04
565
566/*
567 * CLKOUT sources
568 */
569#define PRCMU_CLKSRC_CLK38M 0x00
570#define PRCMU_CLKSRC_ACLK 0x01
571#define PRCMU_CLKSRC_SYSCLK 0x02
572#define PRCMU_CLKSRC_LCDCLK 0x03
573#define PRCMU_CLKSRC_SDMMCCLK 0x04
574#define PRCMU_CLKSRC_TVCLK 0x05
575#define PRCMU_CLKSRC_TIMCLK 0x06
576#define PRCMU_CLKSRC_CLK009 0x07
577/* These are only valid for CLKOUT1: */
578#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
579#define PRCMU_CLKSRC_I2CCLK 0x41
580#define PRCMU_CLKSRC_MSP02CLK 0x42
581#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
582#define PRCMU_CLKSRC_HSIRXCLK 0x44
583#define PRCMU_CLKSRC_HSITXCLK 0x45
584#define PRCMU_CLKSRC_ARMCLKFIX 0x46
585#define PRCMU_CLKSRC_HDMICLK 0x47
586
587/*
588 * Definitions for autonomous power management configuration. 461 * Definitions for autonomous power management configuration.
589 */ 462 */
590 463
@@ -620,88 +493,12 @@ struct prcmu_auto_pm_config {
620 u8 sva_policy; 493 u8 sva_policy;
621}; 494};
622 495
623/**
624 * enum ddr_opp - DDR OPP states definition
625 * @DDR_100_OPP: The new DDR operating point is ddr100opp
626 * @DDR_50_OPP: The new DDR operating point is ddr50opp
627 * @DDR_25_OPP: The new DDR operating point is ddr25opp
628 */
629enum ddr_opp {
630 DDR_100_OPP = 0x00,
631 DDR_50_OPP = 0x01,
632 DDR_25_OPP = 0x02,
633};
634
635/*
636 * Clock identifiers.
637 */
638enum prcmu_clock {
639 PRCMU_SGACLK,
640 PRCMU_UARTCLK,
641 PRCMU_MSP02CLK,
642 PRCMU_MSP1CLK,
643 PRCMU_I2CCLK,
644 PRCMU_SDMMCCLK,
645 PRCMU_SLIMCLK,
646 PRCMU_PER1CLK,
647 PRCMU_PER2CLK,
648 PRCMU_PER3CLK,
649 PRCMU_PER5CLK,
650 PRCMU_PER6CLK,
651 PRCMU_PER7CLK,
652 PRCMU_LCDCLK,
653 PRCMU_BMLCLK,
654 PRCMU_HSITXCLK,
655 PRCMU_HSIRXCLK,
656 PRCMU_HDMICLK,
657 PRCMU_APEATCLK,
658 PRCMU_APETRACECLK,
659 PRCMU_MCDECLK,
660 PRCMU_IPI2CCLK,
661 PRCMU_DSIALTCLK,
662 PRCMU_DMACLK,
663 PRCMU_B2R2CLK,
664 PRCMU_TVCLK,
665 PRCMU_SSPCLK,
666 PRCMU_RNGCLK,
667 PRCMU_UICCCLK,
668 PRCMU_NUM_REG_CLOCKS,
669 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
670 PRCMU_TIMCLK,
671};
672
673/*
674 * Definitions for controlling ESRAM0 in deep sleep.
675 */
676#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
677#define ESRAM0_DEEP_SLEEP_STATE_RET 2
678
679#ifdef CONFIG_MFD_DB8500_PRCMU
680void __init prcmu_early_init(void);
681int prcmu_set_display_clocks(void);
682int prcmu_disable_dsipll(void);
683int prcmu_enable_dsipll(void);
684#else
685static inline void __init prcmu_early_init(void) {}
686#endif
687
688#ifdef CONFIG_MFD_DB8500_PRCMU 496#ifdef CONFIG_MFD_DB8500_PRCMU
689 497
498void db8500_prcmu_early_init(void);
690int prcmu_set_rc_a2p(enum romcode_write); 499int prcmu_set_rc_a2p(enum romcode_write);
691enum romcode_read prcmu_get_rc_p2a(void); 500enum romcode_read prcmu_get_rc_p2a(void);
692enum ap_pwrst prcmu_get_xp70_current_state(void); 501enum ap_pwrst prcmu_get_xp70_current_state(void);
693int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
694
695void prcmu_enable_wakeups(u32 wakeups);
696static inline void prcmu_disable_wakeups(void)
697{
698 prcmu_enable_wakeups(0);
699}
700
701void prcmu_config_abb_event_readout(u32 abb_events);
702void prcmu_get_abb_event_buffer(void __iomem **buf);
703int prcmu_set_arm_opp(u8 opp);
704int prcmu_get_arm_opp(void);
705bool prcmu_has_arm_maxopp(void); 502bool prcmu_has_arm_maxopp(void);
706bool prcmu_is_u8400(void); 503bool prcmu_is_u8400(void);
707int prcmu_set_ape_opp(u8 opp); 504int prcmu_set_ape_opp(u8 opp);
@@ -710,19 +507,14 @@ int prcmu_request_ape_opp_100_voltage(bool enable);
710int prcmu_release_usb_wakeup_state(void); 507int prcmu_release_usb_wakeup_state(void);
711int prcmu_set_ddr_opp(u8 opp); 508int prcmu_set_ddr_opp(u8 opp);
712int prcmu_get_ddr_opp(void); 509int prcmu_get_ddr_opp(void);
713unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
714void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
715/* NOTE! Use regulator framework instead */ 510/* NOTE! Use regulator framework instead */
716int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); 511int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
717int prcmu_set_epod(u16 epod_id, u8 epod_state);
718void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 512void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
719 struct prcmu_auto_pm_config *idle); 513 struct prcmu_auto_pm_config *idle);
720bool prcmu_is_auto_pm_enabled(void); 514bool prcmu_is_auto_pm_enabled(void);
721 515
722int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 516int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
723int prcmu_request_clock(u8 clock, bool enable);
724int prcmu_set_clock_divider(u8 clock, u8 divider); 517int prcmu_set_clock_divider(u8 clock, u8 divider);
725int prcmu_config_esram0_deep_sleep(u8 state);
726int prcmu_config_hotdog(u8 threshold); 518int prcmu_config_hotdog(u8 threshold);
727int prcmu_config_hotmon(u8 low, u8 high); 519int prcmu_config_hotmon(u8 low, u8 high);
728int prcmu_start_temp_sense(u16 cycles32k); 520int prcmu_start_temp_sense(u16 cycles32k);
@@ -732,14 +524,36 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
732 524
733void prcmu_ac_wake_req(void); 525void prcmu_ac_wake_req(void);
734void prcmu_ac_sleep_req(void); 526void prcmu_ac_sleep_req(void);
735void prcmu_system_reset(u16 reset_code);
736void prcmu_modem_reset(void); 527void prcmu_modem_reset(void);
737bool prcmu_is_ac_wake_requested(void);
738void prcmu_enable_spi2(void); 528void prcmu_enable_spi2(void);
739void prcmu_disable_spi2(void); 529void prcmu_disable_spi2(void);
740 530
531int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
532int prcmu_enable_a9wdog(u8 id);
533int prcmu_disable_a9wdog(u8 id);
534int prcmu_kick_a9wdog(u8 id);
535int prcmu_load_a9wdog(u8 id, u32 val);
536
537void db8500_prcmu_system_reset(u16 reset_code);
538int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
539void db8500_prcmu_enable_wakeups(u32 wakeups);
540int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
541int db8500_prcmu_request_clock(u8 clock, bool enable);
542int db8500_prcmu_set_display_clocks(void);
543int db8500_prcmu_disable_dsipll(void);
544int db8500_prcmu_enable_dsipll(void);
545void db8500_prcmu_config_abb_event_readout(u32 abb_events);
546void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
547int db8500_prcmu_config_esram0_deep_sleep(u8 state);
548u16 db8500_prcmu_get_reset_code(void);
549bool db8500_prcmu_is_ac_wake_requested(void);
550int db8500_prcmu_set_arm_opp(u8 opp);
551int db8500_prcmu_get_arm_opp(void);
552
741#else /* !CONFIG_MFD_DB8500_PRCMU */ 553#else /* !CONFIG_MFD_DB8500_PRCMU */
742 554
555static inline void db8500_prcmu_early_init(void) {}
556
743static inline int prcmu_set_rc_a2p(enum romcode_write code) 557static inline int prcmu_set_rc_a2p(enum romcode_write code)
744{ 558{
745 return 0; 559 return 0;
@@ -755,34 +569,12 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
755 return AP_EXECUTE; 569 return AP_EXECUTE;
756} 570}
757 571
758static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 572static inline bool prcmu_has_arm_maxopp(void)
759 bool keep_ap_pll)
760{
761 return 0;
762}
763
764static inline void prcmu_enable_wakeups(u32 wakeups) {}
765
766static inline void prcmu_disable_wakeups(void) {}
767
768static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
769
770static inline int prcmu_set_arm_opp(u8 opp)
771{
772 return 0;
773}
774
775static inline int prcmu_get_arm_opp(void)
776{
777 return ARM_100_OPP;
778}
779
780static bool prcmu_has_arm_maxopp(void)
781{ 573{
782 return false; 574 return false;
783} 575}
784 576
785static bool prcmu_is_u8400(void) 577static inline bool prcmu_is_u8400(void)
786{ 578{
787 return false; 579 return false;
788} 580}
@@ -817,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void)
817 return DDR_100_OPP; 609 return DDR_100_OPP;
818} 610}
819 611
820static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
821{
822 return 0;
823}
824
825static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
826
827static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) 612static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
828{ 613{
829 return 0; 614 return 0;
@@ -844,21 +629,11 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
844 return 0; 629 return 0;
845} 630}
846 631
847static inline int prcmu_request_clock(u8 clock, bool enable)
848{
849 return 0;
850}
851
852static inline int prcmu_set_clock_divider(u8 clock, u8 divider) 632static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
853{ 633{
854 return 0; 634 return 0;
855} 635}
856 636
857int prcmu_config_esram0_deep_sleep(u8 state)
858{
859 return 0;
860}
861
862static inline int prcmu_config_hotdog(u8 threshold) 637static inline int prcmu_config_hotdog(u8 threshold)
863{ 638{
864 return 0; 639 return 0;
@@ -893,86 +668,107 @@ static inline void prcmu_ac_wake_req(void) {}
893 668
894static inline void prcmu_ac_sleep_req(void) {} 669static inline void prcmu_ac_sleep_req(void) {}
895 670
896static inline void prcmu_system_reset(u16 reset_code) {}
897
898static inline void prcmu_modem_reset(void) {} 671static inline void prcmu_modem_reset(void) {}
899 672
900static inline bool prcmu_is_ac_wake_requested(void) 673static inline int prcmu_enable_spi2(void)
901{ 674{
902 return false; 675 return 0;
903} 676}
904 677
905#ifndef CONFIG_UX500_SOC_DB5500 678static inline int prcmu_disable_spi2(void)
906static inline int prcmu_set_display_clocks(void)
907{ 679{
908 return 0; 680 return 0;
909} 681}
910 682
911static inline int prcmu_disable_dsipll(void) 683static inline void db8500_prcmu_system_reset(u16 reset_code) {}
684
685static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
686 bool keep_ap_pll)
912{ 687{
913 return 0; 688 return 0;
914} 689}
915 690
916static inline int prcmu_enable_dsipll(void) 691static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
692
693static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
917{ 694{
918 return 0; 695 return 0;
919} 696}
920#endif
921 697
922static inline int prcmu_enable_spi2(void) 698static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
923{ 699{
924 return 0; 700 return 0;
925} 701}
926 702
927static inline int prcmu_disable_spi2(void) 703static inline int db8500_prcmu_set_display_clocks(void)
928{ 704{
929 return 0; 705 return 0;
930} 706}
931 707
932#endif /* !CONFIG_MFD_DB8500_PRCMU */ 708static inline int db8500_prcmu_disable_dsipll(void)
709{
710 return 0;
711}
712
713static inline int db8500_prcmu_enable_dsipll(void)
714{
715 return 0;
716}
717
718static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
719{
720 return 0;
721}
722
723static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
933 724
934#ifdef CONFIG_UX500_PRCMU_QOS_POWER 725static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
935int prcmu_qos_requirement(int pm_qos_class); 726
936int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); 727static inline u16 db8500_prcmu_get_reset_code(void)
937int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
938void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
939int prcmu_qos_add_notifier(int prcmu_qos_class,
940 struct notifier_block *notifier);
941int prcmu_qos_remove_notifier(int prcmu_qos_class,
942 struct notifier_block *notifier);
943#else
944static inline int prcmu_qos_requirement(int prcmu_qos_class)
945{ 728{
946 return 0; 729 return 0;
947} 730}
948 731
949static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 732static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
950 char *name, s32 value)
951{ 733{
952 return 0; 734 return 0;
953} 735}
954 736
955static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 737static inline int prcmu_enable_a9wdog(u8 id)
956 char *name, s32 new_value)
957{ 738{
958 return 0; 739 return 0;
959} 740}
960 741
961static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 742static inline int prcmu_disable_a9wdog(u8 id)
962{ 743{
744 return 0;
963} 745}
964 746
965static inline int prcmu_qos_add_notifier(int prcmu_qos_class, 747static inline int prcmu_kick_a9wdog(u8 id)
966 struct notifier_block *notifier)
967{ 748{
968 return 0; 749 return 0;
969} 750}
970static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, 751
971 struct notifier_block *notifier) 752static inline int prcmu_load_a9wdog(u8 id, u32 val)
972{ 753{
973 return 0; 754 return 0;
974} 755}
975 756
976#endif 757static inline bool db8500_prcmu_is_ac_wake_requested(void)
758{
759 return 0;
760}
761
762static inline int db8500_prcmu_set_arm_opp(u8 opp)
763{
764 return 0;
765}
766
767static inline int db8500_prcmu_get_arm_opp(void)
768{
769 return 0;
770}
771
772#endif /* !CONFIG_MFD_DB8500_PRCMU */
977 773
978#endif /* __MFD_DB8500_PRCMU_H */ 774#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 6c7584d69d8f..bac942f959c1 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -240,7 +240,7 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
240static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 240static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
241{ 241{
242 if (machine_is_u5500()) 242 if (machine_is_u5500())
243 return db5500_prcmu_set_epod(epod_id, epod_state); 243 return -EINVAL;
244 else 244 else
245 return db8500_prcmu_set_epod(epod_id, epod_state); 245 return db8500_prcmu_set_epod(epod_id, epod_state);
246} 246}
@@ -295,7 +295,7 @@ int prcmu_get_ddr_opp(void);
295static inline int prcmu_set_arm_opp(u8 opp) 295static inline int prcmu_set_arm_opp(u8 opp)
296{ 296{
297 if (machine_is_u5500()) 297 if (machine_is_u5500())
298 return db5500_prcmu_set_arm_opp(opp); 298 return -EINVAL;
299 else 299 else
300 return db8500_prcmu_set_arm_opp(opp); 300 return db8500_prcmu_set_arm_opp(opp);
301} 301}
@@ -303,7 +303,7 @@ static inline int prcmu_set_arm_opp(u8 opp)
303static inline int prcmu_get_arm_opp(void) 303static inline int prcmu_get_arm_opp(void)
304{ 304{
305 if (machine_is_u5500()) 305 if (machine_is_u5500())
306 return db5500_prcmu_get_arm_opp(); 306 return -EINVAL;
307 else 307 else
308 return db8500_prcmu_get_arm_opp(); 308 return db8500_prcmu_get_arm_opp();
309} 309}
@@ -362,7 +362,7 @@ static inline int prcmu_enable_dsipll(void)
362static inline int prcmu_config_esram0_deep_sleep(u8 state) 362static inline int prcmu_config_esram0_deep_sleep(u8 state)
363{ 363{
364 if (machine_is_u5500()) 364 if (machine_is_u5500())
365 return db5500_prcmu_config_esram0_deep_sleep(state); 365 return -EINVAL;
366 else 366 else
367 return db8500_prcmu_config_esram0_deep_sleep(state); 367 return db8500_prcmu_config_esram0_deep_sleep(state);
368} 368}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 13:11:20 -0500