Merge branch 'amd-xgbe-next'

Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver update 2014-07-25

This patch series is dependent on the following patch that was
applied to the net tree and needs to be applied to the net-next
tree:
  332cfc823d18 - amd-xgbe: Fix error return code in xgbe_probe()

The following series of patches includes fixes and new support in the
driver.

- Device bindings documentation update
- Hardware timestamp support
- 2.5GbE support changes
- Fifo sizes based on active queues/rings
- Phylib driver updates for:
  - Rate change completion check
  - KR training initiation
  - Auto-negotiation results
- Traffic class support, including DCB support

This patch series is based on net-next.

Changes in V2:
  - Remove DBGPR(...., __func__) calls
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

14 files changed, 1631 insertions, 127 deletions

diff --git a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
index d01ed63d3ebb..42409bfe04c4 100644
--- a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
+++ b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
@@ -8,10 +8,16 @@ Required properties:
    - SerDes integration registers (1/2)
    - SerDes integration registers (2/2)
 
+Optional properties:
+- amd,speed-set: Speed capabilities of the device
+    0 - 1GbE and 10GbE (default)
+    1 - 2.5GbE and 10GbE
+
 Example:
         xgbe_phy@e1240800 {
                 compatible = "amd,xgbe-phy-seattle-v1a", "ethernet-phy-ieee802.3-c45";
                 reg = <0 0xe1240800 0 0x00400>,
                       <0 0xe1250000 0 0x00060>,
                       <0 0xe1250080 0 0x00004>;
+                amd,speed-set = <0>;
         };
diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt
index ea0c7908a3b8..41354f730beb 100644
--- a/Documentation/devicetree/bindings/net/amd-xgbe.txt
+++ b/Documentation/devicetree/bindings/net/amd-xgbe.txt
@@ -8,16 +8,21 @@ Required properties:
 - interrupt-parent: Should be the phandle for the interrupt controller
   that services interrupts for this device
 - interrupts: Should contain the amd-xgbe interrupt
-- clocks: Should be the DMA clock for the amd-xgbe device (used for
-  calculating the correct Rx interrupt watchdog timer value on a DMA
-  channel for coalescing)
-- clock-names: Should be the name of the DMA clock, "dma_clk"
+- clocks:
+   - DMA clock for the amd-xgbe device (used for calculating the
+     correct Rx interrupt watchdog timer value on a DMA channel
+     for coalescing)
+   - PTP clock for the amd-xgbe device
+- clock-names: Should be the names of the clocks
+   - "dma_clk" for the DMA clock
+   - "ptp_clk" for the PTP clock
 - phy-handle: See ethernet.txt file in the same directory
 - phy-mode: See ethernet.txt file in the same directory
 
 Optional properties:
 - mac-address: mac address to be assigned to the device. Can be overridden
   by UEFI.
+- dma-coherent: Present if dma operations are coherent
 
 Example:
         xgbe@e0700000 {
@@ -26,8 +31,8 @@ Example:
                       <0 0xe0780000 0 0x80000>;
                 interrupt-parent = <&gic>;
                 interrupts = <0 325 4>;
-                clocks = <&xgbe_clk>;
-                clock-names = "dma_clk";
+                clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
+                clock-names = "dma_clk", "ptp_clk";
                 phy-handle = <&phy>;
                 phy-mode = "xgmii";
                 mac-address = [ 02 a1 a2 a3 a4 a5 ];
diff --git a/drivers/net/ethernet/amd/Kconfig b/drivers/net/ethernet/amd/Kconfig
index 6e314dbba805..8319c99331b0 100644
--- a/drivers/net/ethernet/amd/Kconfig
+++ b/drivers/net/ethernet/amd/Kconfig
@@ -184,6 +184,7 @@ config AMD_XGBE
         select AMD_XGBE_PHY
         select BITREVERSE
         select CRC32
+        select PTP_1588_CLOCK
         ---help---
           This driver supports the AMD 10GbE Ethernet device found on an
           AMD SoC.
@@ -191,4 +192,14 @@ config AMD_XGBE
           To compile this driver as a module, choose M here: the module
           will be called amd-xgbe.
 
+config AMD_XGBE_DCB
+        bool "Data Center Bridging (DCB) support"
+        default n
+        depends on AMD_XGBE && DCB
+        ---help---
+          Say Y here to enable Data Center Bridging (DCB) support in the
+          driver.
+
+          If unsure, say N.
+
 endif # NET_VENDOR_AMD
diff --git a/drivers/net/ethernet/amd/xgbe/Makefile b/drivers/net/ethernet/amd/xgbe/Makefile
index 26cf9af1642f..171a7e68048d 100644
--- a/drivers/net/ethernet/amd/xgbe/Makefile
+++ b/drivers/net/ethernet/amd/xgbe/Makefile
@@ -1,6 +1,8 @@
 obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o
 
 amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
-                 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o
+                 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
+                 xgbe-ptp.o
 
+amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
 amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 7ec80ac7043f..cc25a3a9e7cf 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -307,11 +307,24 @@
 #define MAC_MACA0LR                     0x0304
 #define MAC_MACA1HR                     0x0308
 #define MAC_MACA1LR                     0x030c
+#define MAC_TSCR                        0x0d00
+#define MAC_SSIR                        0x0d04
+#define MAC_STSR                        0x0d08
+#define MAC_STNR                        0x0d0c
+#define MAC_STSUR                       0x0d10
+#define MAC_STNUR                       0x0d14
+#define MAC_TSAR                        0x0d18
+#define MAC_TSSR                        0x0d20
+#define MAC_TXSNR                       0x0d30
+#define MAC_TXSSR                       0x0d34
 
 #define MAC_QTFCR_INC                   4
 #define MAC_MACA_INC                    4
 #define MAC_HTR_INC                     4
 
+#define MAC_RQC2_INC                    4
+#define MAC_RQC2_Q_PER_REG              4
+
 /* MAC register entry bit positions and sizes */
 #define MAC_HWF0R_ADDMACADRSEL_INDEX    18
 #define MAC_HWF0R_ADDMACADRSEL_WIDTH    5
@@ -351,6 +364,8 @@
 #define MAC_HWF1R_HASHTBLSZ_WIDTH       3
 #define MAC_HWF1R_L3L4FNUM_INDEX        27
 #define MAC_HWF1R_L3L4FNUM_WIDTH        4
+#define MAC_HWF1R_NUMTC_INDEX           21
+#define MAC_HWF1R_NUMTC_WIDTH           3
 #define MAC_HWF1R_RSSEN_INDEX           20
 #define MAC_HWF1R_RSSEN_WIDTH           1
 #define MAC_HWF1R_RXFIFOSIZE_INDEX      0
@@ -373,12 +388,16 @@
 #define MAC_HWF2R_TXCHCNT_WIDTH         4
 #define MAC_HWF2R_TXQCNT_INDEX          6
 #define MAC_HWF2R_TXQCNT_WIDTH          4
+#define MAC_IER_TSIE_INDEX              12
+#define MAC_IER_TSIE_WIDTH              1
 #define MAC_ISR_MMCRXIS_INDEX           9
 #define MAC_ISR_MMCRXIS_WIDTH           1
 #define MAC_ISR_MMCTXIS_INDEX           10
 #define MAC_ISR_MMCTXIS_WIDTH           1
 #define MAC_ISR_PMTIS_INDEX             4
 #define MAC_ISR_PMTIS_WIDTH             1
+#define MAC_ISR_TSIS_INDEX              12
+#define MAC_ISR_TSIS_WIDTH              1
 #define MAC_MACA1HR_AE_INDEX            31
 #define MAC_MACA1HR_AE_WIDTH            1
 #define MAC_PFR_HMC_INDEX               2
@@ -419,14 +438,56 @@
 #define MAC_RCR_LM_WIDTH                1
 #define MAC_RCR_RE_INDEX                0
 #define MAC_RCR_RE_WIDTH                1
+#define MAC_RFCR_PFCE_INDEX             8
+#define MAC_RFCR_PFCE_WIDTH             1
 #define MAC_RFCR_RFE_INDEX              0
 #define MAC_RFCR_RFE_WIDTH              1
+#define MAC_RFCR_UP_INDEX               1
+#define MAC_RFCR_UP_WIDTH               1
 #define MAC_RQC0R_RXQ0EN_INDEX          0
 #define MAC_RQC0R_RXQ0EN_WIDTH          2
+#define MAC_SSIR_SNSINC_INDEX           8
+#define MAC_SSIR_SNSINC_WIDTH           8
+#define MAC_SSIR_SSINC_INDEX            16
+#define MAC_SSIR_SSINC_WIDTH            8
 #define MAC_TCR_SS_INDEX                29
 #define MAC_TCR_SS_WIDTH                2
 #define MAC_TCR_TE_INDEX                0
 #define MAC_TCR_TE_WIDTH                1
+#define MAC_TSCR_AV8021ASMEN_INDEX      28
+#define MAC_TSCR_AV8021ASMEN_WIDTH      1
+#define MAC_TSCR_SNAPTYPSEL_INDEX       16
+#define MAC_TSCR_SNAPTYPSEL_WIDTH       2
+#define MAC_TSCR_TSADDREG_INDEX         5
+#define MAC_TSCR_TSADDREG_WIDTH         1
+#define MAC_TSCR_TSCFUPDT_INDEX         1
+#define MAC_TSCR_TSCFUPDT_WIDTH         1
+#define MAC_TSCR_TSCTRLSSR_INDEX        9
+#define MAC_TSCR_TSCTRLSSR_WIDTH        1
+#define MAC_TSCR_TSENA_INDEX            0
+#define MAC_TSCR_TSENA_WIDTH            1
+#define MAC_TSCR_TSENALL_INDEX          8
+#define MAC_TSCR_TSENALL_WIDTH          1
+#define MAC_TSCR_TSEVNTENA_INDEX        14
+#define MAC_TSCR_TSEVNTENA_WIDTH        1
+#define MAC_TSCR_TSINIT_INDEX           2
+#define MAC_TSCR_TSINIT_WIDTH           1
+#define MAC_TSCR_TSIPENA_INDEX          11
+#define MAC_TSCR_TSIPENA_WIDTH          1
+#define MAC_TSCR_TSIPV4ENA_INDEX        13
+#define MAC_TSCR_TSIPV4ENA_WIDTH        1
+#define MAC_TSCR_TSIPV6ENA_INDEX        12
+#define MAC_TSCR_TSIPV6ENA_WIDTH        1
+#define MAC_TSCR_TSMSTRENA_INDEX        15
+#define MAC_TSCR_TSMSTRENA_WIDTH        1
+#define MAC_TSCR_TSVER2ENA_INDEX        10
+#define MAC_TSCR_TSVER2ENA_WIDTH        1
+#define MAC_TSCR_TXTSSTSM_INDEX         24
+#define MAC_TSCR_TXTSSTSM_WIDTH         1
+#define MAC_TSSR_TXTSC_INDEX            15
+#define MAC_TSSR_TXTSC_WIDTH            1
+#define MAC_TXSNR_TXTSSTSMIS_INDEX      31
+#define MAC_TXSNR_TXTSSTSMIS_WIDTH      1
 #define MAC_VLANHTR_VLHT_INDEX          0
 #define MAC_VLANHTR_VLHT_WIDTH          16
 #define MAC_VLANIR_VLTI_INDEX           20
@@ -652,6 +713,8 @@
 
 #define MTL_RQDCM_INC                   4
 #define MTL_RQDCM_Q_PER_REG             4
+#define MTL_TCPM_INC                    4
+#define MTL_TCPM_TC_PER_REG             4
 
 /* MTL register entry bit positions and sizes */
 #define MTL_OMR_ETSALG_INDEX            5
@@ -670,9 +733,6 @@
 #define MTL_Q_TQOMR                     0x00
 #define MTL_Q_TQUR                      0x04
 #define MTL_Q_TQDR                      0x08
-#define MTL_Q_TCECR                     0x10
-#define MTL_Q_TCESR                     0x14
-#define MTL_Q_TCQWR                     0x18
 #define MTL_Q_RQOMR                     0x40
 #define MTL_Q_RQMPOCR                   0x44
 #define MTL_Q_RQDR                      0x4c
@@ -680,8 +740,6 @@
 #define MTL_Q_ISR                       0x74
 
 /* MTL queue register entry bit positions and sizes */
-#define MTL_Q_TCQWR_QW_INDEX            0
-#define MTL_Q_TCQWR_QW_WIDTH            21
 #define MTL_Q_RQOMR_EHFC_INDEX          7
 #define MTL_Q_RQOMR_EHFC_WIDTH          1
 #define MTL_Q_RQOMR_RFA_INDEX           8
@@ -696,6 +754,8 @@
 #define MTL_Q_RQOMR_RTC_WIDTH           2
 #define MTL_Q_TQOMR_FTQ_INDEX           0
 #define MTL_Q_TQOMR_FTQ_WIDTH           1
+#define MTL_Q_TQOMR_Q2TCMAP_INDEX       8
+#define MTL_Q_TQOMR_Q2TCMAP_WIDTH       3
 #define MTL_Q_TQOMR_TQS_INDEX           16
 #define MTL_Q_TQOMR_TQS_WIDTH           10
 #define MTL_Q_TQOMR_TSF_INDEX           1
@@ -742,10 +802,14 @@
 #define MTL_TC_INC                      MTL_Q_INC
 
 #define MTL_TC_ETSCR                    0x10
+#define MTL_TC_ETSSR                    0x14
+#define MTL_TC_QWR                      0x18
 
 /* MTL traffic class register entry bit positions and sizes */
 #define MTL_TC_ETSCR_TSA_INDEX          0
 #define MTL_TC_ETSCR_TSA_WIDTH          2
+#define MTL_TC_QWR_QW_INDEX             0
+#define MTL_TC_QWR_QW_WIDTH             21
 
 /* MTL traffic class register value */
 #define MTL_TSA_SP                      0x00
@@ -778,9 +842,19 @@
 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH    1
 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX   2
 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH   1
+#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
+#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
+#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX      4
+#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH      1
+#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX    5
+#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH    1
 
 #define RX_NORMAL_DESC0_OVT_INDEX               0
 #define RX_NORMAL_DESC0_OVT_WIDTH               16
+#define RX_NORMAL_DESC3_CDA_INDEX               27
+#define RX_NORMAL_DESC3_CDA_WIDTH               1
+#define RX_NORMAL_DESC3_CTXT_INDEX              30
+#define RX_NORMAL_DESC3_CTXT_WIDTH              1
 #define RX_NORMAL_DESC3_ES_INDEX                15
 #define RX_NORMAL_DESC3_ES_WIDTH                1
 #define RX_NORMAL_DESC3_ETLT_INDEX              16
@@ -794,12 +868,19 @@
 #define RX_NORMAL_DESC3_PL_INDEX                0
 #define RX_NORMAL_DESC3_PL_WIDTH                14
 
+#define RX_CONTEXT_DESC3_TSA_INDEX              4
+#define RX_CONTEXT_DESC3_TSA_WIDTH              1
+#define RX_CONTEXT_DESC3_TSD_INDEX              6
+#define RX_CONTEXT_DESC3_TSD_WIDTH              1
+
 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX  0
 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH  1
 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX   1
 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH   1
 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX    2
 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH    1
+#define TX_PACKET_ATTRIBUTES_PTP_INDEX          3
+#define TX_PACKET_ATTRIBUTES_PTP_WIDTH          1
 
 #define TX_CONTEXT_DESC2_MSS_INDEX              0
 #define TX_CONTEXT_DESC2_MSS_WIDTH              15
@@ -816,6 +897,8 @@
 #define TX_NORMAL_DESC2_HL_B1L_WIDTH            14
 #define TX_NORMAL_DESC2_IC_INDEX                31
 #define TX_NORMAL_DESC2_IC_WIDTH                1
+#define TX_NORMAL_DESC2_TTSE_INDEX              30
+#define TX_NORMAL_DESC2_TTSE_WIDTH              1
 #define TX_NORMAL_DESC2_VTIR_INDEX              14
 #define TX_NORMAL_DESC2_VTIR_WIDTH              2
 #define TX_NORMAL_DESC3_CIC_INDEX               16
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
new file mode 100644
index 000000000000..7d6a49b24321
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
@@ -0,0 +1,270 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/netdevice.h>
+#include <net/dcbnl.h>
+
+#include "xgbe.h"
+#include "xgbe-common.h"
+
+
+static int xgbe_dcb_ieee_getets(struct net_device *netdev,
+                                struct ieee_ets *ets)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+
+        /* Set number of supported traffic classes */
+        ets->ets_cap = pdata->hw_feat.tc_cnt;
+
+        if (pdata->ets) {
+                ets->cbs = pdata->ets->cbs;
+                memcpy(ets->tc_tx_bw, pdata->ets->tc_tx_bw,
+                       sizeof(ets->tc_tx_bw));
+                memcpy(ets->tc_tsa, pdata->ets->tc_tsa,
+                       sizeof(ets->tc_tsa));
+                memcpy(ets->prio_tc, pdata->ets->prio_tc,
+                       sizeof(ets->prio_tc));
+        }
+
+        return 0;
+}
+
+static int xgbe_dcb_ieee_setets(struct net_device *netdev,
+                                struct ieee_ets *ets)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+        unsigned int i, tc_ets, tc_ets_weight;
+
+        tc_ets = 0;
+        tc_ets_weight = 0;
+        for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
+                DBGPR("  TC%u: tx_bw=%hhu, rx_bw=%hhu, tsa=%hhu\n", i,
+                      ets->tc_tx_bw[i], ets->tc_rx_bw[i], ets->tc_tsa[i]);
+                DBGPR("  PRIO%u: TC=%hhu\n", i, ets->prio_tc[i]);
+
+                if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) &&
+                    (i >= pdata->hw_feat.tc_cnt))
+                                return -EINVAL;
+
+                if (ets->prio_tc[i] >= pdata->hw_feat.tc_cnt)
+                        return -EINVAL;
+
+                switch (ets->tc_tsa[i]) {
+                case IEEE_8021QAZ_TSA_STRICT:
+                        break;
+                case IEEE_8021QAZ_TSA_ETS:
+                        tc_ets = 1;
+                        tc_ets_weight += ets->tc_tx_bw[i];
+                        break;
+
+                default:
+                        return -EINVAL;
+                }
+        }
+
+        /* Weights must add up to 100% */
+        if (tc_ets && (tc_ets_weight != 100))
+                return -EINVAL;
+
+        if (!pdata->ets) {
+                pdata->ets = devm_kzalloc(pdata->dev, sizeof(*pdata->ets),
+                                          GFP_KERNEL);
+                if (!pdata->ets)
+                        return -ENOMEM;
+        }
+
+        memcpy(pdata->ets, ets, sizeof(*pdata->ets));
+
+        pdata->hw_if.config_dcb_tc(pdata);
+
+        return 0;
+}
+
+static int xgbe_dcb_ieee_getpfc(struct net_device *netdev,
+                                struct ieee_pfc *pfc)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+
+        /* Set number of supported PFC traffic classes */
+        pfc->pfc_cap = pdata->hw_feat.tc_cnt;
+
+        if (pdata->pfc) {
+                pfc->pfc_en = pdata->pfc->pfc_en;
+                pfc->mbc = pdata->pfc->mbc;
+                pfc->delay = pdata->pfc->delay;
+        }
+
+        return 0;
+}
+
+static int xgbe_dcb_ieee_setpfc(struct net_device *netdev,
+                                struct ieee_pfc *pfc)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+
+        DBGPR("  cap=%hhu, en=%hhx, mbc=%hhu, delay=%hhu\n",
+              pfc->pfc_cap, pfc->pfc_en, pfc->mbc, pfc->delay);
+
+        if (!pdata->pfc) {
+                pdata->pfc = devm_kzalloc(pdata->dev, sizeof(*pdata->pfc),
+                                          GFP_KERNEL);
+                if (!pdata->pfc)
+                        return -ENOMEM;
+        }
+
+        memcpy(pdata->pfc, pfc, sizeof(*pdata->pfc));
+
+        pdata->hw_if.config_dcb_pfc(pdata);
+
+        return 0;
+}
+
+static u8 xgbe_dcb_getdcbx(struct net_device *netdev)
+{
+        return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
+}
+
+static u8 xgbe_dcb_setdcbx(struct net_device *netdev, u8 dcbx)
+{
+        u8 support = xgbe_dcb_getdcbx(netdev);
+
+        DBGPR("  DCBX=%#hhx\n", dcbx);
+
+        if (dcbx & ~support)
+                return 1;
+
+        if ((dcbx & support) != support)
+                return 1;
+
+        return 0;
+}
+
+static const struct dcbnl_rtnl_ops xgbe_dcbnl_ops = {
+        /* IEEE 802.1Qaz std */
+        .ieee_getets = xgbe_dcb_ieee_getets,
+        .ieee_setets = xgbe_dcb_ieee_setets,
+        .ieee_getpfc = xgbe_dcb_ieee_getpfc,
+        .ieee_setpfc = xgbe_dcb_ieee_setpfc,
+
+        /* DCBX configuration */
+        .getdcbx     = xgbe_dcb_getdcbx,
+        .setdcbx     = xgbe_dcb_setdcbx,
+};
+
+const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void)
+{
+        return &xgbe_dcbnl_ops;
+}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
index a9ce56d5e988..1c5d62e8dab6 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
@@ -359,6 +359,15 @@ static void xgbe_unmap_skb(struct xgbe_prv_data *pdata,
         rdata->len = 0;
         rdata->interrupt = 0;
         rdata->mapped_as_page = 0;
+
+        if (rdata->state_saved) {
+                rdata->state_saved = 0;
+                rdata->state.incomplete = 0;
+                rdata->state.context_next = 0;
+                rdata->state.skb = NULL;
+                rdata->state.len = 0;
+                rdata->state.error = 0;
+        }
 }
 
 static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index 699cff5d3184..edaca4496264 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -131,7 +131,7 @@ static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
 
         DBGPR("-->xgbe_usec_to_riwt\n");
 
-        rate = clk_get_rate(pdata->sysclock);
+        rate = clk_get_rate(pdata->sysclk);
 
         /*
          * Convert the input usec value to the watchdog timer value. Each
@@ -154,7 +154,7 @@ static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
 
         DBGPR("-->xgbe_riwt_to_usec\n");
 
-        rate = clk_get_rate(pdata->sysclock);
+        rate = clk_get_rate(pdata->sysclk);
 
         /*
          * Convert the input watchdog timer value to the usec value. Each
@@ -247,7 +247,7 @@ static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
 {
         unsigned int i;
 
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
 
         return 0;
@@ -257,7 +257,7 @@ static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
 {
         unsigned int i;
 
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
 
         return 0;
@@ -268,7 +268,7 @@ static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
 {
         unsigned int i;
 
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
 
         return 0;
@@ -279,7 +279,7 @@ static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
 {
         unsigned int i;
 
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
 
         return 0;
@@ -343,12 +343,12 @@ static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
         unsigned int i;
 
         /* Clear MTL flow control */
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
 
         /* Clear MAC flow control */
         max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
-        q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt, max_q_count);
+        q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);
         reg = MAC_Q0TFCR;
         for (i = 0; i < q_count; i++) {
                 reg_val = XGMAC_IOREAD(pdata, reg);
@@ -368,12 +368,12 @@ static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
         unsigned int i;
 
         /* Set MTL flow control */
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
 
         /* Set MAC flow control */
         max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
-        q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt, max_q_count);
+        q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);
         reg = MAC_Q0TFCR;
         for (i = 0; i < q_count; i++) {
                 reg_val = XGMAC_IOREAD(pdata, reg);
@@ -407,7 +407,9 @@ static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
 
 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
 {
-        if (pdata->tx_pause)
+        struct ieee_pfc *pfc = pdata->pfc;
+
+        if (pdata->tx_pause || (pfc && pfc->pfc_en))
                 xgbe_enable_tx_flow_control(pdata);
         else
                 xgbe_disable_tx_flow_control(pdata);
@@ -417,7 +419,9 @@ static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
 
 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
 {
-        if (pdata->rx_pause)
+        struct ieee_pfc *pfc = pdata->pfc;
+
+        if (pdata->rx_pause || (pfc && pfc->pfc_en))
                 xgbe_enable_rx_flow_control(pdata);
         else
                 xgbe_disable_rx_flow_control(pdata);
@@ -427,8 +431,13 @@ static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
 
 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
 {
+        struct ieee_pfc *pfc = pdata->pfc;
+
         xgbe_config_tx_flow_control(pdata);
         xgbe_config_rx_flow_control(pdata);
+
+        XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
+                           (pfc && pfc->pfc_en) ? 1 : 0);
 }
 
 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
@@ -492,8 +501,12 @@ static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
 
 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
 {
-        /* No MAC interrupts to be enabled */
-        XGMAC_IOWRITE(pdata, MAC_IER, 0);
+        unsigned int mac_ier = 0;
+
+        /* Enable Timestamp interrupt */
+        XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
+
+        XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
 
         /* Enable all counter interrupts */
         XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xff);
@@ -1012,6 +1025,180 @@ static void xgbe_rx_desc_init(struct xgbe_channel *channel)
         DBGPR("<--rx_desc_init\n");
 }
 
+static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
+                                      unsigned int addend)
+{
+        /* Set the addend register value and tell the device */
+        XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
+        XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
+
+        /* Wait for addend update to complete */
+        while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
+                udelay(5);
+}
+
+static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
+                                 unsigned int nsec)
+{
+        /* Set the time values and tell the device */
+        XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
+        XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
+        XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
+
+        /* Wait for time update to complete */
+        while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
+                udelay(5);
+}
+
+static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
+{
+        u64 nsec;
+
+        nsec = XGMAC_IOREAD(pdata, MAC_STSR);
+        nsec *= NSEC_PER_SEC;
+        nsec += XGMAC_IOREAD(pdata, MAC_STNR);
+
+        return nsec;
+}
+
+static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
+{
+        unsigned int tx_snr;
+        u64 nsec;
+
+        tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
+        if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
+                return 0;
+
+        nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
+        nsec *= NSEC_PER_SEC;
+        nsec += tx_snr;
+
+        return nsec;
+}
+
+static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
+                               struct xgbe_ring_desc *rdesc)
+{
+        u64 nsec;
+
+        if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
+            !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
+                nsec = le32_to_cpu(rdesc->desc1);
+                nsec <<= 32;
+                nsec |= le32_to_cpu(rdesc->desc0);
+                if (nsec != 0xffffffffffffffffULL) {
+                        packet->rx_tstamp = nsec;
+                        XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+                                       RX_TSTAMP, 1);
+                }
+        }
+}
+
+static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
+                              unsigned int mac_tscr)
+{
+        /* Set one nano-second accuracy */
+        XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
+
+        /* Set fine timestamp update */
+        XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
+
+        /* Overwrite earlier timestamps */
+        XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
+
+        XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
+
+        /* Exit if timestamping is not enabled */
+        if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
+                return 0;
+
+        /* Initialize time registers */
+        XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
+        XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
+        xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
+        xgbe_set_tstamp_time(pdata, 0, 0);
+
+        /* Initialize the timecounter */
+        timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
+                         ktime_to_ns(ktime_get_real()));
+
+        return 0;
+}
+
+static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
+{
+        struct ieee_ets *ets = pdata->ets;
+        unsigned int total_weight, min_weight, weight;
+        unsigned int i;
+
+        if (!ets)
+                return;
+
+        /* Set Tx to deficit weighted round robin scheduling algorithm (when
+         * traffic class is using ETS algorithm)
+         */
+        XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
+
+        /* Set Traffic Class algorithms */
+        total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
+        min_weight = total_weight / 100;
+        if (!min_weight)
+                min_weight = 1;
+
+        for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
+                switch (ets->tc_tsa[i]) {
+                case IEEE_8021QAZ_TSA_STRICT:
+                        DBGPR("  TC%u using SP\n", i);
+                        XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
+                                               MTL_TSA_SP);
+                        break;
+                case IEEE_8021QAZ_TSA_ETS:
+                        weight = total_weight * ets->tc_tx_bw[i] / 100;
+                        weight = clamp(weight, min_weight, total_weight);
+
+                        DBGPR("  TC%u using DWRR (weight %u)\n", i, weight);
+                        XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
+                                               MTL_TSA_ETS);
+                        XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
+                                               weight);
+                        break;
+                }
+        }
+}
+
+static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
+{
+        struct ieee_pfc *pfc = pdata->pfc;
+        struct ieee_ets *ets = pdata->ets;
+        unsigned int mask, reg, reg_val;
+        unsigned int tc, prio;
+
+        if (!pfc || !ets)
+                return;
+
+        for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
+                mask = 0;
+                for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
+                        if ((pfc->pfc_en & (1 << prio)) &&
+                            (ets->prio_tc[prio] == tc))
+                                mask |= (1 << prio);
+                }
+                mask &= 0xff;
+
+                DBGPR("  TC%u PFC mask=%#x\n", tc, mask);
+                reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
+                reg_val = XGMAC_IOREAD(pdata, reg);
+
+                reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
+                reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
+
+                XGMAC_IOWRITE(pdata, reg, reg_val);
+        }
+
+        xgbe_config_flow_control(pdata);
+}
+
 static void xgbe_pre_xmit(struct xgbe_channel *channel)
 {
         struct xgbe_prv_data *pdata = channel->pdata;
@@ -1110,6 +1297,10 @@ static void xgbe_pre_xmit(struct xgbe_channel *channel)
                 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
                                   TX_NORMAL_DESC2_VLAN_INSERT);
 
+        /* Timestamp enablement check */
+        if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
+                XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
+
         /* Set IC bit based on Tx coalescing settings */
         XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
         if (tx_coalesce && (!tx_frames ||
@@ -1245,6 +1436,25 @@ static int xgbe_dev_read(struct xgbe_channel *channel)
         xgbe_dump_rx_desc(ring, rdesc, ring->cur);
 #endif
 
+        if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
+                /* Timestamp Context Descriptor */
+                xgbe_get_rx_tstamp(packet, rdesc);
+
+                XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+                               CONTEXT, 1);
+                XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+                               CONTEXT_NEXT, 0);
+                return 0;
+        }
+
+        /* Normal Descriptor, be sure Context Descriptor bit is off */
+        XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
+
+        /* Indicate if a Context Descriptor is next */
+        if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
+                XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
+                               CONTEXT_NEXT, 1);
+
         /* Get the packet length */
         rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
 
@@ -1423,11 +1633,11 @@ static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
 {
         unsigned int i, count;
 
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
 
         /* Poll Until Poll Condition */
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++) {
+        for (i = 0; i < pdata->tx_q_count; i++) {
                 count = 2000;
                 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
                                                         MTL_Q_TQOMR, FTQ))
@@ -1479,14 +1689,15 @@ static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
 {
         unsigned int i;
 
-        /* Set Tx to weighted round robin scheduling algorithm (when
-         * traffic class is using ETS algorithm)
-         */
+        /* Set Tx to weighted round robin scheduling algorithm */
         XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
 
-        /* Set Tx traffic classes to strict priority algorithm */
-        for (i = 0; i < XGBE_TC_CNT; i++)
-                XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, MTL_TSA_SP);
+        /* Set Tx traffic classes to use WRR algorithm with equal weights */
+        for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
+                XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
+                                       MTL_TSA_ETS);
+                XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
+        }
 
         /* Set Rx to strict priority algorithm */
         XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
@@ -1572,13 +1783,13 @@ static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
         unsigned int i;
 
         fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
-                                                  pdata->hw_feat.tx_q_cnt);
+                                                  pdata->tx_q_count);
 
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
 
         netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
-                      pdata->hw_feat.tx_q_cnt, ((fifo_size + 1) * 256));
+                      pdata->tx_q_count, ((fifo_size + 1) * 256));
 }
 
 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
@@ -1587,27 +1798,84 @@ static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
         unsigned int i;
 
         fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
-                                                  pdata->hw_feat.rx_q_cnt);
+                                                  pdata->rx_q_count);
 
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
 
         netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
-                      pdata->hw_feat.rx_q_cnt, ((fifo_size + 1) * 256));
+                      pdata->rx_q_count, ((fifo_size + 1) * 256));
 }
 
-static void xgbe_config_rx_queue_mapping(struct xgbe_prv_data *pdata)
+static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
 {
-        unsigned int i, reg, reg_val;
-        unsigned int q_count = pdata->hw_feat.rx_q_cnt;
+        unsigned int qptc, qptc_extra, queue;
+        unsigned int prio_queues;
+        unsigned int ppq, ppq_extra, prio;
+        unsigned int mask;
+        unsigned int i, j, reg, reg_val;
+
+        /* Map the MTL Tx Queues to Traffic Classes
+         *   Note: Tx Queues >= Traffic Classes
+         */
+        qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
+        qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
+
+        for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
+                for (j = 0; j < qptc; j++) {
+                        DBGPR("  TXq%u mapped to TC%u\n", queue, i);
+                        XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
+                                               Q2TCMAP, i);
+                        pdata->q2tc_map[queue++] = i;
+                }
+
+                if (i < qptc_extra) {
+                        DBGPR("  TXq%u mapped to TC%u\n", queue, i);
+                        XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
+                                               Q2TCMAP, i);
+                        pdata->q2tc_map[queue++] = i;
+                }
+        }
+
+        /* Map the 8 VLAN priority values to available MTL Rx queues */
+        prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
+                            pdata->rx_q_count);
+        ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
+        ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
+
+        reg = MAC_RQC2R;
+        reg_val = 0;
+        for (i = 0, prio = 0; i < prio_queues;) {
+                mask = 0;
+                for (j = 0; j < ppq; j++) {
+                        DBGPR("  PRIO%u mapped to RXq%u\n", prio, i);
+                        mask |= (1 << prio);
+                        pdata->prio2q_map[prio++] = i;
+                }
+
+                if (i < ppq_extra) {
+                        DBGPR("  PRIO%u mapped to RXq%u\n", prio, i);
+                        mask |= (1 << prio);
+                        pdata->prio2q_map[prio++] = i;
+                }
+
+                reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
+
+                if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
+                        continue;
+
+                XGMAC_IOWRITE(pdata, reg, reg_val);
+                reg += MAC_RQC2_INC;
+                reg_val = 0;
+        }
 
         /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
         reg = MTL_RQDCM0R;
         reg_val = 0;
-        for (i = 0; i < q_count;) {
+        for (i = 0; i < pdata->rx_q_count;) {
                 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
 
-                if ((i % MTL_RQDCM_Q_PER_REG) && (i != q_count))
+                if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
                         continue;
 
                 XGMAC_IOWRITE(pdata, reg, reg_val);
@@ -1621,7 +1889,7 @@ static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
 {
         unsigned int i;
 
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++) {
+        for (i = 0; i < pdata->rx_q_count; i++) {
                 /* Activate flow control when less than 4k left in fifo */
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
 
@@ -2013,7 +2281,7 @@ static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
         }
 
         /* Enable each Tx queue */
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
                                        MTL_Q_ENABLED);
 
@@ -2030,7 +2298,7 @@ static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
         XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
 
         /* Disable each Tx queue */
-        for (i = 0; i < pdata->hw_feat.tx_q_cnt; i++)
+        for (i = 0; i < pdata->tx_q_count; i++)
                 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
 
         /* Disable each Tx DMA channel */
@@ -2059,7 +2327,7 @@ static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
 
         /* Enable each Rx queue */
         reg_val = 0;
-        for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++)
+        for (i = 0; i < pdata->rx_q_count; i++)
                 reg_val |= (0x02 << (i << 1));
         XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
 
@@ -2193,9 +2461,7 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
          * Initialize MTL related features
          */
         xgbe_config_mtl_mode(pdata);
-        xgbe_config_rx_queue_mapping(pdata);
-        /*TODO: Program the priorities mapped to the Selected Traffic Classes
-                in MTL_TC_Prty_Map0-3 registers */
+        xgbe_config_queue_mapping(pdata);
         xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
         xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
         xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
@@ -2203,15 +2469,13 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
         xgbe_config_tx_fifo_size(pdata);
         xgbe_config_rx_fifo_size(pdata);
         xgbe_config_flow_control_threshold(pdata);
-        /*TODO: Queue to Traffic Class Mapping (Q2TCMAP) */
         /*TODO: Error Packet and undersized good Packet forwarding enable
                 (FEP and FUP)
          */
+        xgbe_config_dcb_tc(pdata);
+        xgbe_config_dcb_pfc(pdata);
         xgbe_enable_mtl_interrupts(pdata);
 
-        /* Transmit Class Weight */
-        XGMAC_IOWRITE_BITS(pdata, MTL_Q_TCQWR, QW, 0x10);
-
         /*
          * Initialize MAC related features
          */
@@ -2313,5 +2577,16 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
         hw_if->rx_mmc_int = xgbe_rx_mmc_int;
         hw_if->read_mmc_stats = xgbe_read_mmc_stats;
 
+        /* For PTP config */
+        hw_if->config_tstamp = xgbe_config_tstamp;
+        hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
+        hw_if->set_tstamp_time = xgbe_set_tstamp_time;
+        hw_if->get_tstamp_time = xgbe_get_tstamp_time;
+        hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
+
+        /* For Data Center Bridging config */
+        hw_if->config_dcb_tc = xgbe_config_dcb_tc;
+        hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
+
         DBGPR("<--xgbe_init_function_ptrs\n");
 }
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index 344e6b19ec0e..3bf3c0194ad3 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -121,6 +121,7 @@
 #include <net/busy_poll.h>
 #include <linux/clk.h>
 #include <linux/if_ether.h>
+#include <linux/net_tstamp.h>
 
 #include "xgbe.h"
 #include "xgbe-common.h"
@@ -202,7 +203,7 @@ static irqreturn_t xgbe_isr(int irq, void *data)
         struct xgbe_hw_if *hw_if = &pdata->hw_if;
         struct xgbe_channel *channel;
         unsigned int dma_isr, dma_ch_isr;
-        unsigned int mac_isr;
+        unsigned int mac_isr, mac_tssr;
         unsigned int i;
 
         /* The DMA interrupt status register also reports MAC and MTL
@@ -255,6 +256,17 @@ static irqreturn_t xgbe_isr(int irq, void *data)
 
                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
                         hw_if->rx_mmc_int(pdata);
+
+                if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
+                        mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
+
+                        if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
+                                /* Read Tx Timestamp to clear interrupt */
+                                pdata->tx_tstamp =
+                                        hw_if->get_tx_tstamp(pdata);
+                                schedule_work(&pdata->tx_tstamp_work);
+                        }
+                }
         }
 
         DBGPR("  DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR));
@@ -375,6 +387,7 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
+        hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
                                                   HASHTBLSZ);
         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
@@ -668,6 +681,197 @@ static void xgbe_restart(struct work_struct *work)
         rtnl_unlock();
 }
 
+static void xgbe_tx_tstamp(struct work_struct *work)
+{
+        struct xgbe_prv_data *pdata = container_of(work,
+                                                   struct xgbe_prv_data,
+                                                   tx_tstamp_work);
+        struct skb_shared_hwtstamps hwtstamps;
+        u64 nsec;
+        unsigned long flags;
+
+        if (pdata->tx_tstamp) {
+                nsec = timecounter_cyc2time(&pdata->tstamp_tc,
+                                            pdata->tx_tstamp);
+
+                memset(&hwtstamps, 0, sizeof(hwtstamps));
+                hwtstamps.hwtstamp = ns_to_ktime(nsec);
+                skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
+        }
+
+        dev_kfree_skb_any(pdata->tx_tstamp_skb);
+
+        spin_lock_irqsave(&pdata->tstamp_lock, flags);
+        pdata->tx_tstamp_skb = NULL;
+        spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+}
+
+static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
+                                      struct ifreq *ifreq)
+{
+        if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
+                         sizeof(pdata->tstamp_config)))
+                return -EFAULT;
+
+        return 0;
+}
+
+static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
+                                      struct ifreq *ifreq)
+{
+        struct hwtstamp_config config;
+        unsigned int mac_tscr;
+
+        if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
+                return -EFAULT;
+
+        if (config.flags)
+                return -EINVAL;
+
+        mac_tscr = 0;
+
+        switch (config.tx_type) {
+        case HWTSTAMP_TX_OFF:
+                break;
+
+        case HWTSTAMP_TX_ON:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        default:
+                return -ERANGE;
+        }
+
+        switch (config.rx_filter) {
+        case HWTSTAMP_FILTER_NONE:
+                break;
+
+        case HWTSTAMP_FILTER_ALL:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2, UDP, any kind of event packet */
+        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+        /* PTP v1, UDP, any kind of event packet */
+        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2, UDP, Sync packet */
+        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+        /* PTP v1, UDP, Sync packet */
+        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2, UDP, Delay_req packet */
+        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+        /* PTP v1, UDP, Delay_req packet */
+        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* 802.AS1, Ethernet, any kind of event packet */
+        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* 802.AS1, Ethernet, Sync packet */
+        case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* 802.AS1, Ethernet, Delay_req packet */
+        case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2/802.AS1, any layer, any kind of event packet */
+        case HWTSTAMP_FILTER_PTP_V2_EVENT:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2/802.AS1, any layer, Sync packet */
+        case HWTSTAMP_FILTER_PTP_V2_SYNC:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        /* PTP v2/802.AS1, any layer, Delay_req packet */
+        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
+                XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
+                break;
+
+        default:
+                return -ERANGE;
+        }
+
+        pdata->hw_if.config_tstamp(pdata, mac_tscr);
+
+        memcpy(&pdata->tstamp_config, &config, sizeof(config));
+
+        return 0;
+}
+
+static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
+                                struct sk_buff *skb,
+                                struct xgbe_packet_data *packet)
+{
+        unsigned long flags;
+
+        if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
+                spin_lock_irqsave(&pdata->tstamp_lock, flags);
+                if (pdata->tx_tstamp_skb) {
+                        /* Another timestamp in progress, ignore this one */
+                        XGMAC_SET_BITS(packet->attributes,
+                                       TX_PACKET_ATTRIBUTES, PTP, 0);
+                } else {
+                        pdata->tx_tstamp_skb = skb_get(skb);
+                        skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+                }
+                spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+        }
+
+        if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
+                skb_tx_timestamp(skb);
+}
+
 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
 {
         if (vlan_tx_tag_present(skb))
@@ -711,7 +915,8 @@ static int xgbe_is_tso(struct sk_buff *skb)
         return 1;
 }
 
-static void xgbe_packet_info(struct xgbe_ring *ring, struct sk_buff *skb,
+static void xgbe_packet_info(struct xgbe_prv_data *pdata,
+                             struct xgbe_ring *ring, struct sk_buff *skb,
                              struct xgbe_packet_data *packet)
 {
         struct skb_frag_struct *frag;
@@ -753,6 +958,11 @@ static void xgbe_packet_info(struct xgbe_ring *ring, struct sk_buff *skb,
                                VLAN_CTAG, 1);
         }
 
+        if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
+            (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
+                XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
+                               PTP, 1);
+
         for (len = skb_headlen(skb); len;) {
                 packet->rdesc_count++;
                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
@@ -776,26 +986,33 @@ static int xgbe_open(struct net_device *netdev)
 
         DBGPR("-->xgbe_open\n");
 
-        /* Enable the clock */
-        ret = clk_prepare_enable(pdata->sysclock);
+        /* Enable the clocks */
+        ret = clk_prepare_enable(pdata->sysclk);
         if (ret) {
-                netdev_alert(netdev, "clk_prepare_enable failed\n");
+                netdev_alert(netdev, "dma clk_prepare_enable failed\n");
                 return ret;
         }
 
+        ret = clk_prepare_enable(pdata->ptpclk);
+        if (ret) {
+                netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
+                goto err_sysclk;
+        }
+
         /* Calculate the Rx buffer size before allocating rings */
         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
         if (ret < 0)
-                goto err_clk;
+                goto err_ptpclk;
         pdata->rx_buf_size = ret;
 
         /* Allocate the ring descriptors and buffers */
         ret = desc_if->alloc_ring_resources(pdata);
         if (ret)
-                goto err_clk;
+                goto err_ptpclk;
 
-        /* Initialize the device restart work struct */
+        /* Initialize the device restart and Tx timestamp work struct */
         INIT_WORK(&pdata->restart_work, xgbe_restart);
+        INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
 
         /* Request interrupts */
         ret = devm_request_irq(pdata->dev, netdev->irq, xgbe_isr, 0,
@@ -824,8 +1041,11 @@ err_start:
 err_irq:
         desc_if->free_ring_resources(pdata);
 
-err_clk:
-        clk_disable_unprepare(pdata->sysclock);
+err_ptpclk:
+        clk_disable_unprepare(pdata->ptpclk);
+
+err_sysclk:
+        clk_disable_unprepare(pdata->sysclk);
 
         return ret;
 }
@@ -853,8 +1073,9 @@ static int xgbe_close(struct net_device *netdev)
                 pdata->irq_number = 0;
         }
 
-        /* Disable the clock */
-        clk_disable_unprepare(pdata->sysclock);
+        /* Disable the clocks */
+        clk_disable_unprepare(pdata->ptpclk);
+        clk_disable_unprepare(pdata->sysclk);
 
         DBGPR("<--xgbe_close\n");
 
@@ -890,7 +1111,7 @@ static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
 
         /* Calculate preliminary packet info */
         memset(packet, 0, sizeof(*packet));
-        xgbe_packet_info(ring, skb, packet);
+        xgbe_packet_info(pdata, ring, skb, packet);
 
         /* Check that there are enough descriptors available */
         if (packet->rdesc_count > xgbe_tx_avail_desc(ring)) {
@@ -914,6 +1135,8 @@ static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
                 goto tx_netdev_return;
         }
 
+        xgbe_prep_tx_tstamp(pdata, skb, packet);
+
         /* Configure required descriptor fields for transmission */
         hw_if->pre_xmit(channel);
 
@@ -968,6 +1191,27 @@ static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
         return 0;
 }
 
+static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+        int ret;
+
+        switch (cmd) {
+        case SIOCGHWTSTAMP:
+                ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
+                break;
+
+        case SIOCSHWTSTAMP:
+                ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
+                break;
+
+        default:
+                ret = -EOPNOTSUPP;
+        }
+
+        return ret;
+}
+
 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
 {
         struct xgbe_prv_data *pdata = netdev_priv(netdev);
@@ -1069,6 +1313,33 @@ static void xgbe_poll_controller(struct net_device *netdev)
 }
 #endif /* End CONFIG_NET_POLL_CONTROLLER */
 
+static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+        unsigned int offset, queue;
+        u8 i;
+
+        if (tc && (tc != pdata->hw_feat.tc_cnt))
+                return -EINVAL;
+
+        if (tc) {
+                netdev_set_num_tc(netdev, tc);
+                for (i = 0, queue = 0, offset = 0; i < tc; i++) {
+                        while ((queue < pdata->tx_q_count) &&
+                               (pdata->q2tc_map[queue] == i))
+                                queue++;
+
+                        DBGPR("  TC%u using TXq%u-%u\n", i, offset, queue - 1);
+                        netdev_set_tc_queue(netdev, i, queue - offset, offset);
+                        offset = queue;
+                }
+        } else {
+                netdev_reset_tc(netdev);
+        }
+
+        return 0;
+}
+
 static int xgbe_set_features(struct net_device *netdev,
                              netdev_features_t features)
 {
@@ -1109,6 +1380,7 @@ static const struct net_device_ops xgbe_netdev_ops = {
         .ndo_set_rx_mode        = xgbe_set_rx_mode,
         .ndo_set_mac_address    = xgbe_set_mac_address,
         .ndo_validate_addr      = eth_validate_addr,
+        .ndo_do_ioctl           = xgbe_ioctl,
         .ndo_change_mtu         = xgbe_change_mtu,
         .ndo_get_stats64        = xgbe_get_stats64,
         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
@@ -1116,6 +1388,7 @@ static const struct net_device_ops xgbe_netdev_ops = {
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller    = xgbe_poll_controller,
 #endif
+        .ndo_setup_tc           = xgbe_setup_tc,
         .ndo_set_features       = xgbe_set_features,
 };
 
@@ -1202,8 +1475,9 @@ static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
         struct xgbe_packet_data *packet;
         struct net_device *netdev = pdata->netdev;
         struct sk_buff *skb;
-        unsigned int incomplete, error;
-        unsigned int cur_len, put_len, max_len;
+        struct skb_shared_hwtstamps *hwtstamps;
+        unsigned int incomplete, error, context_next, context;
+        unsigned int len, put_len, max_len;
         int received = 0;
 
         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
@@ -1212,22 +1486,33 @@ static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
         if (!ring)
                 return 0;
 
+        rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
         packet = &ring->packet_data;
         while (received < budget) {
                 DBGPR("  cur = %d\n", ring->cur);
 
-                /* Clear the packet data information */
-                memset(packet, 0, sizeof(*packet));
-                skb = NULL;
-                error = 0;
-                cur_len = 0;
+                /* First time in loop see if we need to restore state */
+                if (!received && rdata->state_saved) {
+                        incomplete = rdata->state.incomplete;
+                        context_next = rdata->state.context_next;
+                        skb = rdata->state.skb;
+                        error = rdata->state.error;
+                        len = rdata->state.len;
+                } else {
+                        memset(packet, 0, sizeof(*packet));
+                        incomplete = 0;
+                        context_next = 0;
+                        skb = NULL;
+                        error = 0;
+                        len = 0;
+                }
 
 read_again:
+                rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
+
                 if (ring->dirty > (XGBE_RX_DESC_CNT >> 3))
                         xgbe_rx_refresh(channel);
 
-                rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
-
                 if (hw_if->dev_read(channel))
                         break;
 
@@ -1242,9 +1527,15 @@ read_again:
                 incomplete = XGMAC_GET_BITS(packet->attributes,
                                             RX_PACKET_ATTRIBUTES,
                                             INCOMPLETE);
+                context_next = XGMAC_GET_BITS(packet->attributes,
+                                              RX_PACKET_ATTRIBUTES,
+                                              CONTEXT_NEXT);
+                context = XGMAC_GET_BITS(packet->attributes,
+                                         RX_PACKET_ATTRIBUTES,
+                                         CONTEXT);
 
                 /* Earlier error, just drain the remaining data */
-                if (incomplete && error)
+                if ((incomplete || context_next) && error)
                         goto read_again;
 
                 if (error || packet->errors) {
@@ -1254,30 +1545,37 @@ read_again:
                         continue;
                 }
 
-                put_len = rdata->len - cur_len;
-                if (skb) {
-                        if (pskb_expand_head(skb, 0, put_len, GFP_ATOMIC)) {
-                                DBGPR("pskb_expand_head error\n");
-                                if (incomplete) {
-                                        error = 1;
-                                        goto read_again;
+                if (!context) {
+                        put_len = rdata->len - len;
+                        if (skb) {
+                                if (pskb_expand_head(skb, 0, put_len,
+                                                     GFP_ATOMIC)) {
+                                        DBGPR("pskb_expand_head error\n");
+                                        if (incomplete) {
+                                                error = 1;
+                                                goto read_again;
+                                        }
+
+                                        dev_kfree_skb(skb);
+                                        continue;
                                 }
-
-                                dev_kfree_skb(skb);
-                                continue;
+                                memcpy(skb_tail_pointer(skb), rdata->skb->data,
+                                       put_len);
+                        } else {
+                                skb = rdata->skb;
+                                rdata->skb = NULL;
                         }
-                        memcpy(skb_tail_pointer(skb), rdata->skb->data,
-                               put_len);
-                } else {
-                        skb = rdata->skb;
-                        rdata->skb = NULL;
+                        skb_put(skb, put_len);
+                        len += put_len;
                 }
-                skb_put(skb, put_len);
-                cur_len += put_len;
 
-                if (incomplete)
+                if (incomplete || context_next)
                         goto read_again;
 
+                /* Stray Context Descriptor? */
+                if (!skb)
+                        continue;
+
                 /* Be sure we don't exceed the configured MTU */
                 max_len = netdev->mtu + ETH_HLEN;
                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
@@ -1304,6 +1602,16 @@ read_again:
                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
                                                packet->vlan_ctag);
 
+                if (XGMAC_GET_BITS(packet->attributes,
+                                   RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
+                        u64 nsec;
+
+                        nsec = timecounter_cyc2time(&pdata->tstamp_tc,
+                                                    packet->rx_tstamp);
+                        hwtstamps = skb_hwtstamps(skb);
+                        hwtstamps->hwtstamp = ns_to_ktime(nsec);
+                }
+
                 skb->dev = netdev;
                 skb->protocol = eth_type_trans(skb, netdev);
                 skb_record_rx_queue(skb, channel->queue_index);
@@ -1313,6 +1621,17 @@ read_again:
                 napi_gro_receive(&pdata->napi, skb);
         }
 
+        /* Check if we need to save state before leaving */
+        if (received && (incomplete || context_next)) {
+                rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
+                rdata->state_saved = 1;
+                rdata->state.incomplete = incomplete;
+                rdata->state.context_next = context_next;
+                rdata->state.skb = skb;
+                rdata->state.len = len;
+                rdata->state.error = error;
+        }
+
         DBGPR("<--xgbe_rx_poll: received = %d\n", received);
 
         return received;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
index f7405261f23e..6005b6021f78 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
@@ -116,6 +116,7 @@
 
 #include <linux/spinlock.h>
 #include <linux/phy.h>
+#include <linux/net_tstamp.h>
 
 #include "xgbe.h"
 #include "xgbe-common.h"
@@ -326,10 +327,19 @@ static int xgbe_set_settings(struct net_device *netdev,
             (cmd->autoneg != AUTONEG_DISABLE))
                 goto unlock;
 
-        if ((cmd->autoneg == AUTONEG_DISABLE) &&
-            (((speed != SPEED_10000) && (speed != SPEED_1000)) ||
-             (cmd->duplex != DUPLEX_FULL)))
-                goto unlock;
+        if (cmd->autoneg == AUTONEG_DISABLE) {
+                switch (speed) {
+                case SPEED_10000:
+                case SPEED_2500:
+                case SPEED_1000:
+                        break;
+                default:
+                        goto unlock;
+                }
+
+                if (cmd->duplex != DUPLEX_FULL)
+                        goto unlock;
+        }
 
         cmd->advertising &= phydev->supported;
         if ((cmd->autoneg == AUTONEG_ENABLE) && !cmd->advertising)
@@ -480,6 +490,39 @@ static int xgbe_set_coalesce(struct net_device *netdev,
         return 0;
 }
 
+static int xgbe_get_ts_info(struct net_device *netdev,
+                            struct ethtool_ts_info *ts_info)
+{
+        struct xgbe_prv_data *pdata = netdev_priv(netdev);
+
+        ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
+                                   SOF_TIMESTAMPING_RX_SOFTWARE |
+                                   SOF_TIMESTAMPING_SOFTWARE |
+                                   SOF_TIMESTAMPING_TX_HARDWARE |
+                                   SOF_TIMESTAMPING_RX_HARDWARE |
+                                   SOF_TIMESTAMPING_RAW_HARDWARE;
+
+        if (pdata->ptp_clock)
+                ts_info->phc_index = ptp_clock_index(pdata->ptp_clock);
+        else
+                ts_info->phc_index = -1;
+
+        ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
+        ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+                              (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
+                              (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
+                              (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
+                              (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
+                              (1 << HWTSTAMP_FILTER_ALL);
+
+        return 0;
+}
+
 static const struct ethtool_ops xgbe_ethtool_ops = {
         .get_settings = xgbe_get_settings,
         .set_settings = xgbe_set_settings,
@@ -492,6 +535,7 @@ static const struct ethtool_ops xgbe_ethtool_ops = {
         .get_strings = xgbe_get_strings,
         .get_ethtool_stats = xgbe_get_ethtool_stats,
         .get_sset_count = xgbe_get_sset_count,
+        .get_ts_info = xgbe_get_ts_info,
 };
 
 struct ethtool_ops *xgbe_get_ethtool_ops(void)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
index e56c3d45b30e..ec977d36063f 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
@@ -245,6 +245,7 @@ static int xgbe_probe(struct platform_device *pdev)
 
         spin_lock_init(&pdata->lock);
         mutex_init(&pdata->xpcs_mutex);
+        spin_lock_init(&pdata->tstamp_lock);
 
         /* Set and validate the number of descriptors for a ring */
         BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
@@ -265,10 +266,18 @@ static int xgbe_probe(struct platform_device *pdev)
         }
 
         /* Obtain the system clock setting */
-        pdata->sysclock = devm_clk_get(dev, NULL);
-        if (IS_ERR(pdata->sysclock)) {
-                dev_err(dev, "devm_clk_get failed\n");
-                ret = PTR_ERR(pdata->sysclock);
+        pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
+        if (IS_ERR(pdata->sysclk)) {
+                dev_err(dev, "dma devm_clk_get failed\n");
+                ret = PTR_ERR(pdata->sysclk);
+                goto err_io;
+        }
+
+        /* Obtain the PTP clock setting */
+        pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
+        if (IS_ERR(pdata->ptpclk)) {
+                dev_err(dev, "ptp devm_clk_get failed\n");
+                ret = PTR_ERR(pdata->ptpclk);
                 goto err_io;
         }
 
@@ -346,9 +355,16 @@ static int xgbe_probe(struct platform_device *pdev)
         /* Set default configuration data */
         xgbe_default_config(pdata);
 
-        /* Calculate the number of Tx and Rx rings to be created */
+        /* Calculate the number of Tx and Rx rings to be created
+         *  -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
+         *   the number of Tx queues to the number of Tx channels
+         *   enabled
+         *  -Rx (DMA) Channels do not map 1-to-1 so use the actual
+         *   number of Rx queues
+         */
         pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
                                      pdata->hw_feat.tx_ch_cnt);
+        pdata->tx_q_count = pdata->tx_ring_count;
         ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
         if (ret) {
                 dev_err(dev, "error setting real tx queue count\n");
@@ -358,6 +374,7 @@ static int xgbe_probe(struct platform_device *pdev)
         pdata->rx_ring_count = min_t(unsigned int,
                                      netif_get_num_default_rss_queues(),
                                      pdata->hw_feat.rx_ch_cnt);
+        pdata->rx_q_count = pdata->hw_feat.rx_q_cnt;
         ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
         if (ret) {
                 dev_err(dev, "error setting real rx queue count\n");
@@ -383,9 +400,12 @@ static int xgbe_probe(struct platform_device *pdev)
         if (ret)
                 goto err_bus_id;
 
-        /* Set network and ethtool operations */
+        /* Set device operations */
         netdev->netdev_ops = xgbe_get_netdev_ops();
         netdev->ethtool_ops = xgbe_get_ethtool_ops();
+#ifdef CONFIG_AMD_XGBE_DCB
+        netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
+#endif
 
         /* Set device features */
         netdev->hw_features = NETIF_F_SG |
@@ -420,6 +440,8 @@ static int xgbe_probe(struct platform_device *pdev)
                 goto err_reg_netdev;
         }
 
+        xgbe_ptp_register(pdata);
+
         xgbe_debugfs_init(pdata);
 
         netdev_notice(netdev, "net device enabled\n");
@@ -452,6 +474,8 @@ static int xgbe_remove(struct platform_device *pdev)
 
         xgbe_debugfs_exit(pdata);
 
+        xgbe_ptp_unregister(pdata);
+
         unregister_netdev(netdev);
 
         xgbe_mdio_unregister(pdata);
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
new file mode 100644
index 000000000000..37e64cfa5718
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
@@ -0,0 +1,285 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ * License 2: Modified BSD
+ *
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
+ *     under any End User Software License Agreement or Agreement for Licensed
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
+ *     granted, free of charge, to any person obtaining a copy of this software
+ *     annotated with this license and the Software, to deal in the Software
+ *     without restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ *     of the Software, and to permit persons to whom the Software is furnished
+ *     to do so, subject to the following conditions:
+ *
+ *     The above copyright notice and this permission notice shall be included
+ *     in all copies or substantial portions of the Software.
+ *
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ *     THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/net_tstamp.h>
+
+#include "xgbe.h"
+#include "xgbe-common.h"
+
+
+static cycle_t xgbe_cc_read(const struct cyclecounter *cc)
+{
+        struct xgbe_prv_data *pdata = container_of(cc,
+                                                   struct xgbe_prv_data,
+                                                   tstamp_cc);
+        u64 nsec;
+
+        nsec = pdata->hw_if.get_tstamp_time(pdata);
+
+        return nsec;
+}
+
+static int xgbe_adjfreq(struct ptp_clock_info *info, s32 delta)
+{
+        struct xgbe_prv_data *pdata = container_of(info,
+                                                   struct xgbe_prv_data,
+                                                   ptp_clock_info);
+        unsigned long flags;
+        u64 adjust;
+        u32 addend, diff;
+        unsigned int neg_adjust = 0;
+
+        if (delta < 0) {
+                neg_adjust = 1;
+                delta = -delta;
+        }
+
+        adjust = pdata->tstamp_addend;
+        adjust *= delta;
+        diff = div_u64(adjust, 1000000000UL);
+
+        addend = (neg_adjust) ? pdata->tstamp_addend - diff :
+                                pdata->tstamp_addend + diff;
+
+        spin_lock_irqsave(&pdata->tstamp_lock, flags);
+
+        pdata->hw_if.update_tstamp_addend(pdata, addend);
+
+        spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+
+        return 0;
+}
+
+static int xgbe_adjtime(struct ptp_clock_info *info, s64 delta)
+{
+        struct xgbe_prv_data *pdata = container_of(info,
+                                                   struct xgbe_prv_data,
+                                                   ptp_clock_info);
+        unsigned long flags;
+        u64 nsec;
+
+        spin_lock_irqsave(&pdata->tstamp_lock, flags);
+
+        nsec = timecounter_read(&pdata->tstamp_tc);
+
+        nsec += delta;
+        timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec);
+
+        spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+
+        return 0;
+}
+
+static int xgbe_gettime(struct ptp_clock_info *info, struct timespec *ts)
+{
+        struct xgbe_prv_data *pdata = container_of(info,
+                                                   struct xgbe_prv_data,
+                                                   ptp_clock_info);
+        unsigned long flags;
+        u64 nsec;
+
+        spin_lock_irqsave(&pdata->tstamp_lock, flags);
+
+        nsec = timecounter_read(&pdata->tstamp_tc);
+
+        spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+
+        *ts = ns_to_timespec(nsec);
+
+        return 0;
+}
+
+static int xgbe_settime(struct ptp_clock_info *info, const struct timespec *ts)
+{
+        struct xgbe_prv_data *pdata = container_of(info,
+                                                   struct xgbe_prv_data,
+                                                   ptp_clock_info);
+        unsigned long flags;
+        u64 nsec;
+
+        nsec = timespec_to_ns(ts);
+
+        spin_lock_irqsave(&pdata->tstamp_lock, flags);
+
+        timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec);
+
+        spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
+
+        return 0;
+}
+
+static int xgbe_enable(struct ptp_clock_info *info,
+                       struct ptp_clock_request *request, int on)
+{
+        return -EOPNOTSUPP;
+}
+
+void xgbe_ptp_register(struct xgbe_prv_data *pdata)
+{
+        struct ptp_clock_info *info = &pdata->ptp_clock_info;
+        struct ptp_clock *clock;
+        struct cyclecounter *cc = &pdata->tstamp_cc;
+        u64 dividend;
+
+        snprintf(info->name, sizeof(info->name), "%s",
+                 netdev_name(pdata->netdev));
+        info->owner = THIS_MODULE;
+        info->max_adj = clk_get_rate(pdata->ptpclk);
+        info->adjfreq = xgbe_adjfreq;
+        info->adjtime = xgbe_adjtime;
+        info->gettime = xgbe_gettime;
+        info->settime = xgbe_settime;
+        info->enable = xgbe_enable;
+
+        clock = ptp_clock_register(info, pdata->dev);
+        if (IS_ERR(clock)) {
+                dev_err(pdata->dev, "ptp_clock_register failed\n");
+                return;
+        }
+
+        pdata->ptp_clock = clock;
+
+        /* Calculate the addend:
+         *   addend = 2^32 / (PTP ref clock / 50Mhz)
+         *          = (2^32 * 50Mhz) / PTP ref clock
+         */
+        dividend = 50000000;
+        dividend <<= 32;
+        pdata->tstamp_addend = div_u64(dividend, clk_get_rate(pdata->ptpclk));
+
+        /* Setup the timecounter */
+        cc->read = xgbe_cc_read;
+        cc->mask = CLOCKSOURCE_MASK(64);
+        cc->mult = 1;
+        cc->shift = 0;
+
+        timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
+                         ktime_to_ns(ktime_get_real()));
+
+        /* Disable all timestamping to start */
+        XGMAC_IOWRITE(pdata, MAC_TCR, 0);
+        pdata->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
+        pdata->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
+}
+
+void xgbe_ptp_unregister(struct xgbe_prv_data *pdata)
+{
+        if (pdata->ptp_clock)
+                ptp_clock_unregister(pdata->ptp_clock);
+}
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 9e24b296e272..07bf70a82908 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -123,6 +123,10 @@
 #include <linux/phy.h>
 #include <linux/if_vlan.h>
 #include <linux/bitops.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/clocksource.h>
+#include <linux/net_tstamp.h>
+#include <net/dcbnl.h>
 
 
 #define XGBE_DRV_NAME           "amd-xgbe"
@@ -141,6 +145,7 @@
 #define XGBE_RX_BUF_ALIGN       64
 
 #define XGBE_MAX_DMA_CHANNELS   16
+#define XGBE_MAX_QUEUES         16
 
 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 #define XGBE_DMA_OS_AXDOMAIN    0x2
@@ -164,6 +169,16 @@
 #define XGBE_PHY_NAME           "amd_xgbe_phy"
 #define XGBE_PRTAD              0
 
+/* Device-tree clock names */
+#define XGBE_DMA_CLOCK          "dma_clk"
+#define XGBE_PTP_CLOCK          "ptp_clk"
+
+/* Timestamp support - values based on 50MHz PTP clock
+ *   50MHz => 20 nsec
+ */
+#define XGBE_TSTAMP_SSINC       20
+#define XGBE_TSTAMP_SNSINC      0
+
 /* Driver PMT macros */
 #define XGMAC_DRIVER_CONTEXT    1
 #define XGMAC_IOCTL_CONTEXT     2
@@ -171,7 +186,7 @@
 #define XGBE_FIFO_SIZE_B(x)     (x)
 #define XGBE_FIFO_SIZE_KB(x)    (x * 1024)
 
-#define XGBE_TC_CNT             2
+#define XGBE_TC_MIN_QUANTUM     10
 
 /* Helper macro for descriptor handling
  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
@@ -214,6 +229,8 @@ struct xgbe_packet_data {
         unsigned short mss;
 
         unsigned short vlan_ctag;
+
+        u64 rx_tstamp;
 };
 
 /* Common Rx and Tx descriptor mapping */
@@ -242,6 +259,20 @@ struct xgbe_ring_data {
         unsigned int interrupt;         /* Interrupt indicator */
 
         unsigned int mapped_as_page;
+
+        /* Incomplete receive save location.  If the budget is exhausted
+         * or the last descriptor (last normal descriptor or a following
+         * context descriptor) has not been DMA'd yet the current state
+         * of the receive processing needs to be saved.
+         */
+        unsigned int state_saved;
+        struct {
+                unsigned int incomplete;
+                unsigned int context_next;
+                struct sk_buff *skb;
+                unsigned int len;
+                unsigned int error;
+        } state;
 };
 
 struct xgbe_ring {
@@ -467,6 +498,18 @@ struct xgbe_hw_if {
         void (*rx_mmc_int)(struct xgbe_prv_data *);
         void (*tx_mmc_int)(struct xgbe_prv_data *);
         void (*read_mmc_stats)(struct xgbe_prv_data *);
+
+        /* For Timestamp config */
+        int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
+        void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
+        void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
+                                unsigned int nsec);
+        u64 (*get_tstamp_time)(struct xgbe_prv_data *);
+        u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
+
+        /* For Data Center Bridging config */
+        void (*config_dcb_tc)(struct xgbe_prv_data *);
+        void (*config_dcb_pfc)(struct xgbe_prv_data *);
 };
 
 struct xgbe_desc_if {
@@ -508,6 +551,7 @@ struct xgbe_hw_features {
         unsigned int tso;               /* TCP Segmentation Offload */
         unsigned int dma_debug;         /* DMA Debug Registers */
         unsigned int rss;               /* Receive Side Scaling */
+        unsigned int tc_cnt;            /* Number of Traffic Classes */
         unsigned int hash_table_size;   /* Hash Table Size */
         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 
@@ -553,6 +597,9 @@ struct xgbe_prv_data {
         unsigned int rx_ring_count;
         unsigned int rx_desc_count;
 
+        unsigned int tx_q_count;
+        unsigned int rx_q_count;
+
         /* Tx/Rx common settings */
         unsigned int pblx8;
 
@@ -607,8 +654,27 @@ struct xgbe_prv_data {
         /* Filtering support */
         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 
-        /* System clock value used for Rx watchdog */
-        struct clk *sysclock;
+        /* Device clocks */
+        struct clk *sysclk;
+        struct clk *ptpclk;
+
+        /* Timestamp support */
+        spinlock_t tstamp_lock;
+        struct ptp_clock_info ptp_clock_info;
+        struct ptp_clock *ptp_clock;
+        struct hwtstamp_config tstamp_config;
+        struct cyclecounter tstamp_cc;
+        struct timecounter tstamp_tc;
+        unsigned int tstamp_addend;
+        struct work_struct tx_tstamp_work;
+        struct sk_buff *tx_tstamp_skb;
+        u64 tx_tstamp;
+
+        /* DCB support */
+        struct ieee_ets *ets;
+        struct ieee_pfc *pfc;
+        unsigned int q2tc_map[XGBE_MAX_QUEUES];
+        unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 
         /* Hardware features of the device */
         struct xgbe_hw_features hw_feat;
@@ -635,10 +701,15 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 struct net_device_ops *xgbe_get_netdev_ops(void);
 struct ethtool_ops *xgbe_get_ethtool_ops(void);
+#ifdef CONFIG_AMD_XGBE_DCB
+const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
+#endif
 
 int xgbe_mdio_register(struct xgbe_prv_data *);
 void xgbe_mdio_unregister(struct xgbe_prv_data *);
 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
+void xgbe_ptp_register(struct xgbe_prv_data *);
+void xgbe_ptp_unregister(struct xgbe_prv_data *);
 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
                        unsigned int);
 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
index b57c22442867..388e3029165a 100644
--- a/drivers/net/phy/amd-xgbe-phy.c
+++ b/drivers/net/phy/amd-xgbe-phy.c
@@ -74,7 +74,6 @@
 #include <linux/of_platform.h>
 #include <linux/of_device.h>
 #include <linux/uaccess.h>
-#include <asm/irq.h>
 
 
 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
@@ -85,6 +84,8 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define XGBE_PHY_ID     0x000162d0
 #define XGBE_PHY_MASK   0xfffffff0
 
+#define XGBE_PHY_SPEEDSET_PROPERTY      "amd,speed-set"
+
 #define XGBE_AN_INT_CMPLT               0x01
 #define XGBE_AN_INC_LINK                0x02
 #define XGBE_AN_PG_RCV                  0x04
@@ -94,6 +95,8 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define XNP_MP_FORMATTED                (1 << 13)
 #define XNP_NP_EXCHANGE                 (1 << 15)
 
+#define XGBE_PHY_RATECHANGE_COUNT       100
+
 #ifndef MDIO_PMA_10GBR_PMD_CTRL
 #define MDIO_PMA_10GBR_PMD_CTRL         0x0096
 #endif
@@ -116,10 +119,13 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #endif
 
 /* SerDes integration register offsets */
+#define SIR0_KR_RT_1                    0x002c
 #define SIR0_STATUS                     0x0040
 #define SIR1_SPEED                      0x0000
 
 /* SerDes integration register entry bit positions and sizes */
+#define SIR0_KR_RT_1_RESET_INDEX        11
+#define SIR0_KR_RT_1_RESET_WIDTH        1
 #define SIR0_STATUS_RX_READY_INDEX      0
 #define SIR0_STATUS_RX_READY_WIDTH      1
 #define SIR0_STATUS_TX_READY_INDEX      8
@@ -145,7 +151,7 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 
 #define SPEED_2500_CDR                  0x2
 #define SPEED_2500_PLL                  0x0
-#define SPEED_2500_RATE                 0x2
+#define SPEED_2500_RATE                 0x1
 #define SPEED_2500_TXAMP                0xf
 #define SPEED_2500_WORD                 0x1
 
@@ -192,6 +198,16 @@ do {									\
         (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index));     \
 } while (0)
 
+#define XSIR_GET_BITS(_var, _prefix, _field)                            \
+        GET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH)
+
+#define XSIR_SET_BITS(_var, _prefix, _field, _val)                      \
+        SET_BITS((_var),                                                \
+                 _prefix##_##_field##_INDEX,                            \
+                 _prefix##_##_field##_WIDTH, (_val))
+
 /* Macros for reading or writing SerDes integration registers
  *  The ioread macros will get bit fields or full values using the
  *  register definitions formed using the input names
@@ -292,6 +308,11 @@ enum amd_xgbe_phy_mode {
         AMD_XGBE_MODE_KX,
 };
 
+enum amd_xgbe_phy_speedset {
+        AMD_XGBE_PHY_SPEEDSET_1000_10000,
+        AMD_XGBE_PHY_SPEEDSET_2500_10000,
+};
+
 struct amd_xgbe_phy_priv {
         struct platform_device *pdev;
         struct device *dev;
@@ -311,6 +332,7 @@ struct amd_xgbe_phy_priv {
         /* Maintain link status for re-starting auto-negotiation */
         unsigned int link;
         enum amd_xgbe_phy_mode mode;
+        unsigned int speed_set;
 
         /* Auto-negotiation state machine support */
         struct mutex an_mutex;
@@ -380,14 +402,25 @@ static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
+        unsigned int wait;
+        u16 status;
 
         /* Release Rx and Tx ratechange */
         XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
 
         /* Wait for Rx and Tx ready */
-        while (!XSIR0_IOREAD_BITS(priv, SIR0_STATUS, RX_READY) &&
-               !XSIR0_IOREAD_BITS(priv, SIR0_STATUS, TX_READY))
+        wait = XGBE_PHY_RATECHANGE_COUNT;
+        while (wait--) {
                 usleep_range(10, 20);
+
+                status = XSIR0_IOREAD(priv, SIR0_STATUS);
+                if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
+                    XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
+                        return;
+        }
+
+        netdev_err(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
+                   status);
 }
 
 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
@@ -546,10 +579,14 @@ static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
         int ret;
 
         /* If we are in KR switch to KX, and vice-versa */
-        if (priv->mode == AMD_XGBE_MODE_KR)
-                ret = amd_xgbe_phy_gmii_mode(phydev);
-        else
+        if (priv->mode == AMD_XGBE_MODE_KR) {
+                if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
+                        ret = amd_xgbe_phy_gmii_mode(phydev);
+                else
+                        ret = amd_xgbe_phy_gmii_2500_mode(phydev);
+        } else {
                 ret = amd_xgbe_phy_xgmii_mode(phydev);
+        }
 
         return ret;
 }
@@ -602,9 +639,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
         if (ret < 0)
                 return AMD_XGBE_AN_ERROR;
 
+        XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
+
         ret |= 0x01;
         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
 
+        XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
+
         return AMD_XGBE_AN_EVENT;
 }
 
@@ -713,7 +754,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
         else
                 ret &= ~0x80;
 
-        if (phydev->supported & SUPPORTED_1000baseKX_Full)
+        if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
+            (phydev->supported & SUPPORTED_2500baseX_Full))
                 ret |= 0x20;
         else
                 ret &= ~0x20;
@@ -815,6 +857,7 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
         struct phy_device *phydev = priv->phydev;
         enum amd_xgbe_phy_an cur_state;
         int sleep;
+        unsigned int an_supported = 0;
 
         while (1) {
                 mutex_lock(&priv->an_mutex);
@@ -824,6 +867,7 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
                 switch (priv->an_state) {
                 case AMD_XGBE_AN_START:
                         priv->an_state = amd_xgbe_an_start(phydev);
+                        an_supported = 0;
                         break;
 
                 case AMD_XGBE_AN_EVENT:
@@ -832,6 +876,7 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
 
                 case AMD_XGBE_AN_PAGE_RECEIVED:
                         priv->an_state = amd_xgbe_an_page_received(phydev);
+                        an_supported++;
                         break;
 
                 case AMD_XGBE_AN_INCOMPAT_LINK:
@@ -839,6 +884,11 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
                         break;
 
                 case AMD_XGBE_AN_COMPLETE:
+                        netdev_info(phydev->attached_dev, "%s successful\n",
+                                    an_supported ? "Auto negotiation"
+                                                 : "Parallel detection");
+                        /* fall through */
+
                 case AMD_XGBE_AN_NO_LINK:
                 case AMD_XGBE_AN_EXIT:
                         goto exit_unlock;
@@ -896,14 +946,22 @@ static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
 
 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
 {
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
+
         /* Initialize supported features */
         phydev->supported = SUPPORTED_Autoneg;
         phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
         phydev->supported |= SUPPORTED_Backplane;
-        phydev->supported |= SUPPORTED_1000baseKX_Full |
-                             SUPPORTED_2500baseX_Full;
         phydev->supported |= SUPPORTED_10000baseKR_Full |
                              SUPPORTED_10000baseR_FEC;
+        switch (priv->speed_set) {
+        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
+                phydev->supported |= SUPPORTED_1000baseKX_Full;
+                break;
+        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
+                phydev->supported |= SUPPORTED_2500baseX_Full;
+                break;
+        }
         phydev->advertising = phydev->supported;
 
         /* Turn off and clear interrupts */
@@ -1020,9 +1078,9 @@ static int amd_xgbe_phy_update_link(struct phy_device *phydev)
          * (re-)established (cable connected after the interface is
          * up, etc.), the link status may report no link. If there
          * is no link, try switching modes and checking the status
-         * again.
+         * again if auto negotiation is enabled.
          */
-        check_again = 1;
+        check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0;
 again:
         /* Link status is latched low, so read once to clear
          * and then read again to get current state
@@ -1038,8 +1096,10 @@ again:
         phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
 
         if (!phydev->link) {
-                ret = amd_xgbe_phy_switch_mode(phydev);
                 if (check_again) {
+                        ret = amd_xgbe_phy_switch_mode(phydev);
+                        if (ret < 0)
+                                return ret;
                         check_again = 0;
                         goto again;
                 }
@@ -1059,6 +1119,7 @@ again:
 
 static int amd_xgbe_phy_read_status(struct phy_device *phydev)
 {
+        struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
         int ret, mode, ad_ret, lp_ret;
 
@@ -1108,9 +1169,19 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
                                         return ret;
                         }
                 } else {
-                        phydev->speed = SPEED_1000;
+                        int (*mode_fcn)(struct phy_device *);
+
+                        if (priv->speed_set ==
+                            AMD_XGBE_PHY_SPEEDSET_1000_10000) {
+                                phydev->speed = SPEED_1000;
+                                mode_fcn = amd_xgbe_phy_gmii_mode;
+                        } else {
+                                phydev->speed = SPEED_2500;
+                                mode_fcn = amd_xgbe_phy_gmii_2500_mode;
+                        }
+
                         if (mode == MDIO_PCS_CTRL2_10GBR) {
-                                ret = amd_xgbe_phy_gmii_mode(phydev);
+                                ret = mode_fcn(phydev);
                                 if (ret < 0)
                                         return ret;
                         }
@@ -1118,8 +1189,15 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
 
                 phydev->duplex = DUPLEX_FULL;
         } else {
-                phydev->speed = (mode == MDIO_PCS_CTRL2_10GBR) ? SPEED_10000
-                                                               : SPEED_1000;
+                if (mode == MDIO_PCS_CTRL2_10GBR) {
+                        phydev->speed = SPEED_10000;
+                } else {
+                        if (priv->speed_set ==
+                            AMD_XGBE_PHY_SPEEDSET_1000_10000)
+                                phydev->speed = SPEED_1000;
+                        else
+                                phydev->speed = SPEED_2500;
+                }
                 phydev->duplex = DUPLEX_FULL;
                 phydev->pause = 0;
                 phydev->asym_pause = 0;
@@ -1176,6 +1254,8 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
         struct platform_device *pdev;
         struct device *dev;
         char *wq_name;
+        const __be32 *property;
+        unsigned int speed_set;
         int ret;
 
         if (!phydev->dev.of_node)
@@ -1227,6 +1307,26 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
                 goto err_sir0;
         }
 
+        /* Get the device speed set property */
+        speed_set = 0;
+        property = of_get_property(dev->of_node, XGBE_PHY_SPEEDSET_PROPERTY,
+                                   NULL);
+        if (property)
+                speed_set = be32_to_cpu(*property);
+
+        switch (speed_set) {
+        case 0:
+                priv->speed_set = AMD_XGBE_PHY_SPEEDSET_1000_10000;
+                break;
+        case 1:
+                priv->speed_set = AMD_XGBE_PHY_SPEEDSET_2500_10000;
+                break;
+        default:
+                dev_err(dev, "invalid amd,speed-set property\n");
+                ret = -EINVAL;
+                goto err_sir1;
+        }
+
         priv->link = 1;
 
         ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);