diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2016-06-23 15:35:29 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2016-06-23 15:35:29 -0400 |
commit | 6589c1caa778c61099b0892b8f20b03f9e523687 (patch) | |
tree | cc0396f2d11a73cf23d437a0e1f9ec5b26d76123 | |
parent | d16dcd3d18759eb955e0325572d07457f93494f5 (diff) | |
parent | e04558cbfe61cd06d762eaaa587616798d9b65b6 (diff) |
Merge tag 'irqchip-core-4.8' of git://git.infradead.org/users/jcooper/linux into irq/core
Pull irqchip core changes from Jason Cooper:
- bcm283x avoid handle_IRQ
- Fix sparse warnings on __iomem
- Fix static functions
- Fix missing includes
- Replace __raw IO accessors to support big endian
-rw-r--r-- | drivers/irqchip/exynos-combiner.c | 14 | ||||
-rw-r--r-- | drivers/irqchip/irq-armada-370-xp.c | 2 | ||||
-rw-r--r-- | drivers/irqchip/irq-bcm2835.c | 3 | ||||
-rw-r--r-- | drivers/irqchip/irq-bcm2836.c | 6 | ||||
-rw-r--r-- | drivers/irqchip/irq-bcm7120-l2.c | 10 | ||||
-rw-r--r-- | drivers/irqchip/irq-brcmstb-l2.c | 4 | ||||
-rw-r--r-- | drivers/irqchip/irq-gic-v2m.c | 1 | ||||
-rw-r--r-- | drivers/irqchip/irq-omap-intc.c | 2 | ||||
-rw-r--r-- | drivers/irqchip/irq-s3c24xx.c | 36 | ||||
-rw-r--r-- | drivers/irqchip/irq-sirfsoc.c | 11 | ||||
-rw-r--r-- | drivers/irqchip/irq-tegra.c | 4 | ||||
-rw-r--r-- | drivers/irqchip/irq-vic.c | 5 |
12 files changed, 53 insertions, 45 deletions
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index ead15be2d20a..b78a169c9c83 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c | |||
@@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data) | |||
55 | { | 55 | { |
56 | u32 mask = 1 << (data->hwirq % 32); | 56 | u32 mask = 1 << (data->hwirq % 32); |
57 | 57 | ||
58 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); | 58 | writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); |
59 | } | 59 | } |
60 | 60 | ||
61 | static void combiner_unmask_irq(struct irq_data *data) | 61 | static void combiner_unmask_irq(struct irq_data *data) |
62 | { | 62 | { |
63 | u32 mask = 1 << (data->hwirq % 32); | 63 | u32 mask = 1 << (data->hwirq % 32); |
64 | 64 | ||
65 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); | 65 | writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET); |
66 | } | 66 | } |
67 | 67 | ||
68 | static void combiner_handle_cascade_irq(struct irq_desc *desc) | 68 | static void combiner_handle_cascade_irq(struct irq_desc *desc) |
@@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc) | |||
75 | chained_irq_enter(chip, desc); | 75 | chained_irq_enter(chip, desc); |
76 | 76 | ||
77 | spin_lock(&irq_controller_lock); | 77 | spin_lock(&irq_controller_lock); |
78 | status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); | 78 | status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); |
79 | spin_unlock(&irq_controller_lock); | 79 | spin_unlock(&irq_controller_lock); |
80 | status &= chip_data->irq_mask; | 80 | status &= chip_data->irq_mask; |
81 | 81 | ||
@@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data, | |||
135 | combiner_data->parent_irq = irq; | 135 | combiner_data->parent_irq = irq; |
136 | 136 | ||
137 | /* Disable all interrupts */ | 137 | /* Disable all interrupts */ |
138 | __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); | 138 | writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); |
139 | } | 139 | } |
140 | 140 | ||
141 | static int combiner_irq_domain_xlate(struct irq_domain *d, | 141 | static int combiner_irq_domain_xlate(struct irq_domain *d, |
@@ -218,7 +218,7 @@ static int combiner_suspend(void) | |||
218 | 218 | ||
219 | for (i = 0; i < max_nr; i++) | 219 | for (i = 0; i < max_nr; i++) |
220 | combiner_data[i].pm_save = | 220 | combiner_data[i].pm_save = |
221 | __raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET); | 221 | readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET); |
222 | 222 | ||
223 | return 0; | 223 | return 0; |
224 | } | 224 | } |
@@ -235,9 +235,9 @@ static void combiner_resume(void) | |||
235 | int i; | 235 | int i; |
236 | 236 | ||
237 | for (i = 0; i < max_nr; i++) { | 237 | for (i = 0; i < max_nr; i++) { |
238 | __raw_writel(combiner_data[i].irq_mask, | 238 | writel_relaxed(combiner_data[i].irq_mask, |
239 | combiner_data[i].base + COMBINER_ENABLE_CLEAR); | 239 | combiner_data[i].base + COMBINER_ENABLE_CLEAR); |
240 | __raw_writel(combiner_data[i].pm_save, | 240 | writel_relaxed(combiner_data[i].pm_save, |
241 | combiner_data[i].base + COMBINER_ENABLE_SET); | 241 | combiner_data[i].base + COMBINER_ENABLE_SET); |
242 | } | 242 | } |
243 | } | 243 | } |
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index e7dc6cbda2a1..7c42b1d13faf 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c | |||
@@ -541,7 +541,7 @@ static void armada_370_xp_mpic_resume(void) | |||
541 | writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); | 541 | writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); |
542 | } | 542 | } |
543 | 543 | ||
544 | struct syscore_ops armada_370_xp_mpic_syscore_ops = { | 544 | static struct syscore_ops armada_370_xp_mpic_syscore_ops = { |
545 | .suspend = armada_370_xp_mpic_suspend, | 545 | .suspend = armada_370_xp_mpic_suspend, |
546 | .resume = armada_370_xp_mpic_resume, | 546 | .resume = armada_370_xp_mpic_resume, |
547 | }; | 547 | }; |
diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c index bf9cc5f2e839..44d7c38dde47 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c | |||
@@ -52,7 +52,6 @@ | |||
52 | #include <linux/irqdomain.h> | 52 | #include <linux/irqdomain.h> |
53 | 53 | ||
54 | #include <asm/exception.h> | 54 | #include <asm/exception.h> |
55 | #include <asm/mach/irq.h> | ||
56 | 55 | ||
57 | /* Put the bank and irq (32 bits) into the hwirq */ | 56 | /* Put the bank and irq (32 bits) into the hwirq */ |
58 | #define MAKE_HWIRQ(b, n) ((b << 5) | (n)) | 57 | #define MAKE_HWIRQ(b, n) ((b << 5) | (n)) |
@@ -242,7 +241,7 @@ static void __exception_irq_entry bcm2835_handle_irq( | |||
242 | u32 hwirq; | 241 | u32 hwirq; |
243 | 242 | ||
244 | while ((hwirq = get_next_armctrl_hwirq()) != ~0) | 243 | while ((hwirq = get_next_armctrl_hwirq()) != ~0) |
245 | handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); | 244 | handle_domain_irq(intc.domain, hwirq, regs); |
246 | } | 245 | } |
247 | 246 | ||
248 | static void bcm2836_chained_handle_irq(struct irq_desc *desc) | 247 | static void bcm2836_chained_handle_irq(struct irq_desc *desc) |
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c index 72ff1d5c5de6..df1949c0aa23 100644 --- a/drivers/irqchip/irq-bcm2836.c +++ b/drivers/irqchip/irq-bcm2836.c | |||
@@ -180,7 +180,7 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs) | |||
180 | } else if (stat) { | 180 | } else if (stat) { |
181 | u32 hwirq = ffs(stat) - 1; | 181 | u32 hwirq = ffs(stat) - 1; |
182 | 182 | ||
183 | handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); | 183 | handle_domain_irq(intc.domain, hwirq, regs); |
184 | } | 184 | } |
185 | } | 185 | } |
186 | 186 | ||
@@ -224,8 +224,8 @@ static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = { | |||
224 | }; | 224 | }; |
225 | 225 | ||
226 | #ifdef CONFIG_ARM | 226 | #ifdef CONFIG_ARM |
227 | int __init bcm2836_smp_boot_secondary(unsigned int cpu, | 227 | static int __init bcm2836_smp_boot_secondary(unsigned int cpu, |
228 | struct task_struct *idle) | 228 | struct task_struct *idle) |
229 | { | 229 | { |
230 | unsigned long secondary_startup_phys = | 230 | unsigned long secondary_startup_phys = |
231 | (unsigned long)virt_to_phys((void *)secondary_startup); | 231 | (unsigned long)virt_to_phys((void *)secondary_startup); |
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 61b18ab33ad9..0ec92631e23c 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c | |||
@@ -215,7 +215,7 @@ static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn, | |||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
217 | 217 | ||
218 | int __init bcm7120_l2_intc_probe(struct device_node *dn, | 218 | static int __init bcm7120_l2_intc_probe(struct device_node *dn, |
219 | struct device_node *parent, | 219 | struct device_node *parent, |
220 | int (*iomap_regs_fn)(struct device_node *, | 220 | int (*iomap_regs_fn)(struct device_node *, |
221 | struct bcm7120_l2_intc_data *), | 221 | struct bcm7120_l2_intc_data *), |
@@ -339,15 +339,15 @@ out_unmap: | |||
339 | return ret; | 339 | return ret; |
340 | } | 340 | } |
341 | 341 | ||
342 | int __init bcm7120_l2_intc_probe_7120(struct device_node *dn, | 342 | static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn, |
343 | struct device_node *parent) | 343 | struct device_node *parent) |
344 | { | 344 | { |
345 | return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120, | 345 | return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120, |
346 | "BCM7120 L2"); | 346 | "BCM7120 L2"); |
347 | } | 347 | } |
348 | 348 | ||
349 | int __init bcm7120_l2_intc_probe_3380(struct device_node *dn, | 349 | static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn, |
350 | struct device_node *parent) | 350 | struct device_node *parent) |
351 | { | 351 | { |
352 | return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380, | 352 | return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380, |
353 | "BCM3380 L2"); | 353 | "BCM3380 L2"); |
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index 65cd341f331a..1d4a5b46d9ae 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c | |||
@@ -112,8 +112,8 @@ static void brcmstb_l2_intc_resume(struct irq_data *d) | |||
112 | irq_gc_unlock(gc); | 112 | irq_gc_unlock(gc); |
113 | } | 113 | } |
114 | 114 | ||
115 | int __init brcmstb_l2_intc_of_init(struct device_node *np, | 115 | static int __init brcmstb_l2_intc_of_init(struct device_node *np, |
116 | struct device_node *parent) | 116 | struct device_node *parent) |
117 | { | 117 | { |
118 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | 118 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
119 | struct brcmstb_l2_intc_data *data; | 119 | struct brcmstb_l2_intc_data *data; |
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index ad0d2960b664..35eb7ac5d21f 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/of_pci.h> | 24 | #include <linux/of_pci.h> |
25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
26 | #include <linux/spinlock.h> | 26 | #include <linux/spinlock.h> |
27 | #include <linux/irqchip/arm-gic.h> | ||
27 | 28 | ||
28 | /* | 29 | /* |
29 | * MSI_TYPER: | 30 | * MSI_TYPER: |
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index 9d1bcfc33e4c..b04a8ac6e744 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c | |||
@@ -23,6 +23,8 @@ | |||
23 | #include <linux/of_address.h> | 23 | #include <linux/of_address.h> |
24 | #include <linux/of_irq.h> | 24 | #include <linux/of_irq.h> |
25 | 25 | ||
26 | #include <linux/irqchip/irq-omap-intc.h> | ||
27 | |||
26 | /* Define these here for now until we drop all board-files */ | 28 | /* Define these here for now until we drop all board-files */ |
27 | #define OMAP24XX_IC_BASE 0x480fe000 | 29 | #define OMAP24XX_IC_BASE 0x480fe000 |
28 | #define OMAP34XX_IC_BASE 0x48200000 | 30 | #define OMAP34XX_IC_BASE 0x48200000 |
diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c index 5dc5a760c723..c25ce5af091a 100644 --- a/drivers/irqchip/irq-s3c24xx.c +++ b/drivers/irqchip/irq-s3c24xx.c | |||
@@ -92,9 +92,9 @@ static void s3c_irq_mask(struct irq_data *data) | |||
92 | unsigned long mask; | 92 | unsigned long mask; |
93 | unsigned int irqno; | 93 | unsigned int irqno; |
94 | 94 | ||
95 | mask = __raw_readl(intc->reg_mask); | 95 | mask = readl_relaxed(intc->reg_mask); |
96 | mask |= (1UL << irq_data->offset); | 96 | mask |= (1UL << irq_data->offset); |
97 | __raw_writel(mask, intc->reg_mask); | 97 | writel_relaxed(mask, intc->reg_mask); |
98 | 98 | ||
99 | if (parent_intc) { | 99 | if (parent_intc) { |
100 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; | 100 | parent_data = &parent_intc->irqs[irq_data->parent_irq]; |
@@ -119,9 +119,9 @@ static void s3c_irq_unmask(struct irq_data *data) | |||
119 | unsigned long mask; | 119 | unsigned long mask; |
120 | unsigned int irqno; | 120 | unsigned int irqno; |
121 | 121 | ||
122 | mask = __raw_readl(intc->reg_mask); | 122 | mask = readl_relaxed(intc->reg_mask); |
123 | mask &= ~(1UL << irq_data->offset); | 123 | mask &= ~(1UL << irq_data->offset); |
124 | __raw_writel(mask, intc->reg_mask); | 124 | writel_relaxed(mask, intc->reg_mask); |
125 | 125 | ||
126 | if (parent_intc) { | 126 | if (parent_intc) { |
127 | irqno = irq_find_mapping(parent_intc->domain, | 127 | irqno = irq_find_mapping(parent_intc->domain, |
@@ -136,9 +136,9 @@ static inline void s3c_irq_ack(struct irq_data *data) | |||
136 | struct s3c_irq_intc *intc = irq_data->intc; | 136 | struct s3c_irq_intc *intc = irq_data->intc; |
137 | unsigned long bitval = 1UL << irq_data->offset; | 137 | unsigned long bitval = 1UL << irq_data->offset; |
138 | 138 | ||
139 | __raw_writel(bitval, intc->reg_pending); | 139 | writel_relaxed(bitval, intc->reg_pending); |
140 | if (intc->reg_intpnd) | 140 | if (intc->reg_intpnd) |
141 | __raw_writel(bitval, intc->reg_intpnd); | 141 | writel_relaxed(bitval, intc->reg_intpnd); |
142 | } | 142 | } |
143 | 143 | ||
144 | static int s3c_irq_type(struct irq_data *data, unsigned int type) | 144 | static int s3c_irq_type(struct irq_data *data, unsigned int type) |
@@ -172,9 +172,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg, | |||
172 | unsigned long newvalue = 0, value; | 172 | unsigned long newvalue = 0, value; |
173 | 173 | ||
174 | /* Set the GPIO to external interrupt mode */ | 174 | /* Set the GPIO to external interrupt mode */ |
175 | value = __raw_readl(gpcon_reg); | 175 | value = readl_relaxed(gpcon_reg); |
176 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); | 176 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
177 | __raw_writel(value, gpcon_reg); | 177 | writel_relaxed(value, gpcon_reg); |
178 | 178 | ||
179 | /* Set the external interrupt to pointed trigger type */ | 179 | /* Set the external interrupt to pointed trigger type */ |
180 | switch (type) | 180 | switch (type) |
@@ -208,9 +208,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg, | |||
208 | return -EINVAL; | 208 | return -EINVAL; |
209 | } | 209 | } |
210 | 210 | ||
211 | value = __raw_readl(extint_reg); | 211 | value = readl_relaxed(extint_reg); |
212 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); | 212 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
213 | __raw_writel(value, extint_reg); | 213 | writel_relaxed(value, extint_reg); |
214 | 214 | ||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
@@ -315,8 +315,8 @@ static void s3c_irq_demux(struct irq_desc *desc) | |||
315 | 315 | ||
316 | chained_irq_enter(chip, desc); | 316 | chained_irq_enter(chip, desc); |
317 | 317 | ||
318 | src = __raw_readl(sub_intc->reg_pending); | 318 | src = readl_relaxed(sub_intc->reg_pending); |
319 | msk = __raw_readl(sub_intc->reg_mask); | 319 | msk = readl_relaxed(sub_intc->reg_mask); |
320 | 320 | ||
321 | src &= ~msk; | 321 | src &= ~msk; |
322 | src &= irq_data->sub_bits; | 322 | src &= irq_data->sub_bits; |
@@ -337,7 +337,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, | |||
337 | int pnd; | 337 | int pnd; |
338 | int offset; | 338 | int offset; |
339 | 339 | ||
340 | pnd = __raw_readl(intc->reg_intpnd); | 340 | pnd = readl_relaxed(intc->reg_intpnd); |
341 | if (!pnd) | 341 | if (!pnd) |
342 | return false; | 342 | return false; |
343 | 343 | ||
@@ -352,7 +352,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, | |||
352 | * | 352 | * |
353 | * Thanks to Klaus, Shannon, et al for helping to debug this problem | 353 | * Thanks to Klaus, Shannon, et al for helping to debug this problem |
354 | */ | 354 | */ |
355 | offset = __raw_readl(intc->reg_intpnd + 4); | 355 | offset = readl_relaxed(intc->reg_intpnd + 4); |
356 | 356 | ||
357 | /* Find the bit manually, when the offset is wrong. | 357 | /* Find the bit manually, when the offset is wrong. |
358 | * The pending register only ever contains the one bit of the next | 358 | * The pending register only ever contains the one bit of the next |
@@ -406,7 +406,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on) | |||
406 | intmod = 0; | 406 | intmod = 0; |
407 | } | 407 | } |
408 | 408 | ||
409 | __raw_writel(intmod, S3C2410_INTMOD); | 409 | writel_relaxed(intmod, S3C2410_INTMOD); |
410 | return 0; | 410 | return 0; |
411 | } | 411 | } |
412 | 412 | ||
@@ -508,14 +508,14 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) | |||
508 | 508 | ||
509 | last = 0; | 509 | last = 0; |
510 | for (i = 0; i < 4; i++) { | 510 | for (i = 0; i < 4; i++) { |
511 | pend = __raw_readl(reg_source); | 511 | pend = readl_relaxed(reg_source); |
512 | 512 | ||
513 | if (pend == 0 || pend == last) | 513 | if (pend == 0 || pend == last) |
514 | break; | 514 | break; |
515 | 515 | ||
516 | __raw_writel(pend, intc->reg_pending); | 516 | writel_relaxed(pend, intc->reg_pending); |
517 | if (intc->reg_intpnd) | 517 | if (intc->reg_intpnd) |
518 | __raw_writel(pend, intc->reg_intpnd); | 518 | writel_relaxed(pend, intc->reg_intpnd); |
519 | 519 | ||
520 | pr_info("irq: clearing pending status %08x\n", (int)pend); | 520 | pr_info("irq: clearing pending status %08x\n", (int)pend); |
521 | last = pend; | 521 | last = pend; |
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c index 10cb21b9ba3d..e1336848affa 100644 --- a/drivers/irqchip/irq-sirfsoc.c +++ b/drivers/irqchip/irq-sirfsoc.c | |||
@@ -29,6 +29,11 @@ | |||
29 | 29 | ||
30 | static struct irq_domain *sirfsoc_irqdomain; | 30 | static struct irq_domain *sirfsoc_irqdomain; |
31 | 31 | ||
32 | static void __iomem *sirfsoc_irq_get_regbase(void) | ||
33 | { | ||
34 | return (void __iomem __force *)sirfsoc_irqdomain->host_data; | ||
35 | } | ||
36 | |||
32 | static __init void sirfsoc_alloc_gc(void __iomem *base) | 37 | static __init void sirfsoc_alloc_gc(void __iomem *base) |
33 | { | 38 | { |
34 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | 39 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
@@ -53,7 +58,7 @@ static __init void sirfsoc_alloc_gc(void __iomem *base) | |||
53 | 58 | ||
54 | static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) | 59 | static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) |
55 | { | 60 | { |
56 | void __iomem *base = sirfsoc_irqdomain->host_data; | 61 | void __iomem *base = sirfsoc_irq_get_regbase(); |
57 | u32 irqstat; | 62 | u32 irqstat; |
58 | 63 | ||
59 | irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); | 64 | irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); |
@@ -94,7 +99,7 @@ static struct sirfsoc_irq_status sirfsoc_irq_st; | |||
94 | 99 | ||
95 | static int sirfsoc_irq_suspend(void) | 100 | static int sirfsoc_irq_suspend(void) |
96 | { | 101 | { |
97 | void __iomem *base = sirfsoc_irqdomain->host_data; | 102 | void __iomem *base = sirfsoc_irq_get_regbase(); |
98 | 103 | ||
99 | sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); | 104 | sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); |
100 | sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); | 105 | sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); |
@@ -106,7 +111,7 @@ static int sirfsoc_irq_suspend(void) | |||
106 | 111 | ||
107 | static void sirfsoc_irq_resume(void) | 112 | static void sirfsoc_irq_resume(void) |
108 | { | 113 | { |
109 | void __iomem *base = sirfsoc_irqdomain->host_data; | 114 | void __iomem *base = sirfsoc_irq_get_regbase(); |
110 | 115 | ||
111 | writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); | 116 | writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); |
112 | writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); | 117 | writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); |
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c index e902f081e16c..3973a14bb15b 100644 --- a/drivers/irqchip/irq-tegra.c +++ b/drivers/irqchip/irq-tegra.c | |||
@@ -90,7 +90,7 @@ static struct tegra_ictlr_info *lic; | |||
90 | 90 | ||
91 | static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg) | 91 | static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg) |
92 | { | 92 | { |
93 | void __iomem *base = d->chip_data; | 93 | void __iomem *base = (void __iomem __force *)d->chip_data; |
94 | u32 mask; | 94 | u32 mask; |
95 | 95 | ||
96 | mask = BIT(d->hwirq % 32); | 96 | mask = BIT(d->hwirq % 32); |
@@ -266,7 +266,7 @@ static int tegra_ictlr_domain_alloc(struct irq_domain *domain, | |||
266 | 266 | ||
267 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, | 267 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, |
268 | &tegra_ictlr_chip, | 268 | &tegra_ictlr_chip, |
269 | info->base[ictlr]); | 269 | (void __force *)info->base[ictlr]); |
270 | } | 270 | } |
271 | 271 | ||
272 | parent_fwspec = *fwspec; | 272 | parent_fwspec = *fwspec; |
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c index b956dfffe78c..f811a7de5857 100644 --- a/drivers/irqchip/irq-vic.c +++ b/drivers/irqchip/irq-vic.c | |||
@@ -167,7 +167,7 @@ static int vic_suspend(void) | |||
167 | return 0; | 167 | return 0; |
168 | } | 168 | } |
169 | 169 | ||
170 | struct syscore_ops vic_syscore_ops = { | 170 | static struct syscore_ops vic_syscore_ops = { |
171 | .suspend = vic_suspend, | 171 | .suspend = vic_suspend, |
172 | .resume = vic_resume, | 172 | .resume = vic_resume, |
173 | }; | 173 | }; |
@@ -517,7 +517,8 @@ int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq, | |||
517 | EXPORT_SYMBOL_GPL(vic_init_cascaded); | 517 | EXPORT_SYMBOL_GPL(vic_init_cascaded); |
518 | 518 | ||
519 | #ifdef CONFIG_OF | 519 | #ifdef CONFIG_OF |
520 | int __init vic_of_init(struct device_node *node, struct device_node *parent) | 520 | static int __init vic_of_init(struct device_node *node, |
521 | struct device_node *parent) | ||
521 | { | 522 | { |
522 | void __iomem *regs; | 523 | void __iomem *regs; |
523 | u32 interrupt_mask = ~0; | 524 | u32 interrupt_mask = ~0; |