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authorToshiharu Okada <toshiharu-linux@dsn.okisemi.com>2011-09-01 10:20:07 -0400
committerDavid S. Miller <davem@davemloft.net>2011-09-15 17:31:45 -0400
commit5229d87edcd80a3bceb0708ebd767faff2e589a9 (patch)
treef267f7d65d191e82482b485aeb2495d561e8dbc8
parent483f97f8b2b7f0ab09e14c06fe327d5e346fac28 (diff)
pch_gbe: fixed the issue which receives an unnecessary packet.
This patch fixed the issue which receives an unnecessary packet before link When using PHY of GMII, an unnecessary packet is received, And it becomes impossible to receive a packet after link up. Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/pch_gbe/pch_gbe_main.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/net/pch_gbe/pch_gbe_main.c b/drivers/net/pch_gbe/pch_gbe_main.c
index eac3c5ca9731..48ff87c455ae 100644
--- a/drivers/net/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/pch_gbe/pch_gbe_main.c
@@ -717,13 +717,6 @@ static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
717 iowrite32(rdba, &hw->reg->RX_DSC_BASE); 717 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
718 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); 718 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
719 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); 719 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
720
721 /* Enables Receive DMA */
722 rxdma = ioread32(&hw->reg->DMA_CTRL);
723 rxdma |= PCH_GBE_RX_DMA_EN;
724 iowrite32(rxdma, &hw->reg->DMA_CTRL);
725 /* Enables Receive */
726 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
727} 720}
728 721
729/** 722/**
@@ -1097,6 +1090,19 @@ void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1097 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1090 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1098} 1091}
1099 1092
1093static void pch_gbe_start_receive(struct pch_gbe_hw *hw)
1094{
1095 u32 rxdma;
1096
1097 /* Enables Receive DMA */
1098 rxdma = ioread32(&hw->reg->DMA_CTRL);
1099 rxdma |= PCH_GBE_RX_DMA_EN;
1100 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1101 /* Enables Receive */
1102 iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN);
1103 return;
1104}
1105
1100/** 1106/**
1101 * pch_gbe_intr - Interrupt Handler 1107 * pch_gbe_intr - Interrupt Handler
1102 * @irq: Interrupt number 1108 * @irq: Interrupt number
@@ -1717,6 +1723,7 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter)
1717 pch_gbe_alloc_tx_buffers(adapter, tx_ring); 1723 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1718 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); 1724 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1719 adapter->tx_queue_len = netdev->tx_queue_len; 1725 adapter->tx_queue_len = netdev->tx_queue_len;
1726 pch_gbe_start_receive(&adapter->hw);
1720 1727
1721 mod_timer(&adapter->watchdog_timer, jiffies); 1728 mod_timer(&adapter->watchdog_timer, jiffies);
1722 1729