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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2018-09-05 23:21:16 -0400
committerMark Brown <broonie@kernel.org>2018-09-06 06:12:30 -0400
commit501683d0cd54714de78501efe945bbe4356b922b (patch)
tree33b11295ca3f6295667f85c7e1ac991fbac996c5
parentc24fb71fa4f764f02c17cbf88a969f109794e602 (diff)
ASoC: rsnd: gen: use tab instead of white-space
commit 8c9d75033340 ("ASoC: rsnd: ssiu: Support BUSIF other than BUSIF0") added new SSIU registers. But it is using white-space for it. This patch fixup it to use tab. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/sh/rcar/gen.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c
index 3032869a7f26..1f7881cc16b2 100644
--- a/sound/soc/sh/rcar/gen.c
+++ b/sound/soc/sh/rcar/gen.c
@@ -222,30 +222,30 @@ static int rsnd_gen2_probe(struct rsnd_priv *priv)
222 RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80), 222 RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80),
223 RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80), 223 RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80),
224 RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80), 224 RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80),
225 RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80), 225 RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80),
226 RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80), 226 RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80),
227 RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80), 227 RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80),
228 RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80), 228 RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80),
229 RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80), 229 RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80),
230 RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80), 230 RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80),
231 RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80), 231 RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80),
232 RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80), 232 RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80),
233 RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80), 233 RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80),
234 RSND_GEN_M_REG(SSI_BUSIF4_MODE, 0x500, 0x80), 234 RSND_GEN_M_REG(SSI_BUSIF4_MODE, 0x500, 0x80),
235 RSND_GEN_M_REG(SSI_BUSIF4_ADINR, 0x504, 0x80), 235 RSND_GEN_M_REG(SSI_BUSIF4_ADINR, 0x504, 0x80),
236 RSND_GEN_M_REG(SSI_BUSIF4_DALIGN, 0x508, 0x80), 236 RSND_GEN_M_REG(SSI_BUSIF4_DALIGN, 0x508, 0x80),
237 RSND_GEN_M_REG(SSI_BUSIF5_MODE, 0x520, 0x80), 237 RSND_GEN_M_REG(SSI_BUSIF5_MODE, 0x520, 0x80),
238 RSND_GEN_M_REG(SSI_BUSIF5_ADINR, 0x524, 0x80), 238 RSND_GEN_M_REG(SSI_BUSIF5_ADINR, 0x524, 0x80),
239 RSND_GEN_M_REG(SSI_BUSIF5_DALIGN, 0x528, 0x80), 239 RSND_GEN_M_REG(SSI_BUSIF5_DALIGN, 0x528, 0x80),
240 RSND_GEN_M_REG(SSI_BUSIF6_MODE, 0x540, 0x80), 240 RSND_GEN_M_REG(SSI_BUSIF6_MODE, 0x540, 0x80),
241 RSND_GEN_M_REG(SSI_BUSIF6_ADINR, 0x544, 0x80), 241 RSND_GEN_M_REG(SSI_BUSIF6_ADINR, 0x544, 0x80),
242 RSND_GEN_M_REG(SSI_BUSIF6_DALIGN, 0x548, 0x80), 242 RSND_GEN_M_REG(SSI_BUSIF6_DALIGN, 0x548, 0x80),
243 RSND_GEN_M_REG(SSI_BUSIF7_MODE, 0x560, 0x80), 243 RSND_GEN_M_REG(SSI_BUSIF7_MODE, 0x560, 0x80),
244 RSND_GEN_M_REG(SSI_BUSIF7_ADINR, 0x564, 0x80), 244 RSND_GEN_M_REG(SSI_BUSIF7_ADINR, 0x564, 0x80),
245 RSND_GEN_M_REG(SSI_BUSIF7_DALIGN, 0x568, 0x80), 245 RSND_GEN_M_REG(SSI_BUSIF7_DALIGN, 0x568, 0x80),
246 RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80), 246 RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80),
247 RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), 247 RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80),
248 RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80), 248 RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80),
249 }; 249 };
250 250
251 static const struct rsnd_regmap_field_conf conf_scu[] = { 251 static const struct rsnd_regmap_field_conf conf_scu[] = {