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authorBorislav Petkov <bp@suse.de>2019-08-19 03:01:40 -0400
committerIngo Molnar <mingo@kernel.org>2019-08-19 04:55:44 -0400
commit342061c53a049569fc7f56d237753c26b4b2166d (patch)
tree369dcac067b89a50920fce8f34624434a5054b3b
parentbe261ffce6f13229dad50f59c5e491f933d3167f (diff)
x86/msr-index: Move AMD MSRs where they belong
... sort them in and fixup comment, while at it. No functional changes. Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20190819070140.23708-1-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/include/asm/msr-index.h13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6b4fc2788078..f9a01a04c708 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -375,13 +375,17 @@
375/* Alternative perfctr range with full access. */ 375/* Alternative perfctr range with full access. */
376#define MSR_IA32_PMC0 0x000004c1 376#define MSR_IA32_PMC0 0x000004c1
377 377
378/* AMD64 MSRs. Not complete. See the architecture manual for a more 378/*
379 complete list. */ 379 * AMD64 MSRs. Not complete. See the architecture manual for a more
380 380 * complete list.
381 */
381#define MSR_AMD64_PATCH_LEVEL 0x0000008b 382#define MSR_AMD64_PATCH_LEVEL 0x0000008b
382#define MSR_AMD64_TSC_RATIO 0xc0000104 383#define MSR_AMD64_TSC_RATIO 0xc0000104
383#define MSR_AMD64_NB_CFG 0xc001001f 384#define MSR_AMD64_NB_CFG 0xc001001f
384#define MSR_AMD64_PATCH_LOADER 0xc0010020 385#define MSR_AMD64_PATCH_LOADER 0xc0010020
386#define MSR_AMD_PERF_CTL 0xc0010062
387#define MSR_AMD_PERF_STATUS 0xc0010063
388#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
385#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 389#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
386#define MSR_AMD64_OSVW_STATUS 0xc0010141 390#define MSR_AMD64_OSVW_STATUS 0xc0010141
387#define MSR_AMD64_LS_CFG 0xc0011020 391#define MSR_AMD64_LS_CFG 0xc0011020
@@ -560,9 +564,6 @@
560#define MSR_IA32_PERF_STATUS 0x00000198 564#define MSR_IA32_PERF_STATUS 0x00000198
561#define MSR_IA32_PERF_CTL 0x00000199 565#define MSR_IA32_PERF_CTL 0x00000199
562#define INTEL_PERF_CTL_MASK 0xffff 566#define INTEL_PERF_CTL_MASK 0xffff
563#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
564#define MSR_AMD_PERF_STATUS 0xc0010063
565#define MSR_AMD_PERF_CTL 0xc0010062
566 567
567#define MSR_IA32_MPERF 0x000000e7 568#define MSR_IA32_MPERF 0x000000e7
568#define MSR_IA32_APERF 0x000000e8 569#define MSR_IA32_APERF 0x000000e8