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authorTero Kristo <t-kristo@ti.com>2017-06-13 09:45:50 -0400
committerTony Lindgren <tony@atomide.com>2017-06-14 03:53:51 -0400
commit1df5eaa6bced2d8a9de305d4a5f587adf57ddf35 (patch)
tree06631cbdd58de2af83f170005c77b2f8f9844d6f
parentebea90df78c1f290529e18b85c19653e131954de (diff)
ARM: OMAP4: hwmod_data: add SHAM crypto accelerator
OMAP4 SoC contains SHAM crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef4389ce65fe..3e2d792fd9df 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -880,6 +880,33 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
880 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 880 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
881}; 881};
882 882
883/* sha0 HIB2 (the 'P' (public) device) */
884static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
885 .rev_offs = 0x100,
886 .sysc_offs = 0x110,
887 .syss_offs = 0x114,
888 .sysc_flags = SYSS_HAS_RESET_STATUS,
889};
890
891static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
892 .name = "sham",
893 .sysc = &omap44xx_sha0_sysc,
894};
895
896struct omap_hwmod omap44xx_sha0_hwmod = {
897 .name = "sham",
898 .class = &omap44xx_sha0_hwmod_class,
899 .clkdm_name = "l4_secure_clkdm",
900 .main_clk = "l3_div_ck",
901 .prcm = {
902 .omap4 = {
903 .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
904 .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
905 .modulemode = MODULEMODE_SWCTRL,
906 },
907 },
908};
909
883/* 910/*
884 * 'elm' class 911 * 'elm' class
885 * bch error location module 912 * bch error location module
@@ -3987,6 +4014,14 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3987 .user = OCP_USER_MPU, 4014 .user = OCP_USER_MPU,
3988}; 4015};
3989 4016
4017/* l3_main_2 -> sham */
4018static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
4019 .master = &omap44xx_l3_main_2_hwmod,
4020 .slave = &omap44xx_sha0_hwmod,
4021 .clk = "l3_div_ck",
4022 .user = OCP_USER_MPU | OCP_USER_SDMA,
4023};
4024
3990/* l4_per -> elm */ 4025/* l4_per -> elm */
3991static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = { 4026static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3992 .master = &omap44xx_l4_per_hwmod, 4027 .master = &omap44xx_l4_per_hwmod,
@@ -4901,6 +4936,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4901 &omap44xx_l3_main_2__aes1, 4936 &omap44xx_l3_main_2__aes1,
4902 &omap44xx_l3_main_2__aes2, 4937 &omap44xx_l3_main_2__aes2,
4903 &omap44xx_l3_main_2__des, 4938 &omap44xx_l3_main_2__des,
4939 &omap44xx_l3_main_2__sha0,
4904 NULL, 4940 NULL,
4905}; 4941};
4906 4942