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-rw-r--r--libsmctrl.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/libsmctrl.h b/libsmctrl.h
index a8207b4..eca1f70 100644
--- a/libsmctrl.h
+++ b/libsmctrl.h
@@ -1,5 +1,5 @@
1/** 1/**
2 * Copyright 2023 Joshua Bakita 2 * Copyright 2024 Joshua Bakita
3 * Library to control TPC masks on CUDA launches. Co-opts preexisting debug 3 * Library to control TPC masks on CUDA launches. Co-opts preexisting debug
4 * logic in the CUDA driver library, and thus requires a build with -lcuda. 4 * logic in the CUDA driver library, and thus requires a build with -lcuda.
5 */ 5 */
@@ -21,7 +21,7 @@ extern void libsmctrl_set_global_mask(uint64_t mask);
21// (overrides global mask) 21// (overrides global mask)
22// @param stream A cudaStream_t (aka CUstream_st*) to apply the mask on 22// @param stream A cudaStream_t (aka CUstream_st*) to apply the mask on
23// @param mask A bitmask of enabled/disabled TPCs (see Notes on Bitmasks) 23// @param mask A bitmask of enabled/disabled TPCs (see Notes on Bitmasks)
24// Supported: CUDA 8.0 - CUDA 12.1 24// Supported: CUDA 8.0 - CUDA 12.2, plus 12.4 and 12.6
25extern void libsmctrl_set_stream_mask(void* stream, uint64_t mask); 25extern void libsmctrl_set_stream_mask(void* stream, uint64_t mask);
26extern void libsmctrl_set_stream_mask_ext(void* stream, uint128_t mask); 26extern void libsmctrl_set_stream_mask_ext(void* stream, uint128_t mask);
27// Set TPC mask for the next kernel launch from the caller's CPU thread 27// Set TPC mask for the next kernel launch from the caller's CPU thread
@@ -47,6 +47,10 @@ extern void libsmctrl_set_next_mask(uint64_t mask);
47 * 47 *
48 * Note that the bitwise inversion operator (~, as used above) is very useful, 48 * Note that the bitwise inversion operator (~, as used above) is very useful,
49 * just be sure to apply it to 64-bit integer literals only! (~0x1 != ~0x1ull) 49 * just be sure to apply it to 64-bit integer literals only! (~0x1 != ~0x1ull)
50 *
51 * On GPUs with over 64 TPCs, use the _mask_ext() functions to support 128-bit
52 * masks. If using a 64-bit mask on a GPU with more than 64 TPCs, all TPCs with
53 * IDs over 64 will be disabled.
50 */ 54 */
51 55
52/* INFORMATIONAL FUNCTIONS */ 56/* INFORMATIONAL FUNCTIONS */